Phase-change memory material, method for preparing the same, phase-change memory chip, and device

Abstract

The present application relates to the field of data storage technology, in particular to a phase change memory material, its preparation method, phase change memory chip, and device. The phase change memory material is Ti a Sb b Te c D d where a represents the atomic percentage of Ti, b represents the atomic percentage of Sb, c represents the atomic percentage of Te, and d represents the atomic percentage of element D, where a+b+c+d=1, 3%≦a≦45%, and 0.5≦(b:c)≦3, and D is a doping element, where 0≦d≦15%. The phase change memory material has low operating power consumption and low operating delay.

Description

[Technical Field]

[0001] This application claims priority to Chinese Patent Application No. 202210356787.X, titled "PHASE-CHANGE MEMORY MATERIAL, PREPARATION METHOD THEREOF, PHASE-CHANGE MEMORY CHIP, AND DEVICE," filed with the China National Intellectual Property Administration on April 6, 2022, which is incorporated herein by reference in its entirety.

[0002] This application relates to the field of data storage technology, and more specifically to phase-change memory materials, methods for preparing the same, phase-change memory chips, and devices. [Background technology]

[0003] With advancements in information technology, memory is required to have low latency and large capacity. Low latency helps increase data processing speed. Large capacity helps improve storage density and saves on the cost of manufacturing memory.

[0004] As a non-volatile memory, phase-change memory (PCM) offers high-density data storage capabilities and fast erase and write speeds, and is used in internal memory and other applications. However, current phase-change memory fails to balance low power consumption and low operating latency, resulting in poor performance. [Overview of the project]

[0005] Embodiments of this application provide a phase-change memory material, a method for preparing the same, a phase-change memory chip, and a device that reduce power consumption and operational delay of phase-change memory chips and devices.

[0006] According to the first embodiment, a phase-change memory material is provided. Here, the phase-change memory material includes the material represented by formula (1), Ti a S b Tec D d (1) Here, a represents the atomic percentage of Ti, b represents the atomic percentage of Sb, c represents the atomic percentage of Te, d represents the atomic percentage of element D, and a+b+c+d=1, 3%≦a≦45%, and 0.5≦(b:c)≦3, D is the doping element, and 0≦d≦15%.

[0007] The phase-change memory material provided in this embodiment of the present application is a novel Sb-Te-based phase-change memory material. When SbTe is crystallized, i.e., in a crystalline state, the phase-change memory material is in a low-resistance state, or when SbTe is amorphous, i.e., in an amorphous state, the phase-change memory material is in a high-resistance state. Different resistance states of the phase-change memory material can represent different information and realize information storage. In addition, the information can be read by measuring the resistance state of the phase-change memory material.

[0008] Phase-change memory materials contain the element Ti, where Ti and Te form TiTe nucleation centers. Specifically, the bonding strength between TiTe is greater than the bonding strength between SbTe. During the conversion of SbTe between a crystalline state (i.e., a low-resistance state) and an amorphous state (i.e., a high-resistance state), the TiTe nucleation centers can maintain a stable structure. When SbTe is converted from a crystalline state (i.e., a low-resistance state) to an amorphous state (i.e., a high-resistance state), TiTe as a nucleation center can accelerate the conversion of SbTe from the crystalline state to the amorphous state, and as a result, operational delay can be reduced. Therefore, when phase-change memory materials are used in storage-class memory, the storage-class memory can have low latency.

[0009] In addition, the lattice mismatch between the TiTe lattice and the SbTe lattice is 12%, and the phase-change memory material contains Ti. This can cause lattice distortion or lattice defects in the phase-change memory material, and as a result, the phase-change memory material can be more easily converted from a crystalline state to an amorphous state, and therefore the power consumption required for conversion from a crystalline state to an amorphous state can be reduced.

[0010] In addition, the Ti contained in the phase-change memory material can reduce the grain size of the phase-change memory material, resulting in a more uniform grain size distribution (this can be understood as indicating that the smaller the grain size, the smaller the grain size distribution range, and therefore the more uniform the grain size distribution). Consequently, the fatigue life of the phase-change memory material can be improved.

[0011] In possible implementations, the range of values ​​for the atomic percentage a of Ti can be 5% ≤ a ≤ 40%, 10% ≤ a ≤ 38%, 15% ≤ a ≤ 30%, or 20% ≤ a ≤ 35%, etc. More specifically, in one example, a can be 5%. In another example, a can be 8%. In another example, a can be 10%. In another example, a can be 13%. In another example, a can be 15%. In another example, a can be 18%. In another example, a can be 20%. In another example, a can be 25%. In another example, a can be 28%. In another example, a can be 30%. In another example, a can be 32%. In another example, a can be 35%. In another example, a can be 37%. In one example, a could be 40%. In another example, a could be 45%.

[0012] When the atomic percentage a of Ti is in the range of 20% ≤ a ≤ 35%, the phase-change memory material exhibits better performance in terms of operating delay, power consumption, thermal stability, and fatigue life.

[0013] In possible implementations, the ratio of atomic percentage b of Sb to atomic percentage c of Te can be 0.5 ≤ (b:c) ≤ 1, 0.5 ≤ (b:c) ≤ 2, 1 ≤ (b:c) ≤ 3, or 2 ≤ (b:c) ≤ 3, etc. More specifically, in one example, (b:c) can be 0.5, (2:3), 1, 2, or 3, etc.

[0014] When (b:c) is (2:3), the phase-change memory material exhibits better performance in terms of operating delay, power consumption, thermal stability, and fatigue life.

[0015] In possible implementations, the range of values ​​for the atomic percentage a of Ti is 20% ≤ a ≤ 35%, and the ratio of the atomic percentage b of Sb to the atomic percentage c of Te is 2:3.

[0016] In this implementation, the phase-change memory material has less operational delay, lower power consumption, higher thermal stability, and a longer fatigue life.

[0017] In possible implementations, the atomic percentage d of doping element D can be 0% ≤ d ≤ 10%, 0% ≤ d ≤ 8%, 3% ≤ d ≤ 10%, or 3% ≤ d ≤ 8%. More specifically, in one example, the atomic percentage d of doping element D is 0, i.e., the phase-change memory material does not contain doping element D. In one example, d is 1%. In one example, d is 3%. In one example, d is 5%. In one example, d is 8%. In one example, d is 10%. In one example, d is 15%.

[0018] When 3% ≤ d ≤ 8%, the phase-change memory material has less operational delay and a higher fatigue life.

[0019] In a possible implementation, the doping element comprises one or at least two combinations of a first nonmetallic element, a first metallic element, and a telluride of the first metallic element, wherein the first nonmetallic element is one or at least two combinations of C, O, N, and Si, and the first metallic element is one or at least two combinations of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn.

[0020] In this implementation, doping elements are doped into the phase-change memory material, resulting in improved thermal stability and fatigue life of the phase-change memory material, and further increasing the crystallization rate of the phase-change memory material (specifically, the rate of conversion from a high-resistance state to a low-resistance state). Consequently, operational delay is reduced.

[0021] According to a second embodiment, a method for preparing a phase-change memory material is provided, where the method may be used to prepare the phase-change memory material provided in the first embodiment. The method includes the step of preparing the phase-change memory material in a first deposition method according to the elemental ratio shown by formula (1), the first deposition method being one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). Ti a S b Te c D d (1) That is the case. a represents the atomic percentage of Ti, b represents the atomic percentage of Sb, c represents the atomic percentage of Te, and d represents the atomic percentage of element D. a+b+c+d=1, 3%≦a≦45%, and 0.5≦(b:c)≦3. D is a doping element, and 0≦d≦15%.

[0022] This method allows for the efficient preparation of phase-change memory materials, facilitating operations and facilitating industrial implementation.

[0023] In a possible implementation, the first deposition method is a sputtering method in physical vapor deposition, and the step of preparing a phase-change memory material by the first deposition method according to the elemental ratio shown by equation (1) includes the steps of preparing a first target material according to the atomic percentages shown by equation (1) and performing sputtering on the first target material to obtain the phase-change memory material.

[0024] In this implementation, the alloy target material may be prepared first, and then sputtering is performed on the alloy target material to obtain the phase change memory material. This method is simpler and easier to implement, saves preparation time, and is easy to implement industrially.

[0025] In a possible implementation, the first deposition method is a sputtering method in physical vapor deposition, and the step of preparing a phase-change memory material in the first deposition method according to the elemental ratio shown by equation (1) includes the step of performing simultaneous sputtering on a Ti single-element target material and an SbTe alloy target material to obtain a phase-change memory material, wherein the sputtering power of the different single-element target materials is adjusted in the simultaneous sputtering process according to the atomic percentage shown by equation (1).

[0026] In this implementation, simultaneous sputtering may be performed on single-element target materials and alloy target materials to obtain phase-change memory materials. This method is simple and easy to implement, saves preparation time, and is easy to implement industrially.

[0027] According to a third embodiment, a phase-change memory chip is provided which includes a plurality of memory cells. Here, the plurality of memory cells form a memory cell array, and each memory cell includes a phase-change layer, an electrode provided on one side of the phase-change layer, and an electrode provided on the other side of the phase-change layer, the phase-change layer being made of the phase-change memory material provided in the first embodiment.

[0028] Phase-change memory chips offer advantages such as low operating delay, low power consumption, high thermal stability, and a long fatigue life.

[0029] In a possible implementation, each memory cell further comprises a buffer layer in contact with the phase change layer, the buffer layer being made of one of carbon, a third metal, a nitride of the third metal, and a telluride of a fourth metal, where the third metal is one or at least two of W, Ta, and Ti, and the fourth metal is one or at least two of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, and Sn.

[0030] In this implementation, a buffer layer in contact with the phase change layer is introduced, and as a result, the performance of the phase change layer and the memory chip can be further improved. Specifically, when the buffer layer material is carbon, the buffer layer can improve the thermal insulation effect of the phase change layer, reduce the operating power consumption of the phase change memory chip, prevent elemental diffusion in the phase change layer, and improve the adhesion effect between the phase change layer and the electrodes. When the buffer layer material is a telluride of a fourth metal such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn, the buffer layer can be used as a crystallization template for the phase change memory material, and as a result, the rate of conversion of the phase change memory material from an amorphous state to a crystalline state can be accelerated. Therefore, the operating delay of the phase change memory chip can be reduced, the heating efficiency of the phase change memory chip can be improved, and the operating power consumption of the phase change memory chip can be reduced. When the buffer layer material is a third metal such as W, Ta, or Ti, the buffer layer can prevent elemental diffusion in the phase-change memory material and improve the adhesion effect between the phase-change layer and the electrodes. When the buffer layer material is a nitride of the third metal, the buffer layer can improve the adhesion effect between the phase-change layer and the electrodes, improve the heating efficiency of the phase-change memory material, reduce resistance drift, repair voids at the interface of the phase-change memory material, and improve the adhesion effect between the phase-change layer and the electrodes.

[0031] In possible implementations, the buffer layer is placed between the phase change layer and the electrodes. 、The phase change layer has grooves, and the buffer layer is provided within the grooves of the phase change layer, or the buffer layer has grooves, and the phase change layer is provided within the grooves of the buffer layer.

[0032] In this implementation, the phase change layer and buffer layer may be in contact in multiple ways, and as a result, the phase change memory chip can be flexibly implemented and is easy to prepare.

[0033] In a possible implementation, each memory cell further includes at least one phase-change layer and at least one chalcogenide layer. Both the at least one phase-change layer and the at least one chalcogenide layer are located between a first electrode and a second electrode, and the at least one phase-change layer and the at least one chalcogenide layer are stacked alternately.

[0034] In this implementation, the phase change layer and the chalcogenide layer are stacked alternately, resulting in more interfaces being introduced into the phase change memory material within the phase change memory chip, which can reduce thermal conductivity. Therefore, the operating power consumption of the phase change memory chip is reduced, and the fatigue life of the phase change memory chip is improved. In addition, chalcogenides have good thermal insulation properties. This can further reduce the operating power consumption of the phase change memory chip and improve its fatigue life.

[0035] In possible implementations, the lattice coefficients of the chalcogenide layer are smaller than those of SbTe.

[0036] In this implementation, materials with lattice coefficients smaller than those of SbTe, such as TiTe2, can be used as the material for the chalcogenide layer 115. This prevents elemental diffusion in the phase change layer, improves the fatigue life of the phase change layer, and in other words, improves the fatigue life of the phase change memory chip.

[0037] According to a fourth aspect, a storage device is provided, which includes a controller and a phase-change memory chip provided in a third aspect, wherein the phase-change memory chip is configured to store data, and the controller is configured to write data to or read data from the memory chip.

[0038] A fifth aspect provides an electronic device comprising a processor and a storage device provided in the fourth aspect, wherein the storage device is configured to store data, and the processor is configured to write data to or read data from the storage device.

[0039] The phase-change memory material and phase-change memory chip provided in the embodiments of this application have low operational latency. When the phase-change memory material and phase-change memory chip are used in storage-class memory, the storage-class memory has low latency, and as a result, the operational latency of storage devices and electronic devices equipped with the phase-change memory material and phase-change memory chip can be further reduced. In addition, the phase-change memory material and phase-change memory chip have low operating power consumption, and as a result, the power consumption of storage devices and electronic devices equipped with the phase-change memory material and phase-change memory chip can be reduced. Furthermore, the phase-change memory material and phase-change memory chip have a high fatigue life, and as a result, the service life of storage devices and electronic devices equipped with the phase-change memory material and phase-change memory chip can be improved. [Brief explanation of the drawing]

[0040] [Figure 1A] This is a diagram showing the structure of a phase-change memory cell according to one embodiment of this application. [Figure 1B] This is a diagram showing the structure of another phase-change memory cell according to one embodiment of this application. [Figure 2]This is a diagram showing the structure of a phase-change memory array according to one embodiment of this application. [Figure 3A] This is a diagram showing the low-resistance state of a germanium-antimony-tellurium phase-change memory material. [Figure 3B] This is a diagram showing the high-resistance state of a germanium-antimony-tellurium phase-change memory material. [Figure 4A] This figure shows a low-resistance state of a phase-change memory material according to one embodiment of this application. [Figure 4B] This figure shows a high-resistance state of a phase-change memory material according to one embodiment of this application. [Figure 5A] This is a diagram showing the grain size of a phase-change memory material according to one embodiment of this application. [Figure 5B] This is a diagram showing the grain size of a phase-change memory material according to one embodiment of this application. [Figure 6] This is a diagram showing the resistance-temperature curve of a phase-change memory material according to one embodiment of this application. [Figure 7A] This is a diagram showing the structure of a phase-change memory array according to one embodiment of this application. [Figure 7B] This is a diagram showing the structure of a phase-change memory array according to one embodiment of this application. [Figure 7C] This is a diagram showing the structure of a phase-change memory array according to one embodiment of this application. [Figure 7D] This is a diagram showing the structure of a phase-change memory array according to one embodiment of this application. [Figure 7E] This is a diagram showing the structure of a phase-change memory array according to one embodiment of this application. [Figure 8A] This is a diagram showing the structure of a phase-change memory array according to one embodiment of this application. [Figure 8B] This is a diagram showing the structure of a phase-change memory array according to one embodiment of this application. [Figure 8C] This is a diagram showing the structure of a phase-change memory array according to one embodiment of this application. [Figure 8D] This is a diagram showing the structure of a phase-change memory array according to one embodiment of this application. [Figure 9] This is a diagram showing the structure of a storage device according to one embodiment of this application. [Figure 10] This is a diagram showing the structure of an electronic device according to one embodiment of this application. [Modes for carrying out the invention]

[0041] The following describes the technical solutions in the embodiments of this application with reference to the attached drawings. It is clear that the embodiments described are only a part of the embodiments of this application, and not all of them.

[0042] In this specification, specific features, structures, materials, or properties may be combined in an appropriate manner in any one or more embodiments or examples.

[0043] In the description of embodiments of this application, words such as “example,” “for example,” or “exemplary” are to be understood as being used to indicate that an example, illustration, or explanation is being given. Any embodiment or design described as “example,” “for example,” or “exemplary” in the embodiments of this application should not be construed as being preferable to or having more advantages than another embodiment or design. More precisely, the use of words such as “example,” “for example,” or “exemplary” is intended to present the relevant concepts in a concrete manner.

[0044] In the description of embodiments of this application, the terms "and / or" describe only the relationship between related objects, indicating that there are three possible relationships. For example, A and / or B may indicate the following three cases: A only exists, B only exists, or both A and B exist. Also, unless otherwise specified, the term "multiple" means two or more. For example, "multiple systems" means two or more systems, and "multiple terminals" means two or more terminals.

[0045] A phase-change memory chip is a chip that stores data by using the difference in conductivity exhibited by the phase-change memory material during the conversion of the phase-change memory material between a crystalline state and an amorphous state. Specifically, in the crystalline state, the atoms in the phase-change memory material are arranged in an orderly manner, resulting in the phase-change memory material having long-range atomic energy levels and a high free electron density, and therefore having low resistivity. Thus, the crystalline state can be called a low-resistance state. In the amorphous state, the atoms in the phase-change memory material are arranged in a disordered manner, resulting in the phase-change memory material having short-range atomic energy levels and a low free electron density, and therefore having high resistivity. Thus, the amorphous state can be called a high-resistance state. The phase-change memory material in the low-resistance state may be set to correspond to one of "0" and "1", and the phase-change memory material in the high-resistance state may correspond to the other of "0" and "1".

[0046] When a specific pulse voltage is applied to a phase-change memory material, the material can be converted between a high-resistance state and a low-resistance state. Specifically, a high, narrow electrical pulse (which may be called a reset pulse) may be applied to the phase-change memory chip, resulting in a conversion of the phase-change memory material from a low-resistance state to a high-resistance state. A low, wide electrical pulse (which may be called a set pulse) may also be applied to the phase-change memory chip, resulting in a conversion of the phase-change memory material from a high-resistance state to a low-resistance state. Thus, a write operation to the phase-change memory material can be realized.

[0047] In addition, the high-resistance and low-resistance states of the phase-change memory material correspond to different bit values, respectively. In this way, a low read voltage (a voltage that cannot convert the phase-change memory material between the high-resistance and low-resistance states) is applied to the phase-change memory material, and the resistance value of the phase-change memory material can be read, enabling a read operation.

[0048] Figure 1A shows an implementation of a phase-change memory cell 110 and a corresponding selector 120. The phase-change memory cell is a memory cell located within a phase-change memory chip and configured to store a single bit value ("0" or "1"). As shown in Figure 1A, the phase-change memory cell 110 may include an electrode 111, an electrode 112, and a phase-change layer 113 provided between electrodes 111 and 112. The phase-change layer 113 is made of a phase-change memory material. A voltage or current is applied to the phase-change layer 113 via electrodes 111 and 112 to perform a write or read operation.

[0049] During writing, current or voltage is applied to the word line 130, resulting in the word line 130 becoming high-potential and transistor 120 conducting. Next, current or voltage is applied to the bit line 140, resulting in the phase change layer of the phase change memory cell being converted between a high-resistance state and a low-resistance state to perform the write operation. During reading, the column selection circuit applies a small preset potential to the bit line 140 (thereby the preset potential does not change the resistance state of the phase change memory cell). As described above, the word line 130 is at a high potential. This affects the potential on the bit line 140, and the magnitude of the effect is related to the magnitude of the resistance of the phase change memory cell. The effect of the word line 130 on the potential on the bit line 140 is equivalent to the phase change memory cell outputting a signal, and the result of the effect (the potential on the bit line 140 after being affected by the word line 130) is equivalent to the output signal. The result of the effect is compared with a reference potential to determine the resistance state of the phase change memory cell, and based on the resistance state, the data stored in the phase change memory cell is determined. The column selection circuit is described below, and its details are not explained here.

[0050] FIG. 1B shows another implementation of the phase change memory cell 110. The phase change memory cell 110 may include an electrode 111, a phase change layer 113, an electrode 112, a select layer 116 (the select layer 116 may also be referred to as a select tube 116), and an electrode 117 that are sequentially adjacent to each other. The phase change layer 113 may include a phase change memory material. A voltage or current may be applied to the phase change layer 113 between the electrode 111 and the electrode 112 to realize a write operation or a read operation.

[0051] Specifically, the electrode 112 may be connected to the word line 130 through the select layer 116 and the electrode 117. When the voltage difference between both ends of the select layer 116 exceeds the threshold switching voltage V th of the select layer 116, the select layer 116 is turned on, and the voltage at both ends of the select layer 116 decreases. As a result, more voltage is applied to both ends of the phase change layer 113. Therefore, a write operation or a read operation can be realized.

[0052] In some embodiments, the material of the select layer 116 is an ovonic threshold switching (OTS) material including Ge, Se, and As. The OTS material forming the select layer 116 may be doped with at least one of Si, N, and S. In some embodiments, the material of the select layer 116 is a GeAsSe alloy. In some embodiments, the material of the select layer 116 is a GeAsSe alloy doped with at least one of Si, N, C, As, and Se, etc.

[0053] In addition, the materials of the phase change layer 113, electrodes 111, 112, 116, and 117 are described below. In the following description, unless otherwise specified, electrodes 111, 112, 116, and 117 may be abbreviated as electrodes. Figure 2 shows a phase change memory chip including a phase change memory cell array and peripheral circuits. The phase change memory cell array includes multiple phase change memory cells arranged in a cross pattern to form a high-density memory array. Phase change memory cell 110 may be one phase change memory cell in the phase change memory cell array. Phase change memory cell 110 may use the structure shown in Figure 1A or the structure shown in Figure 1B. In addition, when the phase change memory cells in the phase change memory cell array specifically have the structure shown in Figure 1A, the phase change memory cell array further includes selection transistors (not shown in Figure 2) for the phase change memory cells. For a phase-change memory cell, the phase-change memory cell is selected when the bit line and word line are selected simultaneously and the selector is in a conductive state; otherwise, the phase-change memory cell is in a deselected state. A processor (not shown) may select the phase-change memory cell 110 by selecting the word line 130 via a row selection circuit, selecting the bit line 140 via a column selection circuit, and controlling the selection transistor 120 to conduct. A read / write (R / W) circuit may receive an instruction from the processor, control the row selection circuit and the column selection circuit based on the instruction, and apply voltage to the phase-change memory cell 110 via the word line 130 and the bit line 140 to perform a read or write operation. A drive circuit VS1 may apply voltage to the phase-change memory cell 110 via the word line 130 under the control of the row selection circuit, and a drive circuit VS2 may apply voltage to the phase-change memory cell 110 via the bit line 140 under the control of the column selection circuit.

[0054] The aforementioned examples illustrate the structure of a phase-change memory chip and a phase-change memory cell provided in the embodiments of this application. The phase-change memory materials will be described below.

[0055] The performance of phase-change memory materials, including phase-change power consumption (specifically, the energy consumed for conversion between high-resistance and low-resistance states), fatigue life, phase-change speed (the time required for conversion between high-resistance and low-resistance states), and thermal stability, significantly impacts the operational delay, lifespan, and reliability of phase-change memory chips. Conventional germanium-antimony-tellurium (GeSbTe, GST) phase-change memory materials exhibit good thermal stability and fatigue life. However, as shown in Figures 3A and 3B, the conversion between high-resistance and low-resistance states involves the cleavage and recombination of GeTe bonds, which delays the phase-change process (specifically, the conversion speed between high-resistance and low-resistance states is low). As a result, the operational delay is high (100 ns level). This cannot fully meet the low-latency requirements of storage-class memory (SCM). Therefore, even when phase-change memory materials are used in storage-class memory, the latency of storage-class memory remains high.

[0056] One embodiment of this application provides a Ti-doped SbTe phase-change memory material. Ti doping improves the thermal stability of the SbTe phase-change system, reduces phase-change power consumption, and improves fatigue life. In addition, the presence of TiTe nucleation centers can accelerate crystallization and thus reduce operational delay. The general chemical formula for the Ti-doped SbTe phase-change memory material is Ti a S b Te c D dThe equation is as follows: a represents the atomic percentage of the chemical element titanium (Ti). Specifically, a represents the proportion of the chemical element titanium (Ti) in the total amount of atoms in the phase-change memory material. b represents the atomic percentage of the chemical element antimony (Sb). Specifically, b represents the proportion of the chemical element antimony (Sb) in the total amount of atoms in the phase-change memory material. c represents the atomic percentage of the chemical element tellurium (Te). Specifically, c represents the proportion of the chemical element tellurium (Te) in the total amount of atoms in the phase-change memory material. d represents the atomic percentage of the doping element D. Specifically, d represents the proportion of the doping element D in the total amount of atoms in the phase-change memory material. In short, a + b + c + d = 1.

[0057] In the phase-change memory material provided in this embodiment of the present application, 3% ≤ a ≤ 45%. Specifically, the proportion of Ti in the total amount of atoms in the phase-change memory material is 3% or more and 45% or less. In addition, 0.5 ≤ (b:c) ≤ 3. Specifically, in the phase-change memory material, the ratio of the atomic weight of Sb to the atomic weight of Te is 0.5 or more and 3 or less. 0 ≤ d ≤ 15%. Specifically, the proportion of the doping element D in the total amount of atoms in the phase-change memory material is 15% or less. In other words, the phase-change memory material may or may not contain a doping element, and the atomic percentage of the doping element does not exceed 15%.

[0058] The phase-change memory material provided in this embodiment of the present application is a novel Sb-Te-based phase-change memory material. When SbTe is crystallized, i.e., in a crystalline state, the phase-change memory material is in a low-resistance state, or when SbTe is amorphous, i.e., in an amorphous state, the phase-change memory material is in a high-resistance state. Different resistance states of the phase-change memory material represent different information and can realize information storage. In addition, the information can be read by measuring the resistance state of the phase-change memory material.

[0059] Please refer to Figures 4A and 4B. In the phase-change memory material provided in one embodiment of this application, Ti and Te form TiTe nucleation centers, and TiTe has a stronger bond strength than SbTe. When SbTe is converted from a crystalline state (i.e., a low-resistance state) to an amorphous state (i.e., a high-resistance state), the TiTe nucleation centers can maintain a stable structure. Therefore, TiTe nucleation centers exist in both the low-resistance and high-resistance states of the phase-change memory material. When the phase-change memory material is converted from a high-resistance state (i.e., an amorphous state) to a low-resistance state (i.e., a crystalline state), the TiTe nucleation centers, acting as nucleation centers for recrystallization, can increase the crystallization rate of SbTe, thereby reducing operational delay. Crystallization is the process by which the atomic structure in a material is changed from disorder to an orderly arrangement, i.e., the process of converting an amorphous state to a crystalline state.

[0060] In addition, the lattice mismatch between the TiTe lattice and the SbTe lattice is 12%, and Ti is introduced into the phase-change memory material provided in this embodiment of the present application. This can cause lattice distortion or lattice defects in TiSbTe, and as a result, the phase-change memory material can be more easily converted from a crystalline state to an amorphous state, and therefore the power consumption required for the conversion from a crystalline state to an amorphous state can be reduced.

[0061] In addition, based on experimental tests, the Ti contained in the phase-change memory material provided in this embodiment of the present application can reduce grain size and therefore improve fatigue life.

[0062] In addition, based on experimental tests, the Ti contained in the phase-change memory material provided in this embodiment of the present application can improve the thermal stability of the phase-change memory material in low-resistance and high-resistance states.

[0063] In some embodiments, the range of values ​​for the atomic percentage a of Ti may be 5% ≤ a ≤ 40%, 10% ≤ a ≤ 38%, 15% ≤ a ≤ 30%, or 20% ≤ a ≤ 35%, etc. Details are not listed here one by one. When the range of values ​​for the atomic percentage a of Ti is 20% ≤ a ≤ 35%, the phase-change memory material exhibits better performance in terms of operating delay, power consumption, thermal stability, and fatigue life.

[0064] In one example, a could be 5%. In another example, a could be 8%. In another example, a could be 10%. In another example, a could be 13%. In another example, a could be 15%. In another example, a could be 18%. In another example, a could be 20%. In another example, a could be 25%. In another example, a could be 28%. In another example, a could be 30%. In another example, a could be 32%. In another example, a could be 35%. In another example, a could be 37%. In another example, a could be 40%. In another example, a could be 45%.

[0065] In some embodiments, the ratio of the atomic percentage b of Sb to the atomic percentage c of Te, i.e., (b:c), can be 0.5 ≤ (b:c) ≤ 1, 0.5 ≤ (b:c) ≤ 2, 1 ≤ (b:c) ≤ 3, or 2 ≤ (b:c) ≤ 3, etc. Details are not listed here one by one.

[0066] For example, (b:c) could be 0.5, (2:3), 1, 2, or 3. Details are not listed here. When (b:c) is (2:3), the phase-change memory material exhibits better performance in terms of operating delay, power consumption, thermal stability, and fatigue life.

[0067] In some embodiments, the range of atomic percentage a of Ti is 20% ≤ a ≤ 35%, and the ratio of atomic percentage b of Sb to atomic percentage c of Te is (2:3). In this case, the phase-change memory material has less operational delay, lower power consumption, higher thermal stability, and a higher fatigue life.

[0068] In some embodiments, doping element D may be a combination of one or at least two nonmetallic elements such as C, O, N, and Si. In some embodiments, doping element D may be a combination of one or at least two metallic elements such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn. In some embodiments, doping element D may be a combination of one or at least two tellurides of metallic elements such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn. In some embodiments, doping element D may be a combination of one or at least two nonmetallic elements such as C, O, N, and Si, metallic elements such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn, and tellurides of metallic elements.

[0069] When doping element D is added to the phase-change memory material, the thermal stability and fatigue life of the phase-change memory material can be improved, and the crystallization rate of the phase-change memory material (specifically, the rate of conversion from a high-resistance state to a low-resistance state) can be further increased. Consequently, the operating delay can be reduced.

[0070] In some embodiments, the atomic percentage d of the doping element D can be 0%≦d≦10%, 0%≦d≦8%, 3%≦d≦10%, or 3%≦d≦8%. When 3%≦d≦8%, the phase-change memory material has less operational delay and a higher fatigue life.

[0071] In one example, the atomic percentage d of doping element D is 0, meaning the phase-change memory material does not contain doping element D. In another example, d is 1%. In yet another example, d is 3%. In yet another example, d is 5%. In yet another example, d is 8%. In yet another example, d is 10%. In yet another example, d is 15%.

[0072] The example above illustrates the composition of the phase-change memory material. The following example will be used to describe the preparation solution for the phase-change memory material.

[0073] In the embodiments of this application, the phase-change memory material is Ti, which is deposited using a material deposition method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). a S b Te c D d It can be deposited on a substrate according to the elemental ratio shown. The substrate may also be an electrode. 、 The buffer layer may be one described below, the chalcogenide layer may be one described below, or another specific substrate. Further details are not provided here.

[0074] In some embodiments, the phase-change memory material is prepared on a substrate by using a single-element Ti target material and an SbTe alloy target material. In the sputtering process, different deposition rates may be obtained by controlling the power of different target materials, resulting in phase-change memory materials with corresponding compositional distribution ratios.

[0075] In some embodiments, the phase-change memory material may be prepared on a substrate by sputtering a single target material in a sputtering method (e.g., magnetron sputtering) during physical vapor deposition. Specifically, when doping element D is not present, or when doping element D1 is not N and / or O, sputtering may be performed using a single-element Ti target material, a single-element Sb target material, a single-element Te target material, and a single-element doping element D (when the phase-change material contains doping element D) target material to prepare the phase-change memory material on the substrate. When doping element D1 is N, sputtering may be performed using a titanium nitride alloy target material, a single-element Sb target material, and a single-element Te target material to prepare the phase-change memory material on the substrate. When doping element D1 is O, sputtering may be performed using a titanium oxide alloy target material, a single-element Sb target material, and a single-element Te target material to prepare the phase-change memory material on the substrate. In the sputtering process, different deposition rates can be obtained by controlling the power of different target materials, and phase-change memory materials having corresponding compositional distribution ratios may be obtained.

[0076] In some embodiments, first, a S b Te c D d The alloy can be prepared (e.g., smelted). Then, sputtering is performed on Ti a S b Te c D d The process is carried out using an alloy to prepare a phase-change memory material on a substrate.

[0077] The following describes the preparation process for phase-change memory materials in a specific embodiment.

[0078] Embodiment 1 The elemental composition is Ti8Sb 36.8 Te 55.2 A phase-change memory material is prepared. The details are as follows.

[0079] Ti single-element target material and SbTe alloy target material, each having an atomic percentage purity of 99.99% or higher, are placed at different target material positions within the sputtering cavity. The ratio of Sb atoms to Te atoms in the SbTe alloy is 2:3. The substrate is placed on a sample stage within the sputtering cavity. Sputtering power is applied to the Ti single-element target material and the SbTe alloy target material to generate a sputtering glow. The sputtering power applied to the Ti single-element target material is 10W, and the sputtering power applied to the SbTe alloy target material is 7W. The argon flow rate during the sputtering process is 35 sccm. In this way, the elemental composition is Ti8Sb 36.8 Te 55.2 A phase-change memory material can be prepared on a substrate.

[0080] Embodiment 2 Elemental composition is Ti 22 S 31.2 Te 46.8 A phase-change memory material is prepared. The details are as follows.

[0081] Ti single-element target material and SbTe alloy target material, each having an atomic percentage purity of 99.99% or higher, are placed at different target material positions within the sputtering cavity. The ratio of Sb atoms to Te atoms in the SbTe alloy is 2:3. The substrate is placed on a sample stage within the sputtering cavity. Sputtering power is applied to the Ti single-element target material and the SbTe alloy target material to generate a sputtering glow. The sputtering power applied to the Ti single-element target material is 30W, and the sputtering power applied to the SbTe alloy target material is 7W. The argon flow rate is 35 sccm during the sputtering process. In this way, the elemental composition is Ti 22 S 31.2 Te 46.8A phase-change memory material can be prepared on a substrate.

[0082] Embodiment 3 Elemental composition is Ti 28 S 28.8 Te 43.2 A phase-change memory material is prepared. The details are as follows.

[0083] Ti single-element target material and SbTe alloy target material, each having an atomic percentage purity of 99.99% or higher, are placed at different target material positions within the sputtering cavity. The ratio of Sb atoms to Te atoms in the SbTe alloy is 2:3. The substrate is placed on a sample stage within the sputtering cavity. Sputtering power is applied to the Ti single-element target material and the SbTe alloy target material to generate a sputtering glow. The sputtering power applied to the Ti single-element target material is 40W, and the sputtering power applied to the SbTe alloy target material is 7W. The argon flow rate during the sputtering process is 35 sccm. In this way, the elemental composition is Ti 22 S 31.2 Te 46.8 The phase-change memory material can be prepared on a substrate.

[0084] Embodiment 4 The elemental composition is Ti3Sb 38.8 Te 58.2 A phase-change memory material is prepared. For details of the preparation process, please refer to the description in Embodiment 1. Further details will not be described here.

[0085] Embodiment 5 Elemental composition is Ti 45 S 18.8 Te 36.2 A phase-change memory material is prepared. For details of the preparation process, please refer to the description in Embodiment 1. Further details will not be described here.

[0086] Embodiment 6 Elemental composition is Ti 40 S 23.8 Te 36.2 A phase-change memory material is prepared. For details of the preparation process, please refer to the description in Embodiment 1. Further details will not be described here.

[0087] Embodiment 7 Elemental composition is Ti 21 S 29.6 Te 44.4 A phase-change memory material with C5 elemental composition is prepared. 21 S 29.6 Te 44.4 The alloy, which is C5, is refined. 21 S 29.6 Te 44.4 The C5 alloy is placed at the target material position in the sputtering cavity. The substrate is placed on the sample stage in the sputtering cavity. The sputtering power is Ti 21 S 29.6 Te 44.4 It is applied to a C5 alloy to generate a sputtering glow. Therefore, Ti 21 S 29.6 Te 44.4 C5 alloy is sputtered onto the substrate, Ti 21 S 29.6 Te 44.4 Prepare a phase-change memory material for C5.

[0088] Embodiment 8 Elemental composition is Ti 25.7 S 27.7 Te 41.6 A phase-change memory material with C5 elemental composition is prepared. 25.7 S 27.7 Te 41.6 The alloy, which is C5, is refined. 25.7 S 27.7 Te 41.6 The C5 alloy is placed at the target material position in the sputtering cavity. The substrate is placed on the sample stage in the sputtering cavity. The sputtering power is Ti 25.7 S 27.7 Te41.6 Applied to the C5 alloy to generate a sputtering glow. Thus, Ti 25.7 Sb 27.7 Te 41.6 The C5 alloy is sputtered onto the substrate, and Ti 25.7 Sb 27.7 Te 41.6 A phase change memory material of C5 is prepared.

[0089] Embodiment 9 The element composition is Ti 17 Sb 31.2 Te 46.8 A phase change memory material with an element composition of Ti 17 Sb 31.2 Te 46.8 O5 is refined. Ti 17 Sb 31.2 Te 46.8 The O5 alloy is placed at the target material position in the sputtering cavity. The substrate is placed on the sample stage in the sputtering cavity. Sputtering power is applied to the Ti 17 Sb 31.2 Te 46.8 O5 alloy to generate a sputtering glow. Thus, Ti 17 Sb 31.2 Te 46.8 The O5 alloy is sputtered onto the substrate, and Ti 17 Sb 31.2 Te 46.8 A phase change memory material of O5 is prepared.

[0090] Embodiment 10 The element composition is Ti 14 Sb 31.2 Te 46.8 A phase change memory material with an element composition of Ti 14 Sb 31.2 Te[[ID=�2]] 46.8 Si8 is refined. Ti 14 Sb 31.2 Te 46.8 The Si8 alloy is placed at the target material position in the sputtering cavity. The substrate is placed on the sample stage in the sputtering cavity. Sputtering power is applied to the Ti14 S 31.2 Te 46.8 It is applied to a Si8 alloy to generate sputtering glow. Therefore, Ti 14 S 31.2 Te 46.8 The Si8 alloy is sputtered onto the substrate, Ti 14 S 31.2 Te 46.8 A phase-change memory material of Si8 is prepared.

[0091] The aforementioned example illustrates the preparation solution for the phase-change memory material provided in the embodiments of this application. Below, data related to the fatigue life and thermal stability of the phase-change memory material provided in the embodiments of this application will be described.

[0092] The phase-change memory material prepared in Embodiment 1 and the phase-change memory material prepared in Embodiment 2 were observed separately using a transmission electron microscope, and the results are shown in Figures 5A and 5B, respectively. When the atomic percentage of Ti in the phase-change memory material is 8%, it can be understood that some grain sizes are tens of nanometers. When the atomic percentage of Ti in the phase-change memory material is increased to 28%, the grain size can be reduced to less than 10 nm. This indicates that Ti can reduce the grain size in the phase-change memory material, resulting in a more uniform grain size distribution (this can be understood as the smaller the grain size, the smaller the grain size distribution range, indicating a more uniform grain size distribution). Therefore, the short fatigue life of the phase-change memory material caused by non-uniform grain size can be reduced or prevented. That is, when the atomic percentage of Ti in the phase-change memory material is high (e.g., 28%), the fatigue life of the phase-change memory material is high.

[0093] The resistance of the phase change material prepared in Embodiment 1 is measured at different temperatures. The results are shown by curves 601a and 601b in Figure 6. Curve 601a is the temperature rise curve, and curve 601b is the temperature decrease curve.

[0094] The resistance of the phase change material prepared in Embodiment 2 is measured at different temperatures. The results are shown by curves 602a and 602b in Figure 6. Curve 602a is the temperature rise curve, and curve 602b is the temperature decrease curve.

[0095] The resistance of the phase change material prepared in Embodiment 3 is measured at different temperatures. The results are shown by curves 603a and 603b in Figure 6. Curve 603a is the temperature rise curve, and curve 603b is the temperature decrease curve.

[0096] The temperature decrease curve shows the change in resistance during the temperature decrease process. The temperature increase curve shows the change in resistance during the temperature increase process. As shown in Figure 6, in the temperature increase process of the phase change memory material prepared in the embodiments of this application, the decrease in resistance indicates that the phase change memory material is crystallizing. In the temperature decrease process of the phase change memory material, the resistance of the phase change memory material, which remains essentially unchanged, indicates that crystallization is complete.

[0097] In addition, it can be seen from Figure 6 that as the Ti concentration increases, the initial resistance of the phase-change memory material decreases and the crystallization temperature increases. The horizontal coordinate of the position where the resistance decreases most rapidly is the crystallization temperature. Specifically, the crystallization temperature of the phase-change material prepared in Embodiment 1 is approximately 210°C, the crystallization temperature of the phase-change material prepared in Embodiment 2 is approximately 240°C, and the crystallization temperature of the phase-change material prepared in Embodiment 3 is approximately 260°C. In addition, the initial resistance is the resistance corresponding to the minimum temperature on each curve in Figure 6.

[0098] In the embodiments of this application, Ti is added to the phase-change memory material, and as a result, the crystallization temperature of the phase-change memory material increases, as can be seen from Figure 6. That is, the thermal stability of the phase-change memory material is improved.

[0099] The elemental composition, preparation method, and performance of the phase-change memory material provided in the embodiments of this application have been described above. Below, a phase-change memory chip formed by the phase-change memory material provided in the embodiments of this application will be described.

[0100] The phase-change memory chip provided in this embodiment of the present application may include a phase-change memory cell memory array and peripheral circuits. For further details, please refer to the above description of the embodiment shown in Figure 2. Further details will not be described again here.

[0101] A phase-change memory cell array may include multiple phase-change memory cells. In some embodiments, the structure of the phase-change memory cell may be carried out in relation to the structure shown in Figure 1A. In some embodiments, the structure of the phase-change memory cell may be carried out in relation to the structure shown in Figure 1B. Please refer again to Figure 1A or Figure 1B. The phase-change layer 113 in the phase-change memory cell 110 may be the phase-change memory material provided in embodiments of this application. The electrode material may be a metallic material, a non-metallic material, a metal nitride, etc. More specifically, the material of electrode 1 may be one or at least two combinations of tungsten (W), carbon (C), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc. The electrode material is not specifically limited in this embodiment of this application.

[0102] In embodiment a, the phase-change memory cell 110 may further include a buffer layer 114. The buffer layer 114 is in contact with the phase-change layer 113 and is also provided between electrodes 111 and 112. In examples, the material of the buffer layer 114 may be a nonmetal such as carbon (C). 。In practice, the material of buffer layer 114 may be a metal such as W, Ta, or Ti. In practice, the material of buffer layer 114 may be a metal nitride such as TiN or TaN. In practice, the material of buffer layer 114 may be a metal telluride such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn.

[0103] A buffer layer 114 in contact with the phase change layer 113 is introduced into the phase change memory cell 110, and as a result, the performance of the phase change layer 113 can be further improved. Specifically, when the material of the buffer layer 114 is a nonmetal such as carbon (C), the buffer layer 114 can improve the thermal insulation effect of the phase change layer 113, reduce the operating power consumption of the phase change memory cell, prevent elemental diffusion in the phase change layer 113, and improve the adhesion effect between the phase change layer and the electrodes. When the material of the buffer layer 114 is a metallic telluride such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn, the buffer layer 114 can be used as a crystallization template for the phase change memory material, and as a result, the rate of conversion of the phase change memory material from an amorphous state to a crystalline state can be accelerated. Therefore, the operating delay of the phase-change memory operating cell 110 can be reduced, the heating efficiency of the phase-change memory cell 110 can be improved, and the operating power consumption of the phase-change memory cell 110 can be reduced. When the material of the buffer layer 114 is a metal such as W or Ta, the buffer layer 114 can prevent elemental diffusion in the phase-change memory material and can also improve the adhesion effect between the phase-change layer and the electrode. When the material of the buffer layer 114 is a metal nitride, the buffer layer 114 can improve the adhesion effect between the phase-change layer and the electrode, improve the heating efficiency of the phase-change memory material, reduce resistance drift, repair voids at the interface of the phase-change memory material, and improve the adhesion effect between the phase-change layer and the electrode.

[0104] The materials and functions of the buffer layer 114 were described above. The positional relationship between the buffer layer 114 and the phase change layer 113 will be explained below using an example.

[0105] In an example of Embodiment a, referring to Figure 7A, the buffer layer 114 is in contact with the phase change layer 113, and the buffer layer 114 is provided between the phase change layer 113 and the electrode 111.

[0106] In another example of Embodiment a, referring to Figure 7B, the buffer layer 114 is in contact with the phase change layer 113, and the buffer layer 114 is provided between the phase change layer 113 and the electrode 112.

[0107] In another example of Embodiment a, referring to Figure 7C, the phase-change memory cell 110 includes two buffer layers 114, each buffer layer 114 in contact with the phase-change layer 113. One buffer layer 114 is located between the phase-change layer 113 and the electrode 111, and the other buffer layer 114 is located between the phase-change layer 113 and the electrode 112. The materials of the two buffer layers 114 may be the same or different. For example, the materials of the two buffer layers 114 may both be nonmetals such as carbon (C), metals such as W or Ta, metal nitrides such as TiN or TaN, or metallic tellurides such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn. For example, one of the two buffer layers 114 may be made of a nonmetal such as carbon (C), and the other buffer layer 114 may be made of a nonmetal such as carbon (C), or one buffer layer 114 may be made of a metal nitride such as TiN or TaN, and the other buffer layer 114 may be made of a metallic telluride such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn. Details are not listed here one by one. The materials of the two buffer layers 114 are different, and as a result, the phase-change memory cell 110 may have advantages corresponding to the two materials.

[0108] In another example of Embodiment a, referring to Figure 7D, the phase change layer 113 has grooves, and the buffer layer 114 is provided within the grooves of the phase change layer 113 and in contact with the phase change layer 113. That is, the phase change layer 113 surrounds the buffer layer 114.

[0109] In another example of Embodiment a, referring to Figure 7E, the buffer layer 114 has grooves, and the phase change layer 113 is provided within the grooves of the buffer layer 114 and in contact with the buffer layer 114. That is, the buffer layer 114 surrounds the phase change layer 113.

[0110] In the preceding section, the positional relationship between the phase change layer 113 and the buffer layer 114 was described using the structures shown in Figures 7A to 7E as examples; however, the examples are not exhaustive. In other embodiments, the phase change layer 113 and the buffer layer 114 may have different positional relationships. Details of these are not listed here one by one.

[0111] In embodiment b, the phase-change memory cell 110 may further include at least one chalcogenide layer 115 and at least one phase-change layer 113. The at least one phase-change layer 113 and the at least one chalcogenide layer 115 are alternately stacked and provided together between electrodes 111 and 112.

[0112] In an example of embodiment b, the material of the chalcogenide layer 115 is a metal sulfide, for example, GeS x It is possible.

[0113] In another example of Embodiment b, the material of the chalcogenide layer 115 is a metallic Te compound, for example, TiTe2, Hf x Te y , or Zr x Te y It is possible.

[0114] In another example of Embodiment b, the material of the chalcogenide layer 115 is, as an alternative, a phase-change memory material, for example, Sb x Te y , Ge x S y Te z , Ge x Te y , Bi x Te y , and In x Te yIt can be one or at least two combinations of these. In the chemical formulas above, the subscripts x, y, and z represent the proportions of the corresponding atoms, respectively.

[0115] The phase change layers 113 and chalcogenide layers 115 are stacked alternately. It is not difficult to understand that there is an interface between one phase change layer 113 and one adjacent chalcogenide layer 115. In this way, the alternating stacking of the phase change layers 113 and chalcogenide layers 115 can introduce more interfaces to the phase change memory material, and these interfaces can reduce thermal conductivity. Therefore, the operating power consumption of the phase change memory cell 110 is reduced, and the fatigue life of the phase change memory cell 110 is improved. In addition, chalcogenides have good thermal insulation properties. This can reduce the operating power consumption of the phase change memory cell 110 and improve the fatigue life of the phase change memory cell 110. In addition, when the material of the chalcogenide layer 115 is TiTe2 or the like, the lattice coefficient of the chalcogenide layer 115 is smaller than that of the phase-change memory material provided in the embodiments of this application. As a result, elemental diffusion in the phase-change layer 113 can be prevented, improving the fatigue life of the phase-change layer 113, or in other words, improving the fatigue life of the phase-change memory cell 110.

[0116] In another example of embodiment b, referring to Figure 8A, at least one chalcogenide layer 115 and at least one phase change layer 113 are alternately stacked or periodically arranged in the direction from electrode 111 to electrode 112, so that n periodic repeating stacks can be formed, starting from the phase change layer 113 and ending at the chalcogenide layer 115, where n is an integer of 1 or more.

[0117] In another example of embodiment b, referring to Figure 8B, at least one chalcogenide layer 115 and at least one phase change layer 113 are alternately stacked or periodically arranged in the direction from electrode 111 to electrode 112, so that n periodic repeating stacks can be formed, starting with the chalcogenide layer 115 and ending with the phase change layer 113, where n is an integer of 1 or more. 。

[0118] In another exemplary example of Embodiment b, referring to Figure 8C, at least one chalcogenide layer 115 and at least one phase change layer 113 are alternately stacked or periodically arranged in the direction from electrode 111 to electrode 112. This can start with phase change layer 113 and end with phase change layer 113. Between the phase change layer 113 at the starting position and the phase change layer 113 at the ending position, there are n periodically and repeatedly stacked chalcogenide layers 115 and phase change layers 113. In addition, in the phase change memory cell 110, at least one chalcogenide layer 115 lies between two phase change layers 113, and at least one phase change layer lies between two chalcogenide layers 115, where n is an integer greater than or equal to 1. 。

[0119] In another example of Embodiment b, referring to Figure 8D, at least one chalcogenide layer 115 and at least one phase change layer 113 are alternately stacked or periodically arranged in the direction from electrode 111 to electrode 112. This can start with chalcogenide layer 115 and end with chalcogenide layer 115. Between the chalcogenide layer 115 at the starting position and the chalcogenide layer 115 at the ending position, there are n periodically and repeatedly stacked phase change layers 113 and chalcogenide layers 115. In addition, a phase change memory cell 110 In this configuration, at least one chalcogenide layer 115 lies between two phase-change layers 113, and at least one phase-change layer lies between two chalcogenide layers 115. n is an integer greater than or equal to 1. 。

[0120] In the preceding section, the positional relationship between the phase change layer 113 and the chalcogenide 115 was described using the structures shown in Figures 8A to 8D as examples; however, the examples are not exhaustive. In other embodiments, the phase change layer 113 and the chalcogenide layer 115 may have alternative positional relationships. Details of these are not listed here one by one.

[0121] Refer to Figure 9. One embodiment of the present application provides a storage device 900 including a phase-change memory chip 910 and a controller 920. The phase-change memory chip 910 may be configured to store data, and the controller 920 may be configured to write data to or read data from the phase-change memory chip 910. The phase-change memory chip 910 may include a plurality of phase-change memory cells 110, and the plurality of phase-change memory cells 110 form a memory cell array within the storage device 900.

[0122] In some embodiments, the phase-change memory chip 910 may be implemented with reference to the above-described embodiment shown in Figure 2. The controller 920 may be a data processing device and is configured to control the peripheral circuits of the phase-change memory chip 910 to write data to or read data from the phase-change memory chip 910.

[0123] Refer to Figure 10. One embodiment of the present application provides an electronic device 1000, which may include a processor 1010 and a storage device 900. The storage device 900 may be configured to store data, for example, applications and configuration files for the electronic device 1000. The storage device 900 may provide a data storage space for the processor 1010, which in turn can write data to the data storage space. The data stored in the storage device 900 may be read or retrieved by the processor 1010. The processor 1010 is configured to write data to or read data from the storage device 900. Specifically, the processor 1010 may write data to or read data from the phase-change memory chip 910 via a controller 920. For example, the processor 1010 may retrieve data in the storage device 900 to implement the corresponding function of the electronic device 1000.

[0124] In some embodiments, the storage device 900 may be used as memory for the electronic device 1000. In some embodiments, the storage device 900 may be used as external memory for the electronic device 1000. In some embodiments, the processor 1010 may be a neural network processing unit (NPU). In some embodiments, alternatively, the storage device 900 may be another form of device that has data storage capabilities and is located within the electronic device 1000. The implementation of the storage device 900 is not specifically limited in this application.

[0125] In some embodiments, the processor 1010 may be a central processing unit (CPU). In some embodiments, the processor 1010 may be a graphics processing unit (GPU). In some embodiments, the processor 1010 may be an application-specific integrated circuit (ASIC). In some embodiments, the processor 1010 may be a neural-network processing unit (NPU). In some embodiments, alternatively, the processor 1010 may have data processing capabilities and electronic devices 1000 It may be another form of device located within. The implementation of processor 1010 is not specifically limited in this application.

[0126] In some embodiments, the electronic device 1000 may be a server, a mobile terminal (e.g., a mobile phone, tablet computer, or notebook computer), or an in-vehicle terminal. The implementation of the electronic device in which the processor 1010 and the storage device 900 are provided is not specifically limited in this embodiment of the present application.

[0127] It should be understood that the embodiments described above are merely for illustrating the technical solutions of this application and are not intended to limit this application. Although this application is described in detail with reference to the embodiments described above, modifications to the technical solutions recorded in the embodiments above, or equivalent substitutions of some of their technical features, should still be made, and it should be understood by those skilled in the art that such modifications or substitutions will not deviate the essence of the corresponding technical solutions from the scope of the technical solutions in the embodiments of this application.

[0128] The foregoing description is merely a specific implementation of this application and is not intended to limit the scope of protection of this application. Any modifications or substitutions readily conceivable by a person skilled in the art within the technical scope disclosed in this invention should fall within the scope of protection of this application. Accordingly, the scope of protection of this application should be limited to the scope of protection of the claims.

Claims

1. A phase-change memory material, wherein the phase-change memory material includes a material represented by formula (1), Today a Sb b Te c D d (1) A phase-change memory material in which a represents the atomic percentage of Ti, b represents the atomic percentage of Sb, c represents the atomic percentage of Te, d represents the atomic percentage of element D, a + b + c + d = 1, 20% ≤ a ≤ 35%, and 0.5 ≤ (b:c) ≤ 3, D is a doping element, and 0 ≤ d ≤ 15%.

2. The ratio of the atomic percentage b of Sb to the atomic percentage c of Te is 2:

3. The phase change memory material according to claim 1.

3. The atomic percentage d of the doping element D is 3% ≤ d ≤ 8%. The phase change memory material according to claim 1.

4. The doping element comprises one or at least two combinations of a first nonmetallic element, a first metallic element, and a telluride of the first metallic element, wherein the first nonmetallic element is one or at least two combinations of C, O, N, and Si, and the first metallic element is one or at least two combinations of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn. The phase change memory material according to claim 1.

5. A method for preparing a phase-change memory material, wherein the method is used to prepare the phase-change memory material described in claim 1, and the method is The process includes the step of preparing the phase-change memory material by a first deposition method according to the elemental ratios shown by formula (1), wherein the first deposition method is one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). Today a Sb b Te c D d (1) Preparation method, where a represents the atomic percentage of Ti, b represents the atomic percentage of Sb, c represents the atomic percentage of Te, d represents the atomic percentage of element D, a + b + c + d = 1, 20% ≤ a ≤ 35%, and 0.5 ≤ (b:c) ≤ 3, D is the doping element, and 0 ≤ d ≤ 15%.

6. A phase-change memory chip comprising a plurality of memory cells, wherein the plurality of memory cells form a memory cell array, and each memory cell comprises a phase-change layer, a first electrode provided on one side of the phase-change layer, and a second electrode provided on the other side of the phase-change layer, and the phase-change layer is made of a phase-change memory material according to any one of claims 1 to 4. Phase-change memory chip.

7. A phase-change memory chip comprising a plurality of memory cells, wherein the plurality of memory cells form a memory cell array, and each memory cell comprises a phase-change layer, a first electrode provided on one side of the phase-change layer, and a second electrode provided on the other side of the phase-change layer, and the phase-change layer is made of a phase-change memory material. The phase-change memory material includes the material represented by formula (1), Ti a Sb b Tec D d (1) Here, a represents the atomic percentage of Ti, b represents the atomic percentage of Sb, c represents the atomic percentage of Te, and d represents the atomic percentage of element D. a + b + c + d = 1, 3% ≤ a ≤ 45%, and 0.5 ≤ (b:c) ≤ 3. D is the doping element, and 0 ≤ d ≤ 15%. Each memory cell further comprises at least one phase change layer and at least one chalcogenide layer, both of which are provided between the first electrode and the second electrode, and the at least one phase change layer and the at least one chalcogenide layer are stacked alternately, and the lattice coefficient of the chalcogenide layer is smaller than the lattice coefficient of SbTe. Phase-change memory chip.

8. Each memory cell further comprises a buffer layer in contact with the phase change layer, the buffer layer being made of one of carbon, a third metal, a nitride of the third metal, and a telluride of a fourth metal, the third metal being one or a combination of at least two of W, Ta, and Ti, and the fourth metal being one or a combination of at least two of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, and Sn. The phase-change memory chip according to claim 6.

9. A storage device comprising a controller and a phase-change memory chip as described in claim 6, wherein the phase-change memory chip is configured to store data, and the controller is configured to write data to the phase-change memory chip or read data from the phase-change memory chip.

10. An electronic device comprising a processor and a storage device according to claim 9, wherein the storage device is configured to store data, and the processor is configured to write data to the storage device or read data from the storage device.

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