Memory system, method for operating a memory system, and computer-readable storage medium

Abstract

This application discloses a memory system, a method for operating a memory system, and a computer-readable storage medium related to the field of storage technology. The memory system includes a memory and a memory controller. The memory includes a memory array coupled to n word lines, the n word lines being arranged consecutively by physical word line identifiers, where n≧2. The memory controller is configured to map the n physical word line identifiers to n virtual word line identifiers, where the physical word line identifiers corresponding to m adjacent virtual word line identifiers are spaced apart from each other, where 2≦m≦n, and to generate check data based on data corresponding to the m adjacent virtual word line identifiers. The check data is generated from data corresponding to multiple adjacent virtual word line identifiers. That is, the check data is generated from data corresponding to multiple non-adjacent physical word line identifiers, which reduces the impact on the check data caused by mutual effects between adjacent physical word lines, increases the success rate of data recovery, and improves the reliability of data storage and data reading.

Description

Technical Field

[0001] This application relates to the field of memory technology, and more particularly, to a memory system, a method of operating a memory system, and a computer-readable storage medium.

Background Art

[0002] Memory cells in three-dimensional (3D) memory are coupled to word lines, and data is written into the memory cells through a program voltage applied by the word lines.

[0003] When writing data into 3D memory, check data may be generated according to the data to be written in order to avoid errors in subsequent data reading. In this way, when data is read from the memory, the read data is checked according to the check data, and if the check fails, the correct data can be recovered according to the check data. Ensuring successful data recovery when the check fails has become a current research hot spot.

Summary of the Invention

Means for Solving the Problems

[0004] This application provides a memory system, a method of operating a memory system, and a computer-readable storage medium that can improve programming efficiency. The technical solution is described as follows.

[0005] In one aspect, a memory system is provided, the memory system includes one or more memories and a memory controller coupled to the memory and configured to control the memory, the memory includes a memory array, the memory array is coupled to n word lines, and the n word lines are continuously arranged by physical word line identifiers, where n≧2, the memory controller is configured to obtain a plurality of data to be written into the memory array, The memory controller is configured to map n physical word line identifiers to n virtual word line identifiers, with each physical word line identifier corresponding to m adjacent virtual word line identifiers spaced apart from each other, where 2 ≤ m ≤ n. The memory controller is configured to generate check data based on data corresponding to m adjacent virtual wordline identifiers, and the check data is configured to check and restore data corresponding to m adjacent virtual wordline identifiers.

[0006] In one optional implementation, the memory controller is configured to obtain a pre-configured mapping relationship table, which includes mapping correspondences between physical wordline identifiers and virtual wordline identifiers, and to obtain n virtual wordline identifiers corresponding to n physical wordline identifiers by matching n physical wordline identifiers with the mapping relationship table.

[0007] In one optional implementation, the memory controller is configured to retrieve a pre-configured mapping relationship table from static random-access memory.

[0008] In one arbitrary implementation, the reference number of a physical wordline identifier is distributed among the physical wordline identifiers that correspond to m adjacent virtual wordline identifiers.

[0009] In one optional implementation, the memory controller is configured to obtain a pre-configured algorithm, which maps physical wordline identifiers to virtual wordline identifiers and is configured to substitute n physical wordline identifiers into the pre-configured algorithm in order to obtain n virtual wordline identifiers corresponding to n physical wordline identifiers.

[0010] In one optional implementation, the memory controller is configured to process data corresponding to m adjacent virtual wordline identifiers through a first operator in order to obtain check data, and when there is a data read failure in the data corresponding to m adjacent virtual wordline identifiers, the check data is configured to check and restore the data that failed to be read through a second operator, the first and second operators being operators whose operational logic is opposite to that of the first operator.

[0011] In one optional implementation, the memory controller is configured to send a first read command to memory, wherein the first read command includes a first physical word line identifier corresponding to the first data to be read, and to receive the data read result returned by the memory. The memory controller is configured to determine a first virtual wordline identifier corresponding to a first physical wordline identifier and to obtain target check data corresponding to a first virtual wordline identifier in order to recover the first data that failed to be read, when the data read result indicates that reading the first data corresponding to a first physical wordline identifier has failed.

[0012] In one optional implementation, the memory controller is configured to acquire target check data corresponding to a first virtual word line identifier, acquire a second virtual word line identifier that is consistent with the first virtual word line identifier for generating the target check data, and determine a second physical word line identifier corresponding to the second virtual word line identifier. The memory controller is configured to send a second read command to memory, the second read command being configured to instruct memory to read data stored in a memory cell row associated with a word line corresponding to the second physical word line identifier, the second read command being configured to include a second physical word line identifier, the second data being returned by memory and corresponding to the second physical word line identifier, and the first data that failed to be read being restored based on target check data and the second data.

[0013] In one optional implementation, when the memory controller reads first data corresponding to a first physical word line identifier, it determines a first virtual word line identifier corresponding to the first physical word line identifier, obtains target check data corresponding to the first virtual word line identifier, obtains a second virtual word line identifier that is consistent with the first virtual word line identifier for generating the target check data, and determines a second physical word line identifier corresponding to the second virtual word line identifier. The system is configured to send a read command to memory, the read command being configured to instruct the system to read data stored in a memory cell row coupled to a word line corresponding to a first physical word line identifier and a second physical word line identifier, The memory controller is configured to receive the data read result returned by the memory, and, when the data read result indicates that the reading of the first data failed, to use target check data and second data corresponding to a second physical word line identifier to recover the first data that failed to be read.

[0014] In another embodiment, a method for operating a memory system is provided, the memory system comprising a memory having a memory array, the memory array being connected to n word lines, the n word lines being arranged contiguously by a physical word line identifier, where n ≥ 2.

[0015] The method is, Steps include obtaining multiple data to be written into the memory array, A step of writing check data into memory, wherein the check data is data generated based on data corresponding to spaced-apart physical wordline identifiers, and is configured to check and restore the data. Includes.

[0016] In one optional implementation, the method is to write the check data into memory before... A step of mapping n physical wordline identifiers to n virtual wordline identifiers, wherein the physical wordline identifiers corresponding to m adjacent virtual wordline identifiers are spaced apart from each other, where 2 ≤ m ≤ n. A step of generating check data based on data corresponding to m adjacent virtual wordline identifiers, wherein the check data is configured to check and restore the data corresponding to m adjacent virtual wordline identifiers. It also includes.

[0017] In one arbitrary implementation, the step of mapping n physical wordline identifiers to n virtual wordline identifiers is: A step of obtaining a pre-configured mapping relationship table, wherein the mapping relationship table includes mapping correspondences between physical wordline identifiers and virtual wordline identifiers. The steps include obtaining n virtual wordline identifiers corresponding to n physical wordline identifiers by matching n physical wordline identifiers with a mapping relationship table, and including

[0018] In an optional implementation form, the step of obtaining a preset mapping relationship table includes the step of obtaining a preset mapping relationship table from a static random access memory.

[0019] In an optional implementation form, the reference number of a physical word line identifier is distributed among the physical word line identifiers corresponding to m adjacent virtual word line identifiers respectively.

[0020] In an optional implementation form, the step of mapping n physical word line identifiers to n virtual word line identifiers is the step of obtaining a preset algorithm configured such that the preset algorithm maps a physical word line identifier to a virtual word line identifier, and the step of substituting n physical word line identifiers into the preset algorithm to obtain n virtual word line identifiers corresponding to the n physical word line identifiers including

[0021] In an optional implementation form, the step of generating check data based on data corresponding to m adjacent virtual word line identifiers includes the step of processing data corresponding to m adjacent virtual word line identifiers through a first operator to obtain check data. When there is a data reading failure in the data corresponding to m adjacent virtual word line identifiers, the check data is configured to check and recover the data that failed to be read through a second operator, and the first operator and the second operator are operators with opposite operation logics.

[0022] In an optional implementation form, after writing the check data into the memory, the method Sending a first read command to a memory, wherein the first read command includes a first physical word line identifier corresponding to first data to be read; Receiving a data read result returned by the memory; Determining a first virtual word line identifier corresponding to the first physical word line identifier when the data read result indicates that reading of the first data corresponding to the first physical word line identifier fails; Obtaining target check data corresponding to the first virtual word line identifier for restoring the first data that failed to be read; Further comprising.

[0023] In an optional implementation form, the step of obtaining target check data corresponding to the first virtual word line identifier for restoring the first data that failed to be read includes: Obtaining target check data corresponding to the first virtual word line identifier, obtaining a second virtual word line identifier that is aligned with the first virtual word line identifier for generating the target check data; Determining a second physical word line identifier corresponding to the second virtual word line identifier; Sending a second read command to the memory, wherein the second read command includes the second physical word line identifier and is configured to command the memory to read data stored in a memory cell row coupled to the word line corresponding to the second physical word line identifier; Receiving second data returned by the memory and corresponding to the second physical word line identifier, and restoring the first data that failed to be read based on the target check data and the second data; Including.

[0024] In one optional implementation, the method generates check data based on the data corresponding to m adjacent virtual wordline identifiers, A step of sending a first read instruction to memory, wherein the first read instruction includes a first physical word line identifier corresponding to first data to be read; The steps include determining a first virtual wordline identifier corresponding to a first physical wordline identifier, and obtaining target check data corresponding to the first virtual wordline identifier. The steps include obtaining a second virtual wordline identifier that is consistent with a first virtual wordline identifier for generating target check data, and determining a second physical wordline identifier corresponding to the second virtual wordline identifier. A step of sending a second read instruction to memory, wherein the second read instruction is configured to instruct the memory to read data stored in a memory cell row associated with a word line corresponding to the second physical word line identifier, The steps include receiving the data read result returned by memory, When the data read result indicates that reading the first data failed, the steps include using target check data and second data corresponding to the second physical wordline identifier to recover the first data that failed to be read. It also includes.

[0025] In another embodiment, a computer-readable storage medium is provided, and instructions are stored in the computer-readable storage medium. When the instructions are executed on the memory controller, they perform a method of operating the memory system according to one of the implementation forms described above.

[0026] The technical solutions provided by this application may include the following beneficial effects:

[0027] By setting up a mapping relationship between physical and virtual wordline identifiers such that the physical wordline identifiers corresponding to adjacent virtual wordline identifiers are separated, i.e., not adjacent, a virtual wordline identifier corresponding to a physical wordline identifier is generated. Check data is generated using data corresponding to multiple adjacent virtual wordline identifiers. In other words, the check data is generated using data corresponding to multiple non-adjacent physical wordline identifiers, thereby reducing the impact on the check data due to the interaction between adjacent physical wordlines, increasing the success rate of data recovery, and improving the reliability of data storage and data retrieval.

[0028] To more clearly illustrate the technical solutions in the implementations of this application, the drawings used in the description of the implementations are briefly introduced below. Clearly, the drawings in the following description represent only some of the implementations of this application. Based on these drawings without any creative effort, other drawings can be obtained for those skilled in the art. [Brief explanation of the drawing]

[0029] [Figure 1] This is a schematic diagram of a memory system according to one implementation configuration of this application. [Figure 2] This is a schematic diagram of an integration scenario for a memory system according to the exemplary implementation of this application. [Figure 3] This is a schematic diagram of an integration scenario for a memory system according to another exemplary implementation of this application. [Figure 4] This is a schematic diagram of a memory according to one implementation configuration of this application. [Figure 5] This is a schematic cross-sectional view of a memory array including a memory string according to one implementation embodiment of this application. [Figure 6] This is a schematic diagram of a peripheral circuit according to one implementation configuration of this application. [Figure 7] This is a flowchart illustrating a method for operating a memory system according to an exemplary implementation of this application. [Figure 8]This is a schematic diagram of the mapping relationship table according to an exemplary implementation of this application. [Figure 9] This is a schematic diagram of the check data generation process according to an exemplary implementation of this application. [Figure 10] This is a flowchart of a method for operating a memory system according to another exemplary implementation of this application. [Figure 11] This is a schematic diagram of the data checking and recovery process according to an exemplary implementation of this application. [Figure 12] This is a schematic diagram of the memory controller according to the exemplary implementation configuration of this application. [Modes for carrying out the invention]

[0030] The implementation of this application will be described in further detail below, along with the attached drawings.

[0031] The method for operating a memory system provided in the implementation of this application may be applied to a memory system. The memory system may include 3D memory such as 3D NAND flash.

[0032] Figure 1 is a schematic diagram of a memory system 10 according to one implementation embodiment of the present application. As shown in Figure 1, the memory system 10 includes one or more memories 100 and a memory controller 200 coupled to the memories 100 and configured to control the memories 100.

[0033] The memory controller 200 may be configured to control operations performed by the memory 100, such as read operations, erase operations, and program operations. The memory controller 200 may be further configured to manage various functions related to data stored in or to be stored in the memory 100, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some examples, the memory controller 200 may also be configured to process error correction codes (ECC) for data read from or written to the memory 100. The memory controller 200 may also perform any other preferred functions, such as formatting the memory 100.

[0034] The memory controller 200 can also communicate with external devices according to a specific communication protocol. For example, the memory controller 200 may communicate with external devices via at least one of various interface protocols. Interface protocols may include the Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Extended Small Drive Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, and others.

[0035] In some implementations, the memory controller 200 and one or more memories 100 may be integrated into various types of electronic devices. These electronic devices may be mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, pointing devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage within it. In this scenario, as shown in Figure 1, the memory system 10 further includes a host 300. The memory controller 200 is coupled to the host 300. The memory controller 200 may manage the data stored in the memories 100 and may communicate with the host 300 to perform the functions of the electronic devices as described above.

[0036] In some other implementations, the memory controller 200 and one or more memories 100 may be integrated into various types of storage devices.

[0037] As an example, a memory controller 200 and a single memory 100 may be integrated into a memory card 400 as shown in Figure 2. The memory card 400 may include Personal Computer Memory Card International Association (PCMCIA, PC) cards, CompactFlash® (CF) cards, SmartMedia (SM) cards, Memory Sticks, Multimedia Cards (MMC), Ultra-Miniature MMCs (RS-MMC), MicroMMCs, Secure Digital (SD) cards, Universal Flash Storage (UFS), and the like. As shown in Figure 2, the memory card 400 may further include a connector 410 for connecting the memory card 400 to a host.

[0038] As another example, as shown in Figure 3, the memory controller 200 and multiple memory units 100 may be integrated into a solid-state disk (SSD) 500. The solid-state disk 500 may further include a connector 510 for connecting the solid-state disk 500 to a host. The storage capacity and / or operating speed of the solid-state disk 500 is greater than that of the memory card 400.

[0039] In addition, the memory 100 in Figures 1 to 3 may be any memory involved in the implementation of this application. For example, it may be a 3D NAND (NAND gate) memory. The structure of memory 100 is described below.

[0040] Figure 4 is a schematic diagram of memory 100 according to one implementation embodiment of this application. As shown in Figure 4, memory 100 is A memory array 110 including multiple memory cell rows, Multiple word lines 120 are coupled to multiple memory cell rows, The system includes a peripheral circuit 130 coupled to a plurality of word lines 120 and configured to perform a verification or program operation on a selected memory cell row among a plurality of memory cell rows, wherein the selected memory cell row is a memory cell row coupled to a selected word line, and the peripheral circuit 130 is configured to perform a method of operating the memory provided in the implementation of this application to perform a verification or program operation.

[0041] The memory array 110 may be a NAND flash memory array. As shown in Figure 1, the NAND flash memory array includes a plurality of memory strings 111 arranged in an array on a substrate, each memory string 111 extending vertically above the substrate (not shown). In some implementations, each memory string 111 includes a plurality of memory cells 112 connected in series and stacked vertically.

[0042] As shown in Figure 4, each memory string 111 may further include a source select gate (SSG) 113 at the bottom and a drain select gate (DSG) 114 at the top. The source select gate is also called a lower select transistor, bottom select gate (BSG), or source select transistor, and the drain select gate is also called a top select transistor, top select gate (TSG), or drain select transistor. The source select gate 113 and drain select gate 114 may be configured to activate the selected memory string 111 during read and program operations.

[0043] In some implementations, the drain selection gate 114 of each memory string 111 is coupled to a corresponding bit line 115 from which data can be read and written via an output bus (not shown).

[0044] In some implementations, each memory string 111 is configured to have a selection or deselection voltage (e.g., 0V) applied to the corresponding drain selection gate 114 via one or more DSG lines 116 (e.g., higher than the threshold voltage of the transistor having the drain selection gate 114). As an addition or alternative, in some implementations, each memory string 111 is configured to be selected or deselected by having a selection or deselection voltage (e.g., 0V) applied to the corresponding source selection gate 113 via one or more SSG lines 117 (e.g., higher than the threshold voltage of the transistor having the source selection gate 113).

[0045] As shown in Figure 4, the memory string 111 can be organized into multiple blocks 140, and any block 140 in the multiple blocks 140 can have a source line (SL) 118. The sources of all memory strings 111 in block 140 are connected via a source line 118, also called a common source line or array common source (ACS).

[0046] Source line 118 may be used to ground the source of each memory cell in the memory string in block 140 in some operations later. In some examples, the source of each memory cell in the memory string in block 140 may also be connected to a high voltage via source line 118 in some other operations.

[0047] Each block 140 is a basic data unit for the erase operation. That is, all memory cells 112 on the same block 140 are erased simultaneously. To erase the memory cells 112 in a selected block, the source line connected to the selected block may be biased with an erase voltage (Vers), for example, a positive high voltage (20V or higher).

[0048] Please note that in other implementations, the erase operation may be performed at the 1 / 2 block level, the 1 / 4 block level, or at any suitable number or fraction of blocks.

[0049] As shown in Figure 4, memory cells 112 of the same layer in adjacent memory strings 111 within the same block 140 may be connected via a word line 120. The word line 120 is configured to select which layers of memory cells 112 in block 140 are operated on by read and program operations.

[0050] In some implementations, each word line 120 is coupled to a page to which a memory cell 112 belongs. A page is a basic unit of data used for program operation. The size of a page may relate to the number of memory strings 111 coupled by the word lines 120 within a single block 140. Each word line 120 may be coupled to the control gate (i.e., gate electrode) of each memory cell 112 in its corresponding page.

[0051] Note that while the same layer of memory cells within a single block 140 corresponds to the same word line, the same layer of memory cells can be divided into one or more pages. That is, one word line can be combined into one or more pages. For example, in SLC, one word line is combined into one page. In MLC, one word line is combined into two pages.

[0052] Figure 5 is a schematic cross-sectional view of a memory array 110 including a memory string 111 according to one implementation embodiment of the present application. As shown in Figure 5, the memory string 111 may extend vertically above the substrate 101 and through the stack layer 102. The substrate 101 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0053] The stack layer 102 may include alternating gate conductive layers 103 and intergate dielectric layers 104. The number of memory cells 112 in the memory array 110 may be determined by the number of pairs of gate conductive layers 103 and intergate dielectric layers 104 in the stack layer 102.

[0054] The gate conductive layer 103 may include, but is not limited to, a conductive material including tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some configurations, each gate conductive layer 103 includes a metal layer such as a tungsten layer. In other configurations, each gate conductive layer 103 includes a doped polysilicon layer. In addition, each gate conductive layer 103 may include a control gate surrounding the memory cell 112, which may extend laterally as a DSG line 116 at the top of the stack layer 102 and as an SSG line 117 at the bottom of the stack layer 102, or as a word line 120 extending laterally between the DSG line 116 and the SSG line 117.

[0055] As shown in Figure 5, the memory string 111 includes a channel structure 105 that extends vertically through the stack layer 102. In some implementations, the channel structure 105 includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). The semiconductor channel includes silicon, such as polysilicon. The memory film is a composite dielectric layer including a tunneling layer, a storage layer (also called a "charge trapping / storage layer"), and a blocking layer.

[0056] In some implementations, the channel structure 105 has a cylindrical shape (for example, a pillar shape). The semiconductor channel and the layers within the memory film are arranged radially in this order from the center of the cylinder toward the outer surface of the cylinder.

[0057] Although not shown in Figure 5, please understand that the memory array 110 may also include, but is not limited to, other additional components such as gate line slits / source contacts, local contacts, and interconnection layers.

[0058] Referring again to Figure 4, the peripheral circuit 130 may be coupled to the memory array 110 via the bit line 115, word line 120, source line 118, SSG line 117, and DSG line 116. The peripheral circuit 130 may include any preferred analog, digital, and mixed-signal circuit configurations for applying voltage and / or current signals to the memory cells 112 via the bit line 115, word line 120, source line 118, SSG line 117, and DSG line 116, and for sensing voltage and / or current signals from the memory cells 112, in order to facilitate the operation of the memory array 110.

[0059] The peripheral circuitry 130 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 shows several exemplary peripheral circuits 130, including a page buffer / sense amplifier 131, a column decoder / bit-line (BL) driver 132, a row decoder / word-line (WL) driver 133, a voltage generator 134, a control logic unit 135, a register 136, an interface 137, and a data bus 138. It should be understood that some examples may include additional peripheral circuits not shown in Figure 6.

[0060] The page buffer / sense amplifier 131 may be configured to read data from the memory array 110 and program (write) data to the memory array 110 according to control signals from the control logic unit 135. For example, the page buffer / sense amplifier 131 may store one page of program data (write data) to be programmed into one page 130 of the memory array 110. The page buffer / sense amplifier 131 may also perform verification operations to ensure that the data is correctly programmed into the memory cell 112 coupled to the selected word line 120. The page buffer / sense amplifier 131 may also sense a low-power signal from the bit line 115 representing the data bits stored in the memory cell 112 and amplify small voltage fluctuations during a read operation to a recognizable logic level.

[0061] The column decoder / bitline driver 132 may be controlled by a control logic unit 135 and configured to select one or more memory strings 111 by applying bitline voltages generated from a voltage generator 134.

[0062] The row decoder / wordline driver 133 is controlled by a control logic unit 135 and may be configured to select / deselect block 140 of the memory array 110 and the wordline 120 of block 140. The row decoder / wordline driver 133 may also be configured to drive the wordline 120 using the wordline voltage (VWL) generated from a voltage generator 134. In some implementations, the row decoder / wordline driver 133 can also select / deselect and drive SSG line 117 and DSG line 116. As described in detail below, the row decoder / wordline driver 133 is configured to perform an erase operation on the memory cell 112 coupled to the selected wordline 120.

[0063] The voltage generator 134 may be controlled by the control logic unit 135 and configured to generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 110.

[0064] The control logic unit 135 may be coupled to each of the peripheral circuits described above, or it may be configured to control the operation of each of the circuits.

[0065] Register 136 may be coupled to control logic unit 135, and the register may include a status register, a command register, and an address register for storing status information, command operation codes (opcodes), and command addresses for controlling the operation of each circuit in the peripheral circuit.

[0066] Interface (I / F) 137 may be coupled to the control logic unit 135 and may function as a control buffer for buffering control commands received from a host (not shown) and relaying them to the control logic unit 135, and for buffering status information received from the control logic unit 135 and relaying it to the host. Interface 137 may also be coupled to the column decoder / bit line driver 132 via the data bus 138 and may function as a data I / O interface and data buffer for buffering and relaying data to and from the memory array 110.

[0067] The above description of memory-related hardware implementations has similar beneficial effects to those of the following method implementations. Technical details not disclosed in the memory-related hardware implementations may be understood by referring to the description of the method implementations in this application.

[0068] Taking the memory system shown in Figure 1 as an example, the memory system includes one or more memories and a memory controller configured to be coupled to the memories and to control them. The memories include a memory array, the memory array is coupled to n word lines, the n word lines are arranged contiguously by a physical word line identifier, where n ≥ 2.

[0069] In this implementation, the memory controller is configured to retrieve multiple data to be written into the memory array, map n physical wordline identifiers to n virtual wordline identifiers, and space out the physical wordline identifiers corresponding to m adjacent virtual wordline identifiers, where 2 ≤ m ≤ n. The memory controller is configured to generate check data based on the data corresponding to the m adjacent virtual wordline identifiers, and the check data is configured to check and restore the data corresponding to the m adjacent virtual wordline identifiers.

[0070] In some implementations, the memory controller is configured to obtain a pre-configured mapping relationship table, which includes mapping correspondences between physical wordline identifiers and virtual wordline identifiers, and to obtain n virtual wordline identifiers corresponding to n physical wordline identifiers by matching n physical wordline identifiers with the mapping relationship table.

[0071] In some implementations, the memory controller is configured to retrieve a pre-configured mapping relation table from static random-access memory.

[0072] In some implementations, the reference number of a physical wordline identifier is distributed among the physical wordline identifiers that correspond to m adjacent virtual wordline identifiers.

[0073] In some implementations, the memory controller is configured to obtain a pre-configured algorithm that maps physical wordline identifiers to virtual wordline identifiers and is configured to substitute n physical wordline identifiers into the pre-configured algorithm in order to obtain n virtual wordline identifiers corresponding to n physical wordline identifiers.

[0074] In some implementations, the memory controller is configured to process data corresponding to m adjacent virtual wordline identifiers through a first operator in order to obtain check data, and when there is a data read failure in the data corresponding to m adjacent virtual wordline identifiers, the check data is configured to check and restore the data that failed to be read through a second operator, where the first and second operators are operators whose operational logic is opposite.

[0075] In some implementations, the memory controller is configured to send a first read instruction to memory, wherein the first read instruction includes a first physical word line identifier corresponding to the first data to be read, and to receive the data read result returned by the memory. The memory controller is configured to determine a first virtual wordline identifier corresponding to a first physical wordline identifier and to obtain target check data corresponding to a first virtual wordline identifier in order to recover the first data that failed to be read, when the data read result indicates that reading the first data corresponding to a first physical wordline identifier has failed.

[0076] In some implementations, the memory controller is configured to obtain target check data corresponding to a first virtual word line identifier, obtain a second virtual word line identifier that is consistent with the first virtual word line identifier for generating the target check data, and determine a second physical word line identifier corresponding to the second virtual word line identifier. The memory controller is configured to send a second read command to memory, the second read command being configured to instruct memory to read data stored in a memory cell row associated with a word line corresponding to the second physical word line identifier, the second read command being configured to include a second physical word line identifier, the second data being returned by memory and corresponding to the second physical word line identifier, and the first data that failed to be read being restored based on target check data and the second data.

[0077] In some implementations, when the memory controller reads first data corresponding to a first physical word line identifier, it determines a first virtual word line identifier corresponding to the first physical word line identifier, obtains target check data corresponding to the first virtual word line identifier, obtains a second virtual word line identifier that is consistent with the first virtual word line identifier for generating the target check data, and determines a second physical word line identifier corresponding to the second virtual word line identifier. The system is configured to send a read command to memory, the read command being configured to instruct the system to read data stored in a memory cell row coupled to a word line corresponding to a first physical word line identifier and a second physical word line identifier, The memory controller is configured to receive the data read result returned by the memory, and, when the data read result indicates that the reading of the first data failed, to use target check data and second data corresponding to a second physical word line identifier to recover the first data that failed to be read.

[0078] Figure 7 is a flowchart of a method for operating a memory system according to an exemplary implementation of this application. Taking the application of the method to a memory system as an example, the method includes the following, as shown in Figure 7:

[0079] Step 701: Retrieve multiple data items to be written into the memory array.

[0080] Multiple data are data to be written into the memory array of the memory. In some implementations, the memory array contains n memory cell rows, each of which is coupled to n word lines, where the i-th memory cell row is coupled to the i-th word line, and i is less than a positive integer equal to n. Multiple data are data to be written into the memory cell rows. The n word lines coupled to the n memory cell rows are arranged contiguously by physical word line identifiers. That is, each of the n word lines corresponds to a physical word line identifier that uniquely identifies the word line according to the order of word line arrangement.

[0081] In some implementations, the memory controller within the memory system receives multiple data items to be written to the memory array. Alternatively, the memory controller actively retrieves multiple data items to be written to the memory array periodically.

[0082] In some implementations, the memory controller retrieves multiple data items and then writes them into the memory array based on the physical wordline identifier.

[0083] Step 702: The check data is written to memory. The check data is generated based on data corresponding to spaced-out physical wordline identifiers and is configured to check and restore the data.

[0084] The memory controller first determines the placement of multiple data to be written into a memory cell row, that is, the data corresponding to the physical word line identifier corresponding to the memory cell row to which it is written. For example, suppose there are data a, data b, data c, and data d, where data a is written into a memory cell row associated with word line 1, data b is written into a memory cell row associated with word line 2, data c is written into a memory cell row associated with word line 3, and data d is written into a memory cell row associated with word line 4.

[0085] The memory controller generates check data based on the arrangement of multiple data to be written to a memory cell row and writes this check data to memory. The check data is generated based on data corresponding to spaced-out physical word line identifiers. That is, taking the above-mentioned data a, data b, data c, and data d as examples, since word line 2 is spaced between word line 1 and word line 3, and word line 3 is spaced between word line 2 and word line 4, check data is generated based on data a and data c, and check data is generated based on data b and data d.

[0086] In some implementations, when generating check data based on data corresponding to separated physical wordline identifiers, first, n physical wordline identifiers are mapped to n virtual wordline identifiers, where the physical wordline identifiers corresponding to m adjacent virtual wordline identifiers are separated from each other, where 2 ≤ m ≤ n, and the check data is generated based on the data corresponding to m adjacent virtual wordline identifiers and is configured to check and restore the data corresponding to m adjacent virtual wordline identifiers. For example, m should be 2, which is taken as an example for explanation. That is, the check data is generated based on the data corresponding to two adjacent virtual wordline identifiers, where the physical wordline identifiers corresponding to two adjacent virtual wordline identifiers are separated from each other.

[0087] In some examples, m virtual wordline identifiers include adjacent first and second virtual wordline identifiers, where the first virtual wordline identifier is mapped to a first physical wordline identifier, the second virtual wordline identifier is mapped to a second physical wordline identifier, and at least one physical wordline identifier is distributed between the first and second physical wordline identifiers.

[0088] In some implementations, physical wordline identifiers are distributed between a first and second physical wordline identifier. That is, by separating physical wordlines, check data is generated based on the data corresponding to the separated physical wordlines. Alternatively, multiple physical wordline identifiers are distributed between the first and second physical wordline identifiers. For example, the reference numbers of physical wordline identifiers are distributed among the physical wordline identifiers corresponding to m adjacent virtual wordline identifiers. That is, by separating multiple physical wordlines, check data is generated for the data corresponding to the separated physical wordlines. Alternatively, the number of physical wordline identifiers distributed between the first and second physical wordline identifiers is an indeterminate number determined by an algorithm. That is, by separating one or more physical wordlines, check data is generated for the data corresponding to the separated physical wordlines.

[0089] For example, when mapping between physical wordline identifiers and virtual wordline identifiers, at least one of the following methods is employed.

[0090] Firstly, a pre-configured mapping relationship table is obtained, which includes the mapping relationships between physical wordline identifiers and virtual wordline identifiers. By matching n physical wordline identifiers with the mapping relationship table, n virtual wordline identifiers corresponding to n physical wordline identifiers are obtained.

[0091] In some implementations, the mapping relationship table is stored in static random access memory (SRAM), and the pre-configured mapping relationship table is retrieved from the SRAM. Alternatively, the mapping relationship table is stored in 3D NAND memory, and the memory controller retrieves the pre-configured mapping relationship table from the 3D NAND.

[0092] In some implementations, the correspondence between physical wordline identifiers and virtual wordline identifiers is stored in a mapping relationship table in the form of key-value pairs. For example, physical wordline identifier 1 is stored as a key, and virtual wordline identifier 1, which corresponds to physical wordline identifier 1, is stored as a value. Physical wordline identifier 2 is stored as a key, and virtual wordline identifier 6, which corresponds to physical wordline identifier 1, is stored as a value. Figure 8 shows a schematic diagram of a mapping relationship table in an exemplary implementation of this application. As shown in Figure 8, the virtual wordline identifiers 810 marked as 1-5 correspond to the physical wordline identifiers 820 marked as 1 / 6 / 11 / 16 / 21 respectively, and the corresponding data 830 are data 1 / data 6 / data 11 / data 16 / data 21 respectively, and the generated check data 840 has parity 1. The virtual wordline identifiers 810 marked as 6-10 correspond to the physical wordline identifiers 820 marked as 26 / 31 / 36 / 41 / 46 respectively, and the corresponding data 830 are data 26 / data 31 / data 36 / data 41 / data 46 respectively, and the generated check data 840 has parity 2, and so on.

[0093] Note that in the mapping relationship table above, as an example, the physical wordline identifiers corresponding to two adjacent virtual wordline identifiers are separated by only four physical wordline identifiers. However, the above number of separations is merely illustrative. In some implementations, taking the check data generated by five wordlines as an example, virtual wordline identifiers 1-5 can also correspond to physical wordline identifiers 1 / 3 / 5 / 7 / 9, virtual wordline identifiers 6-10 correspond to physical wordline identifiers 2 / 4 / 6 / 8 / 10, and so on. That is, there is one physical wordline identifier spaced between the physical wordline identifiers corresponding to two adjacent virtual wordline identifiers. Alternatively, virtual wordline identifiers 1-5 may also correspond to physical wordline identifiers 1 / 4 / 7 / 10 / 13, virtual wordline identifiers 6-10 correspond to physical wordline identifiers 2 / 5 / 8 / 11 / 14, and so on. That is, there are two physical wordline identifiers spaced between the physical wordline identifiers corresponding to two adjacent virtual wordline identifiers. Alternatively, based on ensuring a one-to-one correspondence between virtual wordline identifiers and physical wordline identifiers, there may be any number of physical wordline identifiers spaced apart between two adjacent virtual wordline identifiers. The implementations of this application do not limit the number of spacings. In some implementations, the number of spacings between physical wordline identifiers corresponding to two different groups of adjacent virtual wordline identifiers may differ.

[0094] Secondly, a pre-configured algorithm is obtained that is set up to map physical wordline identifiers to virtual wordline identifiers, and the n physical wordline identifiers are substituted into the pre-configured algorithm in order to obtain n virtual wordline identifiers corresponding to n physical wordline identifiers.

[0095] In some implementations, pre-configured algorithms stored in advance are retrieved from SRAM.

[0096] In some examples, a pre-configured algorithm includes a parameter substitution bit for the physical wordline identifier. After substituting the physical wordline identifier into the parameter substitution bit, the virtual wordline identifier corresponding to the physical wordline identifier is output through algorithmic processing by the pre-configured algorithm.

[0097] Taking 50 physical wordline identifiers as an example, the physical wordline identifiers are in the sequence 1 to 50, and the pre-configured algorithm is performed as follows: When the physical wordline identifier is odd, the virtual wordline identifier is equal to the physical wordline identifier; when the physical wordline identifier is even, the virtual wordline identifier is equal to 50 minus the value of the physical wordline identifier.

[0098] It should be noted that the above method of mapping between physical wordline identifiers and virtual wordline identifiers is merely an illustrative example and is not limited to this implementation of the present application.

[0099] In some implementations, at least one of the following methods is employed when generating check data.

[0100] 1. To obtain check data, an exclusive OR algorithm is used to perform operations on the data corresponding to m adjacent virtual wordline identifiers.

[0101] In some implementations, check data may be generated by parity checks. For example, for any data, the total number of bits that are 1 in each bit of the data under the binary code is determined, and then check data is generated to record the parity of that total number in order to facilitate subsequent checks of the data being read by the check data.

[0102] 2. In order to obtain check data, data corresponding to m adjacent virtual wordline identifiers is processed through a first operator, where, if there is a data read failure in the data corresponding to m adjacent virtual wordline identifiers, the check data is configured to check and restore the data that failed to be read through a second operator, the first and second operators being operators whose operational logic is opposite.

[0103] Figure 9 is a schematic diagram of the check data generation process according to an exemplary implementation of the present application. As shown in Figure 9, K data 900 to be written into memory are first acquired, where data 1 is written into physical word lines 1-5, data 2 is written into physical word lines 6-10, and so on, until data K is written into physical word lines k-k+4. First, the physical word line identifiers are mapped to virtual word line identifiers by the mapping 910, where physical word line identifiers 1-5 are mapped to virtual word line identifiers 1 / 6 / 11 / 16 / 21, and physical word line identifiers 6-10 are mapped to virtual word line identifiers 2 / 7 / 12 / 17 / 22. After the mapping between virtual word line identifiers and physical word line identifiers, data 920 for consecutive virtual word line identifiers are acquired. For example, the data for virtual word line identifiers 1-5 are acquired, and check data 1 is acquired by the summation 930. Data for virtual wordline identifiers 6-10 is obtained, check data 2 is obtained by summing 930, and so on.

[0104] In some implementations, a logic analyzer performs a series of write operations to the memory, and observes whether the NAND write address sent by the memory controller on the logic analyzer is a non-contiguous WL number. If that address is a non-contiguous WL number, it is proven that the method for operating the memory system according to the implementation of this application is being used.

[0105] In summary, according to the method provided by the implementation of this application, a virtual wordline identifier is generated corresponding to a physical wordline identifier by setting a mapping relationship between physical wordline identifiers and virtual wordline identifiers such that the physical wordline identifiers corresponding to adjacent virtual wordline identifiers are separated, i.e., not adjacent. Check data is generated using data corresponding to multiple adjacent virtual wordline identifiers. That is, the check data is generated using data corresponding to multiple non-adjacent physical wordline identifiers, thereby reducing the impact on the check data due to the interaction between adjacent physical wordlines, increasing the success rate of data recovery, and improving the reliability of data storage and data reading.

[0106] According to the method provided in this implementation, a one-to-one correspondence between physical wordline identifiers and virtual wordline identifiers is intuitively established by pre-configuring a mapping relationship table. As a result, physical wordline identifiers are mapped to virtual wordline identifiers through the mapping relationship table, which improves the efficiency of determining virtual wordline identifiers.

[0107] The method provided in this implementation aligns physical wordline identifiers with virtual wordline identifiers using a pre-configured algorithm, thereby mapping physical wordline identifiers to virtual wordline identifiers using a pre-configured algorithm, which improves the efficiency of determining virtual wordline identifiers.

[0108] In an exemplary implementation, the process further includes reading the stored data after the check data has been generated and stored. Figure 10 is a flowchart of a method for operating the memory system according to another exemplary implementation of the present application. For example, the method is applied to the memory system shown in Figure 1 and is performed after step 702 shown in Figure 7. The method includes the following:

[0109] Step 1001: A first read command is sent to memory, the first read command containing a first physical word line identifier corresponding to the first data to be read.

[0110] From a memory perspective, data is still accessed by physical word line identifiers; therefore, when reading data, a first read instruction having a first physical word line identifier is sent to memory, and data reading is performed in the memory cell row associated with the word line corresponding to the first physical word line identifier.

[0111] In some implementations, when a computer device at the location of the memory system receives a data read operation, the memory controller sends a first read command to the memory, and the first data stored in a memory cell row associated with a word line corresponding to a first physical word line identifier is read.

[0112] In some implementations, the data reading process corresponding to the first read command includes at least one of the following situations:

[0113] First, if reading the data fails, a virtual wordline identifier is determined and check data is retrieved.

[0114] Step 1021: Receive the data read result returned by memory.

[0115] If the first data can be read successfully, the data read result includes the first data read from the memory cell row associated with the word line corresponding to the first physical word line identifier. If the first data cannot be read successfully, for example, if the memory cell row associated with the word line corresponding to the first physical word line identifier is damaged, the first data cannot be read correctly, and the data read result includes an indicator that the reading of the first data failed.

[0116] In other words, the data reading result includes at least one of the following: 1. the data obtained from the read, and 2. an indicator of a read failure.

[0117] In some implementations, a first read instruction is configured to read multiple first physical word lines. The first data then includes sub-data corresponding to each of the multiple physical word lines, and the data read result may further include an indicator indicating that some of the data failed to be read. In some implementations, the data read result includes first physical word line identifiers corresponding to the data that failed to be read, and other data that was successfully read.

[0118] Step 1031, if the data read result indicates that reading the first data corresponding to the first physical wordline identifier has failed, determine the first virtual wordline identifier corresponding to the first physical wordline identifier.

[0119] In some examples, when generating check data, the check data is generated by mapping physical wordline identifiers to virtual wordline identifiers. Therefore, a first physical wordline identifier is mapped using the same mapping scheme to determine the corresponding first virtual wordline identifier. For example, when generating check data, physical wordline identifiers are mapped to virtual wordline identifiers through a mapping relationship table. If the first data cannot be read, the first virtual wordline identifier corresponding to the first physical wordline identifier is determined through the mapping relationship table. When generating check data, physical wordline identifiers are mapped to virtual wordline identifiers through a pre-configured algorithm. If the first data cannot be read, the first virtual wordline identifier corresponding to the first physical wordline identifier is determined by the pre-configured algorithm.

[0120] Step 1041: Obtain target check data corresponding to the first virtual wordline identifier in order to recover the first data that failed to be read.

[0121] In some implementations, target check data corresponding to the first virtual wordline identifier is read from memory to check the first data.

[0122] In some implementations, target check data corresponding to a first virtual wordline identifier is retrieved, and a second virtual wordline identifier is retrieved that is consistent with the first virtual wordline for generating the target check data. In some examples, during the check data storage process, the physical and virtual wordline identifiers corresponding to the check data, as well as the data for generating the check data, are stored accordingly, and then the corresponding second virtual wordline identifier in the target check data containing the first virtual wordline identifier is retrieved to determine the second physical wordline identifier corresponding to the second virtual wordline identifier. In some examples, when generating check data, a mapping occurs to map the physical wordline identifier to the virtual wordline identifier, and a reverse mapping occurs to map the second virtual wordline identifier to the corresponding second physical wordline identifier. For example, when generating check data, a physical wordline identifier is mapped to a virtual wordline identifier through a mapping relationship table, and the second virtual wordline identifier is still mapped to the second physical wordline identifier through a mapping relationship table. When generating check data, physical wordline identifiers are mapped to virtual wordline identifiers through a pre-configured algorithm, and then a second virtual wordline identifier is substituted using the same pre-configured algorithm to determine the corresponding second physical wordline identifier.

[0123] A second read command is sent to memory. The second read command includes a second physical word line identifier and is configured to instruct memory to read data stored in a memory cell row associated with the word line corresponding to the second physical word line identifier, to receive the second data corresponding to the second physical word line identifier returned by memory, and to recover the first data that failed to be read based on target check data and the second data.

[0124] As an example, Figure 11 is a schematic diagram of the data checking and recovery process according to an exemplary implementation of the present application. As shown in Figure 11, when the memory controller 1101 sends a read command to the memory 1102 instructing it to read the data corresponding to physical word line identifiers 1-5, the memory 1102 feeds back to the memory controller 1101 that it failed to read the data corresponding to physical word line identifier 5. Next, the memory controller 1101 first determines the virtual word line identifier 21 corresponding to physical word line identifier 5 through mapping 1110, and determines the check data n corresponding to the virtual word line identifier 21 through check data lookup 1120. Other virtual word line identifiers p constituting the check data n are obtained through searching for data to generate the check data n 1130, and the physical word line identifier q corresponding to the virtual word line identifier p is determined through mapping 1140. The memory controller 1101 sends a read command to the memory 1102 instructing it to read the data corresponding to physical word line identifier q. After memory 1102 feeds data q back to memory controller 1101, memory controller 1101 checks and restores the data corresponding to physical word line identifier 5.

[0125] In the second method, the target check data and the second data are acquired in advance, and if reading the first data fails, the check is performed through the target check data and the second data.

[0126] Step 1022: Determine the first virtual wordline identifier corresponding to the first physical wordline identifier, and obtain the target check data corresponding to the first virtual wordline identifier.

[0127] In some implementations, when generating check data, physical wordline identifiers are mapped to virtual wordline identifiers through a mapping relationship table. If the first data cannot be read, a first virtual wordline identifier corresponding to the first physical wordline identifier is determined through the mapping relationship table. When generating check data, physical wordline identifiers are mapped to virtual wordline identifiers through a pre-configured algorithm. If the first data cannot be read, a first virtual wordline identifier corresponding to the first physical wordline identifier is determined through a pre-configured algorithm.

[0128] Step 1032: Obtain a second virtual wordline identifier that is consistent with a first virtual wordline identifier for generating target check data, and determine a second physical wordline identifier that corresponds to the second virtual wordline identifier.

[0129] In some implementations, target check data corresponding to a first virtual wordline identifier is retrieved, and a second virtual wordline identifier is retrieved that is consistent with the first virtual wordline for generating the target check data. In some examples, during the check data storage process, the physical and virtual wordline identifiers corresponding to the check data, as well as the data for generating the check data, are stored accordingly, and then the corresponding second virtual wordline identifier in the target check data containing the first virtual wordline identifier is retrieved to determine the second physical wordline identifier corresponding to the second virtual wordline identifier. In some examples, when generating check data, mapping maps the physical wordline identifier to the virtual wordline identifier, and reverse mapping maps the second virtual wordline identifier to the corresponding second physical wordline identifier.

[0130] Step 1042: A second read instruction is sent to memory, the second read instruction containing a second physical word line identifier.

[0131] The second read instruction is configured to instruct the memory to read data stored in a memory cell row associated with a word line corresponding to a second physical word line identifier.

[0132] Step 1052: Receive the data read result returned by memory.

[0133] In some examples, the data read results include the results of reading memory cell rows associated with the word line corresponding to a first physical word line identifier, and the results of reading memory cell rows associated with the word line corresponding to a second physical word line identifier.

[0134] In the implementation of this application, if reading the first data fails but reading the second data succeeds, the first data is checked and restored.

[0135] Step 1062, if the data read result indicates that reading the first data failed, the target check data and the second data corresponding to the second physical wordline identifier are used to recover the first data that failed to be read.

[0136] In summary, according to the method provided by the implementation of this application, a virtual wordline identifier is generated corresponding to a physical wordline identifier by setting a mapping relationship between physical wordline identifiers and virtual wordline identifiers such that the physical wordline identifiers corresponding to adjacent virtual wordline identifiers are separated, i.e., not adjacent. Check data is generated using data corresponding to multiple adjacent virtual wordline identifiers. That is, the check data is generated using data corresponding to multiple non-adjacent physical wordline identifiers, thereby reducing the impact on the check data due to the interaction between adjacent physical wordlines, increasing the success rate of data recovery, and improving the reliability of data storage and data reading.

[0137] In the method provided by this implementation, in the event of a data read failure, the data is checked and restored using check data. On the one hand, it avoids situations where data cannot be checked and restored by check data due to interaction between adjacent word lines. On the other hand, it improves the security and accuracy of data storage.

[0138] Figure 12 is a schematic diagram of a memory controller according to an exemplary implementation of the present application. The method of operating the memory system provided in the implementation of the present application is mainly carried out by the memory controller. As shown in Figure 12, the memory controller 1200 includes a memory interface 1210, a memory controller 1220, a configuration register 1230, and a bus interface 1240.

[0139] The memory interface 1210 is connected to the memory and configured to convert data exchange on the bus into data exchange that is compatible with the storage timing of the storage medium.

[0140] The memory controller 1220 is configured to control the overall function of the memory controller, control the memory interface to ensure that data exchange between the memory and the internal bus of the microcontroller unit (MCU) is completed correctly, and manage interrupt signals.

[0141] The configuration register 1230 is configured to configure the functions of the memory controller, such as the timing configuration of the memory interface.

[0142] The bus interface 1240 connects to the internal bus of the MCU and is typically configured to: 1. transmit memory controller configuration information, and 2. transmit stored data that is compatible with the memory controller interface.

[0143] In some implementations, the memory controller 1200 includes at least two interfaces. These at least two interfaces include at least one interface for communicating with memory and at least one front-end interface for communicating with the host.

[0144] The present invention provides an implementation of a control circuit. The control circuit includes a programmable logic circuit and / or program instructions and may be used to carry out a method for operating a memory system as provided in the above implementation of the present invention.

[0145] The implementation of this application provides a computer-readable storage medium in which instructions are stored. When the instructions are executed on a memory controller, they implement a method for operating the memory system as provided in the above implementation of this application.

[0146] In this application, the terms “first” and “second” are for illustrative purposes only and should not be construed as indicating or implying relative importance. Unless otherwise expressly provided, “at least one” means “one or more,” and “multiple” means “two or more.”

[0147] In this application, the term "and / or" simply describes a combination of related objects, meaning there can be three possible relationships. For example, A and / or B means A only, both A and B, and B only. In addition, the letter " / " in this specification generally indicates that the objects in the context are in an "or" relationship.

[0148] The above description is merely an exemplary implementation of this application and does not limit it. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification shall be included within the scope of protection of this application. [Explanation of symbols]

[0149] 10 Memory System 100 memory 101 circuit board 102 stack layers 103 Gate conductive layer 104 Intergate dielectric layer 105 Channel Structure 110 memory arrays 111 memory string 112 memory cells 113 Source Selection Gate (SSG) 114 Drain Selection Gate (DSG) 115 bit lines 116 DSG Line 117 SSG Line 118 Source Line (SL) 120 Wordlines 130 Peripheral Circuits 131 Page Buffer / Sense Amplifier 132-column decoder / bitline (BL) driver 133-line decoder / word line (WL) driver 134 Voltage Generator 135 Control Logic Unit 136 registers 137 Interface 138 Data Bus 140 blocks 200 memory controllers 300 hosts 400 memory cards 410 connector 500 Solid State Disks (SSDs) 510 connector 810 Virtual Wordline Identifier 820 Physical Wordline Identifier 830 data 840 Check Data 1101 Memory Controller 1102 memory 1200 Memory Controller 1210 Memory Interface 1220 Memory Controller 1230 Configuration Registers 1240 bus interface

Claims

1. A memory array comprising n word lines, wherein the n word lines are arranged contiguously by a physical word line identifier, and where n ≥ 2, and at least one memory comprising this memory array, A memory controller coupled to at least one of the aforementioned memories and The memory controller is equipped with, Acquiring multiple data to be written into the aforementioned memory array, The mapping of n physical wordline identifiers to n virtual wordline identifiers, wherein the physical wordline identifiers corresponding to m adjacent virtual wordline identifiers are spaced apart from each other, and where 2 ≤ m ≤ n. The process involves generating check data based on data corresponding to the aforementioned m adjacent virtual wordline identifiers, wherein the check data is configured to check and restore the data corresponding to the aforementioned m adjacent virtual wordline identifiers. A memory system configured to perform the following actions.

2. The aforementioned memory controller Obtaining a mapping relationship table, wherein the mapping relationship table includes a mapping correspondence between the physical wordline identifier and the virtual wordline identifier. By matching the n physical wordline identifiers with the mapping relationship table, the n virtual wordline identifiers corresponding to the n physical wordline identifiers are obtained. The memory system according to claim 1, further configured to perform the following:

3. The memory system according to claim 2, wherein the memory controller is further configured to obtain the mapping relation table from static random access memory.

4. The memory system according to claim 1, wherein the reference numbers of the physical wordline identifiers are distributed among the physical wordline identifiers, each corresponding to one of the m adjacent virtual wordline identifiers.

5. The aforementioned memory controller Obtaining a pre-configured algorithm, wherein the pre-configured algorithm is configured to map the physical wordline identifier to the virtual wordline identifier. In order to obtain the n virtual wordline identifiers corresponding to the n physical wordline identifiers, the n physical wordline identifiers are substituted into the pre-configured algorithm. The memory system according to claim 1, configured to perform the following:

6. The aforementioned memory controller To obtain the aforementioned check data, the system is further configured to process the data corresponding to the m adjacent virtual wordline identifiers through a first operator. When there is a data read failure in the data corresponding to the m adjacent virtual word line identifiers, the check data is configured to check and restore the data that failed to be read through a second operator. The memory system according to claim 1, wherein the first operator and the second operator are operators whose operational logic is opposite to that of the first operator.

7. The aforementioned memory controller Sending a first read command to the memory, wherein the first read command includes a first physical word line identifier corresponding to the first data to be read. Receiving the data read result returned by the aforementioned memory, When the data reading result indicates that reading the first data corresponding to the first physical word line identifier has failed, the first virtual word line identifier corresponding to the first physical word line identifier is determined, To recover the first data that failed to be read, obtain target check data corresponding to the first virtual wordline identifier. The memory system according to claim 1, further configured to perform the following:

8. The aforementioned memory controller Obtaining the target check data corresponding to the first virtual wordline identifier, Obtaining a second virtual wordline identifier that is consistent with the first virtual wordline identifier for generating the target check data, Determining a second physical wordline identifier corresponding to the second virtual wordline identifier, Sending a second read command to the memory, wherein the second read command is configured to instruct the memory to read the data stored in a memory cell row that includes the second physical word line identifier and is associated with a word line corresponding to the second physical word line identifier. Receiving second data returned by the memory and corresponding to the second physical word line identifier, The first data that failed to be read is to be restored based on the target check data and the second data. The memory system according to claim 7, further configured to perform the following:

9. The aforementioned memory controller When reading the first data corresponding to the first physical wordline identifier, the first virtual wordline identifier corresponding to the first physical wordline identifier is determined, Obtaining target check data corresponding to the first virtual wordline identifier, Obtaining a second virtual wordline identifier that is consistent with the first virtual wordline identifier for generating the target check data, Determining a second physical wordline identifier corresponding to the second virtual wordline identifier, Sending a read command to the memory, wherein the read command is configured to instruct the reading of the data stored in a memory cell row coupled to the word lines corresponding to the first physical word line identifier and the second physical word line identifier, Receiving the data read result returned by the aforementioned memory, When the data reading result indicates that reading the first data has failed, the target check data and the second data corresponding to the second physical wordline identifier are used to recover the first data that failed to be read. The memory system according to claim 1, further configured to perform the following:

10. A method for operating memory, A step of obtaining a plurality of data to be written into the memory array of the memory, wherein the memory array is connected to n word lines, and the n word lines are arranged contiguously by a physical word line identifier, where n ≥ 2. A step of writing check data into the memory, wherein the check data is data generated based on data corresponding to spaced-apart physical wordline identifiers, and is configured to check and restore the data. A method that includes [a certain feature].

11. Before the step of writing the aforementioned check data into the memory, A step of mapping n physical wordline identifiers to n virtual wordline identifiers, wherein the physical wordline identifiers corresponding to m adjacent virtual wordline identifiers are spaced apart from each other, where 2 ≤ m ≤ n. A step of generating check data based on data corresponding to the m adjacent virtual wordline identifiers, wherein the check data is configured to check and restore the data corresponding to the m adjacent virtual wordline identifiers. The method according to claim 10, further comprising:

12. The step of mapping the n physical wordline identifiers to the n virtual wordline identifiers is: A step of obtaining a mapping relationship table, wherein the mapping relationship table includes a mapping correspondence between the physical wordline identifier and the virtual wordline identifier. The steps include obtaining the n virtual wordline identifiers corresponding to the n physical wordline identifiers by matching the n physical wordline identifiers with the mapping relationship table, and The method according to claim 11, comprising:

13. The method according to claim 12, wherein the step of obtaining the mapping relationship table comprises the step of obtaining the mapping relationship table from static random access memory.

14. The method according to claim 11, wherein the reference number of the physical wordline identifier is distributed among the physical wordline identifiers corresponding to the m adjacent virtual wordline identifiers.

15. The step of mapping the n physical wordline identifiers to the n virtual wordline identifiers is: A step of obtaining a pre-configured algorithm, wherein the pre-configured algorithm is configured to map the physical wordline identifier to the virtual wordline identifier, In order to obtain the n virtual wordline identifiers corresponding to the n physical wordline identifiers, the steps include substituting the n physical wordline identifiers into the pre-configured algorithm. The method according to claim 11, comprising:

16. The step of generating the check data based on the data corresponding to the m adjacent virtual wordline identifiers comprises the step of processing the data corresponding to the m adjacent virtual wordline identifiers through a first operator in order to obtain the check data, When there is a data read failure in the data corresponding to the m adjacent virtual word line identifiers, the check data is configured to check and restore the data that failed to be read through a second operator. The method according to claim 11, wherein the first operator and the second operator are operators whose operational logic is opposite to that of the first operator.

17. After writing the aforementioned check data to the memory, A step of sending a first read command to the memory, wherein the first read command includes a first physical word line identifier corresponding to the first data to be read; The steps include receiving the data read result returned by the memory, When the data reading result indicates that reading the first data corresponding to the first physical word line identifier has failed, the steps include determining the first virtual word line identifier corresponding to the first physical word line identifier, A step of obtaining target check data corresponding to the first virtual word line identifier in order to restore the first data that failed to be read, and The method according to claim 16, further comprising:

18. The step of obtaining the target check data corresponding to the first virtual wordline identifier in order to restore the first data that failed to be read is: The steps include obtaining the target check data corresponding to the first virtual word line identifier, The steps include obtaining a second virtual wordline identifier that is consistent with the first virtual wordline identifier for generating the target check data, The steps include determining a second physical wordline identifier corresponding to the second virtual wordline identifier, A step of sending a second read command to the memory, wherein the second read command is configured to instruct the memory to read the data stored in a memory cell row associated with the word line corresponding to the second physical word line identifier, The steps include receiving second data returned by the memory and corresponding to the second physical word line identifier, The steps include: recovering the first data that failed to be read based on the target check data and the second data; The method according to claim 17, comprising:

19. After generating the check data based on the data corresponding to the m adjacent virtual word line identifiers, A step of sending a first read command to the memory, wherein the first read command includes a first physical word line identifier corresponding to the first data to be read; The steps include determining a first virtual wordline identifier corresponding to the first physical wordline identifier, The steps include obtaining the target check data corresponding to the first virtual word line identifier, The steps include obtaining a second virtual wordline identifier that is consistent with the first virtual wordline identifier for generating the target check data, The steps include determining a second physical wordline identifier corresponding to the second virtual wordline identifier, A step of sending a second read command to the memory, wherein the second read command is configured to instruct the memory to read the data stored in a memory cell row associated with the word line corresponding to the second physical word line identifier, The steps include receiving the data read result returned by the memory, When the data reading result indicates that reading the first data has failed, the steps include using the target check data and the second data corresponding to the second physical wordline identifier to recover the first data that failed to be read. The method according to claim 18, further comprising:

20. A computer-readable storage medium that stores instructions, wherein when an instruction is executed on a memory controller, the memory controller... The process of retrieving multiple data to be written into a memory array, wherein the memory array is connected to n word lines, and the n word lines are arranged contiguously by a physical word line identifier, where n ≥ 2. The process involves writing check data into the memory, wherein the check data is data generated based on data corresponding to spaced-apart physical wordline identifiers, and the system is configured to check and restore the data. A computer-readable storage medium that enables execution of [something].

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