Silicon-on-insulator semiconductor components and process platforms, and manufacturing methods

Abstract

The present application relates to a silicon-on-insulator semiconductor component including a substrate, a buried dielectric layer, a first electrode, a second electrode, and a drift region, the buried dielectric layer being disposed on the substrate, the drift region being disposed on the buried dielectric layer, a stepped structure formed on an upper surface of the drift region, the stepped structure including a first side proximate to the first electrode, a second side proximate to the second electrode, and a transition region between the first and second sides, the upper surface of the second side being higher than the lower surface of the first side, such that a thickness of the drift region on the second side is greater than a thickness of the drift region on the first side, and the first and second electrodes being configured such that when a reverse bias voltage is applied to the component, a voltage applied to the second electrode is greater than a voltage applied to the first electrode.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, particularly to silicon-on-insulator semiconductor components, and further to a silicon-on-insulator semiconductor process platform and a method for manufacturing silicon-on-insulator semiconductor components.

Background Art

[0002] This application claims the priority of a Chinese patent application filed on June 15, 2023, with application number 2023107131192 and invention title "Silicon-on-Insulator Semiconductor Component and Process Platform, Manufacturing Method", and all of its contents are incorporated herein by reference.

[0003] With the wide application of very large scale integrated circuits in various fields, the development requirements for high voltage and high power semiconductor components of the system are becoming increasingly high. Integrated high voltage components (such as LDMOS, LIGBT, and high voltage Diode, etc.) using silicon-on-insulator (SOI) technology have the advantages of SOI technology and the components themselves, with fast operating speed, low parasitic effects, high breakdown voltage, simple process manufacturing, and convenient integration, so they are widely studied and applied. However, it is difficult for conventional silicon-on-insulator integrated high voltage components to achieve a breakdown voltage of 1200V and above. The thickness of the buried oxide layer is related to the breakdown voltage, but a thick buried oxide layer deteriorates the thermal conductivity of the component, and when the buried oxide layer is thick enough, it does not contribute to the breakdown voltage and causes an increase in cost. Therefore, when the breakdown voltage increases to a certain value, it is not practical to continuously increase the thickness of the buried oxide layer to improve the breakdown voltage.

Summary of the Invention

Means for Solving the Problems

[0004] The first embodiment provides a silicon-on-insulator semiconductor component. The component includes a substrate, an embedded dielectric layer, a first electrode, a second electrode, and a drift region, wherein the embedded dielectric layer is provided on the substrate, the drift region is provided on the embedded dielectric layer, a drop structure is formed on the upper surface of the drift region, the drop structure includes a first side adjacent to the first electrode, a second side adjacent to the second electrode, and a transition region between the first and second sides, the upper surface of the second side is higher than the lower surface of the first side, thereby the thickness of the drift region on the second side is greater than the thickness of the drift region on the first side, and the first and second electrodes are configured such that when a reverse bias voltage is applied to the component, the voltage applied to the second electrode is greater than the voltage applied to the first electrode.

[0005] In one embodiment, the component is a transversely double-diffusion metal-oxide-semiconductor field-effect transistor, the first electrode is a source, the second electrode is a drain, and the transversely double-diffusion metal-oxide-semiconductor field-effect transistor further includes a gate.

[0006] In one embodiment, the component is a lateral insulated-gate bipolar transistor, the first electrode is an emitter, the second electrode is a collector, and the lateral insulated-gate bipolar transistor further includes a gate.

[0007] In one embodiment, the component is a diode, the first electrode is the anode, and the second electrode is the cathode.

[0008] In one embodiment, the drop structure is a stepped structure, comprising a first surface located on the first side, a second surface located on the second side, and a stepped wall located in the transition region, wherein the height difference between the second surface and the first surface is 3 to 10 microns.

[0009] In one embodiment, the inclination angle of the stepped wall is between 20 and 90 degrees.

[0010] In one embodiment, the drift region has a first conductivity type, and the component further includes a protective layer of a second conductivity type, the protective layer of the second conductivity type being located in the drift region and surrounding the corner formed by the first base surface and the stepped wall and the corner formed by the second base surface and the stepped wall, and the first conductivity type and the second conductivity type are opposite conductivity types.

[0011] In one embodiment, the component further includes a first electrode extraction region and a second electrode extraction region, the first electrode extraction region and the second electrode extraction region being provided in the embedded dielectric layer.

[0012] In one embodiment, the component further includes a field oxide layer, the field oxide layer extending from a second side adjacent to the second electrode to a first side adjacent to the first electrode on the upper surface of the drift region.

[0013] In one embodiment, the component further includes an interlayer dielectric layer, the interlayer dielectric layer covering at least the field oxide layer, the first electrode extraction region and the second electrode extraction region.

[0014] A second embodiment provides a silicon-on-insulator semiconductor process platform comprising the silicon-on-insulator semiconductor component described in any of the above embodiments, further comprising at least one of a complementary metal-oxide-semiconductor field-effect transistor and a well resistor.

[0015] A third aspect provides a method for manufacturing a silicon-on-insulator semiconductor component. The method includes the steps of: obtaining a wafer including a substrate, an embedded dielectric layer on the substrate, and a drift region on the embedded dielectric layer; forming a drop structure on the upper surface of the drift region by photolithography and etching, wherein the drop structure includes a first side, a second side, and a transition region between the first side and the second side, and the upper surface of the second side is higher than the lower surface of the first side, thereby the thickness of the drift region on the second side is greater than the thickness of the drift region on the first side; and forming a first electrode and a second electrode, wherein the first side is one side adjacent to the first electrode and the second side is one side adjacent to the second electrode, wherein the first electrode and the second electrode are configured such that when a reverse bias voltage is applied to the component, the voltage applied to the second electrode is greater than the voltage applied to the first electrode.

[0016] In one embodiment, the drop structure is a stepped structure, comprising a first base surface located on the first side, a second base surface located on the second side, and a stepped wall located in the transition region, wherein, prior to forming the first and second electrodes, the method further comprises forming a protective layer in the drift region of the stepped structure by ion implantation, wherein the protective layer surrounds the corner formed by the first base surface and the stepped wall and the corner formed by the second base surface and the stepped wall.

[0017] In one embodiment, the etching is a reactive ion etching process.

[0018] A fourth aspect provides a method for manufacturing another type of silicon-on-insulator semiconductor component. This method includes the steps of: obtaining a wafer including a substrate, an embedded dielectric layer on the substrate, and a first epitaxial layer on the embedded dielectric layer; forming a second epitaxial layer on a portion of the first epitaxial layer and forming a drop structure at the boundary between the first epitaxial layer and the second epitaxial layer, including a first side on the second epitaxial layer side, a second side on the first epitaxial layer side, and a transition region between the first side and the second side; and forming a first electrode and a second electrode, wherein the first side is one side adjacent to the first electrode and the second side is one side adjacent to the second electrode, and the first electrode and the second electrode are configured such that when a reverse bias voltage is applied to the component, the voltage applied to the second electrode is greater than the voltage applied to the first electrode.

[0019] Details of one or more embodiments of this application are described in the accompanying drawings and the following description. Other features, purposes and advantages of this application will become apparent from the specification, drawings and claims. [Brief explanation of the drawing]

[0020] One or more drawings may be used to better illustrate and describe the embodiments and / or examples of the invention disclosed herein. Any additional details or examples used to illustrate the drawings should not be considered to limit the scope of the disclosed invention, the embodiments and / or examples described herein, or the best mode of such invention as currently understood. [Figure 1] This is a schematic cross-sectional view of a component in one embodiment where the silicon-on-insulator semiconductor component is an LDMOS. [Figure 2a] This is a schematic cross-sectional view of an SOI LDMOS in which an integral protective layer is formed in one embodiment. [Figure 2b] This is a schematic cross-sectional view of an SOI LDMOS in which protective layers are formed surrounding two corners in one embodiment. [Figure 2c] Schematic cross-sectional view of a SOI LDMOS formed using a secondary epitaxial method in one embodiment. [Figure 3] Schematic cross-sectional view of a component in one embodiment where the silicon-on-insulator semiconductor component is a LIGBT. [Figure 4] Schematic cross-sectional view of a LIGBT formed using a secondary epitaxial method in one embodiment. [Figure 5] Schematic cross-sectional view of a diode in one embodiment where the silicon-on-insulator semiconductor component is a diode. [Figure 6] Schematic cross-sectional view of a diode formed using a secondary epitaxial method in one embodiment. [Figure 7] Schematic cross-sectional view of a silicon-on-insulator semiconductor process platform in one embodiment of the present application. [Figure 8] Flowchart of a method for manufacturing a silicon-on-insulator semiconductor component in one embodiment of the present application. [Figure 9] Flowchart of a method for manufacturing a silicon-on-insulator semiconductor component in another embodiment of the present application. [Figure 10] Flowchart of the steps between steps S420 and S430 in one embodiment where the component to be manufactured is a SOI LDMOS. [Figure 11a] Schematic cross-sectional view of a component during the process of manufacturing a SOI LDMOS based on the method shown in FIG. 10. [Figure 11b] Schematic cross-sectional view of a component during the process of manufacturing a SOI LDMOS based on the method shown in FIG. 10. [Figure 11c] Schematic cross-sectional view of a component during the process of manufacturing a SOI LDMOS based on the method shown in FIG. 10. [Figure 11d] Schematic cross-sectional view of a component during the process of manufacturing a SOI LDMOS based on the method shown in FIG. 10. [Figure 11e]Figure 10 shows a schematic cross-sectional view of a component during the manufacturing process of an SOI LDMOS based on the method shown. [Figure 12] This is a flowchart of the steps between steps S420 and S430 in one embodiment where the component being manufactured is an SOI LIGBT. [Figure 13a] Figure 12 shows a schematic cross-sectional view of a component during the manufacturing process of an SOI LIGBT based on the method shown. [Figure 13b] Figure 12 shows a schematic cross-sectional view of a component during the manufacturing process of an SOI LIGBT based on the method shown. [Figure 13c] Figure 12 shows a schematic cross-sectional view of a component during the manufacturing process of an SOI LIGBT based on the method shown. [Figure 13d] Figure 12 shows a schematic cross-sectional view of a component during the manufacturing process of an SOI LIGBT based on the method shown. [Figure 13e] Figure 12 shows a schematic cross-sectional view of a component during the manufacturing process of an SOI LIGBT based on the method shown. [Figure 14] This is a flowchart of the steps between steps S420 and S430 in one embodiment where the component being manufactured is an SOI diode. [Figure 15a] This is a schematic cross-sectional view of a component during the manufacturing process of an SOI diode based on the method shown in Figure 14. [Figure 15b] This is a schematic cross-sectional view of a component during the manufacturing process of an SOI diode based on the method shown in Figure 14. [Figure 15c] This is a schematic cross-sectional view of a component during the manufacturing process of an SOI diode based on the method shown in Figure 14. [Figure 15d] This is a schematic cross-sectional view of a component during the manufacturing process of an SOI diode based on the method shown in Figure 14. [Figure 16] This is a schematic cross-sectional view of a silicon-on-insulator semiconductor process platform in one embodiment where a stepped structure in the drift region is formed using reactive ion etching. [Figure 17]This is a schematic cross-sectional view of a silicon-on-insulator semiconductor process platform in one embodiment where a stepped structure in the drift region is formed using secondary epitaxial processing. [Modes for carrying out the invention]

[0021] To facilitate understanding of the present invention, the invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. Conversely, these embodiments are provided to make the disclosure of the invention more complete.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art. Terms used herein are for illustrative purposes only to describe specific embodiments and are not intended to limit the invention. The terms “and / or” as used herein include any one or more and all combinations of the relevant enumerated items.

[0023] When an element or layer is referred to as "located on," "adjacent to," "connected to," or "joined to" another element or layer, it may be directly located on, adjacent to, connected to, or joined to the other element or layer, or there may be an intervening element or layer. When an element or layer is referred to as "directly located on," "directly adjacent to," "directly connected to," or "directly joined to" another element or layer, there is no intervening element or layer. In this specification, "connection" should be understood as "electrical connection," "communication connection," etc., when there is a transmission of electrical signals or data between connected circuits, modules, units, etc. The terms 1, 2, 3, etc., may be used to describe various elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used solely to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, the first element, component, region, layer, or section described below may be referred to as the second element, component, region, layer, or section without departing from the teachings of the present invention.

[0024] Spatially relative terms such as “below,” “downward,” “below,” “below,” “on top,” and “above” may be used herein to facilitate the description of the relationship between one element or feature shown in a figure and another element or feature. It should be noted that spatially relative terms are intended to encompass different orientations of the device in use and operation, in addition to the orientation shown in the figure. For example, if the device in the figure is inverted, an element or feature described as “below,” “below that,” or “below that” another element would be oriented as “above” the other element or feature. Thus, the exemplary terms “below” and “downward” may include both up and down orientations. The device may be oriented differently (rotated by 90 degrees or other orientations), and the spatial terms used herein may be interpreted accordingly.

[0025] The terms used herein are for illustrative purposes only to describe specific embodiments and are not intended to limit the invention. Where used herein, the singular forms “1,” “one,” and “the / the said” are intended to include the plural form unless the context explicitly indicates otherwise. “At least one” may be understood to mean one or more, and “plural” to mean two or more. “At least part of an element” means part or all of an element. Where used herein, the terms “consisting of” and / or “including” specify the presence of the described features, integers, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof. Where used herein, the terms “and / or” include any and all combinations of the relevant enumerated items.

[0026] Embodiments of the present invention are described herein with reference to schematic cross-sections of idealized embodiments (and intervening structures) of the present invention. Thus, deformations from the illustrated shapes may be expected, for example, due to manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be limited to specific shapes of the regions shown herein, but should include, for example, deviations of shape due to manufacturing. For example, an injection region shown as a rectangle typically has rounded or curved features at its edges and / or an injection concentration gradient, rather than a binary change from the injection region to the non-injected region. Similarly, a filled region formed by injection may result in some injection in the region between the filled region and the surface on which the injection is performed. Accordingly, the regions shown in the figures are essentially schematic, and their shapes are not intended to represent the actual shapes of regions of a part, nor are they intended to limit the scope of the present invention.

[0027] The semiconductor terminology used herein is technical terminology commonly used by those skilled in the art. For example, to distinguish between doping concentrations of P-type and N-type impurities, P+ type indicates a high doping concentration of P-type, P- type indicates a medium doping concentration of P-type, P- type indicates a low doping concentration of P-type, N+ type indicates a high doping concentration of N-type, N- type indicates a medium doping concentration of N-type, and N- type indicates a low doping concentration of N-type.

[0028] In typical SOI semiconductor process platforms, integrated high-voltage components can usually only reach a breakdown voltage of around 600V, and it is difficult for them to reach a breakdown voltage of 1200V or higher. Furthermore, increasing the thickness of the top silicon layer does not improve the withstand voltage of integrated high-voltage components beyond 1200V. This is because simply increasing the thickness of the top silicon layer does not solve the problem of premature breakdown in the longitudinal direction. In a typical SOI semiconductor process platform, by using a structure with a thick embedded oxide layer and a thin top silicon layer, integrated high-voltage components can reach a breakdown voltage of 1200V. This is because the breakdown voltage of the component increases with increasing thickness of the embedded oxide layer within a certain range, and the thin top silicon layer limits the energy that carriers gain from the longitudinal electric field, making the component less prone to breakdown. However, such technical proposals have clear drawbacks. The embedded oxide layer in the SOI structure blocks heat transfer to the substrate, resulting in poor heat dissipation of the component. This causes the temperature of the local crystal lattice of the component to rise, leading to a degradation of the component's electrical parameters. These degradation phenomena worsen the reliability of the component, and this problem is more pronounced for components with thick embedded oxide layers.

[0029] This application proposes a silicon-on-insulator semiconductor component comprising a substrate, an embedded dielectric layer, a first electrode, a second electrode, and a drift region. The embedded dielectric layer is provided on the substrate, The drift region is provided on the embedded dielectric layer, and a drop structure is formed on the upper surface of the drift region, the drop structure includes a first side adjacent to the first electrode, a second side adjacent to the second electrode, and a transition region between the first side and the second side, the upper surface of the second side is higher than the lower surface of the first side, and thereafter the thickness of the drift region on the second side is greater than the thickness of the drift region on the first side. The first electrode and the second electrode are configured such that when a reverse bias voltage is applied to the component, the voltage applied to the second electrode is greater than the voltage applied to the first electrode.

[0030] The above silicon-on-insulator semiconductor component employs a structure in which the thickness of the drift region at the low-voltage end of the component is smaller than the thickness of the drift region at the high-voltage end when a reverse bias voltage is applied. This allows the breakdown point of the component to be controlled below the high-voltage end, completely depleting the drift region, and still improving the breakdown voltage of the component without increasing the thickness of the embedded oxide layer.

[0031] In one embodiment of the present application, the silicon-on-insulator semiconductor component further includes a first electrode extraction region and a second electrode extraction region. The first electrode extraction region and the second electrode extraction region are provided in a buried dielectric layer and have P-type doping or N-type doping. The first electrode is located in the first electrode extraction region and electrically connected to the first electrode extraction region, and the second electrode is located in the second electrode extraction region and electrically connected to the second electrode extraction region.

[0032] In one embodiment of this application, the drift region has a first conductivity type, the component further includes a protective layer of a second conductivity type, the protective layer of the second conductivity type is located in the drift region and surrounds the corner formed by the first base surface and the stepped wall and the corner formed by the second base surface and the stepped wall, and the first conductivity type and the second conductivity type are opposite conductivity types.

[0033] Figure 1 is a schematic cross-sectional view of a component in one embodiment in which the silicon-on-insulator semiconductor component is a lateral double-diffused metal-oxide-semiconductor field effect transistor (simply referred to as LDMOS). The LDMOS includes a substrate 110, an embedded dielectric layer 120, a drift region 130, a first electrode 162, a second electrode 164, and a gate 166. The first electrode 162 is the source, and the second electrode 164 is the drain. One side of the upper surface of the drift region 130 that is close to the drain (hereinafter referred to as the high side of the drift region) is higher than the other side that is close to the source (hereinafter referred to as the low side of the drift region), thereby forming a drop structure 131.

[0034] The LDMOS further includes a first electrode extraction region (i.e., a source region) 142 located on the low side of the drift region and a second electrode extraction region (i.e., a drain region) 144 located on the high side of the drift region. The first electrode 162 (i.e., the source) is located in the first electrode extraction region 142 and is electrically connected to the first electrode extraction region 142. The second electrode 164 (i.e., the drain) is located in the second electrode extraction region 144 and is electrically connected to the second electrode extraction region 144. In the embodiment shown in Figure 1, the gate 166 can extend from the low side of the drift region to the edge of the first electrode extraction region 142 and have a certain area overlap with the first electrode extraction region 142.

[0035] In the embodiment shown in Figure 1, the LDMOS further includes a field oxide layer 147, which extends from the high side of the drift region to the low side of the drift region. A portion of the gate 166 extends onto the field oxide layer 147.

[0036] In the embodiment shown in Figure 1, the LDMOS is an N-type LDMOS, the drift region 130 is an N-type drift region, and the LDMOS further includes a P-type body region 132 located on the lower side of the drift region and an N-well 134 located on the higher side of the drift region. The first electrode extraction region 142 is an N+ region and is located in the P-type body region 132. The second electrode extraction region 144 is an N+ region and is located in the N-well 134.

[0037] In the embodiment shown in Figure 1, the LDMOS further includes a body lead-out region 146 located within the P-type body region 132. The body lead-out region 146 is a P+ region. The first electrode 162 is electrically connected to the body lead-out region 146.

[0038] In one embodiment of this application, the LDMOS further includes an interlayer dielectric (ILD) layer 150. The interlayer dielectric layer 150 covers structures such as a gate 166, a field oxide layer 147, a first electrode extraction region 142, a second electrode extraction region 144, and a body extraction region 146.

[0039] In one embodiment of this application, the embedded dielectric layer 120 is an embedded oxide layer, and its material may be silicon dioxide.

[0040] In one embodiment of this application, the drop structure is a stepped structure, comprising a first base surface located on the first side, a second base surface located on the second side, and a stepped wall located in the transition region, wherein the height difference between the second base surface and the first base surface (corresponding to H1 in Figure 1) is 3 to 10 microns, and an appropriate height difference can ensure that the drift region is completely depleted. The inclination angle of the stepped wall (corresponding to θ1 in Figure 1) is 20 to 90 degrees, and an appropriate θ1 can ensure that the part does not break down prematurely at this angle.

[0041] When a reverse bias voltage is applied to the LDMOS, a positive voltage is applied to the drain, and the gate 166, source, and substrate are grounded. The PN junction, composed of a P-type body region 132 and an N-type drift region 130, is reverse-biased, and as the applied bias voltage continuously increases, the space charge region within the less doped drift region 130 expands toward the drain end. The depletion region within the drift region 130 can expand at most to the upper surface of the embedded oxide layer, and the electric field in this depletion region is hardly affected by the substrate 110. The presence of the embedded oxide layer improves the longitudinal breakdown voltage of the component and prevents premature longitudinal breakdown when the depletion region expands toward the drain end. At the same time, the thickness of the drift region at the source end is smaller than that of the drift region at the drain end, and thus the depletion region tends to extend further toward the drain end when the component is operating in a reverse withstand voltage state, making it easier to deplete from the source end to the drain end, and the drift region 130 can be completely depleted before longitudinal breakdown, controlling the breakdown point to the boundary between the drift region at the drain end and the embedded oxide layer. In this way, the breakdown voltage of the component can still be improved without increasing the thickness of the embedded oxide layer, and the breakdown voltage of the component can reach 1200V or more.

[0042] Referring to Figure 2a, in one embodiment of the present application, the LDMOS further includes a protective layer 136. The protective layer 136 is located in the drift region 130, has a conductivity type opposite to that of the drift region 130, and surrounds the corner formed by the first base surface and the stepped wall and the corner formed by the second base surface and the stepped wall. The protective layer 136 may be an integral structure as shown in Figure 2a, or it may be a structure that surrounds two corners, as shown in Figure 2b. By forming a protective layer with a conductivity type opposite to that of the drift region 130 at the stepped corner, premature breakdown of the component caused by the concentration of electric field lines at the stepped corner can be avoided.

[0043] In some embodiments of this application, the stepped structure of the drift region of the silicon-on-insulator semiconductor component can be formed using a reactive ion etching (RIE) method or a secondary epitaxial method. Referring to Figure 2c, a more "vertical" step in the drift region can be obtained with secondary epitaxial method. Figure 2c may also be an LDMOS formed using the secondary epitaxial method, the main difference from the structure shown in Figure 1 being that the step structure is steeper, and the specific structure will not be described in detail here. The structure shown in Figure 1 can be formed using a reactive ion etching method. Primary epitaxial vs. Reactive ion etching or secondary epitaxial method By realizing the stepped structure of the drift region proposed in this application, a 1200V silicon-on-insulator semiconductor process platform can be realized. Using a general primary epitaxial method, a 600V silicon-on-insulator semiconductor process platform can be realized. Therefore, the 1200V process platform proposed in this application is compatible with the 600V process platform and has good compatibility.

[0044] Figure 3 is a schematic cross-sectional view of a component in one embodiment in which the silicon-on-insulator semiconductor component is a lateral insulated gate bipolar transistor (LIGBT). The LIGBT includes a substrate 210, an embedded dielectric layer 220, a drift region 230, a first electrode 262, a second electrode 264, and a gate 266. The first electrode 262 is the emitter, and the second electrode 264 is the collector. One side of the upper surface of the drift region 230 that is close to the collector (hereinafter referred to as the high side of the drift region) is higher than the other side that is close to the emitter (hereinafter referred to as the low side of the drift region), thereby forming a drop structure 231.

[0045] In the embodiment shown in Figure 3, the LIGBT is an N-type LIGBT, the drift region 230 is an N-type drift region, and the LIGBT further includes a P-type first body region 234 and a second body region 236, as well as an N-well 232. The N-well 232 and the second body region 236 are located on the high side of the drift region, and the first body region 234 is located on the low side of the drift region. A first N+ region 242 and a first P+ region 246 are provided in the first body region 234, and the emitter 262 is electrically connected to the first N+ region 242 and the first P+ region 246. A second P+ region 248 is provided in the N-well 232, and a second N+ region 244 is provided in the second body region 236, and the collector 264 is electrically connected to the second N+ region 244, the second P+ region 248, and the second body region 236. In the embodiment shown in Figure 3, the gate 266 can extend from the low side of the drift region to the edge of the first N+ region 242 and have a certain area overlap with the first N+ region 242. When a reverse bias voltage is applied to the LIGBT, the collector is connected to a high voltage, and the emitter is connected to a low voltage or grounded.

[0046] In the embodiment shown in Figure 3, the LIGBT further includes a field oxide layer 247, which extends from the high side of the drift region to the low side of the drift region. A portion of the gate 266 extends onto the field oxide layer 247.

[0047] In one embodiment of this application, the LIGBT further includes an interlayer dielectric layer 250. The interlayer dielectric layer 250 covers structures such as a gate 266, a field oxide layer 247, a first N+ region 242, a first P+ region 246, a second N+ region 244, a second P+ region 248, and a second body region 236.

[0048] The stepped structure of the drift region of a LIGBT can similarly be formed using reactive ion etching or secondary epitaxial methods. Referring to Figure 4, a more "vertical" drift region step can be obtained by secondary epitaxial etching. The main difference between Figure 4 and Figure 3 is that the stepped structure is steeper, and its specific structure will not be described in detail. The structure shown in Figure 3 was formed using the reactive ion etching method, with a height difference H2 between the second and first surfaces being 3 to 10 microns, and the inclination angle θ2 of the stepped wall being 20 to 90 degrees.

[0049] In one embodiment of this application, the LIGBT further includes a protective layer. The protective layer is located in the drift region, has a conductivity opposite to that of the drift region, and surrounds the corner formed by the first base surface and the stepped wall and the corner formed by the second base surface and the stepped wall. The protective layer may be a single, integrated structure, or it may be a structure that surrounds each of the two corners.

[0050] Figure 5 is a schematic cross-sectional view of a diode in one embodiment in which the silicon-on-insulator semiconductor component is a diode. The diode includes a substrate 310, an embedded dielectric layer 320, a drift region 330, a first electrode 362, and a second electrode 364. The first electrode 362 is the anode, and the second electrode 364 is the cathode. One side of the upper surface of the drift region 330 that is close to the cathode (hereinafter referred to as the high side of the drift region) is higher than the other side that is close to the anode (hereinafter referred to as the low side of the drift region), thereby forming a drop structure 331.

[0051] The diode further includes a first electrode extraction region (i.e., anode region) 342 located on the low side of the drift region and a second electrode extraction region (i.e., cathode region) 344 located on the high side of the drift region. The first electrode 362 (i.e., anode) is located in and electrically connected to the first electrode extraction region 342. The second electrode 364 (i.e., cathode) is located in and electrically connected to the second electrode extraction region 344. When a reverse bias voltage is applied to the diode, the cathode is connected to a high voltage and the anode is connected to a low voltage or grounded.

[0052] In the embodiment shown in Figure 5, the drift region 330 is an N-type drift region, and the diode further includes an N-well 334 located on the high side of the drift region. The second electrode extraction region 344 is an N+ region and is located within the N-well 334. The first electrode extraction region 342 is a P+ region and is located on the low side of the drift region.

[0053] In the embodiment shown in Figure 5, the diode further includes a field oxide layer 347, which extends from the high drift region to the low drift region.

[0054] In one embodiment of this application, the diode further includes an interlayer dielectric layer 350. The interlayer dielectric layer 350 covers structures such as a field oxide layer 347, a first electrode extraction region 342, and a second electrode extraction region 344.

[0055] The stepped structure of the diode's drift region can similarly be formed using reactive ion etching or secondary epitaxial etching. Referring to Figure 6, a more "vertical" drift region step can be obtained by secondary epitaxial etching. The main difference between Figure 6 and Figure 5 is that the stepped structure is steeper, and its specific structure will not be described in detail. The structure shown in Figure 5 can be formed using reactive ion etching, with a height difference H3 between the second and first surfaces being 3 to 10 microns, and a step wall inclination angle θ3 being 20 to 90 degrees.

[0056] In one embodiment of this application, the diode further includes a protective layer. The protective layer is located in the drift region, has a conductivity type opposite to that of the drift region, and surrounds the corner formed by the first base surface and the stepped wall and the corner formed by the second base surface and the stepped wall. The protective layer may be a single, integrated structure, or it may be a structure that surrounds each of the two corners.

[0057] This application further provides a silicon-on-insulator semiconductor process platform, which includes silicon-on-insulator semiconductor components as described in any of the embodiments above, and further includes low-voltage components and / or passive components. In one embodiment of this application, the low-voltage component may be a Complementary Metal-Oxide-Semiconductor Field Effect Transistor (simply referred to as CMOS), and the passive component may be a well resistor. Figure 7 is a schematic cross-sectional view of a silicon-on-insulator semiconductor process platform in one embodiment of this application, in which the silicon-on-insulator semiconductor process platform includes an LDMOS, a LIGBT, a diode, a CMOS, and a well resistor. The structures of the LDMOS, LIGBT, and diode have been described above and will not be repeated here. Different components are isolated from each other by isolation structures. The height of the top surface of the drift region of the CMOS and well resistor structures is the same as the height of the drift region height side.

[0058] This application correspondingly provides a method for manufacturing a silicon-on-insulator semiconductor component, which can be used to manufacture the silicon-on-insulator semiconductor component described in any of the above embodiments. Figure 8 is a flowchart of a method for manufacturing a silicon-on-insulator semiconductor component in one embodiment of this application, in which the stepped structure of the drift region is formed by an etching method, and the manufacturing method includes the following steps.

[0059] In step S410, a wafer is acquired. The wafer includes a substrate, an embedded dielectric layer on the substrate, and a drift region on the embedded dielectric layer. The drift region can be formed epitaxially in the embedded oxide layer.

[0060] In step S420, a drop structure is formed on the upper surface of the drift region by photolithography and etching.

[0061] In the region where the photoresist is exposed, a drift region (epitaxial layer) of a certain thickness is etched, thereby making the thickness of the epitaxial layer in the etched region smaller than the thickness of the epitaxial layer in other parts. That is, the drop structure includes a first side, a second side, and a transition region between the first and second sides. The upper surface of the second side is higher than the lower surface of the first side, and thereafter, the thickness of the drift region on the second side is greater than the thickness on the first side.

[0062] In one embodiment of this application, etching is specifically performed using a reactive ion etching process, which provides good anisotropy and allows for the acquisition of a steep transition region. Furthermore, reactive ion etching has a fast etching rate and allows for precise control of the etching depth.

[0063] In step S430, the first electrode and the second electrode are formed.

[0064] The first side is the side adjacent to the first electrode, and the second side is the side adjacent to the second electrode.

[0065] The component formed by the above-described silicon-on-insulator semiconductor component manufacturing method has a structure in which the thickness of the drift region at the low-voltage end of the component is smaller than the thickness of the drift region at the high-voltage end (when a reverse bias voltage is applied). In this way, the breakdown point of the component can be controlled below the high-voltage end, completely depleting the drift region and improving the breakdown voltage of the component without increasing the thickness of the embedded oxide layer.

[0066] In one embodiment of this application, the step of forming a protective layer in the drift region of the stepped structure by ion implantation may be further included after step S420 and before step S430. The protective layer surrounds the corner formed by the first base surface and the stepped wall and the corner formed by the second base surface and the stepped wall. The conductivity type of the protective layer is opposite to that of the drift region. The protective layer may be a single structure or it may be a structure that surrounds two corners. In an embodiment in which the protective layer is a single structure, the length of the implantation window of the protective layer (the length direction is the length direction of the conductive channel) is 110% to 120% of the length of the transition region (the length direction is the length direction of the conductive channel). Figure 16 is a schematic cross-sectional view of a silicon-on-insulator semiconductor process platform in an embodiment in which a stepped structure of the drift region is formed using reactive ion etching, in which the protective layer is a single structure. In an embodiment where the protective layer has a structure that surrounds two corners, the length of each injection window in the protective layer is 5% to 10% of the length of the transition region.

[0067] Figure 9 is a flowchart of a method for manufacturing a silicon-on-insulator semiconductor component in another embodiment of the present application, in which the stepped structure of the drift region is formed using a secondary epitaxial method, and includes the following steps.

[0068] In step S510, a wafer is acquired.

[0069] The wafer includes a substrate, an embedded dielectric layer on the substrate, and a first epitaxial layer on the embedded dielectric layer.

[0070] In step S520, a second epitaxial layer is formed on a portion of the first epitaxial layer.

[0071] A portion of the surface of the first epitaxial layer is exposed by photolithography, and then epitaxial cutting is performed to form the second epitaxial layer in the exposed region. In this way, a drop structure is formed at the boundary between the first and second epitaxial layers, and this drop structure includes a first side on the second epitaxial layer side, a second side on the first epitaxial layer side, and a transition region between the first and second sides.

[0072] In step S530, the first electrode and the second electrode are formed.

[0073] In one embodiment of this application, the drop structure is a stepped structure, comprising a first platform located on the first side, a second platform located on the second side, and a stepped wall located in the transition region, wherein the height difference between the second platform and the first platform is 3 to 10 microns, and the inclination angle of the stepped wall is 20 to 90 degrees.

[0074] In one embodiment of this application, after step S520 and before step S530, the step of forming a protective layer in the drift region of the stepped structure by ion implantation may be further included. The protective layer surrounds the corner formed by the first base surface and the stepped wall and the corner formed by the second base surface and the stepped wall. The conductivity of the protective layer is opposite to that of the drift region. The protective layer may be a single structure or it may be a structure that surrounds two corners. In embodiments where the protective layer is a single structure, the length of the implantation window of the protective layer (the length direction is the length direction of the conductive channel) is 110% to 120% of the length of the transition region (the length direction is the length direction of the conductive channel). In embodiments where the protective layer surrounds two corners, the length of each implantation window of the protective layer is 5% to 10% of the length of the transition region. Figure 17 is a schematic cross-sectional view of a silicon-on-insulator semiconductor process platform in one embodiment in which a stepped structure in the drift region is formed using a secondary epitaxial layer, in which the protective layer has a structure that surrounds two corners.

[0075] Taking the manufacture of SOI LDMOS as an example, the structure after step S420 is as shown in Figure 11a. Referring to Figure 10, the method for manufacturing SOI LDMOS further includes the following steps after step S420.

[0076] In step S421, a P-type body region and an N-well are formed.

[0077] Referring to Figure 11b, the P-type body region 132 and N-well 134 can be formed by photolithography and ion implantation. The P-type body region 132 is formed on the first side of the drop structure, and the N-well 134 is formed on the second side of the drop structure.

[0078] In step S422, a field oxide layer is formed.

[0079] Referring to Figure 11c, a field oxide layer 147 is formed on the surface of the drift region 130, between the P-type body region 132 and the N-well 134. The field oxide layer 147 can be formed by deposition or thermal oxidation.

[0080] In step S423, a gate is formed.

[0081] In the embodiment shown in Figure 11d, the gate 166 extends from the P-type body region 132 to the field oxide layer 147. The material of the gate 166 may be polycrystalline silicon. The gate 166 can be formed by deposition, photolithography, and etching methods.

[0082] In step S424, the source region, drain region, and body lead-out region are formed.

[0083] Referring to Figure 11e, the N+ source region (i.e., the first electrode extraction region 142) is formed in the P-type body region 132, the N+ drain region (i.e., the second electrode extraction region 144) is formed in the N-well 134, and the P+ body extraction region 146 is formed in the P-type body region 132.

[0084] In step S425, an interlayer dielectric layer and contact holes are formed.

[0085] After depositing the interlayer dielectric layer 150, the interlayer dielectric layer 150 is etched to form contact holes. Then, step S430 is performed to form the first electrode 162 and the second electrode 164 to obtain the structure shown in Figure 1. The first electrode 162 is electrically connected to the N+ source region, and the second electrode 164 is electrically connected to the N+ drain region. Steps S421 to S425 above are applicable to an embodiment in which a stepped structure of the drift region is formed by reactive ion etching, as well as an embodiment in which a stepped structure of the drift region is similarly formed by secondary epitaxial etching, and the stepped structure formed by secondary epitaxial etching is steeper.

[0086] Taking the manufacture of an SOI LIGBT as an example, the structure after step S420 is as shown in Figure 13a. Referring to Figure 12, the method for manufacturing an SOI LIGBT further includes the following steps after step S420.

[0087] In step S621, the first body region and the N well are formed.

[0088] Referring to Figure 13b, the first body region 234 and the N well 232 can be formed by photolithography and ion implantation. The first body region 234 is formed on the first side of the drop structure, and the N well 232 is formed on the second side of the drop structure.

[0089] In step S622, a field oxide layer is formed.

[0090] Referring to Figure 13c, a field oxide layer 247 is formed between the first body region 234 and the N well 232 on the surface of the drift region 130. The field oxide layer 247 can be formed by deposition or thermal oxidation.

[0091] In step S623, a gate is formed.

[0092] In the embodiment shown in Figure 13d, the gate 266 extends from the first body region 234 to the field oxide layer 247. The material of the gate 266 may be polycrystalline silicon. The gate 266 can be formed by deposition, photolithography, and etching methods.

[0093] In step S624, a first N+ region, a second N+ region, a first P+ region, a second P+ region, and a second body region are formed.

[0094] Referring to Figure 13e, the first N+ region 242 and the first P+ region 246 are formed in the first body region 234. The second P+ region 248 is formed in the N well 232, and the second N+ region 244 is formed in the second body region 236.

[0095] In step S625, an interlayer dielectric layer and contact holes are formed.

[0096] After depositing the interlayer dielectric layer 250, the interlayer dielectric layer 250 is etched to form contact holes. Then, step S430 is performed to form the first electrode 262 and the second electrode 264 to obtain the structure shown in Figure 3. The first electrode 262 is electrically connected to the first N+ region 242 and the first P+ region 246, and the second electrode 264 is electrically connected to the second P+ region 248, the second N+ region 244 and the second body region 236. Steps S621 to S625 above are applicable to an embodiment in which a stepped structure of the drift region is formed by reactive ion etching, as well as to an embodiment in which a stepped structure of the drift region is similarly formed by secondary epitaxial etching, and the stepped structure formed by secondary epitaxial etching is steeper.

[0097] Taking the manufacture of an SOI diode as an example, the structure after step S420 is as shown in Figure 15a. Referring to Figure 14, the method for manufacturing an SOI diode includes the following steps after step S420.

[0098] In step S721, N wells are formed.

[0099] Referring to Figure 15b, the N-well 334 can be formed by photolithography and ion implantation. The N-well 334 is formed on the second side of the drop structure.

[0100] In step S722, a field oxide layer is formed.

[0101] Referring to Figure 15c, a field oxide layer 347 is formed on the surface of the drift region 330. The field oxide layer 347 can be formed by deposition or thermal oxidation.

[0102] In step S723, an anode region and a cathode region are formed.

[0103] Referring to Figure 15d, the N+ cathode region (i.e., the second electrode extraction region 344) is located in the N well 334, and the P+ anode region (i.e., the first electrode extraction region 342) is formed on the first side of the drop structure.

[0104] In step S724, an interlayer dielectric layer and contact holes are formed.

[0105] After depositing the interlayer dielectric layer 350, the interlayer dielectric layer 350 is etched to form contact holes. Then, step S430 is performed to form the first electrode 362 and the second electrode 364 to obtain the structure shown in Figure 5. The first electrode 362 is electrically connected to the P+ anode region, and the second electrode 364 is electrically connected to the N+ cathode region. Steps S721 to S724 above are applicable to an embodiment in which a stepped structure of the drift region is formed by reactive ion etching, as well as to an embodiment in which a stepped structure of the drift region is similarly formed by secondary epitaxial etching, and the stepped structure formed by secondary epitaxial etching is steeper.

[0106] In the flowchart of this application, each step is shown sequentially according to the arrows, but these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise expressly described herein, the execution of these steps is not limited to a strict order, and these steps may be performed in other orders. Furthermore, at least some steps in the flowchart of this application may include multiple steps or stages, and these steps or stages are not necessarily performed and completed at the same time, but may be performed at different times, and the execution of these steps or stages is not necessarily sequential, but may be performed sequentially or alternately with other steps or at least some of the steps or stages in other steps.

[0107] In this specification, any description referring to terms such as “several examples,” “other examples,” or “ideal examples” means that the specific features, structures, materials, or characteristics described by reference to such examples are included in at least one example of this application. In this specification, illustrative descriptions of the above terms do not necessarily refer to the same examples.

[0108] Each of the technical features of the above embodiments can be combined in any way, and for the sake of brevity, not all possible combinations of each of the technical features in the above embodiments are described. However, as long as these combinations of technical features are inconsistent, they should be considered to fall within the scope described herein.

[0109] The above embodiments are merely examples of some of the embodiments of this application, and although the descriptions are specific and detailed, they should not be understood as limiting the scope of the patent application. Furthermore, those skilled in the art can make several further modifications and improvements without departing from the concept of this application, and all of these fall within the scope of protection of this application. Therefore, the scope of protection of the patent application should be based on the attached claims.

Claims

1. A silicon-on-insulator semiconductor component comprising a substrate, an embedded dielectric layer, a first electrode, a second electrode, and a drift region, The embedded dielectric layer is provided on the substrate, The drift region is provided on the embedded dielectric layer, and a drop structure is formed on the upper surface of the drift region, the drop structure includes a first side adjacent to the first electrode, a second side adjacent to the second electrode, and a transition region between the first side and the second side, the upper surface of the second side is higher than the lower surface of the first side, and thereafter the thickness of the drift region on the second side is greater than the thickness of the drift region on the first side. The aforementioned drop structure is a stepped structure and includes a first platform located on the first side, a second platform located on the second side, and a stepped wall located in the transition region. A silicon-on-insulator semiconductor component characterized in that the drift region has a first conductivity type, the component further includes a protective layer of a second conductivity type, the protective layer of the second conductivity type is located in the drift region and surrounds the corner formed by the first base surface and the stepped wall and the corner formed by the second base surface and the stepped wall, and the first conductivity type and the second conductivity type are opposite conductivity types.

2. The silicon-on-insulator semiconductor component according to claim 1, wherein the component is a transversely double-diffusion metal-oxide-semiconductor field-effect transistor, the first electrode is a source, the second electrode is a drain, and the transversely double-diffusion metal-oxide-semiconductor field-effect transistor further includes a gate.

3. The silicon-on-insulator semiconductor component according to claim 1, characterized in that the component is a lateral insulated-gate bipolar transistor, the first electrode is an emitter, the second electrode is a collector, and the lateral insulated-gate bipolar transistor further includes a gate.

4. The silicon-on-insulator semiconductor component according to claim 1, characterized in that the component is a diode, the first electrode is an anode, and the second electrode is a cathode.

5. The silicon-on-insulator semiconductor component according to Claim 1, characterized in that the height difference between the second base surface and the first base surface is 3 to 10 microns.

6. The silicon-on-insulator semiconductor component according to claim 5, characterized in that the inclination angle of the stepped wall is 20 degrees to 90 degrees.

7. The silicon-on-insulator semiconductor component according to claim 5, further comprising a first electrode extraction region and a second electrode extraction region, wherein the first electrode extraction region and the second electrode extraction region are provided on the embedded dielectric layer.

8. The silicon-on-insulator semiconductor component according to claim 7, further comprising a field oxide layer, wherein the field oxide layer extends from a second side adjacent to the second electrode on the upper surface of the drift region to a first side adjacent to the first electrode.

9. The silicon-on-insulator semiconductor component according to claim 8, further comprising an interlayer dielectric layer, wherein the interlayer dielectric layer covers at least the field oxide layer, the first electrode extraction region, and the second electrode extraction region.

10. A silicon-on-insulator semiconductor component comprising a substrate, an embedded dielectric layer, a first electrode, a second electrode, and a drift region, The embedded dielectric layer is provided on the substrate, The drift region is provided on the embedded dielectric layer, and a drop structure is formed on the upper surface of the drift region, the drop structure includes a first side adjacent to the first electrode, a second side adjacent to the second electrode, and a transition region between the first side and the second side, the upper surface of the second side is higher than the lower surface of the first side, and thereafter the thickness of the drift region on the second side is greater than the thickness of the drift region on the first side. A silicon-on-insulator semiconductor component characterized in that the component is a diode, the first electrode is an anode, and the second electrode is a cathode.

11. A silicon-on-insulator semiconductor process platform comprising a silicon-on-insulator semiconductor component according to any one of claims 1 to 10, further comprising at least one of a complementary metal-oxide-semiconductor field-effect transistor and a well resistor.

12. A method for manufacturing silicon-on-insulator semiconductor components, A step of obtaining a wafer including a substrate, an embedded dielectric layer on the substrate, and a drift region on the embedded dielectric layer, A step of forming a drop structure on the upper surface of the drift region by photolithography and etching, wherein the drop structure includes a first side, a second side, and a transition region between the first side and the second side, and the upper surface of the second side is higher than the lower surface of the first side, thereby the thickness of the drift region on the second side is greater than the thickness of the drift region on the first side. The steps of forming a first electrode and a second electrode include the step of the first side being one side adjacent to the first electrode and the second side being one side adjacent to the second electrode, The aforementioned drop structure is a stepped structure, comprising a first base surface located on the first side, a second base surface located on the second side, and a stepped wall located in the transition region, and before forming the first electrode and the second electrode, the method further, A method for manufacturing a silicon-on-insulator semiconductor component, characterized by forming a protective layer in the drift region of the stepped structure by ion implantation, wherein the protective layer surrounds the corner formed by the first base surface and the stepped wall and the corner formed by the second base surface and the stepped wall.

13. The method for manufacturing a silicon-on-insulator semiconductor component according to claim 12, characterized in that the etching is a reactive ion etching process.

14. A method for manufacturing a silicon-on-insulator semiconductor component, A step of obtaining a wafer including a substrate, an embedded dielectric layer on the substrate, and a drift region on the embedded dielectric layer, A step of forming a drop structure on the upper surface of the drift region by photolithography and etching, wherein the drop structure includes a first side, a second side, and a transition region between the first side and the second side, and the upper surface of the second side is higher than the lower surface of the first side, thereby the thickness of the drift region on the second side is greater than the thickness of the drift region on the first side. The steps of forming a first electrode and a second electrode include the step of the first side being one side adjacent to the first electrode and the second side being one side adjacent to the second electrode, A method for manufacturing a silicon-on-insulator semiconductor component, characterized in that the component is a diode, the first electrode is an anode, and the second electrode is a cathode.

15. A method for manufacturing silicon-on-insulator semiconductor components, A step of obtaining a wafer including a substrate, an embedded dielectric layer on the substrate, and a first epitaxial layer on the embedded dielectric layer, The steps include forming a second epitaxial layer in a portion of the first epitaxial layer, and forming a drop structure at the boundary between the first epitaxial layer and the second epitaxial layer, which includes a first side on the second epitaxial layer side, a second side on the first epitaxial layer side, and a transition region between the first side and the second side. A method for manufacturing a silicon-on-insulator semiconductor component, characterized by comprising the step of forming a first electrode and a second electrode, wherein the first side is one side adjacent to the first electrode and the second side is one side adjacent to the second electrode.

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