Information processing system

Abstract

If a first encryption key is stored in a nonvolatile memory (23), an erase controller (14) compresses data read from a designated position of a storage area to generate first sample data. The erase controller (14) controls a storage device (13) to change the first encryption key stored in the nonvolatile memory (23) into a second encryption key. When the second encryption key is stored in the nonvolatile memory (23), the erase controller (14) compresses the data read from the designated position of the storage area to generate second sample data. If the second sample data is different from the first sample data, the erase controller (14) outputs a verification result indicating that the data stored in the storage device (13) has been successfully erased. Otherwise, the erase controller (14) outputs a verification result indicating that the data stored in the storage device (13) has failed to be erased.

Description

Information Processing Systems

[0001] The present disclosure relates to an information processing device, an information processing method, an information processing system, and a program.

[0002] When discarding an information processing device such as a personal computer, in order to prevent leakage of confidential data, it is necessary to erase the data stored in the storage device (or equivalently, make the data inaccessible) and verify that the data has been securely erased. For example, Patent Document 1 and Non-Patent Document 1 disclose methods for verifying data erasure.

[0003] Patent No. 7096829

[0004] Richard Kissel et al., "Guidelines for Media Sanitization," NIST Special Publication 800-88, Revision 1, National Institute of Standards and Technology, December 2014 [Retrieved December 1, 2022], Internet <URL: http: / / dx.doi.org / 10.6028 / NIST.SP.800-88r1>

[0005] Conventionally, to verify whether data erasure was successful, the current data stored in the storage device after erasure (e.g., pattern data or random data overwritten on the original data) is compared with the original data stored in the storage device before erasure. In this case, a large amount of data is compared, which places a heavy load on the information processing device. Therefore, it is required to verify whether data erasure was successful with a smaller load than conventional methods.

[0006] The present disclosure provides an information processing device, an information processing method, an information processing system, and a program that can verify whether data stored in a storage device has been successfully erased with a smaller load than conventional methods.

[0007] An information processing device according to one aspect of the present disclosure is an information processing device according to a first aspect of the present disclosure, comprising: a storage device having a self-encryption function for data to be stored; and an erasure controller that controls erasure of data stored in the storage device, wherein the storage device comprises: a storage medium having a storage area; a non-volatile memory that stores an encryption key; and an input / output controller that writes input data to the storage area, outputs data read from the storage area, encrypts at least a portion of the data to be written to the storage area using the encryption key, and decrypts at least a portion of the data read from the storage area using the encryption key, wherein the erasure controller controls the storage device to compress data read from a specified position in the storage area to generate first sample data, if a first encryption key is stored in the non-volatile memory, change the first encryption key stored in the non-volatile memory to a second encryption key, compress data read from the specified position in the storage area to generate second sample data, if the second encryption key is stored in the non-volatile memory, and output a verification result indicating that the erasure of the data stored in the storage device was successful, If the second sample data matches the first sample data, a verification result indicating that erasure of the data stored in the storage device has failed is output.

[0008] According to an information processing device according to an aspect of the present disclosure, it is possible to verify whether data stored in a storage device has been successfully erased with a smaller load than conventionally required.

[0009] 1 is a block diagram showing the configuration of an information processing device 1 according to a first embodiment. 2 is a block diagram showing the configuration of a storage device 13 of FIG. 1. 3 is a schematic diagram showing logical blocks 31 of the flash memory 24 of FIG. 2, showing an example of an arrangement of logical blocks 31 to be compared to verify erasure of data. 4 is a flowchart showing an erasure process according to a first comparative example. 5 is a flowchart showing an erasure process according to a second comparative example. 6 is a flowchart showing an erasure process according to a first embodiment executed by the erasure controller 14 of FIG. 1. 7 is a schematic diagram showing logical blocks 31 of the flash memory 24 of FIG. 2, showing a first modified example of an arrangement of logical blocks 31 to be compared to verify erasure of data. 8 is a schematic diagram showing logical blocks 31 of the flash memory 24 of FIG. 2, showing a second modified example of an arrangement of logical blocks 31 to be compared to verify erasure of data. 9 is a flowchart showing an erasure process according to a second embodiment executed by the erasure controller 14 of FIG. 1. 10 is a flowchart showing an erasure process according to a third embodiment executed by the erasure controller 14 of FIG. 1. 11 is a flowchart showing an erasure process according to a fourth embodiment executed by the erasure controller 14 of FIG. 1. 12 is a flowchart showing an erasure process according to a fifth embodiment executed by the erasure controller 14 of FIG. 1. 13 is a flowchart showing an erasure process according to a sixth embodiment executed by the erasure controller 14 of FIG. 1. 16 is a flowchart showing erasure processing according to a seventh embodiment executed by the erasure controller 14 of FIG. 1. FIG. 17 is a flowchart showing erasure processing according to an eighth embodiment executed by the erasure controller 14 of FIG. 1. FIG. 18 is a block diagram showing the configuration of an information processing device 1A according to a modified example of the first embodiment. FIG. 19 is a flowchart showing erasure processing according to a ninth embodiment executed by the erasure controller 14 of FIG. 16. FIG. 20 is a flowchart showing erasure processing performed by an information processing device 1 according to a second embodiment. FIG. 21 is a flowchart showing a subroutine of the pre-processing (step S101) of FIG. 18. FIG. 22 is a flowchart showing a subroutine of the key change processing (step S102) of FIG. 18. FIG. 23 is a flowchart showing a subroutine of the verification processing (step S103) of FIG. 18.27 is a diagram showing an example of an image indicating the progress of data erasure, which is displayed on the display device 18 of FIG. 1 by executing the erasure process of FIG. 18. FIG. 28 is a diagram showing another example of an image indicating the progress of data erasure, which is displayed on the display device 18 of FIG. 1 by executing the erasure process of FIG. 18. FIG. 29 is a flowchart showing a first modified example of the verification process of FIG. 18. FIG. 30 is a flowchart showing a second modified example of the verification process of FIG. 18. FIG. 31 is a flowchart showing a third modified example of the verification process of FIG. 18. FIG. 32 is a block diagram showing a configuration of an information processing system including an information processing device 1 and a server device according to a third embodiment. FIG. 33 is a block diagram showing a configuration of the server device 2 of FIG. 27. FIG. 34 is a flowchart showing the erasure process executed by the server device 2 of FIG. 27. FIG. 35 is a flowchart showing the erasure process executed by the information processing device 1 of FIG. 27. FIG. 36 is a flowchart showing a modified example of the erasure process executed by the server device 2 of FIG. 27. FIG. 37 is a flowchart showing a subroutine of the pre-processing (step S231) of FIG. 32. FIG. 38 is a flowchart showing a subroutine of the key change process (step S232) of FIG. 32. FIG. 39 is a flowchart showing a subroutine of the verification process (step S233) of FIG. 32.

[0010] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, more detailed description than necessary may be omitted. For example, detailed description of well-known matters or redundant description of substantially identical configurations may be omitted. This is to avoid unnecessary redundancy in the following description and to facilitate understanding by those skilled in the art.

[0011] The inventor(s) provide the accompanying drawings and the following description to enable those skilled in the art to fully understand the present disclosure, and do not intend for them to limit the subject matter described in the claims.

[0012] 1 is a block diagram showing the configuration of an information processing device 1 according to embodiment 1. The information processing device 1 includes a bus 10, a central processing unit (CPU) 11, a random access memory (RAM) 12, a storage device 13, an erasure controller 14, a non-volatile memory 15, a communication device 16, an input device 17, and a display device 18.

[0013] The CPU 11 controls the overall operation of the information processing device 1 .

[0014] The RAM 12 temporarily stores programs and data necessary for the operation of the information processing device 1 .

[0015] The storage device 13 stores data including an operating system, application programs, and user data. The storage device 13 is a self-encrypting drive (SED) that has a function of self-encrypting the data stored therein, such as a solid-state drive (SSD) that has a function of self-encrypting.

[0016] The erasure controller 14 controls erasure of data stored in the storage device 13 by executing an erasure process described later with reference to Fig. 6 etc. In the present disclosure, "erasure" means making at least a portion of data stored in the storage device 13 inaccessible. The erasure controller 14 includes, for example, a microprocessor.

[0017] The nonvolatile memory 15 stores programs and data required for executing the erasure process. The nonvolatile memory 15 includes a nonvolatile storage medium such as a flash memory.

[0018] The program for the erasure process may be incorporated into a firmware program of the information processing device 1, such as a UEFI (Unified Extensible Firmware Interface) or BIOS (Basic Input / Output System) program. In this case, the program for the erasure process may be stored in the same storage medium as the UEFI or BIOS program, and may be executed by the same microprocessor as the UEFI or BIOS program.

[0019] The communication device 16 is connected to other external information processing devices via a communication line such as a local area network (LAN) so as to be able to communicate with them.

[0020] The input device 17 receives user inputs that control the operation of the information processing device 1. The input device 17 includes, for example, a keyboard and a pointing device.

[0021] The display device 18 displays information related to the state of the information processing device 1 , for example, information related to erasure of data stored in the storage device 13 .

[0022] The CPU 11 , RAM 12 , storage device 13 , erasure controller 14 , non-volatile memory 15 , communication device 16 , input device 17 , and display device 18 are connected to one another via a bus 10 .

[0023] The information processing device 1 is, for example, a personal computer.

[0024] FIG. 2 is a block diagram showing the configuration of the storage device 13 in FIG. 1. The storage device 13 includes an input / output controller 21, a random access memory (RAM) 22, a nonvolatile memory 23, and a flash memory 24. The input / output controller 21 controls the writing and reading of data to and from the storage device 13. The RAM 22 is a buffer memory that temporarily stores data to be written to and read from the storage device 13. The nonvolatile memory 23 stores a firmware program (FW) and an encryption key for the storage device 13. The flash memory 24 is a nonvolatile storage medium having a storage area. The input / output controller 21 controls the operation of the storage device 13 by executing the firmware program stored in the nonvolatile memory 23. The input / output controller 21 writes input data to the storage area of ​​the flash memory 24 and outputs data read from the storage area.

[0025] As described above, the storage device 13 has a self-encryption function. The storage device 13 may encrypt and decrypt data stored in the entire storage area of ​​the flash memory 24, or may encrypt and decrypt only data stored in a portion of the storage area. The input / output controller 21 encrypts at least a portion of the data to be written to the storage area of ​​the flash memory 24 using an encryption key stored in the non-volatile memory 23. The input / output controller 21 also decrypts at least a portion of the data read from the storage area of ​​the flash memory 24 using the encryption key. The input / output controller 21 may use hardware, software, or a combination thereof to encrypt and decrypt data.

[0026] By including such a storage device 13, the information processing device 1 can encrypt and decrypt data stored in the storage device 13 without relying on an operating system or application program.

[0027] In a storage device 13 having a self-encrypting function, when the encryption key is changed, data encrypted with the previous encryption key and stored in a storage area of ​​the flash memory 24 cannot be decrypted using the changed encryption key. Therefore, by changing the encryption key of the storage device 13, the original data stored in the storage device 13 becomes inaccessible, and the original data stored in the storage device 13 can be equivalently erased (cryptographically erased). The input / output controller 21 changes the encryption key stored in the non-volatile memory 23 under the control of the erasure controller 14. The encryption key may be changed, for example, by the input / output controller 21 executing a revert command included in the firmware of the storage device 13.

[0028] As described above, if only data stored in a portion of the storage area is encrypted and decrypted, the data that is not encrypted or decrypted will not become inaccessible even if the encryption key is changed, and therefore will not be erased. To verify whether the data has been successfully erased, the erasure controller 14 compares the current data stored in the storage device 13 after the encryption key has been changed with the original data that was stored in the storage device 13 before the encryption key was changed. If the current data is different from the original data, the erasure controller 14 determines that the data has been successfully erased, and if the current data matches the original data, the erasure controller 14 determines that the data has not been erased.

[0029] FIG. 3 is a schematic diagram showing logical blocks 31 of the flash memory 24 of FIG. 2 , illustrating an example of the arrangement of logical blocks 31 compared to verify data erasure. The storage area of ​​the flash memory 24 includes multiple logical blocks 31. Each logical block 31 is a partial area logically divided from the storage area. For example, a 1 TB storage area may be divided into 10,000 logical blocks 31, each having a size of 100 MB. To verify whether data erasure was successful, the erasure controller 14 may compare data before and after the encryption key change for the entire storage area, or may compare only a portion of the storage area (e.g., 1,000 logical blocks 31 equivalent to 10% of the entire storage area). In the latter case, the logical blocks 31 to be compared may be specified according to a predetermined rule (e.g., the hatched logical blocks 31 in FIG. 3 ) or may be specified randomly.

[0030] Although the storage area of ​​the flash memory 24 is shown two-dimensionally in FIG. 3 and other figures, the storage area may be considered as a continuous memory space.

[0031] [Comparative Example] Here, verification of data erasure according to the conventional technique will be described with reference to Fig. 4 and Fig. 5. For the purpose of explanation, it is assumed that the information processing device 1 of Fig. 1 executes the erasure process shown in Fig. 4 and Fig. 5.

[0032] 4 is a flowchart showing the erasure process according to Comparative Example 1. FIG. 4 shows the method of verifying data erasure disclosed in Non-Patent Document 1.

[0033] The erasure process shown in FIG. 4 is started when an instruction to erase data stored in the storage device 13 is issued via the BIOS or UEFI program, for example.

[0034] In step S1, the erasure controller 14 reads the original data from a specified logical block 31, as shown in FIG. 3 . Here, “original data” refers to data read from a specified logical block 31 in the storage area when the pre-change encryption key is stored in the non-volatile memory 23. If this logical block 31 is the target of encryption and decryption, the erasure controller 14 acquires data decrypted using the pre-change encryption key. On the other hand, if this logical block 31 is not the target of encryption and decryption, the erasure controller 14 acquires the data read from the logical block 31 as is without decrypting it. Generally, for example, if the RAM 12 has a size of several GB to several tens of GB, the storage device 13 has a storage area of ​​1 TB, and 10% of the storage area, i.e., 100 GB of data, is read, it is not possible to store all of that data in the RAM 12. Therefore, in step S2, the erasure controller 14 transmits the original data to an external information processing device to temporarily save it.

[0035] In step S3, the erasure controller 14 changes the encryption key stored in the nonvolatile memory 23. In this specification, the encryption key before the change is also referred to as the "first encryption key," and the encryption key after the change is also referred to as the "second encryption key."

[0036] In step S4, the erasure controller 14 reads the current data of the specified logical block 31, the same as in step S1. Here, "current data" refers to data read from the specified logical block 31 of the storage area when the changed encryption key is stored in the non-volatile memory 23. If this logical block 31 is to be encrypted and decrypted, the erasure controller 14 obtains data decrypted using the changed encryption key. On the other hand, if this logical block 31 is not to be encrypted or decrypted, the erasure controller 14 obtains the data read from the logical block 31 without decrypting it.

[0037] In step S5, the erasure controller 14 receives the temporarily saved original data from the external information processing device.

[0038] In step S6, the erasure controller 14 determines whether the current data is different from the original data, and if YES, proceeds to step S7, and if NO, proceeds to step S8. Here, the current data and the original data are compared for each logical block 31, so this can be performed using a RAM 12 having a size of several GB to several tens of GB.

[0039] In step S7, the erasure controller 14 outputs a verification result indicating that the data erasure was successful to the display device 18. In step S8, the erasure controller 14 outputs a verification result indicating that the data erasure was unsuccessful to the display device 18.

[0040] 4 requires an external information processing device to temporarily save the data because it compares a large amount of data that cannot be stored in the RAM 12. Therefore, a method for verifying data erasure that can be executed by the information processing device 1 alone without requiring an external information processing device is required.

[0041] 5 is a flowchart showing an erasure process according to Comparative Example 2. FIG. 5 shows the method of verifying data erasure disclosed in Patent Document 1.

[0042] In step S11, the erasure controller 14 writes known pattern data to a specified logical block 31, for example, as shown in FIG. 3. The pattern data includes, for example, a bit string consisting of all 1s, a bit string consisting of all 0s, a random bit string, etc. The pattern data is pre-stored in the non-volatile memory 15. The pattern data is encrypted using the encryption key before being changed and written to the specified logical block 31 in the storage area.

[0043] In step S12 , the erasure controller 14 changes the encryption key stored in the nonvolatile memory 23 .

[0044] In step S13, the erase controller 14 reads the current data in the same designated logical block 31 as in step S11.

[0045] In step S14, the erase controller 14 determines whether the current data is different from the pattern data, and if YES, the process proceeds to step S15, and if NO, the process proceeds to step S16.

[0046] In step S15, the erasure controller 14 outputs a verification result indicating that the data erasure was successful to the display device 18. In step S16, the erasure controller 14 outputs a verification result indicating that the data erasure was unsuccessful to the display device 18.

[0047] As described above, the pattern data is written to the specified logical block 31 of the storage area when the encryption key before the change is stored in the nonvolatile memory 23. Therefore, the pattern data essentially corresponds to the "original data" in the process of Fig. 4, i.e., the data read from the specified logical block 31 of the storage area when the encryption key before the change is stored in the nonvolatile memory 23.

[0048] 5 uses known pattern data and can be executed by the information processing device 1 alone, without the need for an external information processing device. However, like the process in Fig. 4, the process in Fig. 5 compares a large amount of data, placing a heavy load on the information processing device 1. Therefore, there is a need for an erasure process that can verify whether data erasure has been successful with a smaller load.

[0049] Next, an erasure process according to an embodiment will be described, which can verify whether data has been successfully erased with a smaller load.

[0050] First Embodiment FIG. 6 is a flowchart showing an erasure process according to a first embodiment, which is executed by the erasure controller 14 of FIG.

[0051] In step S21, the erasure controller 14 reads the original data of a specified logical block 31, for example, as shown in Fig. 3. Next, in step S22, the erasure controller 14 compresses the original data using a predetermined compression algorithm. Since the power supply of the information processing device 1 is not turned off during the execution of the process of Fig. 6 (especially before and after the encryption key is changed), the compressed original data may be stored in the RAM 12.

[0052] In step S23, the erasure controller 14 changes the encryption key stored in the nonvolatile memory 23.

[0053] In step S24, the erase controller 14 reads the current data in the same designated logical block 31 as in step S21.

[0054] In step S25, the erasure controller 14 reads out the compressed original data and decompresses it.

[0055] In step S26, the erasure controller 14 determines whether the current data is different from the original data based on the current data and the original data obtained in steps S24 to S25, and if the answer is YES, proceeds to step S27, and if the answer is NO, proceeds to step S28.

[0056] In step S27, the erasure controller 14 outputs a verification result indicating that the data erasure was successful to the display device 18. In step S28, the erasure controller 14 outputs a verification result indicating that the data erasure was unsuccessful to the display device 18.

[0057] According to the process of Fig. 6, it is not necessary to temporarily save data to an external information processing device. Furthermore, in general, writing data takes longer than reading data in a solid state drive. According to the process of Fig. 6, since it is not necessary to write pattern data to the storage device 13, it is possible to shorten the processing time compared to the case of Fig. 5. Thus, according to the first embodiment, it is possible to verify whether data erasure has been successful with a small load.

[0058] According to the process of Figure 4, for example, if data stored in a storage device with a storage capacity of 256 GB is erased and data before and after the encryption key change is compared using 10% of the storage area, 25.6 GB of original data must be temporarily saved. Similarly, according to the process of Figure 4, for storage devices with storage capacities of 512 GB, 1 TB, and 2 TB, 51.2 GB, 100 GB, and 200 GB of original data must be temporarily saved. On the other hand, according to the process of Figure 6, for example, if data stored in a storage device with a storage capacity of 256 GB is erased and data before and after the encryption key change is compared using 10% of the storage area, using a compression algorithm that compresses the data size by 40%, the compressed original data will be 10 GB. Similarly, according to the process of Figure 6, for storage devices with storage capacities of 512 GB, 1 TB, and 2 TB, the compressed original data will be 20 GB, 40 GB, and 80 GB, respectively. 6 is executed on a commercially available personal computer equipped with a standard RAM and storage device, the compressed original data can be stored in RAM, which allows verification of whether the data has been successfully erased with a small load, without the need to temporarily save the data to an external information processing device.

[0059] When the logical blocks 31 to be compared are randomly specified, it is necessary to further store the addresses of the logical blocks 31. When the storage area is divided into 10,000 or 1,000 logical blocks 31, the address (0 to 9999 or 0 to 999) of each logical block 31 is represented by two bytes. Therefore, when reading and verifying data from 1,000, 500, 100, or 50 logical blocks 31, the total size of the addresses to be stored will be 2,000 bytes, 1,000 bytes, 200 bytes, or 100 bytes. In either case, the size of the addresses to be stored is relatively small.

[0060] FIG. 7 is a schematic diagram showing logical blocks 31 of the flash memory 24 of FIG. 2, illustrating a first modified example of the arrangement of logical blocks 31 compared to verify data erasure. The storage area may include multiple partial areas 24a-1 to 24a-2, each of which is a logical division of the storage area and includes multiple logically contiguous logical blocks 31. In the example of FIG. 7, the partial area 24a-1 has a logical address smaller than the logical address of the partial area 24a-2. The erasure controller 14 may specify a different proportion of the logical blocks 31 for each of the partial areas 24a-1 to 24a-2 (e.g., the hatched logical blocks 31 in FIG. 7). Important files of the information processing device 1 (e.g., confidential data such as a login password for the information processing device 1) are likely to be stored in logical blocks 31 with smaller logical addresses. Therefore, the erasure controller 14 may specify a larger proportion of logical blocks 31 in the partial area 24a-1 than in the partial area 24a-2. By specifying logical blocks 31 as shown in Figure 7, it is possible to more reliably verify the erasure of data stored in an area that is thought to contain important files of the information processing device 1.

[0061] The storage area of ​​the storage device 13 is not limited to the two partial areas 24a-1 and 24a-2, but may be divided into three or more partial areas.

[0062] 8 is a schematic diagram showing logical blocks 31 of the flash memory 24 of FIG. 2, illustrating a second variation of the arrangement of the logical blocks 31 to be compared to verify the erasure of data. The erasure controller 14 may specify multiple logical blocks 31 that are logically adjacent to each other (for example, the hatched logical blocks 31 in FIG. 8).

[0063] Second Embodiment FIG. 9 is a flowchart showing an erasure process according to a second embodiment, which is executed by the erasure controller 14 of FIG.

[0064] In step S31, the erasure controller 14 reads the original data of the specified logical block 31, for example, as shown in Figure 3, 7, or 8. Then, in step S32, the erasure controller 14 compresses the original data using a predetermined compression algorithm. In the second embodiment, the compressed original data constitutes first sample data.

[0065] In step S33, the erasure controller 14 changes the encryption key stored in the nonvolatile memory 23.

[0066] In step S34, the erasure controller 14 reads the current data in the same specified logical block 31 as in step S31. Then, in step S35, the erasure controller 14 compresses the current data using the same compression algorithm as that used to compress the original data. In the second embodiment, the compressed current data constitutes the second sample data.

[0067] In step S36, the erasure controller 14 determines whether the compressed current data is different from the compressed original data without expanding the compressed original data and the current data, and if YES, proceeds to step S37, and if NO, proceeds to step S38.

[0068] If the compressed data is not decompressed, a lossy compression algorithm may be used. When a lossy compression algorithm is used, there is a possibility that the compressed data of different data will match. However, it is considered extremely unlikely that the compressed original data and the compressed current data will match in all compared logical blocks 31. Therefore, for example, when comparing compressed data in 1,000 logical blocks 31, even if the compressed data matches in only a few logical blocks 31, the erasure controller 14 may determine that the data erasure has been successful. Furthermore, if the compressed data differs in more than half of the logical blocks 31, the erasure controller 14 may determine that the data erasure has been successful.

[0069] Furthermore, if the compressed original data and the compressed current data match in several adjacent logical blocks 31, the erasure controller 14 may determine that the data erasure has failed. In this case, it is considered that the area including these logical blocks 31 is not subject to encryption and decryption.

[0070] In step S37, the erasure controller 14 outputs a verification result indicating that the data erasure was successful to the display device 18. In step S38, the erasure controller 14 outputs a verification result indicating that the data erasure was unsuccessful to the display device 18.

[0071] If two pieces of data are different, then the two compressed versions of the data will generally also be different. Therefore, the compressed original data and the current data can be compared to each other without decompression. According to the process of Figure 9, by comparing the compressed original data and the current data, the processing time and the size of the RAM 12 required for the processing can be reduced compared to comparing the uncompressed original data and the current data.

[0072] Third Embodiment Fig. 10 is a flowchart showing an erasure process according to a third embodiment, which is executed by the erasure controller 14 of Fig. 1. The process of Fig. 10 includes steps S41 to S43 instead of step S36 of Fig. 9.

[0073] In step S41, the erasure controller 14 extracts one or more predetermined portions from the original data compressed in step S32. The predetermined portions include, for example, the first 10 bytes of the original data. It is not necessary to retain the entire compressed original data; only the extracted portions are retained in the RAM 12 or the non-volatile memory 15. In the third embodiment, the portions extracted from the original data constitute first sample data.

[0074] In step S42, the erasure controller 14 extracts the same predetermined portion or portions as in step S41 from the current data compressed in step S35. In the third embodiment, the portions extracted from the current data constitute the second sample data.

[0075] In step S43, the erasure controller 14 determines whether the data portion extracted in step S42 is different from the data portion extracted in step S41, and if YES, proceeds to step S37, and if NO, proceeds to step S38.

[0076] According to the process of FIG. 10, by comparing portions of the compressed original data and the current data with each other, it is possible to reduce the processing time and the size of the RAM 12 required for the process compared to when the entire compressed original data and the entire current data are compared with each other.

[0077] Fourth Embodiment Fig. 11 is a flowchart showing an erasure process according to a fourth embodiment, which is executed by the erasure controller 14 of Fig. 1. The process of Fig. 11 includes steps S51 to S53 instead of step S36 of Fig. 9.

[0078] In step S51, the erasure controller 14 acquires the file size of the original data compressed in step S32. It is not necessary to store the entire compressed original data, and only the file size is stored in the RAM 12 or the non-volatile memory 15. In the fourth embodiment, the file size of the compressed original data constitutes the first sample data.

[0079] In step S52, the erasure controller 14 obtains the file size of the current data compressed in step S35. In the fourth embodiment, the file size of the current data compressed constitutes the second sample data.

[0080] In step S53, the erasure controller 14 determines whether the file size of the current compressed data is different from the file size of the original compressed data, and if YES, proceeds to step S37, and if NO, proceeds to step S38.

[0081] When two pieces of data are different from each other, the file sizes of the two compressed pieces of data generally also differ from each other. According to the process of Figure 11, by comparing the file sizes of the compressed original data and the current data with each other, it is possible to reduce the processing time and the size of the RAM 12 required for processing compared to when the compressed original data and the current data are compared with each other in their entirety.

[0082] Fifth Embodiment Fig. 12 is a flowchart showing an erasure process according to a fifth embodiment, which is executed by the erasure controller 14 of Fig. 1. The process of Fig. 12 includes steps S32A, S35A, and S36A instead of steps S32, S35, and S36 of Fig. 9.

[0083] In step S32A, the erasure controller 14 compresses a portion of the original data and calculates a hash value for another portion of the original data using an arbitrary hash function. The original data may be compressed and hash values ​​may be calculated alternately for multiple specified logical blocks 31. The original data may be compressed for all specified logical blocks 31 and hash values ​​for the original data for all specified logical blocks 31. Alternatively, the original data may be compressed for all specified logical blocks 31 and hash values ​​for some of the specified logical blocks 31. Alternatively, hash values ​​for the original data may be calculated for all specified logical blocks 31 and the original data may be compressed for some of the specified logical blocks 31.

[0084] The hash function may be, for example, a SHA-2 function such as SHA-256. The SHA-256 function has a maximum length of 2 （６４－１） A 256-bit (32-byte) hash value is generated from data of any length up to 1280 bits.

[0085] When calculating hash values ​​of the original data, one hash value may be calculated for each logical block 31, or one hash value may be calculated for a predetermined number of logical blocks 31. In the latter case, a buffer memory for storing the read data is provided in the RAM 12. The buffer memory has, for example, a size ten times that of the logical blocks 31. The erasure controller 14 writes the read data sequentially to the buffer memory, and calculates the hash value of the data when the buffer memory becomes full.

[0086] The hash value may be calculated based on data stored in multiple logical blocks 31 that are logically adjacent to each other, as shown in Fig. 8. The hash value may be calculated based on the logical product, logical sum, or exclusive sum of data stored in two logically adjacent logical blocks 31. By specifying the logical blocks 31 as shown in Fig. 8, it may be possible to avoid collisions of hash values.

[0087] In the fifth embodiment, the compressed original data and the hash value of the original data constitute first sample data. The first sample data may include a portion of the compressed original data instead of the entire compressed original data, or may include the file size of the compressed original data.

[0088] In step S35A, the erasure controller 14 compresses a portion of the current data and calculates a hash value for another portion of the current data using the same hash function as that used to calculate the hash value of the original data. The current data to be compressed is read from the same logical block 31 as the logical block 31 containing the compressed original data. The current data for which a hash value is to be calculated is also read from the same logical block 31 as the logical block 31 containing the original data for which the hash value was calculated.

[0089] When calculating the hash value of the current data, similar to when calculating the hash value of the original data, one hash value may be calculated for each logical block 31, or one hash value may be calculated for each predetermined number of logical blocks 31. In this way, for the same one or more logical blocks 31, the hash value of the original data is calculated, and the hash value of the current data is calculated.

[0090] In the fifth embodiment, the compressed current data and the hash value of the current data constitute second sample data. The second sample data may include a portion of the compressed current data instead of the entire compressed current data, or may include the file size of the compressed current data.

[0091] In step S36A, the erasure controller 14 determines whether the second sample data generated in step S35A is different from the first sample data generated in step S32A. If the answer is YES, the process proceeds to step S37. If the answer is NO, the process proceeds to step S38. The erasure controller 14 may first determine whether the hash value of the current data is different from the hash value of the original data. If the hash values ​​match, the erasure controller 14 may determine whether the compressed current data is different from the compressed original data. Hash values ​​fluctuate even if only a portion of the data in the storage area changes. Hash value collisions are extremely rare. Generally, the size of the hash value is smaller than the file size of the compressed data, so comparing the hash values ​​first can reduce processing time and load. Furthermore, if the file size of the compressed data is smaller than the size of the hash value (e.g., if a portion or file size of the compressed data is used), the erasure controller 14 may first determine whether the compressed current data is different from the compressed original data. If the data match, the erasure controller 14 may determine whether the hash value of the current data is different from the hash value of the original data.

[0092] There is a possibility that the hash values ​​of different data will collide. However, it is considered extremely unlikely that the hash values ​​of the original data and the current data will collide in all of the compared logical blocks 31. Therefore, for example, when comparing hash values ​​in 1,000 logical blocks 31, the erasure controller 14 may determine that the data erasure was successful even if the hash values ​​match in several logical blocks 31. Furthermore, if the hash values ​​differ in more than half of the logical blocks 31, the erasure controller 14 may determine that the data erasure was successful.

[0093] Furthermore, if the hash values ​​of the original data and the current data match in several adjacent logical blocks 31, the erasure controller 14 may determine that the data erasure has failed. In this case, it is considered that the area including these logical blocks 31 is not subject to encryption or decryption.

[0094] According to the process of FIG. 12, by combining the compressed data and the hash value, even if one of them accidentally collides, verification can be continued using the other, making it possible to more reliably verify whether the data has been successfully erased.

[0095] Furthermore, when one hash value is calculated for each of multiple logical blocks 31, the amount of calculation is reduced compared to when one hash value is calculated for each logical block 31, improving processing speed and reducing the memory capacity required to store the calculated hash values.

[0096] Sixth Embodiment Fig. 13 is a flowchart showing an erasure process according to a sixth embodiment, which is executed by the erasure controller 14 of Fig. 1. The process of Fig. 13 includes steps S32B, S35B, and S36B instead of steps S32, S35, and S36 of Fig. 9.

[0097] In step S32B, the erasure controller 14 compresses a portion of the original data and retains another portion of the original data as is. The original data may be compressed and retained as is alternately for the specified multiple logical blocks 31. The original data may be compressed for all of the specified logical blocks 31 and retained as is for all of the specified logical blocks 31. Alternatively, the original data may be compressed for all of the specified logical blocks 31 and retained as is for some of the specified logical blocks 31.

[0098] In the sixth embodiment, the compressed original data and the original data that is retained as is constitute first sample data. The first sample data may include a portion of the compressed original data instead of the entire compressed original data, or may include the file size of the compressed original data.

[0099] In step S35B, the erasure controller 14 compresses a portion of the current data and retains another portion of the current data. The current data to be compressed is read from the same logical block 31 as the logical block 31 containing the compressed original data. The current data to be retained is read from the same logical block 31 as the logical block 31 containing the retained original data.

[0100] In the sixth embodiment, the compressed current data and the retained current data constitute second sample data, which may include a portion of the compressed current data instead of the entire compressed current data, or may include the file size of the compressed current data.

[0101] In step S36B, the erasure controller 14 determines whether the second sample data generated in step S35B is different from the first sample data generated in step S32B, and if YES, proceeds to step S37, and if NO, proceeds to step S38. The erasure controller 14 may first determine whether the compressed current data is different from the compressed original data, and if the data match, determine whether the uncompressed current data is different from the uncompressed original data.

[0102] According to the process of FIG. 13, by combining compressed data and uncompressed data, even if one data accidentally collides, verification can be continued using the other data, and it is possible to more reliably verify whether the data has been successfully erased.

[0103] Seventh Embodiment Fig. 14 is a flowchart showing an erasure process according to a seventh embodiment, which is executed by the erasure controller 14 of Fig. 1. The process of Fig. 14 includes steps S32C, S35C, and S36C instead of steps S32, S35, and S36 of Fig. 9.

[0104] In step S32C, the erasure controller 14 calculates a hash value for part of the original data using an arbitrary hash function, and retains another part of the original data as is. Alternatively, the erasure controller 14 may calculate hash values ​​for the original data alternately for multiple specified logical blocks 31, and retain the original data as is. Alternatively, the erasure controller 14 may calculate hash values ​​for the original data for all specified logical blocks 31, and retain the original data for all specified logical blocks 31 as is. Alternatively, the erasure controller 14 may calculate hash values ​​for the original data for all specified logical blocks 31, and retain the original data for some specified logical blocks 31 as is.

[0105] In the seventh embodiment, the hash value of the original data and the original data that is retained as is constitute the first sample data.

[0106] In step S35C, the erasure controller 14 calculates a hash value for part of the current data using the same hash function as that used to calculate the hash value of the original data, and retains the other part of the current data as is. The current data for which a hash value is to be calculated is read from the same logical block 31 as the logical block 31 containing the original data for which the hash value was calculated. Furthermore, the current data to be retained as is is read from the same logical block 31 as the logical block 31 containing the retained original data as is.

[0107] In the seventh embodiment, the hash value of the current data and the current data that is retained as is constitute the second sample data.

[0108] In step S36C, the erasure controller 14 determines whether the second sample data generated in step S35C is different from the first sample data generated in step S32C, and if YES, proceeds to step S37, and if NO, proceeds to step S38. The erasure controller 14 may first determine whether the hash value of the current data is different from the hash value of the original data, and if the data match, determine whether the uncompressed current data is different from the uncompressed original data.

[0109] According to the process of FIG. 14, by combining the hash value and the uncompressed data, even if one of them accidentally collides, the other can continue verification, making it possible to more reliably verify whether the data has been successfully erased.

[0110] Eighth Embodiment Fig. 15 is a flowchart showing an erasure process according to an eighth embodiment, which is executed by the erasure controller 14 of Fig. 1. The process of Fig. 15 includes steps S32D, S35D, and S36D instead of steps S32, S35, and S36 of Fig. 9.

[0111] In step S32D, the erasure controller 14 compresses a portion of the original data, calculates a hash value for another portion of the original data using an arbitrary hash function, and retains yet another portion of the original data as is. It may compress a portion of the original data for each of the specified logical blocks 31 in turn, calculate a hash value for the original data, and retain the original data as is. It may compress the original data for all of the specified logical blocks 31, calculate a hash value for the original data for all of the specified logical blocks 31, and retain the original data as is for all of the specified logical blocks 31. It may also compress the original data for all of the specified logical blocks 31, calculate a hash value for the original data for all of the specified logical blocks 31, and retain the original data as is for some of the specified logical blocks 31. It may also compress the original data for all of the specified logical blocks 31, calculate a hash value for the original data for some of the specified logical blocks 31, and retain the original data as is for some of the specified logical blocks 31. It may also compress the original data for all of the specified logical blocks 31, calculate a hash value for the original data for some of the specified logical blocks 31, and retain the original data as is for some of the specified logical blocks 31. It may also calculate a hash value for the original data for all of the specified logical blocks 31, compress ...

[0112] In the eighth embodiment, the compressed original data, the hash value of the original data, and the original data retained as is constitute first sample data. The first sample data may include a portion of the compressed original data instead of the entire compressed original data, or may include the file size of the compressed original data.

[0113] In step S35D, the erasure controller 14 compresses a portion of the current data, calculates a hash value for another portion of the current data using the same hash function as that used to calculate the hash value of the original data, and retains yet another portion of the current data as is. The current data to be compressed is read from the same logical block 31 as the logical block 31 containing the compressed original data. The current data for which a hash value is to be calculated is read from the same logical block 31 as the logical block 31 containing the original data for which the hash value was calculated. The current data to be retained as is is read from the same logical block 31 as the logical block 31 containing the original data retained as is.

[0114] In the eighth embodiment, the compressed current data, the hash value of the current data, and the current data that is retained as is constitute second sample data. The second sample data may include a portion of the compressed current data instead of the entire compressed current data, or may include the file size of the compressed current data.

[0115] In step S36D, the erasure controller 14 determines whether the second sample data generated in step S35D is different from the first sample data generated in step S32D. If the result is YES, the process proceeds to step S37. If the result is NO, the process proceeds to step S38. The erasure controller 14 may first determine whether the compressed data, hash value, and uncompressed data with the smallest file size match. If they match, the erasure controller 14 may determine whether the compressed data with the next smallest file size match. If they match, the erasure controller 14 may determine whether the remaining data match. For example, the erasure controller 14 may first determine whether the hash value of the current data is different from the hash value of the original data. If the hash values ​​match, the erasure controller 14 may determine whether the compressed current data is different from the compressed original data. Alternatively, if the file size of the compressed data is smaller than the size of the hash value (e.g., if a portion of the compressed data or file size is used), the erasure controller 14 may first determine whether the compressed current data is different from the compressed original data. If the data match, the erasure controller 14 may determine whether the hash value of the current data is different from the hash value of the original data.

[0116] According to the process of FIG. 15, by combining compressed data, hash values, and uncompressed data, even if one of them accidentally collides, verification can continue using other data, making it possible to more reliably verify whether the data has been successfully erased.

[0117] [Modification of First Embodiment] Fig. 16 is a block diagram showing the configuration of an information processing device 1A according to a modification of the first embodiment. In addition to the components of the information processing device 1 in Fig. 1, the information processing device 1A further includes a device interface (I / F) 19 for connecting to an external device. The device interface 19 is, for example, a USB. In the example of Fig. 16, the device interface 19 is connected to an external storage device 41 such as a USB memory, a solid state drive, or a hard disk drive.

[0118] The program for the erasure process described with reference to FIG. 6 and other figures may be stored in the external storage device 41 instead of being stored in the nonvolatile memory 15. In this case, the erasure controller 14 reads out and executes the program for the erasure process from the external storage device 41. The program for the erasure process may also be divided into multiple parts, one part stored in the nonvolatile memory 15, and the other part stored in the external storage device 41. In this case, by executing the program part stored in the external storage device 41, the program part stored in the nonvolatile memory 15 is called and executed.

[0119] For example, when the information processing device 1A performs an erasure process, the compressed original data, the hash value of the original data, and / or the uncompressed original data may be stored in the external storage device 41 instead of being stored in the RAM 12 or the non-volatile memory 15.

[0120] The compressed original data, the hash value of the original data, and / or the uncompressed original data may be transmitted to and stored in an external information processing device connected via the communication device 16. The information processing device 1, 1A may further include a drive device for a storage medium such as a CD or DVD, and in this case, the compressed original data, the hash value of the original data, and / or the uncompressed original data may be stored on a CD, DVD, or the like.

[0121] [Ninth Example] Fig. 17 is a flowchart showing an erasure process according to a ninth example, which is executed by the erasure controller 14 of Fig. 16. The process of Fig. 17 includes steps S61 to S64 in addition to the steps of Fig. 9.

[0122] In step S61, the erasure controller 14 encrypts the compressed original data, and in step S62, the erasure controller 14 stores the encrypted original data in the external storage device 41.

[0123] In step S63, the erasure controller 14 reads the encrypted original data from the external storage device 41. In step S64, the erasure controller 14 decrypts the encrypted original data.

[0124] Generally, the external storage device 41 has a larger storage capacity than the RAM 12 and the non-volatile memory 15. Therefore, according to the process of Fig. 17, by using the external storage device 41, it is possible to specify a larger number of logical blocks 31 to determine whether data erasure has been successful. Furthermore, according to the process of Fig. 17, by encrypting the compressed original data and storing it in the external storage device 41, the possibility of confidential data being leaked is reduced even if the external storage device 41 is lost or stolen.

[0125] The processing of Figure 17 shows the case where the processing of Figure 9 is applied to the information processing device 1A of Figure 16, but by adding encryption and decryption steps, the processing of Figures 6 and Figures 10 to 15 may also be applied to the information processing device 1A of Figure 16.

[0126] [Advantages of the First Embodiment] The information processing device 1 according to the first embodiment includes a storage device 13 having a self-encryption function for stored data and an erasure controller 14 that controls erasure of data stored in the storage device 13. The storage device 13 includes a storage medium having a storage area, a nonvolatile memory 23 that stores an encryption key, and an input / output controller 21 that writes input data to the storage area, outputs data read from the storage area, encrypts at least a portion of the data written to the storage area using the encryption key, and decrypts at least a portion of the data read from the storage area using the encryption key. If a first encryption key is stored in the nonvolatile memory 23, the erasure controller 14 compresses data read from a specified location in the storage area to generate first sample data. The erasure controller 14 controls the storage device 13 to change the first encryption key stored in the nonvolatile memory 23 to a second encryption key. If a second encryption key is stored in the nonvolatile memory 23, the erasure controller 14 compresses data read from a specified location in the storage area to generate second sample data. If the second sample data is different from the first sample data, the erasure controller 14 outputs a verification result indicating successful erasure of the data stored in the storage device 13. If the second sample data matches the first sample data, the erasure controller 14 outputs a verification result indicating unsuccessful erasure of the data stored in the storage device 13.

[0127] This makes it possible to verify whether the data stored in the storage device 13 has been successfully erased with a smaller load than before.

[0128] According to the information processing device 1 of the first embodiment, the first sample data may include first compressed data obtained by compressing first data read from a first location in the storage area and a first hash value calculated based on second data read from a second location in the storage area. The second sample data may include second compressed data obtained by compressing third data read from the first location in the storage area and a second hash value calculated based on fourth data read from the second location in the storage area.

[0129] This allows verification to continue using either the compressed data or the hash value even if they happen to collide, making it possible to more reliably verify whether the data has been successfully erased.

[0130] According to the information processing device 1 of the first embodiment, the first sample data may include first compressed data obtained by compressing first data read from a first location in the storage area and second data read from a second location in the storage area. The second sample data may include second compressed data obtained by compressing third data read from the first location in the storage area and fourth data read from the second location in the storage area.

[0131] This allows verification to continue using the other even if compressed data and uncompressed data collide by chance, making it possible to more reliably verify whether data erasure has been successful or not.

[0132] According to the information processing device 1 of the first embodiment, the first sample data may include first compressed data obtained by compressing first data read from a first location in the storage area, a first hash value calculated based on second data read from a second location in the storage area, and third data read from a third location in the storage area. The second sample data may include second compressed data obtained by compressing fourth data read from the first location in the storage area, a second hash value calculated based on fifth data read from the second location in the storage area, and sixth data read from the third location in the storage area.

[0133] This allows verification to continue using other data even if any of the compressed data, hash value, and uncompressed data accidentally collides, making it possible to more reliably verify whether the data has been successfully erased.

[0134] According to the information processing device 1 of the first embodiment, if a portion of the second sample data is different from a corresponding portion of the first sample data, the erasure controller 14 may output a verification result indicating that erasure of the data stored in the storage device 13 was successful. If a portion of the second sample data matches a corresponding portion of the first sample data, the erasure controller 14 may output a verification result indicating that erasure of the data stored in the storage device 13 was unsuccessful.

[0135] This makes it possible to reduce processing time and load compared to when all sample data is compared.

[0136] According to the information processing device 1 according to the first embodiment, if the file size of the second sample data is different from the file size of the first sample data, the erasure controller 14 may output a verification result indicating that erasure of the data stored in the storage device 13 was successful. If the file size of the second sample data is the same as the file size of the first sample data, the erasure controller 14 may output a verification result indicating that erasure of the data stored in the storage device 13 was unsuccessful.

[0137] This makes it possible to reduce processing time and load compared to when the sample data itself is compared.

[0138] According to the information processing device 1 according to the first embodiment, the erasure controller 14 may encrypt the first sample data. The erasure controller 14 may store the encrypted first sample data in an external storage device 41 provided outside the information processing device 1A.

[0139] This allows more locations in the storage area to be specified to determine whether data erasure was successful. Also, by encrypting the compressed original data and storing it in the external storage device 41, the possibility of confidential data being leaked is reduced even if the external storage device 41 is lost or stolen.

[0140] According to the information processing device 1 of the first embodiment, the storage area may include a plurality of blocks, and the first and second sample data may be calculated for each of a predetermined number of blocks based on the data stored in the blocks.

[0141] This reduces the amount of calculation compared to when one hash value is calculated for each logical block 31, improving processing speed and reducing the memory capacity required to store the calculated hash values.

[0142] According to the information processing device 1 of the first embodiment, the storage area may include a plurality of partial areas obtained by logically dividing the storage area, each of which includes a plurality of logically contiguous blocks. The erasure controller 14 may specify, for each of the plurality of partial areas, a different proportion of blocks among the plurality of blocks included in the partial area. The first and second sample data may be calculated based on data stored in the specified plurality of blocks.

[0143] This makes it possible to more reliably verify the erasure of data stored in an area of ​​the information processing device 1 that is thought to contain important files.

[0144] According to the information processing device 1 of the first embodiment, the storage area may include a plurality of blocks, and the first and second sample data are calculated based on data stored in a plurality of blocks that are logically adjacent to each other.

[0145] This may prevent hash value collisions.

[0146] The information processing device 1 according to the first embodiment may include a display device 18 that outputs the verification result.

[0147] This makes it possible to know whether the data stored in the storage device 13 has been successfully erased.

[0148] The information processing device 1 according to the first embodiment includes a storage device 13 having a self-encryption function for stored data and an erasure controller 14 that controls erasure of data stored in the storage device 13. The storage device 13 includes a storage medium having a storage area, a nonvolatile memory 23 storing an encryption key, and an input / output controller 21 that writes input data to the storage area, outputs data read from the storage area, encrypts at least a portion of the data written to the storage area using the encryption key, and decrypts at least a portion of the data read from the storage area using the encryption key. If a first encryption key is stored in the nonvolatile memory 23, the erasure controller 14 compresses first data read from a specified location in the storage area. The erasure controller 14 controls the storage device 13 to change the first encryption key stored in the nonvolatile memory 23 to a second encryption key. If a second encryption key is stored in the nonvolatile memory 23, the erasure controller 14 acquires second data read from a specified location in the storage area. If the second data is different from the first data, the erasure controller 14 outputs a verification result indicating successful erasure of the data stored in the storage device 13. If the second data matches the first data, the erasure controller 14 outputs a verification result indicating that erasure of the data stored in the storage device 13 has failed.

[0149] This makes it possible to verify whether the data stored in the storage device 13 has been successfully erased with a smaller load than before.

[0150] An information processing device 1 according to a first embodiment includes a storage device 13 having a self-encryption function for stored data and an erasure controller 14 that controls erasure of data stored in the storage device 13. The storage device 13 includes a storage medium having a storage area, a nonvolatile memory 23 that stores an encryption key, and an input / output controller 21 that writes input data to the storage area, outputs data read from the storage area, encrypts at least a portion of the data written to the storage area using the encryption key, and decrypts at least a portion of the data read from the storage area using the encryption key. When a first encryption key is stored in the nonvolatile memory 23, the erasure controller 14 generates first sample data including a first hash value calculated based on first data read from a first location in the storage area and second data read from a second location in the storage area. The erasure controller 14 controls the storage device 13 to change the first encryption key stored in the nonvolatile memory 23 to a second encryption key. When the second encryption key is stored in the nonvolatile memory 23, the erasure controller 14 generates second sample data including a second hash value calculated based on the third data read from the first location in the storage area and fourth data read from the second location in the storage area. When the second sample data is different from the first sample data, the erasure controller 14 outputs a verification result indicating that the erasure of the data stored in the storage device 13 was successful. When the second sample data matches the first sample data, the erasure controller 14 outputs a verification result indicating that the erasure of the data stored in the storage device 13 was unsuccessful.

[0151] This makes it possible to verify whether the data stored in the storage device 13 has been successfully erased with a smaller load than before.

[0152] An information processing method according to a first embodiment controls erasure of data stored in a storage device 13 having a self-encrypting function. The storage device 13 includes a storage medium having a storage area, a nonvolatile memory 23 storing an encryption key, and an input / output controller 21 that writes input data to the storage area, outputs data read from the storage area, encrypts at least a portion of the data written to the storage area using the encryption key, and decrypts at least a portion of the data read from the storage area using the encryption key. The information processing method includes, when a first encryption key is stored in the nonvolatile memory 23, compressing data read from a specified location in the storage area to generate first sample data. The information processing method also includes controlling the storage device 13 to change the first encryption key stored in the nonvolatile memory 23 to a second encryption key. The information processing method also includes, when a second encryption key is stored in the nonvolatile memory 23, compressing data read from a specified location in the storage area to generate second sample data. The information processing method also includes, when the second sample data is different from the first sample data, outputting a verification result indicating successful erasure of the data stored in the storage device 13. The information processing method includes outputting a verification result indicating that erasure of the data stored in the storage device 13 has failed if the second sample data matches the first sample data.

[0153] This makes it possible to verify whether the data stored in the storage device 13 has been successfully erased with a smaller load than before.

[0154] A program according to the first embodiment includes instructions to be executed by a processor implemented in the information processing device 1. The information processing device 1 further includes a storage device 13 having a self-encryption function for stored data. The storage device 13 includes a storage medium having a storage area, a nonvolatile memory 23 storing an encryption key, and an input / output controller 21 that writes input data to the storage area, outputs data read from the storage area, encrypts at least a portion of the data written to the storage area using the encryption key, and decrypts at least a portion of the data read from the storage area using the encryption key. The instructions cause the processor to compress data read from a specified location in the storage area to generate first sample data if a first encryption key is stored in the nonvolatile memory 23. The instructions cause the processor to control the storage device 13 to change the first encryption key stored in the nonvolatile memory 23 to a second encryption key. The instructions cause the processor to compress data read from a specified location in the storage area to generate second sample data if a second encryption key is stored in the nonvolatile memory 23. The instructions cause the processor to output a verification result indicating successful erasure of the data stored in the storage device 13 if the second sample data is different from the first sample data. The instructions cause the processor to output a verification result indicating unsuccessful erasure of the data stored in the storage device 13 if the second sample data matches the first sample data.

[0155] This makes it possible to verify whether the data stored in the storage device 13 has been successfully erased with a smaller load than before.

[0156] Second Embodiment In a second embodiment, a case will be described in which the progress of data erasure is displayed while the erasure process of the first embodiment (see FIG. 9) is being performed.

[0157] 18 is a flowchart showing the erasure process executed by the information processing device 1 according to the second embodiment. The information processing device 1 according to the second embodiment has the same configuration as that of the first embodiment. The erasure process of FIG. 18 is executed by the erasure controller 14 of FIG. 1.

[0158] In step S101, the erasure controller 14 performs preprocessing to compress the original data of the specified logical block 31.

[0159] In step S102, the erasure controller 14 executes a key change process to change the encryption key stored in the nonvolatile memory 23.

[0160] In step S103, the erasure controller 14 performs a verification process to determine whether the current compressed data is different from the original compressed data, i.e., whether the data has been successfully erased.

[0161] FIG. 19 is a flowchart showing a subroutine of the pre-processing (step S101) of FIG.

[0162] In step S111, the erasure controller 14 initializes a parameter i1 to 1. The parameter i1 indicates one of a plurality of logical blocks 31 designated, for example, as shown in Figure 3, Figure 7, or Figure 8. In the example of Figure 19, N1 logical blocks 31 are designated.

[0163] In step S112, the erasure controller 14 reads the original data from the i1-th logical block 31 among the specified logical blocks 31. Next, in step S113, the erasure controller 14 compresses the original data. Steps S112 to S113 are the same as steps S31 to S32 in FIG. 9 except that they are performed for one of the specified logical blocks 31.

[0164] In step S114, the erasure controller 14 stores the compressed original data and the address of the i1th logical block 31 in the RAM 12 or nonvolatile memory 15 (or the external storage device 41 in FIG. 16).

[0165] In step S115, the erasure controller 14 outputs the number of logical blocks 31 for which the processes in steps S112 to S114 have been executed to the display device 18 in a predetermined format.

[0166] In step S116, the erasure controller 14 determines whether the parameter i1 exceeds the threshold value N1. If YES, the process proceeds to step S102 in FIG. 18, and if NO, the process proceeds to step S117.

[0167] In step S117, the erasure controller 14 increments the parameter i1 by 1, and repeats steps S112 to S116.

[0168] FIG. 20 is a flowchart showing a subroutine of the key change process (step S102) of FIG.

[0169] In step S121, the erasure controller 14 changes the encryption key stored in the nonvolatile memory 23. Step S121 is similar to step S33 in FIG.

[0170] In step S122, the erasure controller 14 outputs to the display device 18 in a predetermined format a message indicating that the encryption key has been changed.

[0171] FIG. 21 is a flowchart showing a subroutine of the verification process (step S103) of FIG.

[0172] In step S131, the erasure controller 14 initializes a parameter i2 to 1. The parameter i2 indicates one of the N1 logical blocks 31 specified in the preprocessing of FIG.

[0173] In step S132, the erasure controller 14 reads the compressed original data and address stored in the RAM 12 or nonvolatile memory 15 (or the external storage device 41 in FIG. 16 ). Based on this address, the logical block 31 whose hash value was calculated in the preprocessing is identified.

[0174] In step S133, the erasure controller 14 reads the current data of the i2th logical block 31 among the logical blocks 31 identified by the address read in step S132. Then, in step S134, the erasure controller 14 compresses the current data. Steps S133 and S134 are similar to steps S34 and S35 in FIG. 9 except that they are performed for one of the specified logical blocks 31.

[0175] In step S135, the erasure controller 14 determines whether the current compressed data is different from the original compressed data, and if YES, proceeds to step S136, and if NO, proceeds to step S140. Step S136 is the same as step S36 in Figure 9, except that it is performed for one of the specified logical blocks 31.

[0176] In step S136, the erasure controller 14 outputs the number of verified logical blocks 31, i.e., the number of logical blocks 31 for which it has been determined whether the compressed current data is different from the compressed original data, to the display device 18 in a predetermined format.

[0177] In step S137, the erasure controller 14 determines whether the parameter i2 exceeds the threshold value N1 or not, and if YES, ends the process, and if NO, proceeds to step S138.

[0178] In step S138, the erasure controller 14 increments the parameter i2 by 1, and repeats steps S132 to S137.

[0179] In step S139, the erasure controller 14 outputs a verification result indicating that the data erasure was successful to the display device 18. In step S140, the erasure controller 14 outputs a verification result indicating that the data erasure was unsuccessful to the display device 18.

[0180] 22A and 22B are diagrams showing an example of an image indicating the progress of data erasure, which is displayed on the display device 18 of FIG. 1 by executing the erasure process of FIG. 18 . FIG. 22A is an image showing the progress of preprocessing. The progress of preprocessing is represented, for example, by a progress bar indicating the ratio of the number of processed logical blocks 31 to the number of specified logical blocks 31, i.e., i1 / N1. FIG. 22B is an image showing the progress of key change processing. The progress of key change processing is represented, for example, by a progress bar indicating whether the encryption key change has been completed. FIG. 22C is an image showing the progress of verification processing. The progress of verification processing is represented, for example, by a progress bar indicating the ratio of the number of verified logical blocks 31 to the number of specified logical blocks 31, i.e., i2 / N1.

[0181] Fig. 23 is a diagram showing another example of an image showing the progress of data erasure, which is displayed on the display device 18 of Fig. 1 by executing the erasure process of Fig. 18. The three progress bars shown in Fig. 22 may be displayed together as one.

[0182] The progress of data erasure may be displayed as text such as the following instead of being displayed as an image as in FIGS.

[0183] Pre-processing: a1 Key change processing: a2 Verification processing: a3

[0184] Here, a1 starts from the specified number of blocks N1 and decreases as the parameter i1 increases (a1=N1-i1), a2 is "1" before the encryption key is changed and becomes "0" after the encryption key is changed, and a3 starts from the specified number of blocks N1 and decreases as the parameter i2 increases (a3=N1-i2).

[0185] The progress of the data erasure may also be displayed as text such as:

[0186] Pre-processing: b1 / N1 Key change processing: b2 Verification processing: b3 / N1

[0187] Here, b1=i1, b2 is "0" before the encryption key is changed and is "1" after the encryption key is changed, and b3=i2.

[0188] The progress of data erasure may be displayed as "c", where c = a1 + a2 + a3, or as "d / N", where d = b1 + b2 + b3, and N = N1 x 2 + 1.

[0189] In the verification process of Fig. 21, if the current data compressed in one logical block 31 matches the original compressed data, it is determined that the data erasure has failed. However, as mentioned above, when a lossy compression algorithm is used, there is a possibility that the compressed data of different data will match. In this case, even if the compressed data matches in part of the specified logical block 31, the erasure controller 14 may determine that the data erasure has been successful. Next, with reference to Figs. 24 to 26, a modified version of the verification process that allows such a match in compressed data will be described.

[0190] Fig. 24 is a flowchart showing a first modification of the verification process of Fig. 18. The process of Fig. 24 includes steps S141 to S143 in addition to the steps of Fig. 21.

[0191] In step S141, the erasure controller 14 initializes a parameter j1 to 0. Using the parameter j1, the number of logical blocks 31 in which the compressed current data matches the compressed original data is counted.

[0192] If it is determined in step S135 that the compressed current data matches the compressed original data, the process proceeds to step S142, in which the erasure controller 14 increments the parameter j1 by one.

[0193] In step S143, the erasure controller 14 determines whether the parameter j1 exceeds the threshold value Th1, and if YES, the process proceeds to step S140, and if NO, the process proceeds to step S136.

[0194] According to the verification process of FIG. 24, even if the compressed data matches in the number of logical blocks 31 equal to or less than the threshold value Th1, if the compressed data differs in the other logical blocks 31, it can be determined that the data has been successfully erased.

[0195] Fig. 25 is a flowchart showing a second modification of the verification process of Fig. 18. The process of Fig. 25 includes steps S151 to S156 in addition to the steps of Fig. 21.

[0196] In step S151, the erasure controller 14 initializes a parameter j2 to 0. Using the parameter j2, the number of times that compressed data matches occur consecutively in several adjacent logical blocks 31 among the specified logical blocks 31 are counted.

[0197] If it is determined in step S135 that the current compressed data is different from the original compressed data, the process proceeds to step S152; otherwise, the process proceeds to step S153. In step S152, the erasure controller 14 decrements the parameter j2 by 1. In step S153, the erasure controller 14 increments the parameter j2 by 1.

[0198] In step S154, the erasure controller 14 determines whether the parameter j2 is less than 0. If YES, the process proceeds to step S155, and if NO, the process proceeds to step S156. In step S155, the erasure controller 14 reinitializes the parameter j2 to 0.

[0199] In step S156, the erasure controller 14 determines whether the parameter j2 exceeds the threshold value Th2 or not, and if YES, the process proceeds to step S140, and if NO, the process proceeds to step S136.

[0200] According to the verification process of Figure 25, parameter j2 increases or decreases depending on whether the compressed data matches or does not match. Therefore, if compressed data matches consecutively in several closely spaced logical blocks 31 among the specified logical blocks 31, parameter j2 increases. In this case, it is considered that the storage area including these logical blocks 31 is not subject to encryption, and the data is stored in plain text. On the other hand, if compressed data matches and does not match almost alternately in several closely spaced logical blocks 31 among the specified logical blocks 31, parameter j2 does not increase. In this case, it is considered that the compressed data matches are coincidental.

[0201] Fig. 26 is a flowchart showing a third modification of the verification process of Fig. 18. The process of Fig. 26 includes steps S161 to S169 in addition to the steps of Fig. 21.

[0202] If it is determined in step S135 that the current compressed data matches the original compressed data, the process proceeds to step S161, in which the erasure controller 14 stores the address of the logical block 31 where the compressed data match occurs in the RAM 12 or non-volatile memory 15 (or the external storage device 41 in FIG. 16).

[0203] When parameter i2 exceeds threshold value N1 in step S137, the process proceeds to step S162. In step S162, the erasure controller 14 initializes parameters i3 and i4 to 1, and parameter j3 to 0. In the verification process of FIG. 26, the number of times compressed data matches in a group of a predetermined number of logical blocks 31 that are close to each other among the specified logical blocks 31 is counted. Parameter i3 indicates the position of the group of logical blocks 31. Parameter i4 indicates one of the logical blocks 31 included in a certain group. In the example of FIG. 26, each group includes N4 logical blocks 31, and the position of the group is shifted N3=N1-N4 times among the specified logical blocks 31. Parameter j3 is used to count the number of times compressed data matches in a certain group.

[0204] In step S163, the erasure controller 14 determines whether the compressed current data matches the compressed original data in the i3+i4th logical block 31 based on the address stored in step S161, and if the answer is YES, proceeds to step S164, and if the answer is NO, proceeds to step S165. In step S164, the erasure controller 14 increments the parameter j3 by 1.

[0205] In step S165, the erasure controller 14 determines whether the parameter i4 has exceeded the threshold value N4, i.e., whether all logical blocks 31 included in the current group have been processed; if YES, the process proceeds to step S167; if NO, the process proceeds to step S166.

[0206] In step S166, the erasure controller 14 increments the parameter i4 by 1, and repeats steps S163 to S165.

[0207] In step S167, the erasure controller 14 determines whether the parameter j3 exceeds the threshold value Th3 or not, and if YES, the process proceeds to step S140, and if NO, the process proceeds to step S168.

[0208] In step S168, the erasure controller 14 determines whether the parameter i3 has exceeded the threshold value N3, i.e., whether the group of logical blocks 31 has been shifted to all positions; if YES, the process proceeds to step S139; if NO, the process proceeds to step S169.

[0209] In step S169, the erasure controller 14 increments the parameter i3 by 1, and repeats steps S163 to S168.

[0210] According to the process of Figure 26, if compressed data matches repeatedly occur in a group of a predetermined number of logical blocks 31 that are close to each other, it is assumed that the storage area containing these logical blocks 31 is not subject to encryption and that the data is stored in plain text.

[0211] The threshold value Th3 in step S167 may be set to a value close to the number N3 of logical blocks 31 included in the group. In addition, in step S168, the erasure controller 14 may calculate j3 / N3, in which case the threshold value Th3 may be set to a value close to 1, for example.

[0212] Effects of the Second Embodiment According to the information processing device 1 according to the second embodiment, the erasure controller 14 may output the progress of erasure of data stored in the storage device 13 to the display device 18 .

[0213] This allows the progress of data erasure to be ascertained.

[0214] [Third Embodiment] Fig. 27 is a block diagram showing the configuration of an information processing system including an information processing device 1 and a server device according to a third embodiment. The information processing system of Fig. 27 includes a plurality of information processing devices 1-1 to 1-3, a server device 2, and a communication line 3. Each of the information processing devices 1-1 to 1-3 has the same configuration as the information processing device 1 of Fig. 1. The server device 2 is connected to each of the information processing devices 1-1 to 1-3 via the communication line 3.

[0215] In this specification, the information processing devices 1-1 to 1-3 are collectively referred to as "information processing device 1."

[0216] FIG. 28 is a block diagram showing the configuration of the server device 2 of FIG. 27 . The server device 2 includes a bus 120, a CPU 121, a RAM 122, a storage device 123, a communication device 126, an input device 127, and a display device 128. The CPU 121 controls the overall operation of the server device 2 and manages the erasure of data stored in the storage device 13 of each information processing device 1. The RAM 122 temporarily stores programs and data necessary for the operation of the server device 2. The storage device 123 is a non-volatile storage medium that stores programs necessary for the operation of the server device 2. The communication device 126 is communicably connected to each information processing device 1 via the communication line 3. The input device 127 receives user input that controls the operation of the server device 2. The input device 127 includes, for example, a keyboard and a pointing device. The display device 128 displays information related to the erasure of data stored in the storage device 13 of each information processing device 1. The CPU 121 , RAM 122 , storage device 123 , communication device 126 , input device 127 , and display device 128 are connected to one another via a bus 120 .

[0217] Fig. 29 is a flowchart showing the erasure process executed by the server device 2 of Fig. 27. Fig. 30 is a flowchart showing the erasure process executed by the information processing device 1 of Fig. 27.

[0218] In step S201 of FIG. 29, the CPU 121 of the server device 2 transmits a control signal to the information processing device 1 to instruct the data deletion.

[0219] In step S211 of FIG. 30, the erasure controller 14 of the information processing device 1 receives a control signal from the server device 2 instructing the erasure of data. Next, the erasure controller 14 executes steps S212 to S219 in accordance with the control signal. Steps S212 to S217 are the same as steps S31 to S36 of FIG. 9. If it is determined in step S217 that the compressed current data is different from the compressed original data, the process proceeds to step S218; if not, the process proceeds to step S219. In step S218, the erasure controller 14 transmits a notification signal to the server device 2 including a verification result indicating that the data erasure was successful. In step S219, the erasure controller 14 transmits a notification signal to the server device 2 including a verification result indicating that the data erasure was unsuccessful.

[0220] 29, the CPU 121 of the server device 2 receives a notification signal indicating the verification result from the information processing device 1. In step S203, the CPU 121 outputs the verification result to the display device 128.

[0221] According to the processing of Figures 29 and 30, the erasure of data stored in the storage devices 13 of multiple information processing devices 1 can be centrally controlled by the server device 2, and it is also possible to verify with a small load whether the data has been successfully erased.

[0222] As will be described with reference to FIGS. 31 to 35, the progress of the data erasure may be output to the display device 128 of the server device 2.

[0223] Fig. 31 is a flowchart showing a modified example of the erasure process executed by the server device 2 in Fig. 27. Fig. 32 is a flowchart showing a modified example of the erasure process executed by the information processing device 1 in Fig. 27. The process in Fig. 31 includes steps S221 to S223 instead of step S202 in Fig. 29. The process in Fig. 32 includes steps S231 to S233 instead of steps S212 to S219 in Fig. 30.

[0224] In step S201 of FIG. 31, the CPU 121 of the server device 2 transmits a control signal to the information processing device 1 to instruct the data deletion.

[0225] 32, the erasure controller 14 of the information processing device 1 receives a control signal instructing data erasure from the server device 2. Next, the erasure controller 14 executes steps S231 to S233 in accordance with the control signal. Steps S231 to S233 are similar to steps S101 to S103 of FIG. 18, except that the progress of data erasure and the verification results are transmitted to the server device 2 instead of being output to the display device 18 of the information processing device 1.

[0226] Fig. 33 is a flowchart showing a subroutine of the pre-processing (step S231) of Fig. 32. The processing of Fig. 33 includes step S115A instead of step S115 of Fig. 19. In step S115A, the erasure controller 14 transmits to the server device 2 a notification signal including the number of logical blocks 31 for which the processing of steps S112 to S114 has been executed, as the progress of data erasure.

[0227] Fig. 34 is a flowchart showing a subroutine of the key change process (step S232) of Fig. 32. The process of Fig. 34 includes step S122A instead of step S122 of Fig. 20. In step S122A, the erasure controller 14 transmits a notification signal to the server device 2 indicating that the encryption key change has been completed, as the progress of the data erasure.

[0228] 35 is a flowchart showing a subroutine of the verification process (step S233) of FIG. 32. The process of FIG. 35 includes steps S136A, S139A, and S140A instead of steps S136, S139, and S140 of FIG. 21. In step S136A, the erasure controller 14 transmits a notification signal including the number of verified logical blocks 31 as the progress of data erasure to the server device 2. In step S139A, the erasure controller 14 transmits a notification signal including a verification result indicating that the data erasure was successful to the server device 2. In step S140A, the erasure controller 14 transmits a notification signal including a verification result indicating that the data erasure failed to the server device 2.

[0229] 31 , the CPU 121 of the server device 2 receives a notification signal including the progress of data erasure from the information processing device 1. In step S222, the CPU 121 outputs the progress of data erasure to the display device 128 in a predetermined format, similar to when outputting to the display device 18 of the information processing device 1. In step S223, the CPU 121 determines whether the data erasure has been completed, i.e., whether a notification signal indicating the verification result has been received from the information processing device 1. If the determination is YES, the process proceeds to step S203, and if the determination is NO, the process returns to step S221. In step S203, the CPU 121 outputs the verification result to the display device 128.

[0230] According to the processes of FIGS. 31 to 35, the progress of erasing data stored in the storage devices 13 of the plurality of information processing devices 1 can be grasped in the server device 2.

[0231] [Effects of the Third Embodiment, etc.] An information processing system 100 according to the third embodiment includes the information processing device 1 according to the first embodiment and a server device 2 connected to the information processing device 1 via a communication line. An erasure controller 14 controls erasure of data stored in the storage device 13 in accordance with a control signal received from the server device 2.

[0232] This makes it possible to verify whether the data stored in the storage device 13 has been successfully erased with a smaller load than before.

[0233] In the information processing system 100 according to the third embodiment, the erasure controller 14 may transmit a first notification signal including the verification result to the server device 2. The server device 2 may include a display device 128 that outputs the verification result.

[0234] This makes it possible to know whether the data stored in the storage device 13 has been successfully erased.

[0235] In the information processing system 100 according to the third embodiment, the erasure controller 14 may transmit a second notification signal including the progress of erasure of data stored in the storage device 13 to the server device 2. In this case, the display device 128 displays the progress.

[0236] This allows the progress of data erasure to be ascertained.

[0237] [Other Embodiments] As described above, the embodiments have been described as examples of the technology disclosed in the present application. However, the technology in the present disclosure is not limited to these, and can be applied to embodiments in which appropriate modifications, substitutions, additions, omissions, etc. are made. Furthermore, it is also possible to combine the components described in the above embodiments to create new embodiments.

[0238] Therefore, other embodiments will be exemplified below.

[0239] The storage device 13 is not limited to a solid state drive, and may be a non-volatile storage medium such as a hard disk drive (HDD) with a self-encrypting function.

[0240] The verification result is not limited to being output to the display device 18, but may also be output to an external information processing device via the communication device 16.

[0241] Since important data is stored at the logical beginning of the storage area, the erasure controller 14 may always specify the first 32 bytes of the storage area.

[0242] The erasure controller 14 may add a salt (a predetermined keyword) to the data when calculating the hash value.

[0243] The erasure controller 14 may shrink the size of the logical block 31 to, for example, 1 / 10.

[0244] 18 to 26 and 31 to 35 have described the case where the progress of data erasure is displayed while the erasure process (see FIG. 9) according to Example 2 is being performed. Alternatively, the progress of data erasure may be similarly displayed while the erasure process (see FIG. 6, 10 to 15, and 17) according to Examples 1 and 3 to 9 is being performed.

[0245] When one hash value is calculated for each of multiple logical blocks 31, the progress of data erasure may be displayed as an image or text based on the number or proportion of groups of logical blocks 31, with each group of logical blocks 31 corresponding to one hash value as a unit.

[0246] As described above, the embodiments have been described as examples of the technology in the present disclosure, and for that purpose, the accompanying drawings and detailed description have been provided.

[0247] Therefore, the components shown in the accompanying drawings and detailed description may include not only essential components for solving the problem, but also components that are not essential for solving the problem in order to illustrate the above technology. Therefore, the fact that these non-essential components are shown in the accompanying drawings or detailed description should not be interpreted as immediately indicating that these non-essential components are essential.

[0248] Furthermore, since the above-described embodiments are intended to illustrate the technology of the present disclosure, various modifications, substitutions, additions, omissions, etc. may be made within the scope of the claims or their equivalents.

[0249] Summary of Embodiments An information processing device according to a first aspect of the present disclosure comprises: a storage device having a function of self-encrypting data to be stored; and an erasure controller that controls erasure of data stored in the storage device, wherein the storage device comprises: a storage medium having a storage area; a non-volatile memory that stores an encryption key; and an input / output controller that writes input data to the storage area, outputs data read from the storage area, encrypts at least a portion of the data to be written to the storage area using the encryption key, and decrypts at least a portion of the data read from the storage area using the encryption key, wherein the erasure controller: when a first encryption key is stored in the non-volatile memory, compresses data read from a specified position in the storage area to generate first sample data; controls the storage device to change the first encryption key stored in the non-volatile memory to a second encryption key; when the second encryption key is stored in the non-volatile memory, compresses data read from the specified position in the storage area to generate second sample data; and when the second sample data is different from the first sample data, outputs a verification result indicating that erasure of the data stored in the storage device was successful, If the second sample data matches the first sample data, a verification result indicating that erasure of the data stored in the storage device has failed is output.

[0250] According to the information processing device of the second aspect of the present disclosure, in the information processing device of the first aspect, the first sample data includes first compressed data obtained by compressing first data read from a first location in the storage area and a first hash value calculated based on second data read from a second location in the storage area, and the second sample data includes second compressed data obtained by compressing third data read from the first location in the storage area and a second hash value calculated based on fourth data read from the second location in the storage area.

[0251] According to the information processing device of the second aspect of the present disclosure, in the information processing device of the first aspect, the first sample data includes first compressed data obtained by compressing first data read from a first position in the memory area and second data read from a second position in the memory area, and the second sample data includes second compressed data obtained by compressing third data read from the first position in the memory area and fourth data read from the second position in the memory area.

[0252] According to an information processing device according to a fourth aspect of the present disclosure, in the information processing device according to the first aspect, the first sample data includes first compressed data obtained by compressing first data read from a first position in the storage area, a first hash value calculated based on second data read from a second position in the storage area, and third data read from a third position in the storage area; and the second sample data includes second compressed data obtained by compressing fourth data read from the first position in the storage area, a second hash value calculated based on fifth data read from the second position in the storage area, and sixth data read from the third position in the storage area.

[0253] According to an information processing device according to a fifth aspect of the present disclosure, in an information processing device according to one of the first to fourth aspects, the erasure controller outputs a verification result indicating that erasure of the data stored in the storage device was successful if a portion of the second sample data is different from a corresponding portion of the first sample data, and outputs a verification result indicating that erasure of the data stored in the storage device was unsuccessful if a portion of the second sample data matches a corresponding portion of the first sample data.

[0254] According to an information processing device according to a sixth aspect of the present disclosure, in an information processing device according to one of the first to fourth aspects, the erasure controller outputs a verification result indicating that the erasure of the data stored in the storage device was successful if the file size of the second sample data is different from the file size of the first sample data, and outputs a verification result indicating that the erasure of the data stored in the storage device was unsuccessful if the file size of the second sample data matches the file size of the first sample data.

[0255] According to the information processing device of the seventh aspect of the present disclosure, in the information processing device of one of the first to sixth aspects, the erasure controller encrypts the first sample data and stores the encrypted first sample data in an external storage device provided outside the information processing device.

[0256] According to an information processing device according to an eighth aspect of the present disclosure, in the information processing device according to one of the first to seventh aspects, the memory area includes a plurality of blocks, and the first and second sample data are calculated for each of a predetermined number of blocks based on the data stored in the blocks.

[0257] According to an information processing device according to a ninth aspect of the present disclosure, in an information processing device according to one of the first to eighth aspects, the storage area includes a plurality of partial areas obtained by logically dividing the storage area, each of which includes a plurality of logically contiguous blocks, the erasure controller specifies, for each of the plurality of partial areas, a different proportion of blocks from the plurality of blocks included in the partial area, and the first and second sample data are calculated based on data stored in the specified plurality of blocks.

[0258] According to an information processing device according to a tenth aspect of the present disclosure, in the information processing device according to one of the first to ninth aspects, the memory area includes a plurality of blocks, and the first and second sample data are calculated based on data stored in a plurality of blocks that are logically adjacent to each other.

[0259] According to an eleventh aspect of the present disclosure, the information processing device according to any one of the first to tenth aspects includes a first display device that outputs the verification result.

[0260] According to the information processing device of the twelfth aspect of the present disclosure, in the information processing device of the eleventh aspect, the erasure controller outputs the progress of erasure of data stored in the storage device to the first display device.

[0261] an information processing device according to a thirteenth aspect of the present disclosure, comprising: a storage device having a function of self-encrypting data to be stored; and an erasure controller that controls erasure of data stored in the storage device; wherein the storage device comprises: a storage medium having a storage area; a nonvolatile memory that stores an encryption key; and an input / output controller that writes input data to the storage area, outputs data read from the storage area, encrypts at least a portion of the data to be written to the storage area using the encryption key, and decrypts at least a portion of the data read from the storage area using the encryption key; wherein the erasure controller: when a first encryption key is stored in the nonvolatile memory, compresses the first data read from a specified location in the storage area; controls the storage device to change the first encryption key stored in the nonvolatile memory to a second encryption key; when the second encryption key is stored in the nonvolatile memory, acquires second data read from the specified location in the storage area; and when the second data is different from the first data, outputs a verification result indicating that erasure of the data stored in the storage device was successful; If the second data matches the first data, a verification result indicating that erasure of the data stored in the storage device has failed is output.

[0262] an information processing device according to a fourteenth aspect of the present disclosure, comprising: a storage device having a self-encryption function for data to be stored; and an erasure controller that controls erasure of data stored in the storage device, wherein the storage device comprises: a storage medium having a storage area; a nonvolatile memory that stores an encryption key; and an input / output controller that writes input data to the storage area, outputs data read from the storage area, encrypts at least a portion of the data to be written to the storage area using the encryption key, and decrypts at least a portion of the data read from the storage area using the encryption key, wherein the erasure controller, when a first encryption key is stored in the nonvolatile memory, generates first sample data including a first hash value calculated based on first data read from a first location in the storage area and second data read from a second location in the storage area; and controls the storage device to change the first encryption key stored in the nonvolatile memory to a second encryption key; If the second encryption key is stored in the non-volatile memory, second sample data is generated, the second sample data including a second hash value calculated based on the third data read from the first location of the storage area and the fourth data read from the second location of the storage area; if the second sample data is different from the first sample data, a verification result indicating that the erasure of the data stored in the storage device was successful is output; and if the second sample data matches the first sample data, a verification result indicating that the erasure of the data stored in the storage device was unsuccessful is output.

[0263] An information processing system according to a fifteenth aspect of the present disclosure comprises an information processing device according to one of the first to fourteenth aspects, and a server device connected to the information processing device via a communication line, wherein the erasure controller controls the erasure of data stored in the storage device in accordance with a control signal received from the server device.

[0264] According to the information processing system of the sixteenth aspect of the present disclosure, in the information processing system of the fifteenth aspect, the erasure controller transmits a first notification signal including the verification result to the server device, and the server device is provided with a second display device that outputs the verification result.

[0265] According to the information processing system of the seventeenth aspect of the present disclosure, in the information processing system of the sixteenth aspect, the erasure controller transmits a second notification signal including a progress degree of erasure of data stored in the storage device to the server device, and the second display device displays the progress degree.

[0266] An information processing method according to an eighteenth aspect of the present disclosure is an information processing method for controlling erasure of data stored in a storage device having a self-encrypting function, wherein the storage device comprises: a storage medium having a storage area; a non-volatile memory storing an encryption key; and an input / output controller that writes input data to the storage area, outputs data read from the storage area, encrypts at least a portion of the data written to the storage area using the encryption key, and decrypts at least a portion of the data read from the storage area using the encryption key, wherein the information processing method comprises: if a first encryption key is stored in the non-volatile memory, compressing data read from a specified position in the storage area to generate first sample data; controlling the storage device to change the first encryption key stored in the non-volatile memory to a second encryption key; if the second encryption key is stored in the non-volatile memory, compressing data read from the specified position in the storage area to generate second sample data; and if the second sample data is different from the first sample data, outputting a verification result indicating that the erasure of the data stored in the storage device was successful; If the second sample data matches the first sample data, outputting a verification result indicating that erasure of the data stored in the storage device has failed.

[0267] A program according to a nineteenth aspect of the present disclosure is a program including instructions to be executed by a processor implemented in an information processing device, wherein the information processing device further includes a storage device having a function of self-encrypting data to be stored, the storage device including: a storage medium having a storage area; a nonvolatile memory storing an encryption key; and an input / output controller that writes input data to the storage area, outputs data read from the storage area, encrypts at least a portion of the data to be written to the storage area using the encryption key, and decrypts at least a portion of the data read from the storage area using the encryption key, wherein the instructions cause the processor to: when a first encryption key is stored in the nonvolatile memory, compress data read from a specified position in the storage area to generate first sample data; control the storage device to change the first encryption key stored in the nonvolatile memory to a second encryption key; when the second encryption key is stored in the nonvolatile memory, compress data read from the specified position in the storage area to generate second sample data; If the second sample data is different from the first sample data, a verification result indicating that the erasure of the data stored in the storage device was successful is output; and if the second sample data matches the first sample data, a verification result indicating that the erasure of the data stored in the storage device was unsuccessful is output.

[0268] An information processing device according to an aspect of the present disclosure is useful for verifying whether data stored in a storage device with a self-encrypting function has been successfully erased.

[0269] 1, 1A Information processing device 10 Bus 11 Central processing unit (CPU) 12 Random access memory (RAM) 13 Storage device 14 Erasure controller 15 Non-volatile memory 16 Communication device 17 Input device 18 Display device 19 Device interface (I / F) 21 Input / output controller 22 Random access memory (RAM) 23 Non-volatile memory 24 Flash memory 31 Logic block 41 External storage device 100 Information processing system 120 Bus 121 Central processing unit (CPU) 122 Random access memory (RAM) 123 Storage device 126 Communication device 127 Input device 128 Display device

Claims

1. A storage device having a self-encryption function for data to be stored, and an erasure controller that controls erasure of data stored in the storage device, the storage device comprising: a storage medium having a storage area; a non-volatile memory storing an encryption key; and an input / output controller that writes input data to the storage area, outputs data read from the storage area, encrypts at least a portion of the data to be written to the storage area using the encryption key, and decrypts at least a portion of the data read from the storage area using the encryption key, the erasure controller controls the storage device to: if a first encryption key is stored in the non-volatile memory, compress data read from a specified position in the storage area to generate first sample data; change the first encryption key stored in the non-volatile memory to a second encryption key; if a second encryption key is stored in the non-volatile memory, compress data read from the specified position in the storage area to generate second sample data; and if the second sample data is different from the first sample data, output a verification result indicating that the erasure of the data stored in the storage device was successful; outputting a verification result indicating that erasure of the data stored in the storage device has failed if the second sample data matches the first sample data.

2. An information processing device as described in claim 1, wherein the first sample data includes first compressed data obtained by compressing first data read from a first location in the memory area and a first hash value calculated based on second data read from a second location in the memory area, and the second sample data includes second compressed data obtained by compressing third data read from the first location in the memory area and a second hash value calculated based on fourth data read from the second location in the memory area.

3. An information processing device as described in claim 1, wherein the first sample data includes first compressed data obtained by compressing first data read from a first location in the memory area and second data read from a second location in the memory area, and the second sample data includes second compressed data obtained by compressing third data read from the first location in the memory area and fourth data read from the second location in the memory area.

4. An information processing device as described in claim 1, wherein the first sample data includes first compressed data obtained by compressing first data read from a first location in the memory area, a first hash value calculated based on second data read from a second location in the memory area, and third data read from a third location in the memory area, and the second sample data includes second compressed data obtained by compressing fourth data read from the first location in the memory area, a second hash value calculated based on fifth data read from the second location in the memory area, and sixth data read from the third location in the memory area.

5. An information processing device according to any one of claims 1 to 4, wherein the erasure controller outputs a verification result indicating successful erasure of the data stored in the storage device when a portion of the second sample data is different from a corresponding portion of the first sample data, and outputs a verification result indicating unsuccessful erasure of the data stored in the storage device when a portion of the second sample data matches a corresponding portion of the first sample data.

6. An information processing device according to any one of claims 1 to 4, wherein the erasure controller outputs a verification result indicating that erasure of the data stored in the storage device has been successful if the file size of the second sample data is different from the file size of the first sample data, and outputs a verification result indicating that erasure of the data stored in the storage device has failed if the file size of the second sample data matches the file size of the first sample data.

7. An information processing device according to any one of claims 1 to 4, wherein the erasure controller encrypts the first sample data, and stores the encrypted first sample data in an external storage device provided outside the information processing device.

8. An information processing device according to any one of claims 1 to 4, wherein the memory area includes a plurality of blocks, and the first and second sample data are calculated for each of a predetermined number of blocks based on data stored in the blocks.

9. An information processing device according to any one of claims 1 to 4, wherein the memory area includes a plurality of partial areas formed by logically dividing the memory area, each partial area including a plurality of logically contiguous blocks, the erasure controller specifies, for each of the plurality of partial areas, a different proportion of blocks among the plurality of blocks included in the partial area, and the first and second sample data are calculated based on data stored in the specified plurality of blocks.

10. An information processing device according to any one of claims 1 to 4, wherein the memory area includes a plurality of blocks, and the first and second sample data are calculated based on data stored in a plurality of blocks that are logically adjacent to each other.

11. The information processing apparatus according to claim 1, further comprising a first display device that outputs the verification result.

12. The information processing device according to claim 11, wherein said erasure controller outputs a progress of erasure of data stored in said storage device to said first display device.

13. An information processing device comprising: a storage device having a self-encryption function for data to be stored; and an erasure controller that controls erasure of data stored in the storage device, wherein the storage device comprises: a storage medium having a storage area; a non-volatile memory storing an encryption key; and an input / output controller that writes input data to the storage area, outputs data read from the storage area, encrypts at least a portion of the data to be written to the storage area using the encryption key, and decrypts at least a portion of the data read from the storage area using the encryption key, wherein the erasure controller: if a first encryption key is stored in the non-volatile memory, compresses first data read from a specified position in the storage area; controls the storage device to change the first encryption key stored in the non-volatile memory to a second encryption key; if the second encryption key is stored in the non-volatile memory, obtains second data read from the specified position in the storage area; if the second data is different from the first data, outputs a verification result indicating that erasure of the data stored in the storage device has been successful; and if the second data matches the first data, outputs a verification result indicating that erasure of the data stored in the storage device has failed.

14. A storage device having a self-encryption function for data to be stored, and an erasure controller for controlling erasure of data stored in the storage device, wherein the storage device comprises: a storage medium having a storage area; a non-volatile memory storing an encryption key; and an input / output controller for writing input data to the storage area, outputting data read from the storage area, encrypting at least a portion of the data to be written to the storage area using the encryption key, and decrypting at least a portion of the data read from the storage area using the encryption key, wherein the erasure controller generates first sample data including a first hash value calculated based on first data read from a first position in the storage area and second data read from a second position in the storage area when a first encryption key is stored in the non-volatile memory, and controls the storage device to change the first encryption key stored in the non-volatile memory to a second encryption key, an information processing device which, when the second encryption key is stored in the non-volatile memory, generates second sample data including a second hash value calculated based on third data read from the first location of the storage area and fourth data read from the second location of the storage area; when the second sample data is different from the first sample data, outputs a verification result indicating that the data stored in the storage device has been successfully erased; and when the second sample data matches the first sample data, outputs a verification result indicating that the data stored in the storage device has not been successfully erased.

15. An information processing system comprising: an information processing device according to claim 1; and a server device connected to said information processing device via a communication line, wherein said erasure controller controls erasure of data stored in said storage device in accordance with a control signal received from said server device.

16. The information processing system according to claim 15, wherein the erasure controller transmits a first notification signal including the verification result to the server device, and the server device includes a second display device that outputs the verification result.

17. The information processing system according to claim 16, wherein the erasure controller transmits a second notification signal including a progress degree of erasure of the data stored in the storage device to the server device, and the second display device displays the progress degree.

18. An information processing method for controlling erasure of data stored in a storage device having a self-encrypting function, the storage device comprising: a storage medium having a storage area; a non-volatile memory storing an encryption key; and an input / output controller for writing input data to the storage area, outputting data read from the storage area, encrypting at least a portion of the data to be written to the storage area using the encryption key, and decrypting at least a portion of the data read from the storage area using the encryption key, the information processing method comprising the steps of: when a first encryption key is stored in the non-volatile memory, compressing data read from a specified position in the storage area to generate first sample data; controlling the storage device to change the first encryption key stored in the non-volatile memory to a second encryption key; when the second encryption key is stored in the non-volatile memory, compressing data read from the specified position in the storage area to generate second sample data; and when the second sample data is different from the first sample data, outputting a verification result indicating that erasure of data stored in the storage device has been successful; outputting a verification result indicating that erasure of the data stored in the storage device has failed if the second sample data matches the first sample data.

19. A program including instructions to be executed by a processor implemented in an information processing device, the information processing device further comprising a storage device having a function of self-encrypting data stored therein, the storage device comprising: a storage medium having a storage area; a non-volatile memory storing an encryption key; and an input / output controller for writing input data to the storage area, outputting data read from the storage area, encrypting at least a portion of the data written to the storage area using the encryption key, and decrypting at least a portion of the data read from the storage area using the encryption key, the instructions causing the processor to: control the storage device to change the first encryption key stored in the non-volatile memory to a second encryption key; control the storage device to compress the data read from the specified position in the storage area to generate first sample data, if a first encryption key is stored in the non-volatile memory; control the storage device to change the first encryption key stored in the non-volatile memory to a second encryption key, if the second encryption key is stored in the non-volatile memory; and outputting a verification result indicating that the erasure of data stored in the storage device was successful, if the second sample data is different from the first sample data. and outputting a verification result indicating that erasure of the data stored in the storage device has failed if the second sample data matches the first sample data.

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