Enhanced serial media independent interface

Abstract

A serial media independent interface (Mil) for a host device and / or a physical layer (PHY) device embeds a register access protocol such as management data input / output (MDIO) in a serial data stream. Symbol ordered sets are exchanged over the Mil and / or enhanced SMII interface. At least one of the symbol ordered sets selectively defines a sync signal allowing removal of a sync signal and corresponding sync pin. Clock speeds are selectively reduced on the enhanced SMII interface. Toggling power is selectively reduced when idles are exchanged.

Description

ENHANCED SERIAL MEDIA INDEPENDENT INTERFACECROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 597,727, filed on November 10, 2023. The entire disclosures of the applications referenced above are incorporated herein by reference.FIELD

[0002] The present disclosure relates to serial media independent interface.BACKGROUND

[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0004] IEEE 802.3 Clause 22 specifies a media independent interface (Mil) that includes a 16-pin digital interface to connect Ethernet media access control (MAC) devices to Ethernet physical layer (PHY) devices in order to exchange Ethernet traffic. Data is passed one nibble (4-bits) per clock cycle along with control signals to indicate non-data symbols. Two nibbles are required to form one byte. There is also a 2-pin digital interface management data clock (MDC) / management data input / output (MDIO) (or MDC / MDIO) to allow the MAC to access registers in the PHY.

[0005] For a device that communicates with multiple PHYs, one 16-pin interface is required to exchange data with each PHY. The 2-pin interface can be shared with the MDC clock sent to all of the PHYs and the MDIO being a multi-drop bidirectional bus. The host device including the MACs can address each of the PHYs individually via a unique PHY address. The bandwidth to access the registers are shared among the PHYs. The host can implement a dedicated 2-pin interface to accesseach PHY so that the registers of the PHYs can be accessed in parallel. The Mil operation is limited to PHYs exchanging data at 10 Mb / s and 100 Mb / s.

[0006] IEEE 802.3 Clause 35 defines the gigabit media independent interface (GM 11) by extending the TXD and RXD signals from 4 pins to 8 pins, hence a 24-pin interface that transfers data. The 2-pin interface to access registers remain unchanged. GMII operation is limited to PHYs exchanging data at 1000 Mb / s.

[0007] IEEE 802.3 Clause 46 defines the 10 gigabit media independent interface (XGMII) which extends the GMII and simplifies it by eliminating support for half duplex operation. The TXD and RXD are extended to 32-pins each and the control signals TXC and RXC are 4-pins each. Two source synchronous clocks round out the interface for a total of 74-pins. The XGMII operation is limited to 10 Gb / s and 25Gb / s operation. In addition to the speed increase, the XGMII defines codes to exchange ordered sets that is not available to the in the original Mil interface.

[0008] IEEE 802.3 Clause 45 modifies the Clause 22 2-pin interface to allow for access to a wider address space. This interface remains 2-pins, but the number of registers accessible per PHY device is greatly expanded. There are additional extensions to the Mil such as in IEEE 802.3 Clause 81 (XLGMII, CGMII) each with a wider bus.

[0009] From a practical implementation perspective, XGMII and faster interfaces are rarely exposed to a chip as a digital interface as the number of pins required on the package is too expensive. They are usually serialized via a SERDES which is a mixed signal device with clock recovery. The extra die area and complexity associated with serializing / deserializing is less costly than implementing a wide parallel bus on the package.SUMMARY

[0010] A method for operating a serial media independent interface includes outputting a transmit serial data stream on a transmit pin; receiving a receive serial data stream on a receive pin;and embedding a register access protocol in at least one of the transmit data stream and the receive data stream.

[0011] In other features, the register access protocol includes a management data input / output (MDIO).

[0012] A method for operating a serial media independent interface includes outputting a transmit serial data stream on a transmit pin; receiving a receive serial data stream on a receive pin; generating a clock signal on a clock pin; reducing a toggle rate of the clock signal on the clock pin; clocking the transmit serial data stream and the receive data stream using rising and falling edges of the clock signal.

[0013] A method for operating a serial media independent interface includes outputting a transmit serial data stream on a transmit pin; receiving a receive serial data stream on a receive pin. The transmit serial data stream periodically includes a sequence ordered set representing a position of a sync signal.

[0014] In other features, the sequence ordered set is a unique sequence that cannot be generated without generating invalid symbols.

[0015] In other features, the sequence ordered set includes a sequence symbol and three data bytes.

[0016] A method for operating a serial media independent interface of a physical layer device includes outputting a transmit serial data stream on a transmit pin; receiving a receive serial data stream on a receive pin; and selectively stalling at least one of a read transaction and a write transaction.

[0017] Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims, and the drawings. The detailed description and specific examplesare intended for purposes of illustration only and are not intended to limit the scope of the disclosure.BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 is a functional block diagram of an example of a serial media independent interface (Mil);

[0019] FIGS. 2 and 3 are functional block diagrams of examples of serial media independent interfaces (Mils) for multiple physical layer devices (PHYs);

[0020] FIG. 3 is an example of a timing diagram for the Mils in FIGS. 2 or 3;

[0021] FIGS. 4 and 5 are examples of write and read timing diagrams;

[0022] FIG. 6 is a functional block diagram of an example of a Mil including a serializer / deserializer (SERDES);

[0023] FIG. 7 is an example of a timing diagram for synchronization, transmitting, and receiving according to the present disclosure;

[0024] FIGS. 8 and 9 are examples of write transaction timing diagrams according to the present disclosure;

[0025] FIGS. 10 and 12 are examples of read transaction timing diagrams according to the present disclosure;

[0026] FIG. 13 is an example of a timing diagram illustrating reducing a toggle rate of the clock according to the present disclosure;

[0027] FIGS. 14 and 15 are examples of code mapping tables according to the present disclosure;

[0028] FIG. 16 is an example of a table illustrating elimination of the sync signal using SMII sequence ordered set according to the present disclosure;

[0029] FIG. 17 is an example of a functional block diagram of the Mil with 2N+1 pins according to the present disclosure;

[0030] FIG. 18 is an example of a functional block diagram of one side of an Mil link supporting asymmetrical traffic according to the present disclosure; and

[0031] FIG. 19 is an example of a functional block diagram of the other side of the Mil link supporting asymmetrical traffic according to the present disclosure.

[0032] In the drawings, reference numbers may be reused to identify similar and / or identical elements.DESCRIPTION

[0033] Referring now to FIGS. 1 and 2, media independent interfaces (Mils) are shown. In FIG. 1, the Mils 10 at the host and an Mil 20 at the PHY include converters 14 and 24, respectively. The Mils 10 and 20 can be serialized without the need for using a serializer / deserializer (SERDES). The serialized data is slow enough that digital I / O pads are used. The Mil signals are serialized and deserialized to a single TX and RX pin in each direction. A single clock CLK is used for both directions. If the TX_CLK and RX_CLK are not frequency locked to CLK then a first in first out (FIFO) buffer is needed in the converters 14 and 24 to occasionally add or drop idle symbols to account for the frequency differences. The register access method remains unchanged. Hence an 18-pin interface is reduced to a 6-pin interface.

[0034] If a host needs to support n PHYs, 2n +4 pins are required on the host device while each PHY requires 6 pins. An Mil 30 in FIG. 2 includes a converter 34 including 2n+4 pins. N PHYs 40-1, 40- 2, 40-3, 40-4, ... include converters 44-1, 44-2, 44-3, 44-4, ... , respectively, each with 6 pins. The disadvantage to this approach is that a management data clock (MDC) / management data input / output (MDIO) bandwidth has to be shared across all N PHYs 40-1, 40-2, 40-3, 40-4, ....,

[0035] Referring now to FIGS. 3 and 4, an alternate method is to implement parallel MDC / MDIO.An Mil 50 includes a converter 54 including 4n+l pins as shown in FIG. 3. N PHYs 60-1, 60-2, 60-3, 60-4, ... include converters 64-1, 64-2, 64-3, 64-4, ... , respectively, each with 6 pins. In this case 4n + 2 pins are required on the host.

[0036] In FIG. 4, the CLK runs at 125MHz for lOOMb / s operation and is nominally 5 times faster than the RX_CLK or TX_CLK. Every 10 clock cycles the SYNC pulse goes high to delineate the 10 bit group of signals. CLK runs at 12.5 MHz for lOMb / s operation.MANAGEMENT INTERFACE OF THE MH

[0037] Referring now to FIG. 5, the MDC / MDIO write and read operation are shown below using IEEE 802.3 Clause 45 as an example. The MDIO is driven by the host or PHY depending on which one is driving the bus and Hi-impedance (Z) if it is not being driven. If neither device is driving the MDIO (both Hi-Z), the MDIO is pulled up by an external resistor.

[0038] At the start of a transaction, the MDIO is driven low by the host. The subsequent 32 MDC clock cycles are active for the transaction. Prior to initiating the transaction, highs are sent over 32 MDC clock cycles to form a preamble. This allows the PHY to establish synchronization. If this synchronization is not required by the PHY, the preamble may be suppressed.

[0039] The host can use one MDC / MDIO interface to serve multiple PHYs. The PHY address P[4:0] of the transaction is used to identify the PHY the transaction is targeting. For read operations, the D15 bit has to be ready within two MDC cycles after the E0 bit is presented. There is no mechanism to defer returning data beyond two MDC cycles. The worst case data return time limits the speed of the MDC frequency.NON-DATA SYMBOLS ON THE *MII

[0040] The Mil is defined to carry a limited set of non-data symbols with idles, error symbol, and low power idle (LPI) being the main ones. In XGMII the sequence ordered set is introduced forindications of faults. Ordered sets are 4-byte sequence starting with a sequence symbol followed by three data symbols.SERDES IMPLEMENTATION

[0041] Referring now to FIG. 6, the *MII interface (e.g., XGMII) is serialized between chips in order to reduce pin count as discussed earlier. In this example, a host 110 includes a 10GBASE-R physical coding sublayer (PCS) 112, a serializer 114, and a deserializer 118. A physical layer device 120 includes a deserializer 124 communicating with the serializer 114 of the host 110. The physical layer device 120 includes a serializer 128 communicating with the deserializer 118 of the host 110.

[0042] An example of a 10 Gb / s path is shown below where a SERDES is used to serialize and deserialize the data. The data is sent on differential pairs (e.g., TXP / TXN). The management interface is implemented separately as MDC / MDIO. The interface occupies a total of 6 pins on the package. A higher speed SERDES can be used to send and receive lower speed data. For example, 1000 Mb / s data can be sent using the 10GBASE-R SERDES by replicating the data 10 times. Another technique is to buffer the data and then send the data full speed (10 Gb / s).

[0043] The present disclosure enhances the serial Mil discussed above. In particular, one or more of the following enhancements are made and any combinations of them can be implemented. In some examples, the MDIO data is embedded in the serial stream. In some examples, symbol ordered sets are exchanged over the Mil and enhanced SMII interface. The clock speeds are reduced on the enhanced SMII interface. In some examples, toggling power is reduced when idles are exchanged. The SYNC signal of the SMII is eliminated.

[0044] In the landscape of multi gigabit speed PHYs, the 100 Mb / s speeds is becoming important again for asymmetrical operation. In other words, one direction operates at 10 Gb / s and the other at lOMb / s or 100 Mb / s. In this optimized PHY, it would not make sense to use a 10G SERDES in both direction to support XGMII operation. One direction would use the SERDES while the other direction can use a simple digital interface.

[0045] The present disclosure discusses the symmetrical operation where both directions operate at lOOMb / s or at 10 Mb / s. In an asymmetrical PHY, the data path that uses the lower speed would implement either the TX or RX interface of the enhanced SMII.EMBEDDING MDIO DATA IN THE SERIAL STREAM

[0046] Referring now to FIG. 7, the SMII cycles every 10 clock cycles and is framed by the SYNC signal. Instead of using TX_ER / TX_EN and CRS / RX_DV, the encoding is compacted using TXC and RXC and one bit is freed up to carry the MDIO.

[0047] Arbitrarily, the MDIO bit is sent when SYNC is high, but we can define it to be in any of the 10 positions as long as it is consistent. Each MDIO bit sent corresponds to a bit sent for each MDC clock cycle in MANAGEMENT INTERFACE OF THE Mil section below. Normally when there is no management data to transfer the MDIO bit is set high. To start a transaction, the MDIO bit on the TX is set low, and the 32 bits (during the time when SYNC is high) are used to exchange data in the transaction. After the transaction completes the MDIO bit is set high.

[0048] Referring now to FIGS. 8 and 9, for a write transaction, the MDIO bits on the TX follow the bit order described in IEEE 802.3 Clause 22 or Clause 45. The M DIO bit on RX remains high for the duration of the transaction if the write can be processed at speed. The period of the SYNC cycle is 80ns for 100 Mb / s operation. This is a lot shorter than the typical MDC clock period. The internal logic of the PHY may not be able to write data this quickly. The PHY can stall by setting bit 31 low and in subsequent SYNC cycles until it is ready for another transaction. The bit is set to 1 to indicate that it is ready to accept another transaction. The host should not send another transaction until then. Note that bits prior to bit 31 can be set low earlier to give an early indication that the transaction will be stalled.

[0049] Referring now to FIGS. 10 to 12, for a read transaction, the initial portion of the transaction is on the TX while the remaining portion is on the RX. Bits 14 and 15 are turnaround cycles. If read data available starting at bit 16 (0 SYNC cycle delay) bit 15 is set to 0 and bit 14 is don't care.

[0050] The period of the SYNC cycle is 80ns for 100 Mb / s operation. This is a lot shorter than the typical MDC clock period. The internal logic may not be able to return data within 80ns. A mechanism is introduced to extend the turnaround. To extend the turnaround time, bit 14 is set low indicating the PHY will respond to the read transaction, and bit 15 is set high to indicate response will not be ready on bit 16. The MDIO bit is held high until read data is ready internally. If the data is ready after N SYNC cycle delay, the bit is set low on SYNC cycle 15 + N to indicate bit D15 will be presented at cycle 16 + N.

[0051] In FIG. 11, in the case where the PHY stalls indefinitely, the host can terminate the transaction by issuing a new transaction, setting the MDIO on TX to low.

[0052] In FIG. 12, in the case where the PHY does not respond, bit 14 and bit 15 are set high indicating no response.EXCHANGING SEQUENCE ORDERED SETS

[0053] The XGMII is a 4-byte wide interface. Sequence ordered sets consisting of 4 bytes are aligned with this interface. The Mil is a nibble wide interface with the expectation that even nibbles are sent to form a byte. However, there is no concept of a 4-byte wide boundary.

[0054] The sequence ordered set can start on any byte on the Mil (extended SMII). This sequence starts with a sequence symbol followed by three data symbols. In cases where the four symbols (bytes) cannot be completely sent because of the start of packet, a sequence ordered set abort symbol is sent to terminate the ordered set early. The partial received bytes of the sequence ordered set are ignored and treated as idles.

[0055] In the CODE MAPPING section below, an example of mapping for the sequence and abort symbols.REDUCING CLK SPEED

[0056] Referring now to FIG. 13, the toggle rate of the CLK can be reduced by 50% if alternate rising and falling edges are used to clock the SYNC, TX, and RX. This can reduce the I / O power. The rising edge sampled bits are referred to as even bits and the falling edge sampled bits as odd bits in the following discussion.CODE MAPPING

[0057] Referring now to FIGS. 14 to 15, the code mapping is shown below. This is one example of the mapping. The codes are chosen to minimize transition on the TX and RX. Assuming MDIO is inactive (set to 1), an idle symbol incurs no transition per SYNC cycle. Low power idle and symbol error incurs one low to high and one high to low transition regardless of the state of the MDIO bit.

[0058] The sequence symbol is the first byte of the sequence ordered set. When a sequenced order set symbol is sent, it is followed by 3 data bytes to indicate what type of ordered set it is.

[0059] If a sequenced ordered set symbol is sent but all 3 following data bytes cannot be completed because a packet is pending, it can be prematurely aborted by sending the abort sequence symbol.

[0060] The invalid (sync) symbols listed are reserved and should never be used for anything in the future. This is explained more fully in the next section.ELIMINATING THE SYNC PIN

[0061] Referring now to FIG. 16, the SYNC signal can be eliminated by periodically sending the sync sequence ordered set on the TX pin. By finding the pattern of the sync sequence ordered set the position of the SYNC can be determined. The bits on the RX pin is aligned to the bits on the TX pin.

[0062] The Sync Mil sequenced ordered set guarantees a unique pattern regardless of the placement of the symbols as long as the Invalid symbols are never used. The gray cells in FIG. 16show the symbols that would cause a false alignment. The sequence symbol of OxAA places l's on all the odd bits and a data symbol can never place l's in all 5 odd bits. Hence data by itself can never create a sequence symbol. It is only in combination with either the sequence symbol itself or one of the invalid symbols that a Sync SMII sequence ordered set can be created.

[0063] When a SYNC SM II sequence order set is received by the PHY, it is converted to an idle or low power idle depending on what was previously seen. This can be sent periodically by the host during idles or at the very beginning during device startup.COMBINED EFFECT

[0064] Referring now to FIG. 17, implementing all the options presented here results in 2N + 1 pins for N ports. A host 310 includes a converter 314 generating TX* and RX* signals a CLK shared by the N PHYs 320-1, 320-2, 320-3, 320-4, ..., where N is an integer greater than one. The N PHYs 320-1, 320-2, 320-3, 320-4, ..., include converters 324-1, 324-2, 324-3, 324-4, ... .ASYMMETRICAL TRAFFIC

[0065] Referring now to FIGS. 18 and 19, the discussion so far has been on symmetrical traffic. For certain applications such as camera, video traffic in one direction is high bandwidth and control traffic in the other direction is very low bandwidth. It would be wasteful to use a full SERDES for traffic in the slow direction.

[0066] In FIG. 18, lOGb / s in one direction and 100 Mb / s in the other shows a less costly solution where only half the SERDES is required. A host 410 includes a XGMII. A 10GBASE-R PCS 414 receives the XGMII data and outputs data to a serializer 416. A converter 420 outputs TX, RX and CLK to a converter 440 of the physical layer device (PHY) 430. The PHY 430 includes an XGMII 432. The PHY 430 further includes a deserializer 436 that outputs deserialized data to a 10GBASE-R PCS 434, which outputs XGMII data.

[0067] The Mil to the enhanced SMII converter is simple digital logic unlike the SERDES. The TX pin of the enhanced SMII is used to exchange data for register access only. Also, only 5 pins are required for this solution if the ELIMINATING THE SYNC PIN section is used to eliminate the SYNC pin.

[0068] In FIG. 19, a similar diagram below is the other half of the link. In this case the RX pin of the enhanced SMII is used to exchange data for register access only.

[0069] IEEE 802.3 Clauses 22, 35, 45, 46, and 81 are hereby incorporated herein by reference in their entirety.

[0070] The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure. Further, although each of the embodiments is described above as having certain features, any one or more of those features described with respect to any embodiment of the disclosure can be implemented in and / or combined with features of any of the other embodiments, even if that combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more embodiments with one another remain within the scope of this disclosure.

[0071] Spatial and functional relationships between elements (for example, between modules, circuit elements, semiconductor layers, etc.) are described using various terms, including "connected," "engaged," "coupled," "adjacent," "next to," "on top of," "above," "below," and "disposed." Unless explicitly described as being "direct," when a relationship between first and second elements is described in the above disclosure, that relationship can be a direct relationship where no other intervening elements are present between the first and second elements, but canalso be an indirect relationship where one or more intervening elements are present (either spatially or functionally) between the first and second elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A OR B OR C), using a non-exclusive logical OR, and should not be construed to mean "at least one of A, at least one of B, and at least one of C."

[0072] In the figures, the direction of an arrow, as indicated by the arrowhead, generally demonstrates the flow of information (such as data or instructions) that is of interest to the illustration. For example, when element A and element B exchange a variety of information but information transmitted from element A to element B is relevant to the illustration, the arrow may point from element A to element B. This unidirectional arrow does not imply that no other information is transmitted from element B to element A. Further, for information sent from element A to element B, element B may send requests for, or receipt acknowledgements of, the information to element A.

[0073] In this application, including the definitions below, the term "module" or the term "controller" may be replaced with the term "circuit." The term "module" may refer to, be part of, or include: an Application Specific Integrated Circuit (ASIC); a digital, analog, or mixed analog / digital discrete circuit; a digital, analog, or mixed analog / digital integrated circuit; a combinational logic circuit; a field programmable gate array (FPGA); a processor circuit (shared, dedicated, or group) that executes code; a memory circuit (shared, dedicated, or group) that stores code executed by the processor circuit; other suitable hardware components that provide the described functionality; or a combination of some or all of the above, such as in a system-on-chip.

[0074] The module may include one or more interface circuits. In some examples, the interface circuits may include wired or wireless interfaces that are connected to a local area network (LAN), the Internet, a wide area network (WAN), or combinations thereof. The functionality of any given module of the present disclosure may be distributed among multiple modules that are connected via interface circuits. For example, multiple modules may allow load balancing. In a further example, aserver (also known as remote, or cloud) module may accomplish some functionality on behalf of a client module.

[0075] The term code, as used above, may include software, firmware, and / or microcode, and may refer to programs, routines, functions, classes, data structures, and / or objects. The term shared processor circuit encompasses a single processor circuit that executes some or all code from multiple modules. The term group processor circuit encompasses a processor circuit that, in combination with additional processor circuits, executes some or all code from one or more modules. References to multiple processor circuits encompass multiple processor circuits on discrete dies, multiple processor circuits on a single die, multiple cores of a single processor circuit, multiple threads of a single processor circuit, or a combination of the above. The term shared memory circuit encompasses a single memory circuit that stores some or all code from multiple modules. The term group memory circuit encompasses a memory circuit that, in combination with additional memories, stores some or all code from one or more modules.

[0076] The term memory circuit is a subset of the term computer-readable medium. The term computer-readable medium, as used herein, does not encompass transitory electrical or electromagnetic signals propagating through a medium (such as on a carrier wave); the term computer-readable medium may therefore be considered tangible and non-transitory. Non-limiting examples of a non-transitory, tangible computer-readable medium are nonvolatile memory circuits (such as a flash memory circuit, an erasable programmable read-only memory circuit, or a mask read-only memory circuit), volatile memory circuits (such as a static random access memory circuit or a dynamic random access memory circuit), magnetic storage media (such as an analog or digital magnetic tape or a hard disk drive), and optical storage media (such as a CD, a DVD, or a Blu-ray Disc).

[0077] In this application, apparatus elements described as having particular attributes or performing particular operations are specifically configured to have those particular attributes andperform those particular operations. Specifically, a description of an element to perform an action means that the element is configured to perform the action. The configuration of an element may include programming of the element, such as by encoding instructions on a non-transitory, tangible computer-readable medium associated with the element.

[0078] The apparatuses and methods described in this application may be partially or fully implemented by a special purpose computer created by configuring a general purpose computer to execute one or more particular functions embodied in computer programs. The functional blocks, flowchart components, and other elements described above serve as software specifications, which can be translated into the computer programs by the routine work of a skilled technician or programmer.

[0079] The computer programs include processor-executable instructions that are stored on at least one non-transitory, tangible computer-readable medium. The computer programs may also include or rely on stored data. The computer programs may encompass a basic input / output system (BIOS) that interacts with hardware of the special purpose computer, device drivers that interact with particular devices of the special purpose computer, one or more operating systems, user applications, background services, background applications, etc.

[0080] The computer programs may include: (i) descriptive text to be parsed, such as HTML (hypertext markup language), XML (extensible markup language), or JSON (JavaScript Object Notation) (ii) assembly code, (iii) object code generated from source code by a compiler, (iv) source code for execution by an interpreter, (v) source code for compilation and execution by a just-in-time compiler, etc. As examples only, source code may be written using syntax from languages including C, C++, C#, Objective-C, Swift, Haskell, Go, SQL, R, Lisp, Java®, Fortran, Perl, Pascal, Curl, OCaml, Javascript®, HTML5 (Hypertext Markup Language Sth revision), Ada, ASP (Active Server Pages), PHP (PHP: Hypertext Preprocessor), Scala, Eiffel, Smalltalk, Erlang, Ruby, Flash®, Visual Basic®, Lua,MATLAB, SIMULINK, and Python®.

Claims

CLAIMSWhat is claimed is:

1. A method for operating a serial media independent interface, comprising: outputting a transmit serial data stream on a transmit pin; receiving a receive serial data stream on a receive pin; and embedding a register access protocol in at least one of the transmit serial data stream and the receive serial data stream.

2. The method of claim 1, wherein the register access protocol includes a management data input / output (MDIO).

3. A method for operating a serial media independent interface, comprising: outputting a transmit serial data stream on a transmit pin; receiving a receive serial data stream on a receive pin; generating a clock signal on a clock pin; reducing a toggle rate of the clock signal on the clock pin; and clocking the transmit serial data stream and the receive serial data stream using rising and falling edges of the clock signal.

4. A method for operating a serial media independent interface, comprising: outputting a transmit serial data stream on a transmit pin; and receiving a receive serial data stream on a receive pin, wherein the transmit serial data stream periodically includes a sequence ordered set representing a position of a sync signal.

5. The method of claim 4, wherein the sequence ordered set is a unique sequence that cannot be generated without generating invalid symbols.

6. The method of claim 4, wherein the sequence ordered set includes a sequence symbol and three data bytes.

7. A method for operating a serial media independent interface of a physical layer device, comprising: outputting a transmit serial data stream on a transmit pin; receiving a receive serial data stream on a receive pin; and selectively stalling at least one of a read transaction and a write transaction.

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