Processor scheduling method and apparatus, electronic device, storage medium, and chip

Abstract

The present application relates to the technical field of information scheduling, and discloses a processor scheduling method and apparatus, an electronic device, a storage medium, and a chip. The processor scheduling method comprises: acquiring a first impact parameter of a first processor, the first impact parameter being used for representing the degree of impact of a storage resource on the computing performance of the first processor; and adjusting the working frequency of the storage resource on the basis of the first impact parameter, wherein the storage resource comprises one or more of a processor cache, a main memory, and a system cache interfaced with the first processor.

Description

Processor scheduling method, device, electronic device, storage medium and chip

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202410343144.0 filed on March 25, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application belongs to the field of information scheduling technology, and specifically relates to a processor scheduling method, device, electronic device, storage medium and chip. Background Art

[0004] Processor scheduling is an important function in the operating system. It enables the concurrent execution of multiple processes / threads by dynamically allocating time slices of the Central Processing Unit (CPU).

[0005] Taking the Linux system as an example, it uses the Completely Fair Scheduler (CFS) for scheduling. CFS uses a time slice round-robin method to allocate CPU time slices to each process, ensuring fair competition between processes and improving system performance and response speed.

[0006] CFS determines the CPU's operating frequency based on the current CPU load and the configured frequency scaling policy. Typically, when the CPU is under high load, the frequency is increased to improve computing power, while when idle, the frequency is reduced to conserve energy. Users can also manually set the CPU's operating frequency to meet different performance and power requirements.

[0007] However, the above scheduling scheme uses the CPU running time as the scheduling basis, which cannot identify the situation where the CPU performance is affected by storage resources and cannot improve the CPU energy efficiency. Summary of the Invention

[0008] The purpose of the embodiments of the present application is to provide a processor scheduling method, device, electronic device, storage medium and chip, which can solve the problem of using the CPU's running time as the scheduling basis, failing to identify that the CPU's performance is affected by storage resources, and failing to improve the CPU's energy efficiency.

[0009] In a first aspect, an embodiment of the present application provides a processor scheduling method, comprising: obtaining a first influencing parameter of a first processor, the first influencing parameter being used to indicate the extent to which the computing performance of the first processor is affected by storage resources; adjusting the operating frequency of the storage resources based on the first influencing parameter; wherein the storage resources include one or more of a processor cache, a main memory, and a system cache connected to the first processor.

[0010] In second aspect, an embodiment of the present application provides a processor scheduling device, comprising: an acquisition module for acquiring a first influencing parameter of a first processor, the first influencing parameter being used to indicate the extent to which the computing performance of the first processor is affected by storage resources; an adjustment module for adjusting the operating frequency of the storage resources based on the first influencing parameter; wherein the storage resources include one or more of a processor cache, a main memory, and a system cache connected to the first processor.

[0011] In a third aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method of the first aspect are implemented.

[0012] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method of the first aspect are implemented.

[0013] In a fifth aspect, an embodiment of the present application provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the steps of the method in the first aspect.

[0014] In a sixth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the steps of the method of the first aspect.

[0015] In an embodiment of the present application, the first influencing parameter obtained can indicate the degree to which the computing performance of the first processor is affected by the storage resources, so the first influencing parameter can be used to adjust the operating frequency of the storage resources. In this process, when the computing performance of the first processor is greatly affected by the storage resources, the operating frequency of the storage resources is adjusted to alleviate or improve the degree to which the computing performance is affected by the storage resources, thereby improving the energy efficiency of the first processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG1 is a diagram showing one of the system architectures of a CPU subsystem in a chip according to some embodiments of the present application;

[0017] FIG2 is a second system architecture diagram of a CPU subsystem in a chip according to some embodiments of the present application;

[0018] FIG3 is a flowchart of a method for scheduling a processor in some embodiments of the present application;

[0019] FIG4 is a flowchart of a chip scheduling method in some embodiments of the present application when the chip includes a large-core central processing unit, a medium-core central processing unit, and a small-core central processing unit;

[0020] FIG5 is a second flow chart of a method for scheduling a processor in some embodiments of the present application;

[0021] FIG6 is a third flowchart of a method for scheduling a processor in some embodiments of the present application;

[0022] FIG7 is a schematic block diagram of a scheduling device for a processor in an embodiment of the present application;

[0023] FIG8 is a schematic block diagram of an electronic device in an embodiment of the present application;

[0024] FIG9 is a schematic diagram of the hardware structure of the electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0026] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0027] The processor cache refers to the processor's private cache and shared cache. In the embodiment of the present application, the processor cache takes the third-level cache (L3 Cache) as an example.

[0028] Main memory, also known as internal memory and main memory, is used to temporarily store the calculation data in the processor and the data interacting with external memory such as hard disk. It is a bridge for communication between external memory and processor.

[0029] The system level cache (System Level Cache) connected to the first processor is a cache shared by the subsystem where the first processor is located and other subsystems, and is located between the processor cache and the main memory.

[0030] The following, in conjunction with the accompanying drawings, describes in detail the processor scheduling method, device, electronic device, storage medium and chip provided in the embodiments of the present application through specific embodiments and their application scenarios.

[0031] Exemplarily, FIG1 shows a system architecture diagram of a CPU subsystem in a chip. As shown in FIG1 , the chip system includes three types of CPU cores, namely, a large-core central processing unit, a medium-core central processing unit, and a small-core central processing unit.

[0032] Specifically, the big-core central processing unit, Big CPU, is used to process high-performance tasks, such as running large games or high-load applications; the middle-core central processing unit, Middle CPU, is used to process medium-load tasks, such as daily applications and browsers; the small-core central processing unit, Little CPU, is used to process low-load tasks, such as background applications and system maintenance tasks.

[0033] Among them, the layered design of Big CPU + Middle CPU + Little CPU can meet performance requirements while minimizing the energy consumption of the chip.

[0034] In some embodiments of the present application, the system architecture diagram of the chip is a combination of a large-core CPU, multiple medium-core CPUs, and multiple small-core CPUs.

[0035] For example, a "1+3+4" design may be adopted, that is, 1 Big CPU + 3 Middle CPUs + 4 Little CPUs, or a "1+5+2" design may be adopted, that is, 1 Big CPU + 5 Middle CPUs + 2 Little CPUs.

[0036] Each CPU core has its own private cache and a shared cache. A typical CPU cache hierarchy consists of a level 1 cache (L1 cache), a level 2 cache (L2 cache), and a level 3 cache (L3 cache). The L1 cache is the cache closest to the CPU, primarily storing the data and instructions the CPU is processing. It is divided into the instruction cache (i cache) and the data cache (d cache). The L2 cache, located between the L1 and L3 caches, can be private or shared, and has a larger capacity than the L1 cache. Its purpose is to improve hit rates and reduce access latency.

[0037] The L3 cache, located between the L2 cache and main memory, is shared by the CPU subsystems, providing a larger cache capacity and further reducing CPU access latency. The L3 cache operates in an independent clock domain, allowing it to adjust its operating clock frequency based on the needs of each CPU. The L3 cache's operating clock can be determined based on votes from each CPU or based on the CPU's operating frequency. Furthermore, the L3 cache can allocate dedicated space to a specific CPU based on its actual needs, increasing its L3 cache hit rate, reducing access latency, and thus improving CPU performance.

[0038] The main memory in the architecture diagram represents the system's main memory, located after the L3 cache. Besides serving the CPU, it may also provide services to other subsystems in the system. The operating frequency of the main memory can be determined based on the bandwidth requirements of each subsystem in the system, or by voting among them.

[0039] Figure 2 shows a system architecture diagram of the CPU subsystem in the chip. As shown in Figure 2, the CPU subsystem in the chip is connected to other subsystems after being connected to the System Level Cache, that is, the system cache connected to the first processor in this application, and then connected to the main memory.

[0040] Among them, the other subsystems can be one or more of a graphics processing unit (GPU) system, a neural network processing unit (NPU) subsystem, and a media subsystem.

[0041] In one embodiment, as shown in FIG3 , a processor scheduling method is proposed, including:

[0042] Step 302: Obtain a first impact parameter of the first processor, where the first impact parameter is used to indicate the degree to which computing performance of the first processor is affected by storage resources.

[0043] Step 304: Adjust the operating frequency of the storage resource based on the first influencing parameter.

[0044] The storage resource includes one or more of a processor cache, a main memory, and a system cache connected to the first processor.

[0045] In an embodiment of the present application, the first influencing parameter obtained can indicate the degree to which the computing performance of the first processor is affected by the storage resources, so the first influencing parameter can be used to adjust the operating frequency of the storage resources. In this process, when the computing performance of the first processor is greatly affected by the storage resources, the operating frequency of the storage resources is adjusted to alleviate or improve the degree to which the computing performance is affected by the storage resources, thereby improving the energy efficiency of the first processor.

[0046] In some embodiments of the present application, the processor cache is also the third-level cache in the present application.

[0047] In some embodiments of the present application, the first influencing parameter includes a ratio of a first duration to a second duration; wherein the first duration represents the working duration of the first processor, and the second duration is used to represent the stop duration of the first processor due to a first condition, and the first condition includes one of the following: front-end congestion caused by storage resource delay, back-end congestion caused by storage resource delay, front-end congestion caused by storage resource delay and back-end congestion caused by storage resource delay, front-end congestion caused by storage resource delay caused by cache miss, back-end congestion caused by storage resource delay caused by cache miss, front-end congestion caused by storage resource delay caused by cache miss, and back-end congestion caused by storage resource delay caused by cache miss.

[0048] In some embodiments of the present application, obtaining a first impact parameter of the first processor specifically includes:

[0049] When the periodic count of the first processor overflows or the execution of the periodic task ends, the first count value and the second count value recorded by the event counter are obtained, where the first count value is used to represent the first duration and the second count value is used to represent the second duration.

[0050] In one embodiment, the event counter is a Performance Monitoring Counter (PMC).

[0051] For example, Table 1 records the monitoring content of some performance events provided by the ARM CPU. For example, event number 0x11 records the number of cycles the CPU runs, and event number 0x24 records the number of cycles the CPU pipeline is blocked due to the backend.

[0052] Table 1

[0053] Among them, the CPU_CYCLES event records the number of cycles run by the CPU, which is counted based on the frequency of the CPU's real-time operation. CPU_CYCLES is also the first count value in this application. Cache miss indicates cache miss, Memory indicates memory, SOC stands for System on Chip, and Dispatch stands for scheduling.

[0054] The STALL_BACKEND_MEM event records the number of cycles blocked by the CPU due to a last-level cache miss. This event is the most direct way to observe pipeline stalls caused by memory bounds. The first influencing parameter, memory bound, can be expressed using the following formula:

[0055] Memory Bound=STALL_FRONTEND_MEM / CPU_CYCLES×100%; or

[0056] Memory Bound=STALL_BACKEND_MEM / CPU_CYCLES×100%; or

[0057] Memory Bound=(STALL_BACKEND_MEM

[0058] +STALL_FRONTEND_MEM) / CPU_CYCLES×100%; or

[0059] Memory Bound=STALL_FRONTEND_MEMBOUND / CPU_CYCLES×100%; or

[0060] Memory Bound=STALL_BACKEND_MEMBOUND / CPU_CYCLES×100%; or

[0061] Memory Bound=(STALL_BACKEND_MEMBOUND

[0062] +STALL_FRONTEND_MEMBOUND) / CPU_CYCLES×100%.

[0063] As can be seen from the preceding description, the Memory Bound metric can be the statistics of the Performance Monitoring Counter of a specific CPU or the statistics of the Performance Monitoring Counter of a thread or process on multiple CPUs.

[0064] In some embodiments of the present application, the operating frequency mentioned above may be a real-time frequency or an average frequency over a period of time.

[0065] The first count value may be obtained based on real-time frequency statistics of the first central processing unit, or may be obtained based on average frequency statistics of the first central processing unit.

[0066] Specifically, the CNT_CYCLES event records the number of cycles the CPU runs at a fixed frequency. The fixed frequency is determined by the SOC manufacturer. For example, the fixed frequency is 24MHz, with a period of 41.667ns. The average frequency of the CPU is expressed as follows:

[0067] CPU Average Frequency = CPU_CYCLES / (CNT_CYCLES × 41.667ns). In some embodiments of the present application, adjusting the operating frequency of the storage resource based on the first influencing parameter specifically includes: increasing the operating frequency of the storage resource when the first influencing parameter is greater than or equal to a first parameter threshold; and maintaining the operating frequency of the storage resource unchanged when the first influencing parameter is less than the first parameter threshold.

[0068] In this embodiment, the first parameter threshold is set so as to use the first parameter threshold to measure the magnitude of the first influencing parameter, thereby determining the extent to which the computing performance of the first processor is affected by the storage resource.

[0069] Specifically, when the first influencing parameter is greater than or equal to the first parameter threshold, it is considered that the computing performance of the first processor is greatly affected by the storage resources. At this time, it is necessary to increase the operating frequency of the storage resources in order to improve the impact of the storage resources on the computing performance of the first processor, thereby improving the energy efficiency of the first processor.

[0070] When the first influencing parameter is less than the first parameter threshold, it is considered that the computing performance of the first processor is less affected by the storage resource. In this case, the operating frequency of the storage resource is kept unchanged to ensure stable operation of the first processor.

[0071] In some embodiments of the present application, the first parameter threshold can be set according to actual usage needs, and its specific value will not be described in detail here.

[0072] In some embodiments of the present application, different first parameter thresholds may be selected according to different storage resources, and then the operating frequencies of different storage resources may be adjusted according to the comparison result between the first influencing parameter and the first parameter threshold.

[0073] Exemplarily, when the storage resource is a processor cache, the first parameter threshold is selected as threshold 1. Then, when the first influencing parameter is greater than or equal to threshold 1, the operating frequency of the processor cache is increased.

[0074] Exemplarily, when the storage resource is a main memory, the first parameter threshold is selected as threshold 2. Then, when the first influencing parameter is greater than or equal to threshold 2, the operating frequency of the main memory is increased.

[0075] Exemplarily, when the storage resource is a system cache connected to a processor, the first parameter threshold is selected as threshold 3. Then, when the first influencing parameter is greater than or equal to threshold 3, the operating frequency of the system cache connected to the first processor is increased.

[0076] In some embodiments of the present application, a mapping relationship between the frequency of the first processor, the first influencing parameter and the target operating frequency is pre-constructed, and then after determining the first influencing parameter and the frequency of the first processor, the operating frequency of the storage resource is directly increased.

[0077] Table 2 shows a mapping relationship between the frequency of the first processor, the first influencing parameter, and the target operating frequency when the storage resource is a processor cache.

[0078] Table 2

[0079] Table 3 shows a mapping relationship between the frequency of the first processor, the first influencing parameter, and the target operating frequency when the storage resource is the main memory.

[0080] Table 3

[0081] Table 4 shows a mapping relationship among the frequency of the first processor, the first influencing parameter, and the target operating frequency when the storage resource is a system cache connected to the first processor.

[0082] Table 4

[0083] In some embodiments of the present application, the processor scheduling method also includes: obtaining operating parameters of the first processor, the operating parameters including operating frequency or operating power consumption; when the first influencing parameter is greater than or equal to the first parameter threshold, increasing the operating frequency of the storage resource, specifically including: when the first influencing parameter is greater than or equal to the first parameter threshold and the operating frequency is greater than or equal to the first frequency, increasing the operating frequency of the storage resource; or when the first influencing parameter is greater than or equal to the first parameter threshold and the operating power consumption is greater than or equal to the first power consumption, increasing the operating frequency of the storage resource.

[0084] In this embodiment, considering that the power consumption of the storage resources will also increase when the operating frequency of the storage resources is increased, it is usually necessary to ensure that the first processor can obtain a positive power consumption benefit only when the CPU obtains a sufficiently large power consumption benefit, such as an increase in power consumption greater than the increase in power consumption caused by increasing the operating frequency of the storage resources, thereby reducing the overall power consumption of the system where the first processor is located.

[0085] To achieve the above objectives, in an embodiment of the present application, operating parameters of the first processor are obtained so as to determine whether increasing the operating frequency of the storage resource can produce positive power consumption benefits based on the operating parameters.

[0086] Specifically, when the operating frequency is greater than or equal to the first frequency, the first processor is considered to be operating in a higher frequency state. At this time, positive power consumption benefits can be generated by increasing the operating frequency of the storage resources. Therefore, when the first influencing parameter is greater than or equal to the first parameter threshold and the operating frequency is greater than or equal to the first frequency, the operating frequency of the storage resources is increased to reduce the overall power consumption of the first processor.

[0087] Similarly, when the operating power consumption is greater than or equal to the first power consumption, it is considered that the first processor is operating in a state of higher power consumption. At this time, positive power consumption benefits can be generated by increasing the operating frequency of the storage resources. Therefore, when the first influencing parameter is greater than or equal to the first parameter threshold and the operating power consumption is greater than or equal to the first power consumption, the operating frequency of the storage resources is increased to reduce the overall power consumption of the first processor.

[0088] In some embodiments of the present application, the first frequency and the first power consumption may be determined based on actual usage requirements, and their specific values ​​will not be described in detail here.

[0089] In some embodiments of the present application, when increasing the operating frequency of the processor cache, the processor scheduling method also includes: increasing the storage space allocated to the first processor in the processor cache; or increasing the storage space allocated to the first thread in the processor cache; wherein the first thread is a thread running on the first processor.

[0090] In this embodiment, the storage space allocated to the first processor in the processor cache is increased to further reduce the access delay of the first processor, thereby reducing the impact of storage resources on the computing performance of the first processor, thereby improving the overall power consumption of the first processor.

[0091] In the above embodiment, when there are multiple threads running in the first processor, different threads have different priorities, and the priority of the first thread is higher than the priority of the second thread, where the second thread is a thread other than the first thread among the threads running in the first processor.

[0092] In this embodiment, more processor caches may be allocated for high-priority threads, thereby limiting the processor caches occupied by the system or background threads where the first processor is located.

[0093] In some embodiments of the present application, the storage space allocated to the first processor in the processor cache can be increased according to a fixed space size, or can be increased according to a fixed share of the processor cache. It can be selected according to actual usage needs, and its specific value will not be repeated here.

[0094] In some embodiments of the present application, when the first influencing parameter is greater than or equal to the first parameter threshold, the operating frequency of the storage resource is increased, specifically including: obtaining a comparison result of the second influencing parameter and the second parameter threshold, the second influencing parameter being the degree to which the computing performance of the second processor is affected by the storage resource, and the second processor and the first processor are provided on the same chip; when the first influencing parameter is greater than or equal to the first parameter threshold, and the second influencing parameter is greater than or equal to the second parameter threshold, increasing the operating frequency of the storage resource; when the first influencing parameter is greater than or equal to the first parameter threshold, and the second influencing parameter is less than the second parameter threshold, keeping the operating frequency of the storage resource unchanged; when the first influencing parameter is less than the first parameter threshold, and the second influencing parameter is greater than or equal to the second parameter threshold, keeping the operating frequency of the storage resource unchanged.

[0095] In this embodiment, when the chip includes multiple central processing units, an increase in the operating frequency of the storage resources will also affect the power consumption of other central processing units.

[0096] In an embodiment of the present application, a second influencing parameter of the second processor is obtained, and based on the comparison result of the second influencing parameter with the second parameter threshold, whether the operating frequency of the storage resource needs to be adjusted is determined using the second processor as a reference. In the process of adjusting the operating frequency of the storage resource based on the first influencing parameter, the determination result of the second processor is used as a reference to determine whether the operating frequency of the storage resource needs to be adjusted. In this process, the operating frequency of the storage resource can be adjusted more reasonably, thereby ensuring the overall energy efficiency of the chip.

[0097] Specifically, if the first influencing parameter is greater than or equal to the first parameter threshold, and the second influencing parameter is greater than or equal to the second parameter threshold, it is considered that both the first processor and the second processor need to increase the operating frequency of the storage resource to ensure the overall energy efficiency of the chip.

[0098] In the case where the first influencing parameter is greater than or equal to the first parameter threshold and the second influencing parameter is less than the second parameter threshold, and in the case where the first influencing parameter is less than the first parameter threshold and the second influencing parameter is greater than or equal to the second parameter threshold, the determination results based on the first processor and the second processor as reference are inconsistent. At this time, the operating frequency of the storage resource can be kept unchanged to ensure stable operation of the chip.

[0099] In some embodiments of the present application, FIG4 shows a flowchart of a chip scheduling method when the chip includes a large-core central processing unit, a medium-core central processing unit, and a small-core central processing unit.

[0100] As shown in FIG4 , in the case where the storage resources include processor cache and main memory, the flowchart of the processor scheduling method includes:

[0101] Step 402: The CPU with a large core needs to increase the resource allocation of the processor cache. If the result is yes, go to step 404; if the result is no, go to step 406.

[0102] Step 404: Increase the operating frequency of the processor cache and increase the allocation of the processor cache to the CPU;

[0103] Step 406: The central processing unit of the core needs to increase the resource allocation of the processor cache. If the result of the judgment is yes, execute step 404; if the result of the judgment is no, execute step 408;

[0104] Step 408: The small-core CPU needs to increase the resource allocation of the processor cache. If the result is yes, execute step 404; if the result is no, end;

[0105] Step 410: The large-core CPU needs to increase the resource allocation of the main memory. If the result is yes, go to step 412; if the result is no, go to step 414;

[0106] Step 412, increasing the operating frequency of the main memory;

[0107] Step 414: The central processing unit of the core needs to increase the resource allocation of the main memory. If the result of the judgment is yes, execute step 412; if the result of the judgment is no, execute step 416;

[0108] Step 416: The small-core CPU needs to increase the resource allocation of the main memory. If the judgment result is yes, execute step 412; if the judgment result is no, end.

[0109] Among them, increasing the resource allocation of the processor cache can be to increase the storage space allocated to the large-core central processing unit, the medium-core central processing unit and the small-core central processing unit in the processor cache; or to increase the storage space allocated to the first thread in the processor cache; wherein the first thread is a thread running on the large-core central processing unit, the medium-core central processing unit and the small-core central processing unit.

[0110] In some embodiments of the present application, as shown in FIG5 , taking the SOC shown in FIG1 as an example, the scheduling method of the processor includes:

[0111] Step 502: Check whether the periodic count has overflowed or the periodic task has been completed. If the result is yes, proceed to step 504. If the result is no, the process ends.

[0112] Step 504: The central processing unit collects PMC events and calculates the first impact parameter and the operating frequency;

[0113] Step 506: Check whether the first influencing parameter exceeds threshold 1. If the result is yes, proceed to step 508; if the result is no, end.

[0114] Step 508: The operating power consumption and operating frequency exceed the set threshold. If the judgment result is yes, execute step 510; if the judgment result is no, end;

[0115] Step 510: Increase the operating frequency of the processor cache and increase the allocation of the processor cache to the central processor;

[0116] Step 512: Check whether the first influencing parameter exceeds threshold 2. If the result is yes, proceed to step 514; if the result is no, end.

[0117] Step 514: If the operating power consumption and operating frequency exceed the set threshold, if the judgment result is yes, proceed to step 516; if the judgment result is no, end;

[0118] Step 516, increase the operating frequency of the main memory.

[0119] In some embodiments of the present application, as shown in FIG6 , taking the SOC shown in FIG2 as an example, the scheduling method of the processor includes:

[0120] Step 602: Check whether the periodic count has overflowed or the periodic task has been completed. If the result is yes, proceed to step 604. If the result is no, the process ends.

[0121] Step 604: The central processing unit collects PMC events and calculates the first impact parameter and the operating frequency;

[0122] Step 606: Check whether the first influencing parameter exceeds threshold 1. If the result is yes, proceed to step 608; if the result is no, end.

[0123] Step 608: If the operating power consumption and operating frequency exceed the set threshold, if the judgment result is yes, execute step 610; if the judgment result is no, end;

[0124] Step 610: Increase the operating frequency of the processor cache and increase the allocation of the processor cache to the central processor;

[0125] Step 612: Check whether the first influencing parameter exceeds threshold 2. If the result is yes, proceed to step 614; if the result is no, end.

[0126] Step 614: If the operating power consumption and operating frequency exceed the set threshold, if the result is yes, proceed to step 616; if the result is no, end;

[0127] Step 616, increasing the operating frequency of the main memory;

[0128] Step 618: Check whether the first influencing parameter exceeds threshold 3. If the result is yes, proceed to step 620; if the result is no, end.

[0129] Step 620: If the operating power consumption and operating frequency exceed the set threshold, if the judgment result is yes, execute step 622; if the judgment result is no, end;

[0130] Step 622: Increase the system cache connected to the central processing unit, and increase the allocation of the system cache to the central processing unit.

[0131] The processor scheduling method provided in the embodiment of the present application can be executed by a processor scheduling device. In the embodiment of the present application, the processor scheduling device provided in the embodiment of the present application is described by taking the processor scheduling method executed by the processor scheduling device as an example.

[0132] In some embodiments of the present application, as shown in Figure 7, a processor scheduling device 700 is provided, including: an acquisition module 702, used to obtain a first influencing parameter of a first processor, the first influencing parameter being used to indicate the degree to which the computing performance of the first processor is affected by the storage resource; an adjustment module 704, used to adjust the operating frequency of the storage resource based on the first influencing parameter; wherein the storage resource includes one or more of a processor cache, a main memory, and a system cache connected to the first processor.

[0133] In an embodiment of the present application, the first influencing parameter obtained can indicate the degree to which the computing performance of the first processor is affected by the storage resources, so the first influencing parameter can be used to adjust the operating frequency of the storage resources. In this process, when the computing performance of the first processor is greatly affected by the storage resources, the operating frequency of the storage resources is adjusted to alleviate or improve the degree to which the computing performance is affected by the storage resources, thereby improving the energy efficiency of the first processor.

[0134] In some embodiments of the present application, the first influencing parameter includes a ratio of a first duration to a second duration; wherein the first duration represents the working duration of the first processor, and the second duration is used to represent the stop duration of the first processor due to a first condition, and the first condition includes one of the following: front-end congestion caused by storage resource delay, back-end congestion caused by storage resource delay, front-end congestion caused by storage resource delay and back-end congestion caused by storage resource delay, front-end congestion caused by storage resource delay caused by cache miss, back-end congestion caused by storage resource delay caused by cache miss, front-end congestion caused by storage resource delay caused by cache miss, and back-end congestion caused by storage resource delay caused by cache miss.

[0135] In some embodiments of the present application, the acquisition module 702 is specifically used to: when the periodic count of the first processor overflows or the execution of the periodic task is completed, obtain the first count value and the second count value recorded by the event counter, the first count value is used to represent the first duration, and the second count value is used to represent the second duration.

[0136] In some embodiments of the present application, the adjustment module 704 is specifically used to: increase the operating frequency of the storage resource when the first influencing parameter is greater than or equal to the first parameter threshold; and maintain the operating frequency of the storage resource unchanged when the first influencing parameter is less than the first parameter threshold.

[0137] In some embodiments of the present application, the acquisition module 702 is further used to: obtain the operating parameters of the first processor, the operating parameters including the operating frequency or the operating power consumption; the adjustment module 704 is specifically used to: increase the operating frequency of the storage resource when the first influencing parameter is greater than or equal to the first parameter threshold and the operating frequency is greater than or equal to the first frequency; or increase the operating frequency of the storage resource when the first influencing parameter is greater than or equal to the first parameter threshold and the operating power consumption is greater than or equal to the first power consumption.

[0138] In some embodiments of the present application, when the operating frequency of the processor cache is increased, the adjustment module 704 is also used to: increase the storage space allocated to the first processor in the processor cache; or increase the storage space allocated to the first thread in the processor cache; wherein the first thread is a thread running on the first processor.

[0139] In some embodiments of the present application, the adjustment module 704 is specifically used to: obtain a comparison result between a second influencing parameter and a second parameter threshold, where the second influencing parameter is the degree to which the computing performance of the second processor is affected by the storage resource, and the second processor and the first processor are arranged on the same chip; when the first influencing parameter is greater than or equal to the first parameter threshold, and the second influencing parameter is greater than or equal to the second parameter threshold, increase the operating frequency of the storage resource; when the first influencing parameter is greater than or equal to the first parameter threshold, and the second influencing parameter is less than the second parameter threshold, keep the operating frequency of the storage resource unchanged; when the first influencing parameter is less than the first parameter threshold, and the second influencing parameter is greater than or equal to the second parameter threshold, keep the operating frequency of the storage resource unchanged.

[0140] The processor scheduling device 700 in the embodiment of the present application can be an electronic device or a component in an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices other than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a mobile Internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc. It can also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), an ATM or a self-service machine, etc., and the embodiment of the present application does not specifically limit it.

[0141] The processor scheduling device in the embodiment of the present application can be a device having an operating system. The operating system can be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0142] The processor scheduling device provided in the embodiment of the present application can implement the various processes implemented by the processor scheduling method embodiment of Figure 3, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0143] As shown in Figure 8, an embodiment of the present application also provides an electronic device 800, including a processor 802 and a memory 804, and the memory 804 stores a program or instruction that can be run on the processor 802. When the program or instruction is executed by the processor 802, the various steps of the above-mentioned processor scheduling method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0144] It should be noted that the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.

[0145] FIG9 is a schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application.

[0146] As shown in Figure 9, the electronic device 900 includes but is not limited to: a radio frequency unit 901, a network module 902, an audio output unit 903, an input unit 904, a sensor 905, a display unit 906, a user input unit 907, an interface unit 908, a memory 909, and a processor 910.

[0147] Those skilled in the art will appreciate that the electronic device 900 may further include a power source (e.g., a battery) to power various components. The power source may be logically connected to the processor 910 via a power management system, thereby enabling the power management system to manage charging, discharging, and power consumption. The electronic device structure shown in FIG9 does not limit the electronic device. The electronic device may include more or fewer components than shown, or may combine certain components or arrange the components differently, which will not be described in detail here.

[0148] In some embodiments of the present application, the processor 910 is used to: obtain a first impact parameter of the first processor, the first impact parameter being used to indicate the extent to which the computing performance of the first processor is affected by the storage resource; adjust the operating frequency of the storage resource based on the first impact parameter; wherein the storage resource includes one or more of a processor cache, a main memory, and a system cache connected to the first processor.

[0149] In some embodiments of the present application, the first influencing parameter includes a ratio of a first duration to a second duration; wherein the first duration represents the working duration of the first processor, and the second duration is used to represent the stop duration of the first processor due to a first condition, and the first condition includes one of the following: front-end congestion caused by storage resource delay, back-end congestion caused by storage resource delay, front-end congestion caused by storage resource delay and back-end congestion caused by storage resource delay, front-end congestion caused by storage resource delay caused by cache miss, back-end congestion caused by storage resource delay caused by cache miss, front-end congestion caused by storage resource delay caused by cache miss, and back-end congestion caused by storage resource delay caused by cache miss.

[0150] In some embodiments of the present application, the processor 910 is specifically used to: when the periodic count of the first processor overflows or the execution of the periodic task is completed, obtain the first count value and the second count value recorded by the event counter, the first count value is used to represent the first duration, and the second count value is used to represent the second duration.

[0151] In some embodiments of the present application, the processor 910 is specifically used to: increase the operating frequency of the storage resource when the first influencing parameter is greater than or equal to the first parameter threshold; and maintain the operating frequency of the storage resource unchanged when the first influencing parameter is less than the first parameter threshold.

[0152] In some embodiments of the present application, the processor 910 is also used to: obtain operating parameters of the first processor, the operating parameters including operating frequency or operating power consumption; when the first influencing parameter is greater than or equal to the first parameter threshold, increase the operating frequency of the storage resource. The processor 910 is specifically used to: when the first influencing parameter is greater than or equal to the first parameter threshold and the operating frequency is greater than or equal to the first frequency, increase the operating frequency of the storage resource; or when the first influencing parameter is greater than or equal to the first parameter threshold and the operating power consumption is greater than or equal to the first power consumption, increase the operating frequency of the storage resource.

[0153] In some embodiments of the present application, when the operating frequency of the processor cache is increased, the processor 910 is further used to: increase the storage space allocated to the first processor in the processor cache; or increase the storage space allocated to the first thread in the processor cache; wherein the first thread is a thread running on the first processor.

[0154] In some embodiments of the present application, the processor 910 is also used to: obtain a comparison result between a second influencing parameter and a second parameter threshold, where the second influencing parameter is the degree to which the computing performance of the second processor is affected by the storage resource, and the second processor and the first processor are provided on the same chip; when the first influencing parameter is greater than or equal to the first parameter threshold, and the second influencing parameter is greater than or equal to the second parameter threshold, increase the operating frequency of the storage resource; when the first influencing parameter is greater than or equal to the first parameter threshold, and the second influencing parameter is less than the second parameter threshold, keep the operating frequency of the storage resource unchanged; when the first influencing parameter is less than the first parameter threshold, and the second influencing parameter is greater than or equal to the second parameter threshold, keep the operating frequency of the storage resource unchanged.

[0155] In an embodiment of the present application, the first influencing parameter obtained can indicate the degree to which the computing performance of the first processor is affected by the storage resources, so the first influencing parameter can be used to adjust the operating frequency of the storage resources. In this process, when the computing performance of the first processor is greatly affected by the storage resources, the operating frequency of the storage resources is adjusted to alleviate or improve the degree to which the computing performance is affected by the storage resources, thereby improving the energy efficiency of the first processor.

[0156] It should be understood that in an embodiment of the present application, the input unit 904 may include a graphics processing unit (GPU) 9041 and a microphone 9042, and the graphics processor 9041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 906 may include a display panel 9061, and the display panel 9061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 907 includes a touch panel 9071 and at least one of other input devices 9072. The touch panel 9071 is also called a touch screen. The touch panel 9071 may include two parts: a touch detection device and a touch controller. Other input devices 9072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and an operating stick, which will not be repeated here.

[0157] The memory 909 can be used to store software programs and various data. The memory 909 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, applications or instructions required for at least one function (such as a sound playback function, an image playback function, etc.). In addition, the memory 909 may include a volatile memory or a non-volatile memory, or the memory 909 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct RAM bus random access memory (DRRAM). The memory 909 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0158] Processor 910 may include one or more processing units. Optionally, processor 910 integrates an application processor and a modem processor. The application processor primarily handles operations related to the operating system, user interface, and application programs, while the modem processor primarily processes wireless communication signals, such as a baseband processor. It is understood that the modem processor may not be integrated into processor 910.

[0159] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by the processor, the various processes of the scheduling method embodiment of the above-mentioned processor are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0160] The processor is the processor in the electronic device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0161] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the various processes of the scheduling method embodiment of the above-mentioned processor, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0162] It should be understood that the processor mentioned in the embodiments of the present application can also be called a system-level processor, a system processor, a processor system, or a system-on-chip processor, etc.

[0163] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the scheduling method embodiment of the above-mentioned processor, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0164] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a" does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0165] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the embodiments of the present application are essentially or the part that contributes to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0166] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A processor scheduling method, comprising: Obtaining a first impact parameter of a first processor, where the first impact parameter is used to indicate the degree to which computing performance of the first processor is affected by storage resources; adjusting the operating frequency of the storage resource based on the first influencing parameter; The storage resource includes one or more of a processor cache, a main memory, and a system cache connected to the first processor.

2. The processor scheduling method according to claim 1, wherein: The first influencing parameter includes a ratio of the first duration to the second duration; The first duration indicates the working duration of the first processor, and the second duration indicates the stopping duration of the first processor due to a first condition, where the first condition includes one of the following: The front-end congestion caused by the storage resource delay, the back-end congestion caused by the storage resource delay, the front-end congestion caused by the storage resource delay and the back-end congestion caused by the storage resource delay, the front-end congestion caused by the storage resource delay due to cache miss, the back-end congestion caused by the storage resource delay due to cache miss, the front-end congestion caused by the storage resource delay due to cache miss and the back-end congestion caused by the storage resource delay due to cache miss.

3. The processor scheduling method according to claim 2, wherein: The obtaining of the first influencing parameter of the first processor specifically includes: When the periodic count of the first processor overflows or the execution of the periodic task ends, the first count value and the second count value recorded by the event counter are obtained, where the first count value is used to represent the first duration and the second count value is used to represent the second duration.

4. The processor scheduling method according to any one of claims 1 to 3, wherein: The adjusting the operating frequency of the storage resource based on the first influencing parameter specifically includes: When the first influencing parameter is greater than or equal to a first parameter threshold, increasing the operating frequency of the storage resource; When the first influencing parameter is less than a first parameter threshold, the operating frequency of the storage resource is kept unchanged.

5. The processor scheduling method according to claim 4, further comprising: Acquiring operating parameters of the first processor, where the operating parameters include operating frequency or operating power consumption; When the first influencing parameter is greater than or equal to a first parameter threshold, increasing the operating frequency of the storage resource specifically includes: When the first influencing parameter is greater than or equal to the first parameter threshold and the operating frequency is greater than or equal to the first frequency, increasing the operating frequency of the storage resource; or When the first influencing parameter is greater than or equal to the first parameter threshold and the operating power consumption is greater than or equal to the first power consumption, the operating frequency of the storage resource is increased.

6. The processor scheduling method according to claim 4, wherein, when the operating frequency of the processor cache is increased, the scheduling method further comprises: increasing the storage space allocated to the first processor in the processor cache; or increasing the storage space allocated to the first thread in the processor cache; The first thread is a thread running on the first processor.

7. The processor scheduling method according to claim 4, wherein: When the first influencing parameter is greater than or equal to a first parameter threshold, increasing the operating frequency of the storage resource specifically includes: Obtaining a comparison result between a second influencing parameter and a second parameter threshold, where the second influencing parameter is the degree to which computing performance of a second processor is affected by storage resources, and the second processor and the first processor are provided on the same chip; When the first influencing parameter is greater than or equal to the first parameter threshold, and the second influencing parameter is greater than or equal to the second parameter threshold, increasing the operating frequency of the storage resource; When the first influencing parameter is greater than or equal to the first parameter threshold and the second influencing parameter is less than the second parameter threshold, maintaining the operating frequency of the storage resource unchanged; When the first influencing parameter is less than the first parameter threshold and the second influencing parameter is greater than or equal to the second parameter threshold, the operating frequency of the storage resource is kept unchanged.

8. A processor scheduling device, comprising: an acquisition module, configured to acquire a first impact parameter of the first processor, where the first impact parameter is used to indicate the degree to which computing performance of the first processor is affected by storage resources; an adjusting module, configured to adjust the operating frequency of the storage resource based on the first influencing parameter; The storage resource includes one or more of a processor cache, a main memory, and a system cache connected to the first processor.

9. The processor scheduling device according to claim 8, wherein: The first influencing parameter includes a ratio of the first duration to the second duration; The first duration indicates the working duration of the first processor, and the second duration indicates the stopping duration of the first processor due to a first condition, where the first condition includes one of the following: The front-end congestion caused by the storage resource delay, the back-end congestion caused by the storage resource delay, the front-end congestion caused by the storage resource delay and the back-end congestion caused by the storage resource delay, the front-end congestion caused by the storage resource delay due to cache miss, the back-end congestion caused by the storage resource delay due to cache miss, the front-end congestion caused by the storage resource delay due to cache miss and the back-end congestion caused by the storage resource delay due to cache miss.

10. The processor scheduling device according to claim 9, wherein: The acquisition module is specifically used to: When the periodic count of the first processor overflows or the execution of the periodic task ends, the first count value and the second count value recorded by the event counter are obtained, where the first count value is used to represent the first duration and the second count value is used to represent the second duration.

11. The processor scheduling device according to any one of claims 8 to 10, wherein: The adjustment module is specifically used to: When the first influencing parameter is greater than or equal to a first parameter threshold, increasing the operating frequency of the storage resource; When the first influencing parameter is less than a first parameter threshold, the operating frequency of the storage resource is kept unchanged.

12. The processor scheduling device according to claim 11, wherein the acquisition module is further configured to: Acquiring operating parameters of the first processor, where the operating parameters include operating frequency or operating power consumption; The adjustment module is specifically used to: When the first influencing parameter is greater than or equal to the first parameter threshold and the operating frequency is greater than or equal to the first frequency, increasing the operating frequency of the storage resource; or When the first influencing parameter is greater than or equal to the first parameter threshold and the operating power consumption is greater than or equal to the first power consumption, the operating frequency of the storage resource is increased.

13. The processor scheduling device according to claim 11, wherein when the operating frequency of the processor cache is increased, the adjustment module is further configured to: increasing the storage space allocated to the first processor in the processor cache; or increasing the storage space allocated to the first thread in the processor cache; in, The first thread is a thread running on the first processor.

14. The processor scheduling device according to claim 11, wherein: The adjustment module is specifically used to: Obtaining a comparison result between a second influencing parameter and a second parameter threshold, where the second influencing parameter is the degree to which computing performance of a second processor is affected by storage resources, and the second processor and the first processor are provided on the same chip; When the first influencing parameter is greater than or equal to the first parameter threshold, and the second influencing parameter is greater than or equal to the second parameter threshold, increasing the operating frequency of the storage resource; When the first influencing parameter is greater than or equal to the first parameter threshold and the second influencing parameter is less than the second parameter threshold, maintaining the operating frequency of the storage resource unchanged; When the first influencing parameter is less than the first parameter threshold and the second influencing parameter is greater than or equal to the second parameter threshold, the operating frequency of the storage resource is kept unchanged. 15 . An electronic device comprising a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the method according to claim 1 are implemented. 16 . A readable storage medium storing a program or instruction, wherein the program or instruction is executed by a processor to implement the steps of the method according to claim 1 .

17. A chip comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is configured to execute a program or instruction to implement the steps of the method according to any one of claims 1 to 7. 18 . A computer program product, wherein the program product is stored in a storage medium and is executed by at least one processor to implement the steps of the method according to claim 1 .

19. An electronic device configured to perform the steps of the method according to any one of claims 1 to 7.

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