Isolation amplifier circuit

Abstract

The present application discloses an isolation amplifier circuit. The isolation amplifier circuit comprises a modulation circuit, an isolation circuit, and a demodulation circuit. The modulation circuit receives an input signal and a first clock signal, and generates a first modulation signal and a second modulation signal according to the first clock signal and the input signal. The isolation circuit receives a second clock signal, the first modulation signal, and the second modulation signal, generates a first clock signal according to the second clock signal, generates a first demodulation signal according to the first modulation signal, and generates a second demodulation signal according to the second modulation signal. The demodulation circuit receives the first demodulation signal, the second demodulation signal, and the second clock signal, and generates an output signal according to the second clock signal, the first demodulation signal, and the second demodulation signal. In the present application, quantization noise generated by a first modulation circuit is canceled by performing, in a demodulation circuit, weighted summation of a second demodulation signal, generated according to the second modulation signal, with the demodulated first modulation signal, thereby achieving low noise in an isolation amplifier circuit.

Description

Isolation amplifier circuit

[0001] This application claims priority to Chinese Patent Application No. 202411427390.0, filed on October 12, 2024, entitled "Isolation Amplifier Circuit", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of isolation amplifier circuit technology, and more specifically, to an isolation amplifier circuit. Background Technology

[0003] An isolation amplifier circuit is a special type of amplifier circuit where there is no direct circuit coupling between its input, output, and power supply circuits. This means that the signal does not have a common ground terminal during transmission, enabling it to perform both signal isolation and amplification. Isolation amplifier circuits are widely used in current and voltage detection applications. Summary of the Invention

[0004] This application discloses an isolation amplifier circuit, which includes:

[0005] A modulation circuit has an input terminal that receives an input signal, a control terminal that receives a first clock signal, a first output terminal that provides a first modulation signal, and a second output terminal that provides a second modulation signal. The modulation circuit generates the first modulation signal and the second modulation signal based on the input signal and the first clock signal.

[0006] An isolation circuit is provided, with a first input terminal receiving the first modulated signal, a second input terminal receiving the second modulated signal, and a control terminal receiving a second clock signal. The control terminal generates a first clock signal based on the second clock signal, a first demodulated signal based on the first modulated signal, and a second demodulated signal based on the second modulated signal. The first clock signal and the second clock signal have the same frequency and amplitude; the first demodulated signal and the first modulated signal have the same frequency and amplitude; and the second demodulated signal and the second modulated signal have the same frequency and amplitude.

[0007] The demodulation circuit has a first input terminal for receiving the first demodulated signal, a second input terminal for receiving the second demodulated signal, and a control terminal for receiving a second clock signal. The demodulation circuit generates an output signal based on the second clock signal, the first demodulated signal, and the second demodulated signal, wherein the amplitude of the output signal is greater than the amplitude of the input signal.

[0008] This application also discloses an isolation amplifier circuit, which includes:

[0009] A modulation circuit has an input terminal for receiving an input signal, a control terminal for receiving a first clock signal, a first output terminal for providing a first modulation signal, and a second output terminal for providing a second modulation signal. The modulation circuit samples the input signal at the frequency of the first clock signal and modulates it into the first modulation signal and the second modulation signal.

[0010] An isolation circuit is provided, with a first input terminal receiving the first modulated signal, a second input terminal receiving the second modulated signal, and a control terminal receiving a first clock signal. The control terminal generates a first demodulated signal based on the first modulated signal, a second demodulated signal based on the second modulated signal, and a second clock signal based on the first clock signal. The first clock signal and the second clock signal have the same frequency and amplitude; the first demodulated signal has the same frequency and amplitude as the first modulated signal; and the second demodulated signal has the same frequency and amplitude as the second modulated signal.

[0011] The demodulation circuit has a first input terminal for receiving the first demodulated signal, a second input terminal for receiving the second demodulated signal, and a control terminal for receiving a second clock signal. The demodulation circuit generates an output signal based on the second clock signal, the first demodulated signal, and the second demodulated signal. Attached Figure Description

[0012] Figure 1A shows a schematic diagram of the circuit structure of an isolation amplifier circuit 100 according to an embodiment of this application;

[0013] Figure 1B shows a schematic diagram of the circuit structure of an isolation amplifier circuit 100 according to an embodiment of this application;

[0014] Figure 2 shows a schematic diagram of the circuit structure of a modulation circuit 10 according to an embodiment of this application;

[0015] Figure 3A shows a schematic diagram of the circuit structure of the first modulation circuit 11 according to an embodiment of this application;

[0016] Figure 3B shows a schematic diagram of the signal waveform of the first modulation circuit 11 according to an embodiment of this application;

[0017] Figure 4A shows a schematic diagram of the circuit structure of the second modulation circuit 12 according to an embodiment of this application;

[0018] Figure 4B shows a schematic diagram of the signal waveform of the second modulation circuit 12 according to an embodiment of this application;

[0019] Figure 5 shows a schematic diagram of the circuit structure of the demodulation circuit 30 according to an embodiment of this application;

[0020] Figure 6 shows a schematic diagram of the circuit structure of the demodulation circuit 30 according to another embodiment of this application;

[0021] Figure 7 shows a schematic diagram of the circuit structure of the first demodulation circuit 31 according to an embodiment of this application;

[0022] Figure 8 shows a schematic diagram of the circuit structure of the second demodulation circuit 32 according to an embodiment of this application;

[0023] Figure 9 shows a schematic diagram of the circuit structure of an isolation circuit 20 according to an embodiment of this application;

[0024] Figure 10 shows a schematic diagram of the circuit structure of an isolation amplifier circuit 100 according to another embodiment of this application;

[0025] Figure 11 shows a schematic diagram of the circuit structure of the isolation circuit 20 according to another embodiment of this application. Detailed Implementation

[0026] To facilitate understanding of the various aspects, features, and advantages of the technical solution of this application, the application will be described in detail below with reference to the accompanying drawings. It should be understood that the various embodiments described below are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0027] In the description of this application, it should be noted that throughout the specification and claims, the term "coupled" is defined as a direct or indirect connection in an electrical or non-electrical manner. When an element is described as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or one or more intermediate elements may be present. Conversely, when an element is described as "directly connected" or "directly coupled" to another element, no intermediate elements are present. Throughout the specification, references to "an embodiment," "an example," or "example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of this application. Therefore, the phrases "in an embodiment," "in an embodiment," "an example," or "example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics may be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. The same reference numerals indicate the same devices. The term “and / or” as used herein includes any and all combinations of one or more of the related listed items.

[0028] The applicant has conducted research on isolation amplifier circuits. The applicant has found that isolation amplifier circuits are widely used in the field of current and voltage detection. For drive systems in industrial and automotive applications, such as electric motor drive systems, there are typically two voltage domains—a high-voltage domain and a low-voltage domain. The microcontroller or digital signal processor in the electric motor drive system is usually located in the low-voltage domain, receiving voltage or current feedback signals and generating digital signals based on these feedback signals to control power switching transistors and other high-voltage circuits. To ensure the reliable operation of the electric motor drive system, electrical isolation between the high-voltage and low-voltage domains is required to prevent damage to the digital signal processor and microcontroller, and to help protect operators from high-voltage hazards. However, when implementing isolation amplification functions, high bandwidth and fast response are often mutually exclusive with high precision. The precision of the isolation amplifier circuit is mainly affected by system noise; improving signal transmission precision often sacrifices response speed.

[0029] This application provides an isolation amplifier circuit designed to address the problems of low signal transmission accuracy and low signal-to-noise ratio in existing isolation amplifier circuits. It achieves at least the following technical effects: This application acquires a second modulated signal through a modulation circuit, and transmits the second modulated signal and a first modulated signal together to a demodulation circuit through an isolation circuit. The isolation circuit generates a second demodulated signal based on the second modulated signal and a first demodulated signal based on the first modulated signal. The demodulation circuit receives the first and second demodulated signals, and performs a weighted sum to cancel out the quantization noise introduced by the modulation circuit during modulation, thereby improving the signal-to-noise ratio during signal transmission in the isolation circuit and ensuring signal transmission accuracy during high-bandwidth, fast-response processes.

[0030] Figure 1A shows a schematic diagram of the circuit structure of an isolation amplifier circuit 100 according to an embodiment of this application. The isolation amplifier circuit 100 includes a modulation circuit 10, an isolation circuit 20, and a demodulation circuit 30. The modulation circuit 10 has an input terminal receiving an input signal VIN, a control terminal receiving a first clock signal CLK_rx, a first output terminal providing a first modulation signal D1_tx, and a second output terminal providing a second modulation signal D2_tx. The modulation circuit 10 generates the first modulation signal D1_tx and the second modulation signal D2_tx based on the input signal VIN and the first clock signal CLK_rx. In one embodiment, the first modulation signal D1_tx represents the input signal VIN, and the second modulation signal D2_tx represents the quantization noise generated when the input signal VIN is used to generate the first modulation signal D1_tx. In one embodiment, the input signal VIN can be a square wave or a sine wave with a frequency between 100kHz and 2MHz. In one embodiment, the frequency range of the first clock signal CLK_rx is between 10MHz and 30MHz.

[0031] The isolation circuit 20 has a first input terminal that receives a first modulation signal D1_tx, a second input terminal that receives a second modulation signal D2_tx, and a control terminal that receives a second clock signal CLK_tx. It generates a first clock signal CLK_rx based on the second clock signal CLK_tx, a first demodulated signal D1_rx based on the first modulation signal D1_tx, and a second demodulated signal D2_rx based on the second modulation signal D2_tx. The first clock signal CLK_tx and the second clock signal CLK_rx have the same frequency and amplitude; the first demodulated signal D1_rx and the first modulation signal D1_tx have the same frequency and amplitude; and the second demodulated signal D2_rx and the second modulation signal D2_tx have the same frequency and amplitude.

[0032] The demodulation circuit 30 has a first input terminal that receives a first demodulated signal D1_rx, a second input terminal that receives a second demodulated signal D2_rx, and a control terminal that receives a second clock signal CLK_tx. The demodulation circuit 30 generates an output signal VOUT based on the second clock signal CLK_tx, the first demodulated signal D1_rx, and the second demodulated signal D2_rx, wherein the amplitude of the output signal is greater than the amplitude of the input signal.

[0033] Figure 1B shows a schematic diagram of the circuit structure of an isolation amplifier circuit according to an embodiment of this application. The isolation circuit 20 includes a first isolation circuit, which has an input terminal that receives a second clock signal CLK_tx and an output terminal that provides a first clock signal CLK_rx. The first isolation circuit generates the first clock signal CLK_rx based on the second clock signal CLK_tx. In the embodiment shown in Figure 1B, the first isolation circuit may include a first receiving circuit RX1 and a first transmitting circuit TX1 that are isolated and coupled together. The first transmitting circuit TX1 receives the second clock signal CLK_tx and generates differential signals P2 and N2, which are coupled and output to the first receiving circuit RX1. The first receiving circuit RX1 receives the differential signals P2 and N2 and generates the first clock signal CLK_rx, which is output to the modulation circuit 10. The isolation circuit 20 further includes a second isolation circuit, which has an input terminal for receiving the first modulation signal D1_tx and an output terminal for providing the first demodulated signal D1_rx. The second isolation circuit generates the first demodulated signal D1_rx based on the first modulation signal D1_tx. In the embodiment shown in FIG1B, the second isolation circuit may include a second receiving circuit RX2 and a second transmitting circuit TX2 with isolation coupling. The second transmitting circuit TX2 receives the first modulation signal D1_tx and generates differential signals P1 and N1, which are coupled and output to the second receiving circuit RX2. The second receiving circuit RX2 receives the differential signals P1 and N1 and generates the first demodulated signal D1_rx, which is output to the demodulation circuit 30. The isolation circuit 20 further includes a third isolation circuit, which has an input terminal for receiving the second modulation signal D2_tx and an output terminal for providing the second demodulated signal D2_rx. The third isolation circuit generates the second demodulated signal D2_rx based on the second modulation signal D2_tx. In the embodiment shown in FIG1B, the third isolation circuit may include a third receiving circuit RX3 and a third transmitting circuit TX3 that are isolated and coupled together. The third transmitting circuit TX3 receives the second modulation signal D2_tx and generates differential signals P3 and N3, which are coupled and output to the third receiving circuit RX3. The third receiving circuit RX3 receives the differential signals P3 and N3 and generates the second demodulated signal D2_rx, which is output to the demodulation circuit 30.

[0034] The modulation circuit 10 generates a second modulation signal D2_tx based on the quantization noise signal Vqn_tx. Quantization noise is the noise generated during the process by which the modulation circuit 10 converts the analog input signal VIN into a digital first modulation signal D1_tx. In one embodiment, the second modulation signal D2_tx is a pulse-width modulated (PWM) signal. The isolation circuit 20 generates a second demodulated signal D2_rx based on the second modulation signal D2_tx, which is also a PWM signal. The demodulation circuit 30 receives the second demodulated signal D2_rx and generates an output signal VOUT based on the second demodulated signal D2_rx and the first demodulated signal D1_rx to counteract the effects of the quantization noise generated in the modulation circuit 10.

[0035] Figure 2 shows a schematic diagram of the circuit structure of a modulation circuit 10 according to an embodiment of this application. The modulation circuit 10 includes a first modulation circuit 11 and a second modulation circuit 12. The first modulation circuit 11 has an input terminal that receives an input signal VIN, a control terminal that receives a first clock signal CLK_rx, a first output terminal that provides a first modulation signal D1_tx, and a second output terminal that provides a quantization noise signal Vqn_tx. Under the control of the first clock signal CLK_rx, the first modulation circuit 11 generates the first modulation signal D1_tx and the quantization noise signal Vqn_tx according to the input signal VIN. The quantization noise signal Vqn_tx represents the noise introduced by the error during the quantization process when the analog signal (input signal VIN) is converted into a discrete digital signal (first modulation signal D1_tx). The second modulation circuit 12 has an input terminal that receives a quantization noise signal Vqn_tx, a control terminal that receives a first clock signal CLK_rx, and a first output terminal that provides a second modulation signal D2_tx. Under the control of the first clock signal CLK_rx, the second modulation circuit 12 generates the second modulation signal D2_tx based on the quantization noise signal Vqn_tx. In one embodiment, the first modulation circuit 11 includes a delta-sigma modulation circuit (SDM, sigma-delta modulator), which can be a continuous delta-sigma modulation circuit or a discrete delta-sigma modulation circuit. In one embodiment, the first modulation circuit 11 can be a second-order 1-bit feedforward SDM. It should be noted that the SDM modulator is only an example; any circuit structure that can generate the first modulation signal D1_tx and the quantization noise signal Vqn_tx based on the input signal VIN under the control of the first clock signal CLK_rx is included in this application. In one embodiment, the second modulation circuit 12 can be a pulse width modulation circuit (PWM), where the pulse width of the second modulation signal D2_tx represents the quantization noise signal Vqn_tx. It should be noted that the pulse width modulation circuit is merely an example; any circuit structure capable of generating the second modulation signal D2_tx based on the quantization noise signal Vqn_tx under the control of the first clock signal CLK_rx is included in this application.

[0036] Figure 3A shows a schematic diagram of the circuit structure of a first modulation circuit 11 according to an embodiment of this application. The first modulation circuit 11 includes a first integrator circuit 111, a second integrator circuit 112, a first adder circuit 113, and a first arithmetic circuit 114. The first integrator circuit 111 has a first input terminal to receive an input signal VIN and a second input terminal to receive a first modulation signal D1_tx, and performs a weighted integral calculation on the input signal VIN and the first modulation signal D1_tx to generate a first converted signal TX1. The second integrator circuit 112 has an input terminal to receive the first converted signal TX1, and performs an integral operation on the first converted signal TX1 to generate a quantization noise signal Vqn_tx. The first adder circuit 113 has a first input terminal to receive the quantization noise signal Vqn_tx, a second input terminal to receive the first converted signal TX1, and a third input terminal to receive the input signal VIN, and performs a weighted sum operation on the quantization noise signal Vqn_tx, the first converted signal TX1, and the input signal VIN to generate a second converted signal TX2. The first operational circuit 114 has an input terminal to receive the second conversion signal TX2 and generates a first modulation signal D1_tx based on the second conversion signal TX2.

[0037] In the embodiment shown in Figure 3A, the first modulation circuit 11 is a second-order 1-bit feedforward Sigma-Delta modulator. The first integrator circuit 111 samples the input voltage VIN at a sampling frequency F, and performs a weighted summation of the sampled voltage and the first modulation signal D1_tx. Weighted summation refers to multiplying the summed objects by corresponding weight coefficients and then summing their products. In this embodiment, the product of the sampled voltage multiplied by a coefficient and the product of the first modulation signal D1_tx multiplied by a coefficient are summed. The summation result is then delayed and integrated to generate the first conversion signal TX1. The second integrator circuit 112 integrates the first conversion signal TX1 to generate a quantization noise signal Vqn_tx. The first adder circuit 113 performs a weighted summation operation on the quantization noise signal Vqn_tx, the first conversion signal TX1, and the input signal VIN to generate the second conversion signal TX2. The first arithmetic circuit 114 generates the first modulation signal D1_tx based on the second conversion signal TX2.

[0038] In the embodiment shown in Figure 3A, the transfer function of the first modulation signal D1_tx in the z-domain is as follows (1): D1_tx(z)=VIN(z)+E(z)·(1-z) -1 ) 2 (1)

[0039] Where D1_tx(z) is the first modulation signal, and E(z) is the quantization noise contributed by the 1-bit quantizer. The 1-bit quantizer works by using oversampling and noise shaping techniques to improve conversion accuracy. Ideally, the bandwidth quantization noise power of a second-order 1-bit SDM is...

[0040] Where OSR is the oversampling rate, and OSR equals half the sampling frequency divided by the signal bandwidth. rms The root mean square value of the quantization noise. When the oversampling rate is fixed, the theoretically obtained quantization noise limits the signal-to-noise ratio (SNR) performance of this structure. When the sampling frequency is fixed, as the frequency range of the input signal VIN increases, the oversampling rate decreases, and the SNR gradually decreases. In the embodiment of Figure 3, this quantization noise is provided by the output of the second integrator circuit 112, which is the quantization noise signal Vqn_tx, and its z-domain transfer function is shown in the following equation (2): V qn_tx (z)=-z -2 E(z)(2)

[0041] As can be seen from the above formula, the quantization noise signal Vqn_tx is the delay of the quantization noise E(z) by two time units (the exponent value of z represents the degree of delay, -1 to the power of z is one time unit delay, and -2 to the power of z is two time unit delay), which can characterize the quantization noise in the first modulation circuit 11 when the input signal VIN generates the first modulation signal D1_tx.

[0042] Figure 3B shows a schematic diagram of the signal waveforms of the first modulation circuit 11 according to an embodiment of this application. The waveforms of each signal in Figure 3B will be explained with reference to the structure of the first modulation circuit 11 shown in Figure 3A. Under the control of the first clock signal CLK_tx, the input signal VIN is modulated into the first modulation signal D1_tx. During the modulation process, the influence of the quantization noise signal Vqn_tx is superimposed. It should be noted that the waveform changes of the quantization noise signal Vqn_tx shown in Figure 3B are illustrative and are only used to characterize the random distribution of the quantization noise signal in different clock cycles; they do not exhibit any regularity.

[0043] In the embodiment shown in Figure 3A, the first operational circuit 114 is a dynamic zero-crossing comparator that periodically compares the second conversion signal TX2 with the reference ground voltage GND according to the frequency of the first clock signal CLK_rx. When the second conversion signal TX2 is greater than the reference ground voltage GND, the first modulation signal D1_tx is output as a logic high level, and vice versa.

[0044] Figure 4A shows a schematic diagram of the circuit structure of the second modulation circuit 12 according to an embodiment of this application. The quantization noise signal differential pair Vqn_tx and -Vqn_tx are input to the second modulation circuit 12, and the first clock signal differential pair CLK_rxP and CLK_rxN are also input to the second modulation circuit 12. Taking a circuit where the quantization noise signal Vqn_tx and the first clock signal CLK_rxP are input on one side as an example, the first switch S1 and the second switch S2 are turned on or off under the control of the second modulation signal D2_tx. When the first switch S1 is on, the second terminal of the resistor Rf1p receives the first reference voltage -Vref1; when the second switch S2 is on, the second terminal of the resistor Rf1p receives the second reference voltage +Vref1. In one embodiment, when the second modulation signal D2_tx is at a logic high level, the first switch S1 is off and the second switch S2 is on. When the second modulation signal D2_tx is at a logic low level, the first switch S1 is on and the second switch S2 is off. In one embodiment, the absolute values ​​of the first reference voltage -Vref1 and the second reference voltage +Vref1 are the same, but their positive and negative polarities are opposite.

[0045] In the embodiment shown in Figure 4A, taking one side of the differential input second modulation circuit 12 as an example, the integrator composed of resistor Rcp, capacitor C1P, and operational amplifier provides a triangular wave signal to the subsequent comparator circuit at the input of the operational amplifier. This triangular wave serves as the carrier wave of the second modulation circuit 12 to achieve pulse width modulation. When the operational amplifier is in a stable state, the output of the integrator is necessarily bounded. Therefore, from the perspective of periodic balance, the average current on capacitor C1P is zero. The duty cycle of the second modulation signal D2_tx is derived according to Thevenin's theorem, and its calculation formula is:

[0046] The bandwidth of the second modulation signal D2_tx is determined by resistors Rcp, Rf1p, capacitor C1P, and the carrier frequency, exhibiting first-order low-pass characteristics. Since quantization noise does not need to be fully transmitted to the demodulation side, the bandwidth of the second modulation signal D2_tx only needs to be greater than the signal bandwidth. In one embodiment, the bandwidth of the second modulation signal D2_tx is 1MHz. In other embodiments, the second modulation circuit 12 can also be a non-differential input circuit, for example, it can include only one side of the circuit shown in FIG4A, that is, only resistors Rcp, Rs1p, capacitor C1P, operational amplifier, comparator, and first switch S1 and second switch S2. Its working principle is similar to the working principle of the differential single-sided second modulation circuit 12 shown in FIG4A, and will not be described in detail here.

[0047] Figure 4B shows a schematic diagram of the signal waveforms of the second modulation circuit 12 according to an embodiment of this application. The waveforms of each signal in Figure 4B will be explained with reference to the structure of the second modulation circuit 12 shown in Figure 4A. Under the control of the clock signal CLK_rx, the quantization noise signal VIN is modulated into a second modulation signal D2_tx. The second modulation circuit 12 is a pulse width modulation circuit, where the pulse width of the second modulation signal D2_tx represents the quantization noise signal Vqn_tx. It should be noted that the waveform changes of the quantization noise signal Vqn_tx shown in Figure 4B are for illustrative purposes only; in practical applications, the quantization noise signal has random value fluctuations.

[0048] In some embodiments, the second modulation circuit 12 may include a first-order 1-bit SDM modulator or a first-order pulse width modulator. The first-order pulse width modulator has superior noise performance. In a first-order pulse width modulator, the signal information is encoded into the time domain. Ideally, PWM does not contribute quantization noise; using PWM to transmit quantization noise can achieve a better signal-to-noise ratio.

[0049] Figure 5 shows a schematic diagram of the circuit structure of a demodulation circuit 30 according to an embodiment of this application. The demodulation circuit 30 includes a first demodulation circuit 31 and a second demodulation circuit 32. The first demodulation circuit 31 has an input terminal that receives a second demodulated signal D2_rx and generates a demodulated quantization noise signal Vqn_rx based on the second demodulated signal D2_rx. The second demodulation circuit 32 has a first input terminal that receives a first demodulated signal D1_rx, a second input terminal that receives the demodulated quantization noise signal Vqn_rx, and a third input terminal that receives a second clock signal CLK_tx. The second demodulation circuit 32 generates an output signal VOUT based on the second clock signal CLK_tx, the first demodulated signal D1_rx, and the demodulated quantization noise signal Vqn_rx. In one embodiment, the first demodulated signal D1_rx and the demodulated quantization noise signal Vqn_rx are weighted and summed to generate the output signal VOUT. It should be noted that the demodulation circuit 30 shown in Figure 5 is only an example. Any circuit structure that can generate a demodulated quantization noise signal Vqn_rx based on the second demodulated signal D2_rx is included in this application.

[0050] Figure 6 shows a schematic diagram of the demodulation circuit 30 according to another embodiment of this application. In the embodiment shown in Figure 5, the first demodulation circuit 31 has an input terminal that receives the second demodulated signal D2_rx and generates a demodulated quantization noise signal Vqn_rx based on the second demodulated signal D2_rx. That is, the first demodulation circuit 31 in Figure 5 does not receive the second clock signal CLK_tx, and its timing control is implemented only based on the timing information of the second demodulated signal D2_rx. In the embodiment shown in Figure 6, the first demodulation circuit 31 has an input terminal that receives the second demodulated signal D2_rx and the second clock signal CLK_tx, and generates a demodulated quantization noise signal Vqn_rx based on the second demodulated signal D2_rx and the second clock signal CLK_tx. The second demodulation circuit 32 has a first input terminal receiving a first demodulated signal D1_rx, a second input terminal receiving a demodulated quantization noise signal Vqn_rx, and a third input terminal receiving a second clock signal CLK_tx. The second demodulation circuit 32 generates an output signal VOUT based on the second clock signal CLK_tx, the first demodulated signal D1_rx, and the demodulated quantization noise signal Vqn_rx. It should be noted that any circuit structure capable of generating the demodulated quantization noise signal Vqn_rx based on the second demodulated signal D2_rx under the control of the second clock signal CLK_tx is included in this application.

[0051] Figure 7 shows a schematic diagram of the circuit structure of a first demodulation circuit 31 according to an embodiment of this application. The first demodulation circuit 31 includes a fifth switch S5, a sixth switch S6, a fourth resistor R4, a sixth operational circuit 311, a second capacitor C2, a sample and hold circuit 312, a seventh operational circuit 313, and a fifth resistor R5.

[0052] The fifth switch S5 has a first terminal receiving the fourth reference voltage -Vref2 and a third terminal receiving the second demodulated signal D2_rx. The sixth switch S6 has a first terminal receiving the third reference voltage +Vref2 and a third terminal receiving the second demodulated signal D2_rx. The fourth resistor R4 has a first terminal coupled to the second terminals of the fifth switch S5 and the sixth switch S6. The sixth operational circuit 311 has a first input terminal coupled to the second terminal of the fourth resistor R4, a second input terminal coupled to reference ground, and an output terminal providing the sixth conversion signal TX6. The second capacitor C2 has a first terminal coupled to the first input terminal of the sixth operational circuit 311 and a second terminal coupled to the output terminal of the sixth operational circuit 311. The sample-and-hold circuit 312 has a first input terminal receiving the sixth conversion signal TX6 and a second input terminal receiving the second demodulated signal D2_rx, and generates a seventh conversion signal TX7 based on the sixth conversion signal TX6 and the second demodulated signal D2_rx. The seventh operational circuit 313 has an input terminal that receives the seventh conversion signal TX7 and generates a demodulated quantization noise signal Vqn_rx based on the seventh conversion signal TX7. The fifth resistor R5 has a first terminal that receives the demodulated quantization noise signal Vqn_rx, and a second terminal coupled to the first input terminal of the sixth operational circuit 311. The fifth switch S5 and the sixth switch S6 are turned on or off under the control of the second demodulated signal D2_rx. When the fifth switch S5 is on, the first terminal of the fourth resistor R4 receives the fourth reference voltage -Vref2; when the sixth switch S6 is on, the first terminal of the fourth resistor R4 receives the third reference voltage +Vref2. In one embodiment, when the second demodulated signal D2_rx is at a logic high level, the fifth switch S5 is off and the sixth switch S6 is on. When the second demodulated signal D2_rx is at a logic low level, the fifth switch S5 is on and the sixth switch S6 is off.

[0053] In the embodiment shown in Figure 7, the first demodulation circuit 31 is used for pulse width demodulation to recover the demodulated quantization noise signal Vqn_rx, which is then output to the second demodulation circuit 32. The voltage of the demodulated quantization noise signal Vqn_rx...

[0054] It also exhibits first-order low-pass characteristics. The sample-and-hold circuit 312 can generate a notch at the carrier frequency to suppress interference signals near the carrier frequency. According to the calculation formula of the second modulation circuit 12, it can be seen that...

[0055] Finally, it was deduced that

[0056] It can be seen that V is equal to or matched with the reference voltage. qn_rx =V qn_tx

[0057] In one embodiment, the first demodulation circuit 31 exhibits the low-pass characteristics of PWM, and the cancellation effect of the portion above the PWM bandwidth is weakened. In order to suppress high-frequency noise, a low-pass filter can be added in the subsequent stage to further filter out high-frequency noise and obtain better noise performance.

[0058] Figure 8 shows a schematic diagram of the circuit structure of a second demodulation circuit 32 according to an embodiment of this application. The second demodulation circuit 32 includes a third switch S3, a fourth switch S4, a third integrator circuit 321, a fourth operational circuit 323, a fourth integrator circuit 322, a fifth operational circuit 324, and a second adder circuit 325.

[0059] The third switch S3 has a first terminal, a second terminal, and a third terminal. The first terminal receives a third reference voltage +Vref2, and the third terminal receives a first demodulated signal D1_rx. The third switch is turned on or off under the control of the first demodulated signal D1_rx. The fourth switch S4 has a first terminal, a second terminal, and a third terminal. The first terminal receives a fourth reference voltage -Vref2, and the third terminal receives the first demodulated signal D1_rx. The fourth switch S4 is turned on or off under the control of the first demodulated signal. The fourth operational circuit 323 has an input terminal that receives an output signal VOUT and generates a third conversion signal TX3 based on the output signal VOUT. The third integrator circuit 321 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the second terminal of the third switch S3 and the second terminal of the fourth switch S4, and the second input terminal receives the third conversion signal TX3. The third switch S3 and the fourth switch S4 are turned on or off under the control of the first demodulated signal D1_rx. When the third switch S3 is on, the first input terminal of the third integrator circuit 321 receives the third reference voltage +Vref2. When the fourth switch S4 is on, the first input terminal of the third integrator circuit 321 receives the fourth reference voltage -Vref2. The third integrator circuit 321 performs a weighted integration operation based on the third reference voltage and the third conversion signal TX3 to generate the fourth conversion signal TX4, or performs a weighted integration operation based on the third reference voltage and the third conversion signal TX3 to generate the fourth conversion signal TX4. The fourth integrator circuit 322 has a first input terminal that receives the fourth conversion signal TX4 and a second input terminal that receives the third conversion signal TX3. It performs a weighted integration operation based on the fourth conversion signal TX4 and the third conversion signal TX3 to generate the fifth conversion signal TX5. The fifth operation circuit 324 has an input terminal that receives the demodulated quantization noise signal Vqn_rx and generates a second noise signal Vqn2 based on the demodulated quantization noise signal Vqn_rx. The second adder circuit 325 has a first input terminal that receives the fifth conversion signal TX5 and a second input terminal that receives the second noise signal Vqn2. It performs a weighted summation operation on the fifth conversion signal TX5 and the second noise signal Vqn2 to generate an output signal VOUT.

[0060] In one embodiment, when the first demodulated signal D1_rx is at a logic low level, the third switch S3 is turned off and the fourth switch S4 is turned on. When the first demodulated signal D1_rx is at a logic high level, the third switch S3 is turned on and the fourth switch S4 is turned off.

[0061] In the embodiment shown in Figure 8, the second demodulation circuit 32 converts the first demodulated signal D1_rx in digital state into an output signal VOUT in analog state, and simultaneously achieves weighted cancellation of the quantization noise generated by the first modulation circuit 10. The expression of the output signal VOUT in the z-domain is as follows (3):

[0062] Where D(z) = 10⁻¹⁵z -1 +6z -2

[0063] The operational circuits, integrator circuits, and adder circuits in the first demodulation circuit 31 and the second demodulation circuit 32 all need to perform calculations based on the frequency of the first clock signal. "z-1" indicates a delay of one time period, and "z-2" indicates a delay of two time periods. The determination of the time period is related to the frequency period of the clock signal.

[0064] In summary, combining formulas (1), (2), and (3), the expression for the output signal VOUT can be derived as follows:

[0065] Figure 9 shows a schematic diagram of the circuit structure of an isolation circuit 20 according to an embodiment of this application. The isolation circuit 20 includes a first isolation circuit 21, a second isolation circuit 22, and a third isolation circuit 23.

[0066] The first isolation circuit 21 has an input terminal that receives a second clock signal CLK_tx and an output terminal that provides a first clock signal CLK_rx. The first isolation circuit 21 generates the first clock signal CLK_rx based on the second clock signal CLK_tx. The second isolation circuit 22 has an input terminal that receives a first modulation signal D1_tx and an output terminal that provides a first demodulated signal D1_rx. The second isolation circuit 22 generates the first demodulated signal D1_rx based on the first modulation signal D1_tx. The third isolation circuit 23 has an input terminal that receives a second modulation signal D2_tx and an output terminal that provides a second demodulated signal D2_rx. The third isolation circuit 23 generates the second demodulated signal D2_rx based on the second modulation signal D2_tx.

[0067] In the embodiment shown in Figure 9, the first isolation circuit 21 includes a first capacitor C1, the second isolation circuit 22 includes a second capacitor C2, and the third isolation circuit 23 includes a third capacitor C3. In some other embodiments, the first isolation circuit 21 may include N capacitors connected in series, where N is an integer greater than or equal to 2.

[0068] Figure 10 shows a schematic diagram of the circuit structure of an isolation amplifier circuit 100 according to another embodiment of this application. The modulation circuit 10 has an input terminal receiving an input signal VIN, a control terminal receiving a first clock signal CLK_tx, a first output terminal providing a first modulation signal D1_tx, and a second output terminal providing a second modulation signal D2_tx. The modulation circuit 10 samples the input signal VIN at the frequency of the first clock signal CLK_tx and modulates it into the first modulation signal D1_tx and the second modulation signal D2_tx. In the embodiment shown in Figure 10, the first clock signal CLK_tx is generated by an oscillator. The isolation circuit 20 has a first input terminal that receives a first modulation signal D1_tx, a second input terminal that receives a second modulation signal D2_tx, and a control terminal that receives a first clock signal CLK_tx. It generates a first demodulated signal D1_rx based on the first modulation signal D1_tx, a second demodulated signal D2_rx based on the second modulation signal D2_tx, and a second clock signal CLK_rx based on the first clock signal CLK_tx. The first clock signal CLK_tx and the second clock signal CLK_rx have the same frequency and amplitude; the first demodulated signal D1_rx has the same frequency and amplitude as the first modulation signal D1_tx; and the second demodulated signal D2_rx has the same frequency and amplitude as the second modulation signal D2_tx. The demodulation circuit 30 has a first input terminal that receives a first demodulated signal D1_rx, a second input terminal that receives a second demodulated signal D2_rx, and a control terminal that receives a second clock signal CLK_rx. The demodulation circuit 30 generates an output signal VOUT based on the second clock signal CLK_rx, the first demodulated signal D1_rx, and the second demodulated signal D2_rx.

[0069] Figure 11 shows a schematic diagram of the circuit structure of an isolation circuit 20 according to another embodiment of this application. The isolation circuit 20 includes a first isolation circuit 21, a second isolation circuit 22, and a third isolation circuit 23. The first isolation circuit 21 has an input terminal that receives a first clock signal CLK_tx and an output terminal that provides a second clock signal CLK_rx. The first isolation circuit 21 generates the second clock signal CLK_rx based on the first clock signal CLK_tx. The second isolation circuit 22 has an input terminal that receives a first modulation signal D1_tx and an output terminal that provides a first demodulated signal D1_rx. The second isolation circuit 22 generates the first demodulated signal D1_rx based on the first modulation signal D1_tx. The third isolation circuit 23 has an input terminal that receives a second modulation signal D2_tx and an output terminal that provides a second demodulated signal D2_rx. The third isolation circuit 23 generates the second demodulated signal D2_rx based on the second modulation signal D2_tx.

[0070] In the embodiment shown in FIG11, the first isolation circuit 21 includes a first capacitor C1, the second isolation circuit 22 includes a second capacitor C2, and the third isolation circuit 23 includes a third capacitor C3.

[0071] Those skilled in the art should understand that the above-disclosed embodiments are merely implementations of this application and should not be construed as limiting the scope of the patent protection claimed in this application. Equivalent variations made according to the implementations of this application shall still fall within the scope of the claims of this application.

Claims

1. An isolation amplifier circuit, comprising: A modulation circuit has an input terminal that receives an input signal, a control terminal that receives a first clock signal, a first output terminal that provides a first modulation signal, and a second output terminal that provides a second modulation signal. The modulation circuit generates the first modulation signal and the second modulation signal based on the input signal and the first clock signal. An isolation circuit has a first input terminal receiving the first modulation signal, a second input terminal receiving the second modulation signal, and a control terminal receiving a second clock signal. The control terminal generates a first clock signal based on the second clock signal, a first demodulated signal based on the first modulation signal, and a second demodulated signal based on the second modulation signal. The first clock signal and the second clock signal have the same frequency and amplitude, the first demodulated signal has the same frequency and amplitude as the first modulation signal, and the second demodulated signal has the same frequency and amplitude as the second modulation signal. as well as The demodulation circuit has a first input terminal for receiving the first demodulated signal, a second input terminal for receiving the second demodulated signal, and a control terminal for receiving a second clock signal. The demodulation circuit generates an output signal based on the second clock signal, the first demodulated signal, and the second demodulated signal, wherein the amplitude of the output signal is greater than the amplitude of the input signal.

2. The isolation amplifier circuit according to claim 1, wherein the first modulation signal represents the input signal, and the second modulation signal represents the quantization noise generated when the input signal generates the first modulation signal.

3. The isolation amplifier circuit according to claim 1, wherein the input signal is a square wave or a sine wave with a frequency between 100kHz and 2MHz.

4. The isolation amplifier circuit according to claim 1, wherein the frequency range of the first clock signal CLKtx is between 10MHz and 30MHz.

5. The isolation amplifier circuit according to claim 1, wherein the modulation circuit comprises: A first modulation circuit has an input terminal for receiving an input signal, a control terminal for receiving a first clock signal, a first output terminal for providing a first modulation signal, and a second output terminal for providing a quantization noise signal. The first modulation circuit generates the first modulation signal and the quantization noise signal according to the input signal under the control of the first clock signal. as well as The second modulation circuit has an input terminal that receives a quantization noise signal, a control terminal that receives a first clock signal, and an output terminal that provides a second modulation signal. The second modulation circuit generates the second modulation signal according to the quantization noise signal under the control of the first clock signal.

6. The isolation amplifier circuit according to claim 5, wherein the first modulation circuit includes a delta-sigma modulation circuit.

7. The isolation amplifier circuit according to claim 5, wherein the second modulation circuit includes a pulse width modulation circuit, and the pulse width of the second modulation signal characterizes the quantization noise signal.

8. The isolation amplifier circuit according to claim 1, wherein the demodulation circuit comprises: The first demodulation circuit has an input terminal for receiving the second demodulated signal and for generating a demodulated quantization noise signal based on the second demodulated signal. as well as The second demodulation circuit has a first input terminal for receiving the first demodulated signal, a second input terminal for receiving the demodulated quantization noise signal, and a third input terminal for receiving a second clock signal. The second demodulation circuit generates the output signal based on the second clock signal, the first demodulated signal, and the demodulated quantization noise signal.

9. The isolation amplifier circuit according to claim 1, wherein the demodulation circuit comprises: The first demodulation circuit has an input terminal that receives the second demodulated signal and a second clock signal, and generates a demodulated quantization noise signal based on the second demodulated signal and the second clock signal. as well as The second demodulation circuit has a first input terminal for receiving the first demodulated signal, a second input terminal for receiving the demodulated quantization noise signal, and a third input terminal for receiving a second clock signal. The second demodulation circuit generates the output signal based on the second clock signal, the first demodulated signal, and the demodulated quantization noise signal.

10. The isolation amplifier circuit according to claim 8 or 9, wherein the first demodulated signal and the demodulated quantization noise signal are weighted and summed to generate the output signal.

11. The isolation amplifier circuit according to claim 1, wherein the isolation circuit comprises: A first isolation circuit has an input terminal that receives a second clock signal and an output terminal that provides a first clock signal. The first isolation circuit generates a first clock signal based on the second clock signal. The second isolation circuit has an input terminal that receives a first modulation signal and an output terminal that provides a first demodulation signal. The second isolation circuit generates the first demodulation signal based on the first modulation signal. as well as The third isolation circuit has an input terminal for receiving the second modulation signal and an output terminal for providing the second demodulation signal. The third isolation circuit generates the second demodulation signal based on the second modulation signal.

12. An isolation amplifier circuit, comprising: A modulation circuit has an input terminal for receiving an input signal, a control terminal for receiving a first clock signal, a first output terminal for providing a first modulation signal, and a second output terminal for providing a second modulation signal. The modulation circuit samples the input signal at the frequency of the first clock signal and modulates it into the first modulation signal and the second modulation signal. An isolation circuit has a first input terminal receiving the first modulation signal, a second input terminal receiving the second modulation signal, and a control terminal receiving a first clock signal. The control terminal generates a first demodulated signal based on the first modulation signal, a second demodulated signal based on the second modulation signal, and a second clock signal based on the first clock signal. The first clock signal and the second clock signal have the same frequency and amplitude, the first demodulated signal has the same frequency and amplitude as the first modulation signal, and the second demodulated signal has the same frequency and amplitude as the second modulation signal. as well as The demodulation circuit has a first input terminal for receiving the first demodulated signal, a second input terminal for receiving the second demodulated signal, and a control terminal for receiving a second clock signal. The demodulation circuit generates an output signal based on the second clock signal, the first demodulated signal, and the second demodulated signal.

13. The isolation amplifier circuit according to claim 12, wherein the modulation circuit comprises: A first modulation circuit has an input terminal for receiving an input signal, a control terminal for receiving a first clock signal, a first output terminal for providing a first modulation signal, and a second output terminal for providing a quantization noise signal. The first modulation circuit generates the first modulation signal and the quantization noise signal according to the input signal under the control of the first clock signal. as well as The second modulation circuit has an input terminal that receives a quantization noise signal, a control terminal that receives a first clock signal, and an output terminal that provides a second modulation signal. The second modulation circuit generates the second modulation signal according to the quantization noise signal under the control of the first clock signal.

14. The isolation amplifier circuit according to claim 12, wherein the isolation circuit comprises: A first isolation circuit has an input terminal that receives a first clock signal and an output terminal that provides a second clock signal. The first isolation circuit generates the second clock signal based on the first clock signal. The second isolation circuit has an input terminal that receives a first modulation signal and an output terminal that provides a first demodulation signal. The second isolation circuit generates the first demodulation signal based on the first modulation signal. as well as The third isolation circuit has an input terminal for receiving the second modulation signal and an output terminal for providing the second demodulation signal. The third isolation circuit generates the second demodulation signal based on the second modulation signal.

15. The isolation amplifier circuit according to claim 12, wherein the demodulation circuit comprises: The first demodulation circuit has an input terminal for receiving the second demodulated signal and for generating a demodulated quantization noise signal based on the second demodulated signal. as well as The second demodulation circuit has a first input terminal for receiving the first demodulated signal, a second input terminal for receiving the demodulated quantization noise signal, and a third input terminal for receiving a second clock signal. The second demodulation circuit generates the output signal based on the second clock signal, the first demodulated signal, and the demodulated quantization noise signal.

16. The isolation amplifier circuit according to claim 14, wherein the first isolation circuit includes a first capacitor, the second isolation circuit includes a second capacitor, and the third isolation circuit includes a third capacitor.

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