Electronic circuit, solid-state imaging device, and readout circuit

Abstract

The present technology relates to an electronic circuit, a solid-state imaging device, and a readout circuit that make it possible to reduce power consumption. An electronic circuit comprises a push-pull buffer circuit, the push-pull buffer circuit including a switch for performing intermittent signal output and a bypass current circuit for forming a bypass current path when the signal output is temporarily halted. The present technology can be applied to solid-state imaging devices.

Description

Electronic circuit, solid-state imaging device, and readout circuit

[0001] This technology relates to electronic circuits, solid-state imaging devices, and readout circuits, and more particularly to electronic circuits, solid-state imaging devices, and readout circuits that can reduce power consumption.

[0002] Conventionally, a technique has been proposed that uses a combination of a high-speed response push-pull buffer circuit and a track-and-hold circuit for communications (see, for example, Non-Patent Document 1).

[0003] In this technology, multiple ADCs (Analog to Digital Converters) are connected to a single track-and-hold circuit, and interleaved operation is achieved by the track-and-hold circuit sequentially outputting signals to each ADC.

[0004] “An 8-bit 56GS / s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS” A. Serdar Yonar, et al, IEEE VLSI Circuits, C19-1, 2022

[0005] Incidentally, it is conceivable to perform signal readout (AD (Analog to Digital) conversion) by combining a sample-and-hold circuit, a push-pull buffer circuit, and an ADC. That is, for example, a configuration in which a push-pull buffer circuit reads a signal from a sample-and-hold circuit and outputs that signal to an ADC could be used in various devices such as CMOS (Complementary Metal Oxide Semiconductor) image sensors. However, in such a case, power consumption may increase.

[0006] Specifically, in a push-pull buffer circuit, for example, the initial response when outputting a signal may become slower, or the IR drop during bias voltage sampling may increase, potentially leading to higher power consumption.

[0007] This technology has been made in view of such a situation, and is intended to reduce power consumption.

[0008] The electronic circuit of the first aspect of this technology has a push - pull buffer circuit, and the push - pull buffer circuit has a switch for intermittent signal output and a bypass current circuit for forming a bypass current path during the休止 of the signal output.

[0009] In the first aspect of this technology, a push - pull buffer circuit is provided, and the push - pull buffer circuit is provided with a switch for intermittent signal output and a bypass current circuit for forming a bypass current path during the休止 of the signal output.

[0010] The solid - state imaging device of the second aspect of this technology has a first push - pull buffer circuit having a switch for intermittent signal output and a bypass current circuit for forming a bypass current path during the休止 of the signal output, and a first AD conversion circuit connected to a plurality of the first push - pull buffer circuits and performing AD conversion of the signal supplied from the first push - pull buffer circuit.

[0011] In the second aspect of this technology, a first push - pull buffer circuit having a switch for intermittent signal output and a bypass current circuit for forming a bypass current path during the休止 of the signal output, and a first AD conversion circuit connected to a plurality of the first push - pull buffer circuits and performing AD conversion of the signal supplied from the first push - pull buffer circuit are provided.

[0012] The read - out circuit of the third aspect of this technology includes an AD conversion circuit that performs AD conversion of the signal output from an arbitrary one of a plurality of pixels connected to each of a plurality of vertical signal lines, based on the signal output from the pixel and a reference signal.

[0013] In the third aspect of this technology, an AD conversion circuit that performs AD conversion of the signal output from a pixel, based on the signal output from an arbitrary one of a plurality of pixels connected to each of a plurality of vertical signal lines and a reference signal, is provided. It should be noted that the word "休止" in the original text seems to be an incorrect or unclear expression. Based on the context, it might be "休止 (rest)" which should probably be "休止 (pause)" or some other more appropriate term. But according to the translation rules, the text is translated as is.

[0014] This figure shows an example of the configuration of a readout circuit. This figure illustrates an example of the operation of the readout circuit. This figure shows an example of the configuration of an S / H circuit and a push-pull buffer circuit. This figure illustrates an example of the operation of the readout circuit. This figure shows an example of the configuration of an electronic circuit to which this technology is applied. This figure illustrates the operating state. This figure illustrates the operating state. This figure illustrates the operating state. This figure illustrates an example of the operation of an S / H circuit with an intermittent push-pull buffer. This figure illustrates an example of application to a CMOS image sensor. This figure illustrates an example of the operation of a CMOS image sensor. This figure illustrates an example of the operation of a CMOS image sensor. This figure illustrates noise reduction. This figure illustrates noise reduction. This figure shows an example of a bypass current circuit an attenuation function. This figure shows an example of an attenuation function. This figure shows an example of the configuration of an S / H circuit with an intermittent push-pull buffer. This figure shows an example of the configuration of a reference bias circuit. This figure shows an example of the configuration of a reference bias circuit. This figure illustrates an example of application to a CMOS image sensor. This figure shows an example of the configuration of a CMOS image sensor. This figure shows an example of the configuration of a CMOS image sensor. This is a diagram illustrating an example of application to a CMOS image sensor. This is a diagram illustrating an example of the configuration of a CMOS image sensor. This is a diagram illustrating an example of the configuration of a CMOS image sensor. This is a diagram illustrating the intermittent operation of a Load MOS. This is a diagram illustrating the intermittent operation of a Load MOS. This is a diagram illustrating an example of application to a CMOS image sensor. This is a diagram illustrating an example of the configuration of a CMOS image sensor. This is a diagram illustrating an example of the configuration of a CMOS image sensor. This is a diagram illustrating the compression of errors caused by PSRR. This is a diagram illustrating an example of the configuration of an S / H circuit and a push-pull buffer circuit a CMOS image sensor. This is a diagram illustrating an example of the configuration of a CMOS image sensor. This is a diagram illustrating an example of the configuration of a CMOS image sensor.It is a diagram showing a configuration example of a reference voltage adjustment unit. It is a diagram for explaining an operation example of a CMOS image sensor. It is a diagram for explaining an auxiliary of an analog clamp function. It is a diagram for explaining an arrangement of HOPB pixels and a reference column. It is a diagram for explaining a connection between HOPB pixels and a reference column. It is a diagram for explaining an arrangement of HOPB pixels and a reference column. It is a diagram for explaining an example of use of an image sensor. It is a diagram showing a configuration example of an imaging device. It is a diagram showing an example of a schematic configuration of an endoscopic surgery system. It is a block diagram showing an example of a functional configuration of a camera head and a CCU. It is a block diagram showing an example of a schematic configuration of a vehicle control system. It is an explanatory diagram showing an example of an installation position of an outside-vehicle information detection unit and an imaging unit.

[0015] Hereinafter, embodiments to which the present technology is applied will be described with reference to the drawings.

[0016] <First Embodiment> <Regarding a combination of a sample-and-hold circuit and a push-pull buffer circuit> The present technology is configured to reduce power consumption by providing a push-pull buffer circuit with an intermittent operation control switch for performing intermittent signal output and a bypass current circuit for forming a bypass current path during signal output suspension.

[0017] For example, as shown in FIG. 1, consider a case where readout circuits of a CMOS image sensor are configured by simply combining sample-and-hold circuits 11-1 to 11-N and push-pull buffer circuits 12-1 to 12-N.

[0018] In the example shown in FIG. 1, one ADC 13 is connected to push-pull buffer circuits 12-1 to 12-N.

[0019] Furthermore, each of the push-pull buffer circuits 12-1 to 12-N is connected to each of the sample-and-hold circuits 11-1 to 11-N. Each of the sample-and-hold circuits 11-1 to 11-N is connected to each of the pixel circuits (not shown) via vertical signal lines.

[0020] Hereafter, unless there is a need to distinguish between sample-and-hold circuits 11-1 to 11-N, they will simply be referred to as sample-and-hold circuit 11. Also, below, a sample-and-hold circuit will be referred to as an S / H circuit. Furthermore, below, unless there is a need to distinguish between push-pull buffer circuits 12-1 to 12-N, they will simply be referred to as push-pull buffer circuit 12.

[0021] In this example, the S / H circuit 11 samples and holds the signal supplied from the pixel circuit via the vertical signal line, and the push-pull buffer circuit 12 supplies a signal with a voltage level corresponding to the signal held by the S / H circuit 11 to the ADC 13. The ADC 13 performs AD conversion on the signal supplied from the push-pull buffer circuit 12 and outputs the resulting signal to the next stage.

[0022] In a readout circuit with such a configuration, for example, as shown in Figure 2, it is conceivable to perform a two-phase interleaved operation in which the signals of all pixels (pixel circuits) are sampled simultaneously, and then the signal hold operation and AD conversion operation of each pixel are performed sequentially.

[0023] In this example, the P-phase (reset level) signal output from the pixel circuit is sampled simultaneously in N S / H circuits 11.

[0024] Subsequently, a hold operation is performed on the sampled signals sequentially from the first S / H circuit 11 to the Nth S / H circuit 11. At this time, the first push-pull buffer circuit 12 to the Nth push-pull buffer circuit 12 sequentially outputs a signal with a voltage level corresponding to the signal held by the S / H circuit 11. The ADC 13 performs AD conversion on the signals supplied sequentially from each of the N push-pull buffer circuits 12 and outputs the resulting P-phase signal.

[0025] Here, for example, while the signal held by the first S / H circuit 11 is being converted by the ADC 13, the hold operation is performed in the second S / H circuit 11, and then at the next timing, the A / D conversion operation is performed for the signal held by the second S / H circuit 11. Also, once the P-phase (reset level) signal has been read out for all pixels, the D-phase (signal level) signal has been read out in the same manner thereafter.

[0026] Figure 3 shows a more specific configuration example of the S / H circuit 11 and the push-pull buffer circuit 12.

[0027] The example in Figure 3 shows a configuration example when an S / H circuit and a push-pull buffer circuit are simply combined. In Figure 3, the left side of the figure shows the operating state of the S / H circuit 11 and the push-pull buffer circuit 12 when they are in a predetermined state a, while the right side of the figure shows the operating state when they are in another state b.

[0028] The S / H circuit 11 includes a switch 41 and a capacitor 42. The input terminal (VSL input) of the switch 41 is connected to the pixel circuit via a vertical signal line (VSL) (not shown), and the switch 41 turns on and off in response to the control signal SAMPLE_EN.

[0029] For example, when the control signal SAMPLE_EN is set to H level (high level) and the switch 41 is turned ON, it supplies the signal output from the pixel circuit (hereinafter also referred to as the pixel output signal) to the capacitor 42 and holds it. In other words, a charge corresponding to the pixel output signal is charged to the capacitor 42.

[0030] The push-pull buffer circuit 12 includes switches 51-1 and 51-2, capacitors 52-1 and 52-2, capacitors 53-1 and 53-2, transistors 54 and 55, switches 56-1 and 56-2, and switch 57.

[0031] Hereinafter, when there is no need to distinguish between switches 51-1 and 51-2, they will simply be referred to as switch 51, and when there is no need to distinguish between capacitors 52-1 and 52-2, they will simply be referred to as capacitor 52. Similarly, when there is no need to distinguish between capacitors 53-1 and 53-2, they will simply be referred to as capacitor 53, and when there is no need to distinguish between switches 56-1 and 56-2, they will simply be referred to as switch 56.

[0032] Switch 51 turns on and off in response to the control signal BIAS_EN, controlling the sampling of the bias voltage supplied from a reference bias circuit (not shown).

[0033] In other words, when the control signal BIAS_EN is set to a high level and switch 51-1 is turned on, a predetermined bias voltage is applied to the gates of capacitor 52 and transistor 54. Similarly, when switch 51-2 is turned on, a predetermined bias voltage is applied to the gates of capacitor 53 and transistor 55. In particular, here the bias voltage supplied by switch 51-1 is higher than the bias voltage supplied by switch 51-2.

[0034] Transistor 54 is an N-channel transistor, or NMOS transistor, and its gate is connected to capacitor 42 and switch 41 via capacitor 52. The drain of transistor 54 is connected to a predetermined power supply, and the source of transistor 54 is connected to switch 56-1.

[0035] Transistor 55 is a P-channel transistor, or PMOS transistor, and its gate is connected to capacitor 42 and switch 41 via capacitor 53. The source of transistor 55 is connected to switch 56-2, and the drain of transistor 55 is connected to ground.

[0036] Switch 56 is a switch for intermittent operation control and is located between transistors 54 and 55. Switch 56 turns on and off in response to a control signal PG.

[0037] Switch 57 is a multiplex switch connected between switches 56-1 and 56-2, and is switched on and off in response to the control signal BUFSEL. The end of switch 57 opposite to the end on switch 56 is an output terminal (MUX output), and this output terminal is connected to the ADC 13 shown in Figure 1.

[0038] State a is when switch 41 is on, switch 51 is off, switch 56 is on, and switch 57 is off. More specifically, state a is the state when switch 51 changes from the on state to the off state. In state a, an output current I is supplied from a predetermined power supply to ground via transistor 54, switch 56, and transistor 55. OUT A current flows. In this example, for example, the output current I OUT It is said to be 50 μA, etc. Below, the output current I OUT The amount of current is also I OUT This is what I will write.

[0039] State b is when switch 41 is off, switch 51 is off, switch 56 is off, and switch 57 is off. More specifically, state b is the state when switch 41 changes from the ON state to the OFF state.

[0040] Referring to Figure 4, the operation of the readout circuit shown in Figure 1, and more specifically the operation of the S / H circuit 11 and the push-pull buffer circuit 12 shown in Figure 3 within the readout circuit, will be explained. Note that in Figure 4, for the sake of clarity, only the operation of one column, that is, one S / H circuit 11 and one push-pull buffer circuit 12 connected to that S / H circuit 11, is shown. Here, a circuit portion containing one pair of S / H circuit 11 and push-pull buffer circuit 12 connected to one vertical signal line is referred to as one column.

[0041] In Figure 4, the horizontal axis represents time, and the vertical axis represents the levels (potential) at the control signals, input terminals, and output terminals. The area indicated by arrow Q11 shows the current consumption in the readout circuit.

[0042] First, at time t1, the control signals BIAS_EN, SAMPLE_EN, and PG are simultaneously set to high level in all columns, and switches 51, 41, and 56 are turned on. At this time, the control signal BUFSEL is set to low level, and switch 57 is turned off. In other words, all N push-pull buffer circuits 12 are electrically disconnected from the ADC 13.

[0043] Subsequently, at time t2, the control signals BIAS_EN and PG are simultaneously set to the L level in all columns, and switches 51 and 56 are turned off. More specifically, switch 51 is turned off, and immediately afterward, switch 56 is turned off. The state at time t2, immediately before switch 56 is turned off, is state a described above.

[0044] When switch 51 is turned off, a charge corresponding to the bias voltage is charged from a reference bias circuit (not shown) to capacitors 52 and 53. In other words, the bias voltage is sampled.

[0045] At this time, capacitor 52 accumulates charge corresponding to the difference between the bias voltage (potential) supplied by switch 51-1 and the voltage (potential) on the vertical signal line side. Similarly, capacitor 53 accumulates charge corresponding to the difference between the bias voltage (potential) supplied by switch 51-2 and the voltage (potential) on the vertical signal line side.

[0046] During the period from time t1 to time t2, since switch 56 is ON, all N push-pull buffer circuits 12 continuously output current I OUT The current continues to flow. In other words, the total current consumption in the entire readout circuit is N × I OUT This is the result.

[0047] At time t3, the control signal SAMPLE_EN is set to L level in all columns, and switch 41 is turned off. As a result, the S / H circuit 11 and the vertical signal line (pixel circuit) are electrically disconnected. This state is state b described above.

[0048] When switch 41 is turned off, the P-phase signals output from the pixel circuits in all columns are sampled by the S / H circuit 11. In other words, a charge corresponding to the difference between the potential of the vertical signal line and the potential of ground is charged to capacitor 42 via switch 41.

[0049] At time t4, the control signals PG and BUFSEL in one column (hereinafter also referred to as the selected column) are set to the H level, and switches 56 and 57 are turned on. As a result, the push-pull buffer circuit 12 of the selected column is electrically connected to the ADC 13.

[0050] Columns other than the selected column will also be referred to as non-selected columns. In the case of non-selected columns, the switch 57 remains off, so the push-pull buffer circuit 12 of the non-selected column is electrically disconnected from the ADC 13.

[0051] In the push - pull buffer circuit 12 of the selected column, a voltage corresponding to the charge held in the capacitor 52 is applied to the gate of the transistor 54, and a voltage corresponding to the charge held in the capacitor 53 is applied to the gate of the transistor 55.

[0052] When the switch 56 and the switch 57 are turned on, an output current I OUT flows in the push - pull buffer circuit 12. Also, the potential of the output terminal connected to the switch 57 gradually changes to a potential corresponding to the amount of charge held in the capacitor 42, that is, the magnitude of the P - phase signal.

[0053] As a result, a signal with a voltage level corresponding to the P - phase signal output from the pixel circuit is supplied (output) from the push - pull buffer circuit 12 of the selected column to the ADC 13, and the ADC 13 performs AD conversion on the signal supplied from the push - pull buffer circuit 12.

[0054] Then, at time t5, the control signal PG and the control signal BUFSEL in the selected column are set to the L level, and the switch 56 and the switch 57 are turned off. As a result, the column that has been the selected column so far becomes a non - selected column.

[0055] During the period from time t4 to time t5, in the push - pull buffer circuit 12 of the selected column, the output current I OUT continues to flow, and in the non - selected column, the output current I OUT does not flow. Therefore, the current consumption of the entire readout circuit becomes I OUT .

[0056] After time t5, columns that have not been selected columns so far are sequentially selected as new selected columns, and for each timing, the same operation as the operation from time t4 to time t5 is performed on the column that is the selected column at that time. That is, a multiplexing operation is performed in which the columns that output signals by turning on and off the switch 56 and the switch 57 are sequentially switched. As a result, the P - phase signals are read out from all columns (pixel circuits).

[0057] Once the reading of the P-phase signal is complete, the reading of the D-phase signal will then be performed from time t6 onwards.

[0058] In other words, at time t6, the control signal SAMPLE_EN is simultaneously set to the H level in all columns, and switch 41 is turned on.

[0059] At time t7, the control signal SAMPLE_EN is simultaneously set to L level in all columns, and switch 41 is turned off, resulting in the state b described above.

[0060] As a result, the D-phase signal output from the pixel circuit is sampled by the S / H circuit 11 in all columns. In this case, a charge corresponding to the difference between the potential of the vertical signal line and the potential of ground is charged (stored) in the capacitor 42 via the switch 41. Furthermore, according to the law of conservation of charge, the voltage applied to the gate of transistor 54 and the voltage applied to the gate of transistor 55 change by the difference ΔVSL between the potential of the vertical signal line at the current time and the potential of the vertical signal line at time t3.

[0061] At time t8, one column is selected as the selected column, the control signals PG and BUFSEL in that selected column are set to the H level, and switches 56 and 57 are turned on.

[0062] As a result, the push-pull buffer circuit 12 of the selected column is electrically connected to the ADC 13, while the push-pull buffer circuit 12 of the non-selected column remains electrically disconnected from the ADC 13.

[0063] When the push-pull buffer circuit 12 of the selected column is connected to the ADC 13, a signal with a voltage level corresponding to the D-phase signal is supplied to the ADC 13, as in the case at time t4, and the ADC 13 performs AD conversion on that signal. At this time, the push-pull buffer circuit 12 outputs current I OUT The current flows. The D-phase signal has a voltage level that is different from the P-phase signal by the amount of the difference ΔVSL mentioned above.

[0064] Subsequently, at time t9, the control signals PG and BUFSEL in the selected column are set to L level, switching switches 56 and 57 off, and the push-pull buffer circuit 12 is disconnected from the ADC 13. During the period from time t8 to time t9, as in the period from time t4 to time t5, the current consumption in the entire readout circuit is I OUT This is the result.

[0065] After time t9, columns that have not been selected up to that point are sequentially selected as new selected columns, and the same operation as from time t8 to time t9 is performed on the selected columns at each timing. As a result, the D-phase signal is read out from all columns (pixel circuits).

[0066] In the example shown in Figure 3, the S / H circuit and the push-pull buffer circuit are simply combined, and a switch 56 for intermittent operation control and a switch 57 for multiplex operation are added to the push-pull buffer circuit.

[0067] However, this configuration results in high power consumption.

[0068] Specifically, in the output transistors that output signals, i.e., transistors 54 and 55 which function as switches, the initial response is slow because the rate-limiting factor is the charging and discharging until they return to the saturation region once they have moved to a stable signal output state.

[0069] In other words, because the voltage fluctuates until the source current reaches zero, transistors 54 and 55 enter a linear state. Therefore, when transistors 54 and 55 transition to the signal output state, there is no amplification effect until they return to the operating point in the saturation region, and charging and discharging occur, resulting in a delay in response.

[0070] In the example shown in Figure 4, at times t4 and t8, it takes time (the response is slow) for the potential of the output terminal to change to the potential corresponding to the D-phase and P-phase signals held in the S / H circuit 11, which increases the time from turning the switch 57 on to turning it off. In other words, the intermittency rate when performing intermittent signal readout becomes low.

[0071] In the push-pull buffer circuit 12, the output current I continues to flow while switch 57 (switch 56) is ON. OUT Because the current flows continuously, the longer the period that switch 57 is on, that is, the lower the intermittency rate, the greater the power consumption. Also, if the intermittency rate is low (output response is slow), multiplex operation, that is, switching of the columns that output signals, cannot be performed at high speed, and it takes time to read out the signal.

[0072] Furthermore, in the example shown in Figure 3, when sampling the bias voltage, it is necessary to turn on switch 56 in order to erase the history of the source potentials of transistors 54 and 55, that is, to set the gate-source voltage to a predetermined voltage. Specifically, in the example shown in Figure 4, at time t1, the control signal PG is set to the H level simultaneously in all columns and switch 56 is turned on. In this case, the current consumption in the readout circuit is N × I OUT This results in a large IR drop. Consequently, not only does power consumption increase, but the IR drop when all columns are operating simultaneously may be unacceptable, making wiring design difficult and raising concerns about degradation of signal readout accuracy.

[0073] <Example of Electronic Circuit Configuration> Therefore, in this technology, power consumption can be reduced by providing a switch for intermittent operation control and a bypass current circuit in the push-pull buffer circuit.

[0074] Figure 5 shows an example configuration of one embodiment of an electronic circuit to which this technology is applied. This electronic circuit is equipped with an intermittently operating push-pull buffer S / H circuit to which this technology is applied. The intermittently operating push-pull buffer S / H circuit is a sample-and-hold circuit (S / H circuit) to which a push-pull buffer circuit having an intermittently operating control switch and a bypass current circuit is provided.

[0075] The electronic circuit 81 shown in Figure 5 includes a reference bias circuit 91 and an S / H circuit 92 with an intermittently operating push-pull buffer.

[0076] The reference bias circuit 91 is a bias voltage source circuit that supplies a predetermined bias voltage to the S / H circuit 92 with an intermittently operating push-pull buffer.

[0077] The reference bias circuit 91 includes a current source 101, a transistor 102, a switch 103, a switch 104, a transistor 105, a resistor 106, and a transistor 107.

[0078] In particular, transistors 102 and 107 are N-channel transistors (NMOS transistors), and transistor 105 is a P-channel transistor (PMOS transistor). Furthermore, the back gate of each transistor is connected to the source.

[0079] In the reference bias circuit 91, a current source 101, a transistor 102, a switch 103, a switch 104, a transistor 105, and a resistor 106 are connected in a row between the power supply and ground.

[0080] Furthermore, transistors 107 are connected to both ends of the two switches 103 and 104, which are arranged side by side. Specifically, the gate and drain of transistor 107 are connected between switch 103 and the source of transistor 102, and the source of transistor 107 is connected between switch 104 and the source of transistor 105.

[0081] In the reference bias circuit 91, switches 103 and 104 are basically in the ON state, and a reference current flows from the current source 101 to ground via transistor 102, switch 103, switch 104, transistor 105, and resistor 106. In addition, the potential (voltage level) at terminal P11 between switch 103 and switch 104 becomes the reference voltage for the signal output from the intermittently operating push-pull buffered S / H circuit 92.

[0082] The intermittently operating push-pull buffered S / H circuit 92 includes a sample-and-hold circuit 151 (S / H circuit 151), a push-pull buffer circuit 152, an attenuation circuit 153, a capacitor 154, and a capacitor 155.

[0083] The intermittently operating push-pull buffered S / H circuit 92 can be described as an S / H circuit with a push-pull buffer, or as a push-pull buffer circuit with an S / H circuit. The intermittently operating push-pull buffered S / H circuit 92 is provided with input terminals IP11, IP12, IP13, and output terminal OP11. Although these input terminals IP11 to output terminal OP11 are referred to as terminals for the sake of clarity, more precisely, any end where input or output takes place does not need to be actually a terminal. The same applies to each terminal described below.

[0084] Input terminal IP11 is connected to a circuit that supplies the signal to be read, and output terminal OP11 is connected to a circuit that receives the read signal.

[0085] Terminals IP12 and IP13 are connected to the reference bias circuit 91. Specifically, terminal IP12 is connected between the current source 101 and the transistor 102, and terminal IP13 is connected between the transistor 105 and the resistor 106.

[0086] The S / H circuit 151 includes a switch 161 and a capacitor 162.

[0087] One end of switch 161 is connected to input terminal IP11, and the other end of switch 161 is connected to capacitor 162. Switch 161 turns on and off in response to the control signal SAMPLE_EN. Capacitor 162 is located between switch 161 and ground and holds the signal input through switch 161.

[0088] For example, if an intermittent push-pull buffered S / H circuit 92 (electronic circuit 81) is provided on a CMOS image sensor, the input terminal IP11 is connected to the vertical signal line (VSL), and the signal output from the pixel circuit is supplied to the capacitor 162 via the vertical signal line, the input terminal IP11, and the switch 161.

[0089] The push-pull buffer circuit 152 outputs a signal corresponding to the signal held in the S / H circuit 151.

[0090] The push-pull buffer circuit 152 includes switches 171-1 and 171-2, capacitors 172-1 and 172-2, capacitors 173-1 and 173-2, transistors 174 and 175, switches 176-1 and 176-2, transistor 177, and switch 178.

[0091] Hereinafter, when there is no need to distinguish between switches 171-1 and 171-2, they will simply be referred to as switch 171, and when there is no need to distinguish between capacitors 172-1 and 172-2, they will simply be referred to as capacitor 172. Similarly, when there is no need to distinguish between capacitors 173-1 and 173-2, they will simply be referred to as capacitor 173, and when there is no need to distinguish between switches 176-1 and 176-2, they will simply be referred to as switch 176.

[0092] One end of switch 171-1 is connected to capacitor 154 and terminal IP12, and the other end of switch 171-1 is connected to the gate of transistor 174, capacitor 172-1, and capacitor 172-2.

[0093] Capacitor 154 is positioned between switch 171-1 and terminal IP12 and ground, and functions as a decoupling capacitance to improve the stability of the voltage supplied from terminal IP12. A predetermined bias voltage (hereinafter also referred to as NGTE_BIAS as appropriate) is supplied from the reference bias circuit 91 to capacitor 154, capacitor 172, and the gate of transistor 174.

[0094] One end of switch 171-2 is connected to capacitor 155 and terminal IP13, and the other end of switch 171-2 is connected to the gate of transistor 175, capacitor 173-1, and capacitor 173-2.

[0095] Capacitor 155 is positioned between switch 171-2 and terminal IP13 and ground, and functions as a decoupling capacitance to improve the stability of the voltage supplied from terminal IP13. A predetermined bias voltage (hereinafter also referred to as PGTE_BIAS as appropriate) is supplied from the reference bias circuit 91 to capacitor 155, capacitor 173, and the gate of transistor 175. In this example, the bias voltage NGTE_BIAS is set to a voltage greater than the bias voltage PGTE_BIAS.

[0096] Switch 171 turns on and off in response to the control signal BIAS_EN, controlling the sampling of the bias voltage supplied from the reference bias circuit 91.

[0097] Transistor 174 is an N-channel (N-type conductivity) transistor, i.e., an NMOS transistor. The gate of transistor 174 is connected to switch 171-1, capacitor 172-1, and capacitor 172-2. The back gate of transistor 174 is connected to the source of transistor 174. The drain of transistor 174 is connected to a predetermined power supply, and the source of transistor 174 is connected to switch 176-1 and transistor 177.

[0098] Transistor 175 is a P-channel transistor (P-type conductivity), i.e., a PMOS transistor. The gate of transistor 175 is connected to switch 171-2, capacitor 173-1, and capacitor 173-2. The back gate of transistor 175 is connected to the source of transistor 175. The drain of transistor 175 is connected to ground via switch 178, and the source of transistor 175 is connected to switch 176-2 and transistor 177.

[0099] Switches 176-1 and 176-2 are located between transistors 174 and 175, which are connected in parallel and have different conductivity types. In other words, two switches 176 are arranged side by side between transistors 174 and 175. An output terminal OP11 is connected between switches 176-1 and 176-2. The push-pull buffer circuit 152 outputs a signal with a voltage level corresponding to the signal held by the S / H circuit 151 from the output terminal OP11 and supplies it to the subsequent block. In other words, the signal output is generated from between the two side by side switches 176.

[0100] Switch 176 is a switch for intermittent operation control, that is, a switch for intermittent signal output from the push-pull buffer circuit 152, and turns on and off according to the control signal BUFSEL.

[0101] Transistor 177 is located (connected) between transistors 174 and 175, which are connected in parallel. Transistor 177 is also connected to both ends of two switches 176 that are arranged side by side.

[0102] Transistor 177 is an N-channel transistor (NMOS transistor). The gate and drain of transistor 177 are connected to the source and switch 176-1 of transistor 174, and the source of transistor 177 is connected to the source and switch 176-2 of transistor 175. In this example, transistor 177 is configured in a self-bias configuration with its back gate connected to its source.

[0103] Transistor 177 functions as a bypass current circuit that forms a bypass current path when the signal output by the push-pull buffer circuit 152 is paused. Specifically, transistor 177 forms a bypass current path when switch 176 is in the off state.

[0104] Switch 178 is a current control switch located between transistor 175 and ground, i.e., on the bypass current path, and controls whether or not bypass current flows through the bypass current path (control of bypass current).

[0105] Switch 178 turns on and off according to the control signal XSTB.

[0106] For example, during the operating period for reading signals from the intermittently operating push-pull buffered S / H circuit 92, such as the duration of one frame, that is, during the settling and reading of the P-phase and D-phase signals described later, the switch 178 remains in the ON state.

[0107] In contrast, during periods when the intermittent push-pull buffered S / H circuit 92 is not operating (periods when no signal is read out), such as between frames, the switch 178 is kept in the OFF state. In this case, no bypass current flows through the bypass current path, thus reducing power consumption.

[0108] In the following explanation, we will assume that switch 178 is generally in the ON state.

[0109] The attenuation circuit 153 is provided between the S / H circuit 151 and the push-pull buffer circuit 152, and implements an attenuation function that reduces the signal output from the push-pull buffer circuit 152 (output terminal OP11).

[0110] The attenuation circuit 153 includes capacitors 172-1, 172-2, switch 181-1, switch 182-1, capacitor 173-1, capacitor 173-2, switch 181-2, and switch 182-2.

[0111] In the following, when there is no need to distinguish between switch 181-1 and switch 181-2, they will simply be referred to as switch 181. Similarly, when there is no need to distinguish between switch 182-1 and switch 182-2, they will simply be referred to as switch 182.

[0112] Capacitors 172 and 173 are shared between the attenuation circuit 153 and the push-pull buffer circuit 152. In other words, capacitors 172 and 173 are components of both the attenuation circuit 153 and the push-pull buffer circuit 152.

[0113] Capacitor 172-1 is located between the gate of transistor 174 and switch 171-1, and switch 161 and capacitor 162.

[0114] Capacitor 172-2 is located between the gate of transistor 174 and switch 171-1, and switches 181-1 and 182-1. Switch 181-1 is located between capacitor 172-2 and switches 161 and 162. Switch 182-1 is located between capacitor 172-2 and ground.

[0115] Capacitor 173-1 is located between the gate of transistor 175 and switch 171-2, and switch 161 and capacitor 162.

[0116] Capacitor 173-2 is located between the gate of transistor 175 and switch 171-2, and switches 181-2 and 182-2. Switch 181-2 is located between capacitor 173-2 and switches 161 and 162. Switch 182-2 is located between capacitor 173-2 and ground.

[0117] When the signal output from the push-pull buffer circuit 152 is not attenuated, switch 181 is in the ON state and switch 182 is in the OFF state. Hereinafter, the state in which switch 181 is ON and switch 182 is OFF will also be referred to as the state in which the attenuation function is OFF.

[0118] When the attenuation function is off, the two capacitors 172 are connected in parallel, and the sum of the capacitances of these two capacitors 172 becomes the equivalent capacitance. Similarly, the two capacitors 173 are also connected in parallel. Therefore, the voltage applied to the gates of transistors 174 and 175 becomes the voltage corresponding to the signal held in the S / H circuit 151.

[0119] In contrast, when the signal output from the push-pull buffer circuit 152 is attenuated, switch 181 is set to the OFF state and switch 182 is set to the ON state. Hereafter, the state in which switch 181 is OFF and switch 182 is ON will also be referred to as the state in which the attenuation function is ON.

[0120] When the attenuation function is on, the two capacitors 172 are connected in series, and the gate of transistor 174 is connected between them. Similarly, the two capacitors 173 are also connected in series, and the gate of transistor 175 is connected between them. Therefore, compared to when the attenuation function is off, the voltage applied to the gates of transistors 174 and 175 is lower, and the voltage level of the signal output from output terminal OP11 is also lower.

[0121] For the sake of simplicity, in this embodiment, the attenuation function will not be used. That is, the explanation will continue assuming that switch 181 is in the ON state and switch 182 is in the OFF state.

[0122] The intermittently operating push-pull buffered S / H circuit 92 can take on any of the operating states shown in Figures 6 to 8.

[0123] The operating state shown in Figure 6 is the state in which switch 171 is switched to the OFF position, starting from a state where switch 161 is ON, switch 171 is ON, switch 176 is OFF, switch 181 is ON, switch 182 is OFF, and switch 178 is ON. Hereafter, the operating state shown in Figure 6 will also be referred to as state a.

[0124] In state a, since switch 176 is off, a bypass current path indicated by arrow BP11 is formed by transistor 177. That is, a bypass current I flows from the power supply to ground via transistors 174, 177, 175, and switch 178. Bypass This bypass current I flows. Bypass This is the subthreshold current (subthreshold leakage current), that is, the current that flows when transistors 174 and 175 operate in the subthreshold region.

[0125] Furthermore, in state a, a reference current flows through the reference bias circuit 91. The magnitude of this reference current is the output current I of the push-pull buffer circuit 152, which will be described later. OUT It is the same size as [this].

[0126] The operating state shown in Figure 7 is the state in which switch 161 is switched off from the state in which switch 161 is on, switch 171 is off, switch 176 is off, switch 181 is on, switch 182 is off, and switch 178 is on. Hereafter, the operating state shown in Figure 7 will also be referred to as state b.

[0127] In state b, as in state a, switch 176 is off, so bypass current I flows through the bypass current path. Bypass The following current flows. Also, in the reference bias circuit 91, the output current I, which will be described later, flows. OUT A reference current of the same magnitude flows.

[0128] The operating state shown in Figure 8 is the state in which switch 176 is switched to ON, starting from a state where switch 161 is OFF, switch 171 is OFF, switch 176 is OFF, switch 181 is ON, switch 182 is OFF, and switch 178 is ON. Hereafter, the operating state shown in Figure 8 will also be referred to as state c.

[0129] In state c, since switch 176 is ON, the output current I flows through the path indicated by arrow BO11. OUT As current flows, the potential of the output terminal OP11 changes to a potential corresponding to the amount of charge held by the capacitor 162, that is, the signal held in the S / H circuit 151. In this example, the output current I flows from the power supply to ground via transistor 174, switch 176, transistor 175, and switch 178. OUT A current flows. Also, in the reference bias circuit 91, the output current I OUT A reference current of the same magnitude flows.

[0130] In the push-pull buffer circuit 152, when the switch 176 is turned off, such as in state a or state b, and no signal output is being made from the push-pull buffer circuit 152, that is, when the signal output is in a dormant state, a bypass current path is formed. That is, a bypass current I is formed in the bypass current path. Bypass It plays.

[0131] This bypass current I Bypass The output current I OUT Compared to the example in Figure 3, it is extremely small, and therefore, power consumption can be significantly reduced. Details of the power consumption reduction effect will be described later.

[0132] For example, the channel width W and channel length L of transistor 177 can be set to W / L = 2.4 μm / 0.55 μm. In this case, transistor 177 will have an area similar to that of a normal switch, and this area (size) is relatively small for an analog component. Therefore, in the push-pull buffer circuit 152, power consumption can be reduced simply by adding a small transistor 177. As an example, consider the output current I. OUT If we set it to 50 μA, the bypass current I Bypass This will be approximately 100nA. In other words, the bypass current I Bypass The output current I OUT This results in an extremely small current, equivalent to 0.002 times the original, enabling a significant reduction in power consumption.

[0133] <Example of operation of an intermittent push-pull buffered S / H circuit> Referring to Figure 9, an example of operation (driving example) of the intermittent push-pull buffered S / H circuit 92 will be explained.

[0134] In this example, the input terminal IP11 of the intermittently operating push-pull buffered S / H circuit 92 is connected to the pixel circuit via a vertical signal line, and the P-phase signal (hereinafter also referred to as the P-phase signal) and the D-phase signal (hereinafter also referred to as the D-phase signal) are read from the pixel circuit. It is also assumed that the output terminal OP11 is connected to an ADC (AD conversion circuit).

[0135] In Figure 9, the horizontal axis represents time, and the vertical axis represents potential (voltage level). In Figure 9, curve L11 represents the vertical signal line, i.e., the potential of input terminal IP11, at each time point. The broken lines L12, L13, and L14 represent the control signals BIAS_EN, SAMPLE_EN, and BUFSEL, respectively. In particular, the upward-convex portion in the figure for each control signal indicates the H level.

[0136] Curve L15 shows the voltage level of the signal output from output terminal OP11, i.e., the potential of output terminal OP11. The portion indicated by arrow Q21 shows the amount of current consumed at each time in the intermittently operating push-pull buffered S / H circuit 92.

[0137] At time t21, the control signals BIAS_EN and SAMPLE_EN are set to the H level, and switches 171 and 161 are turned on. At this time, the control signal BUFSEL is set to the L level, and switch 176 is turned off.

[0138] At the following time t22, the control signal BIAS_EN is set to the L level, and switch 171 is turned off. As a result, the operating state of the intermittent push-pull buffered S / H circuit 92 becomes state a as shown in Figure 6.

[0139] When switch 171 is turned off, the bias voltage is sampled. That is, immediately before time t22, the bias voltage NGTE_BIAS is supplied from the reference bias circuit 91 to terminal IP12, and the bias voltage PGTE_BIAS is supplied from the reference bias circuit 91 to terminal IP13. Therefore, at time t22, capacitor 172 holds a charge corresponding to the bias voltage NGTE_BIAS, and capacitor 173 holds a charge corresponding to the bias voltage PGTE_BIAS.

[0140] Specifically, the sum of the capacitances of capacitor 172-1 and capacitor 172-2 is C. GN Therefore, the difference between the bias voltage NGTE_BIAS and the voltage (potential) on the vertical signal line is C. GN The charge obtained by multiplying by is held across the capacitor 172.

[0141] Similarly, the sum of the capacitances of capacitor 173-1 and capacitor 173-2 is C. GP Therefore, the difference between the bias voltage PGTE_BIAS and the voltage (potential) on the vertical signal line is C. GP The charge obtained by multiplying by is held across the capacitor 173.

[0142] At time t23, the control signal SAMPLE_EN is set to L level, turning off switch 161 and electrically disconnecting the S / H circuit 151 from the vertical signal line (pixel circuit). As a result, the operating state of the intermittently operating push-pull buffered S / H circuit 92 becomes state b shown in Figure 7, and the P-phase signal is sampled by the S / H circuit 151. That is, the capacitance of capacitor 162 is set to C S Therefore, the difference between the voltage (potential) on the vertical signal line and the ground voltage (potential) is C. S The charge obtained by multiplying by is held across the ends of capacitor 162.

[0143] At time t24, the control signal BUFSEL is set to the H level, and switch 176 is turned on. That is, the operating state of the intermittently operating push-pull buffered S / H circuit 92 becomes state c as shown in Figure 8. As a result, the push-pull buffer circuit 152 (output terminal OP11) is electrically connected to the ADC, the sampled (read out) P-phase signal is output to the ADC, and the ADC performs AD conversion of the P-phase signal.

[0144] In the push-pull buffer circuit 152, a voltage corresponding to the charge held in capacitor 172 is applied to the gate of transistor 174, and a voltage corresponding to the charge held in capacitor 173 is applied to the gate of transistor 175.

[0145] When switch 176 is turned on, the push-pull buffer circuit 152 outputs current I OUT A current flows through the terminal. Furthermore, the potential of the output terminal OP11 gradually changes to a potential corresponding to the amount of charge held by the capacitor 162. In particular, in an ideal state without mismatch, the potential of the output terminal OP11 becomes the same as the potential (voltage level) at terminal P11 of the reference bias circuit 91. The potential (voltage level) of the output terminal OP11 at this time is read out as the P-phase signal (supplied to the ADC), and the ADC performs AD conversion on the signal supplied from the output terminal OP11 at the appropriate timing.

[0146] Subsequently, at time t25, the control signal BUFSEL is set to the L level, and switch 176 is turned off. As a result, the push-pull buffer circuit 152 enters a state of signal output suspension.

[0147] In the above, the period from time t21 to time t24 is the P-phase settling period, and the period from time t24 to time t25 is the AD conversion period (readout period) of the P-phase signal.

[0148] As shown by arrow Q21, during the period from time t21 to time t24, the push-pull buffer circuit 152 (S / H circuit 92 with intermittent push-pull buffer) continuously provides bypass current I Bypass The current flows. Also, during the period from time t24 to time t25, the push-pull buffer circuit 152 continuously outputs current I OUT It plays.

[0149] Once the P-phase signal has been read out, the D-phase signal is then read out.

[0150] In other words, at time t26, the control signal SAMPLE_EN is set to the H level, and switch 161 is turned on. As a result, the S / H circuit 151 is connected to the pixel circuit via the vertical signal line.

[0151] At time t26, the pixel circuit is in a state where the signal obtained by the exposure operation including photoelectric conversion (D-phase signal) is output to the vertical signal line. Therefore, the potential of the vertical signal line, i.e., the input terminal IP11, gradually decreases by the amount of charge obtained by the photoelectric conversion in the pixel (pixel circuit).

[0152] At time t27, the control signal SAMPLE_EN is set to L level, turning off switch 161 and electrically disconnecting the S / H circuit 151 from the vertical signal line (pixel circuit). As a result, the operating state of the intermittently operating push-pull buffered S / H circuit 92 becomes state b shown in Figure 7, and the D-phase signal is sampled by the S / H circuit 151.

[0153] In other words, the capacitance of capacitor 162 is C S Therefore, the difference between the voltage (potential) on the vertical signal line and the ground voltage (potential) is C.S The charge obtained by multiplying by is held across capacitor 162. Furthermore, according to the law of conservation of charge, the voltage applied to the gate of transistor 174 and the voltage applied to the gate of transistor 175 change (decrease) by the difference ΔVSL (ΔVSL < 0) between the potential of the vertical signal line at the current time and the potential of the vertical signal line at time t23.

[0154] At time t28, when the control signal BUFSEL is set to the H level and switch 176 is turned on, the operating state of the intermittently operating push-pull buffered S / H circuit 92 becomes state c as shown in Figure 8. As a result, the push-pull buffer circuit 152 (output terminal OP11) is electrically connected to the ADC, the sampled (read out) D-phase signal is output to the ADC, and the ADC performs AD conversion of the D-phase signal.

[0155] When switch 176 is turned on, the push-pull buffer circuit 152 outputs current I OUT As the current flows, the potential of the output terminal OP11 gradually changes to a potential corresponding to the amount of charge held by the capacitor 162.

[0156] For example, let V be the potential (voltage level at time t25) when reading out the P-phase signal. COM If we write it this way, in an ideal state without mismatch, the potential of output terminal OP11 is V COM The voltage gradually changes to +ΔVSL. At this time, the potential (voltage level) of the output terminal OP11 is read out as the D-phase signal (supplied to the ADC), and the ADC performs AD conversion on the signal supplied from the output terminal OP11 at the appropriate timing.

[0157] At time t29, the control signal BUFSEL is set to the L level, the switch 176 is turned off, and the intermittent push-pull buffered S / H circuit 92 is disconnected from the ADC. In other words, the signal output is put into a pause state.

[0158] In the above, the period from time t25 to time t28 is the D-phase settling period, the period from time t28 to time t29 is the AD conversion period (readout period) of the D-phase signal, and the period from time t29 onwards is the idling period.

[0159] As shown by arrow Q21, during the period from time t25 to time t28, the push-pull buffer circuit 152 (S / H circuit 92 with intermittent push-pull buffer) continuously provides bypass current I Bypass The current flows. Also, during the period from time t28 to time t29, the push-pull buffer circuit 152 continuously outputs current I OUT It plays.

[0160] In the electronic circuit 81 (S / H circuit 92 with intermittent push-pull buffer), power consumption can be reduced by providing a switch 176 for intermittent operation control and a transistor 177 for stabilizing the operating point during intermittent operation in the push-pull buffer circuit 152.

[0161] Specifically, for example, because transistor 177 is provided, the bypass current I that flows through the push-pull buffer circuit 152 when sampling the bias voltage Bypass This is significantly smaller compared to the example explained with reference to Figure 4. Therefore, power consumption can be reduced, and IR drop can also be minimized.

[0162] Therefore, even if multiple intermittently operating push-pull buffer S / H circuits 92 are provided in parallel, for example, IR drop during simultaneous operation of all columns is acceptable, thus avoiding difficulties in wiring design and preventing concerns about degradation of signal readout accuracy.

[0163] Furthermore, immediately before the signal readout period (settling period), the bypass current I continues to flow through the push-pull buffer circuit 152. Bypass This bypass current I continues to flow. Bypass This is a small current called the subthreshold current, but it is sufficient to erase the source potential history of transistors 174 and 175.

[0164] In other words, bypass current I BypassAs the current continues to flow, transistors 174 and 175 stabilize in the saturation region, maintaining a constant gm (transconductance), i.e., a sufficiently high gm. Therefore, the initial response of transistors 174 and 175 when switch 176 is turned on at time t24 or t28, i.e., the response speed (output response) at the time of signal output, becomes faster. This makes it possible to shorten the signal readout period, i.e., the period during which switch 176 is turned on and connected to the subsequent stage (intermittent operation period). In other words, the intermittency rate can be improved.

[0165] If the signal readout period can be shortened, the output current I in the push-pull buffer circuit 152 will be reduced during signal readout. OUT Since the duration for which the current flows is shortened, it is possible to achieve a further reduction in power consumption.

[0166] Furthermore, by improving the intermittency rate, for example, when multiple S / H circuits 92 with intermittent operation push-pull buffers are provided in parallel, multiplex operation can be performed at high speed to sequentially switch the column to be selected (S / H circuits 92 with intermittent operation push-pull buffers).

[0167] <Second Embodiment> <Circuit Configuration Example> The intermittently operating push-pull buffered S / H circuit 92 may be used individually in various electronic circuits (devices), or multiple circuits may be connected in parallel.

[0168] For example, consider the case where N intermittent push-pull buffer-equipped S / H circuits 92 are connected in parallel in a CMOS image sensor (solid-state imaging device).

[0169] In such a case, if we denote each of the N intermittently operating push-pull buffered S / H circuits 92 as intermittently operating push-pull buffered S / H circuit 92-1 to intermittently operating push-pull buffered S / H circuit 92-N, then the CMOS image sensor will be provided with a circuit configuration such as that shown in Figure 10. That is, Figure 10 is a diagram showing an example of a partial configuration of a CMOS image sensor.

[0170] In Figure 10, the same reference numerals are used for parts corresponding to those in Figure 5, and their explanations are omitted as appropriate. Furthermore, when there is no need to distinguish between the intermittently operating push-pull buffered S / H circuits 92-1 to 92-N, they will simply be referred to as the intermittently operating push-pull buffered S / H circuit 92.

[0171] In the example shown in Figure 10, intermittent push-pull buffered S / H circuits 92-1 to 92-N are connected in parallel, and these N intermittent push-pull buffered S / H circuits 92 are connected to one ADC 251.

[0172] Furthermore, each intermittent push-pull buffered S / H circuit 92 is connected to a reference bias circuit 91. Note that each intermittent push-pull buffered S / H circuit 92 may be connected to the same reference bias circuit 91, or they may be connected to different reference bias circuits 91.

[0173] Each of the N intermittently operating push-pull buffered S / H circuits 92 has the same configuration as the intermittently operating push-pull buffered S / H circuit 92 shown in Figure 5. However, the input terminals IP11 of each of the N intermittently operating push-pull buffered S / H circuits 92 are connected to different vertical signal lines. That is, the S / H circuits 151 of each of the N intermittently operating push-pull buffered S / H circuits 92 hold signals output from different pixel circuits (pixels).

[0174] Here, a circuit section including one intermittently operating push-pull buffered S / H circuit 92 connected to one vertical signal line is referred to as one column. That is, in the example shown in Figure 10, N columns are arranged in parallel.

[0175] The ADC 251 is connected to multiple (N) intermittently operating push-pull buffered S / H circuits 92 (push-pull buffer circuits 152) connected in parallel. The ADC 251 is an ADC conversion circuit that performs AD conversion on the signal supplied from the output terminal OP11 of the intermittently operating push-pull buffered S / H circuits 92. For example, the ADC 251 may be a SAR ADC (Successive Approximation Register Analog-to-Digital Converter).

[0176] Furthermore, in the example shown in Figure 10, the CMOS image sensor is equipped with a control circuit 252. For example, a Gray code is input to the control circuit 252 as a signal for multiplex operation, and the control circuit 252 functions as a Gray code decoder.

[0177] The control circuit 252 generates a control signal BUFSEL for controlling the operation of the switch 176 by decoding based on the supplied Gray code. The control circuit 252 supplies the generated control signal BUFSEL to the switch 176 of each intermittently operating push-pull buffered S / H circuit 92, thereby controlling the operation of the switch 176.

[0178] In this case, the control circuit 252 achieves multiplex operation by sequentially selecting each of the N columns (intermittent push-pull buffered S / H circuits 92) as a column, that is, by sequentially switching the intermittent push-pull buffered S / H circuits 92 that turn on the switch 176. Note that a control circuit 252 may be provided for each column, or a single control circuit 252 may be provided common to multiple columns.

[0179] When the switch 176 is ON in the intermittent push-pull buffered S / H circuit 92 of the selected column, the switches 176 are OFF in the remaining (N-1) columns (non-selected columns) of the intermittent push-pull buffered S / H circuits 92. Therefore, by performing multiplex operation, signals are supplied sequentially from each of the N intermittent push-pull buffered S / H circuits 92 to the ADC 251.

[0180] In the example shown in Figure 10, multiplex operation is achieved by controlling the switch 176 of each column. Therefore, the switch 176 functions not only as a switch for intermittent operation control but also as a switch for multiplex operation. That is, by controlling the switch 176, multiplex operation is possible in which signals are supplied sequentially to the ADC 251 from each of the multiple intermittent push-pull buffered S / H circuits 92 (push-pull buffer circuits 152).

[0181] <Operation Example> An example of operation of a CMOS image sensor (electronic circuit) having the configuration shown in Figure 10 will be described.

[0182] Figure 11 shows an image of the signal readout operation using the circuit shown in Figure 10.

[0183] In Figure 11, the horizontal axis represents time, the upper section shows the operating timing of each column, and the lower section shows the timing of the AD conversion of the signals read from each column.

[0184] In the example shown in Figure 11, the P-phase signal is sampled simultaneously in all columns. Then, each column is selected in sequence as a selected column, and the hold operation, i.e., the read operation, of the P-phase signal in the selected column is performed sequentially. Simultaneously with the hold operation (read operation) of the P-phase signal in the next selected column, the AD conversion of the P-phase signal read from the previous selected column is performed.

[0185] Once the P-phase signal readout and AD conversion are complete for all columns, the D-phase signal is then sampled simultaneously for all columns. Each column is then selected in sequence, and the D-phase signal hold operation, i.e., the readout operation, is performed sequentially for each selected column. At this time, as with the P-phase, the AD conversion of the D-phase signal read from the previous selected column is performed simultaneously with the D-phase signal hold operation (readout operation) of the next selected column.

[0186] Referring to Figure 12, a more specific example of the operation of the circuit shown in Figure 10 will be explained. In Figure 12, the horizontal direction represents time, and the vertical direction represents potential (voltage level). In particular, the upward-convex portion of each control signal in the figure indicates the H level.

[0187] In Figure 12, curve L31 shows the potential of the vertical signal line, i.e., the input terminal IP11, at each time step. In particular, for clarity, the potential change is shown for only one column. Linear graphs L32, L33, and L34 represent the control signals BIAS_EN, SAMPLE_EN, and the 5-bit Gray code input to control circuit 252. Specifically, the control signals BIAS_EN and SAMPLE_EN are common to all columns.

[0188] The broken lines L35-1 to L35-N (however, broken lines L35-3 to L35-(N-1) are not shown) represent the control signal BUFSEL of the intermittently operating push-pull buffered S / H circuits 92-1 to 92-N.

[0189] Hereinafter, the intermittently operating push-pull buffered S / H circuit 92-n (where n = 1, 2, ..., N) will also be referred to as the nth intermittently operating push-pull buffered S / H circuit 92, and the column on which the nth intermittently operating push-pull buffered S / H circuit 92 is provided will also be referred to as the nth column. Furthermore, the control signal BUFSEL supplied to the nth intermittently operating push-pull buffered S / H circuit 92 will be specifically referred to as the control signal BUFSEL_n.

[0190] Curve L36 shows the potential at the input terminal of ADC251, i.e., the voltage level of the signal supplied to ADC251. The portion indicated by arrow Q31 shows the amount of current consumed at each time point across all N columns.

[0191] First, at time t41, the control signals BIAS_EN and SAMPLE_EN are simultaneously set to the H level in all columns, and switches 171 and 161 are turned on.

[0192] At time t42, the control signal BIAS_EN is simultaneously set to L level in all columns, the switch 171 is turned off, and bias voltage sampling is performed.

[0193] At time t43, the control signal SAMPLE_EN is simultaneously set to L level in all columns, turning off switch 161 and performing sampling of the P-phase signal. That is, the S / H circuits 151 of the multiple intermittently operating push-pull buffered S / H circuits 92 connected to one ADC 251 simultaneously perform the operation of sampling the signal output from the pixel circuit.

[0194] The operation from time t41 to time t43 described above is the same as the operation from time t21 to time t23 in Figure 9.

[0195] Subsequently, for example, when a 5-bit Gray code is supplied to the control circuit 252, the control circuit 252 generates a control signal BUFSEL based on the Gray code and supplies it to the switch 176.

[0196] As a result, from time t44 onward, each column is selected as a selected column in sequence, and a P-phase signal is output from the S / H circuit 92 with an intermittent push-pull buffer for the selected column. At each timing, one of all the columns is designated as a selected column, and the P-phase signal is read out (output) from that selected column, while the remaining columns are designated as unselected columns, and the P-phase signals from those unselected columns are not read out.

[0197] During the period from time t44 to time t46, a multiplex operation is performed in which the P-phase signal is read out from the selected column while switching between the selected columns.

[0198] For example, at time t44, only control signal BUFSEL_1 is set to the H level, and switch 176 of the intermittent push-pull buffered S / H circuit 92 of the first column is turned on. At this time, the other control signals BUFSEL_2 to BUFSEL_N are set to the L level.

[0199] In the first column, when switch 176 is turned on, the sampled P-phase signal is output from output terminal OP11 to ADC251, similar to the case at time t24 in Figure 9, and ADC251 performs AD conversion of the P-phase signal.

[0200] At time t45, the control signal BUFSEL_1 is set to the L level, turning off the switch 176 of the first column, and that first column becomes a non-selected column.

[0201] Simultaneously, at time t45, the control signal BUFSEL_2 is set to the H level, turning on the switch 176 of the second column, and the second column becomes the selected column. In other words, the selected column is switched, a P-phase signal is output from the output terminal OP11 of the second column to the ADC 251, and the AD conversion of that P-phase signal is performed.

[0202] Subsequently, the same process is repeated until time t46, during which the P-phase signals from each column are read out and AD conversion is performed.

[0203] When the control signal BUFSEL_N is set to the L level at time t46 and the switch 176 of the Nth column is turned off, the reading of the P-phase signals from all columns is completed.

[0204] In the above, the period from time t41 to time t44 is the P-phase settling period, and the period from time t44 to time t46 is the AD conversion period (readout period) of the P-phase signal.

[0205] As shown by arrow Q31, during the period from time t41 to time t44, the bypass current I continues in each column. Bypass Since current flows, the total current consumption is N × I Bypass This is the result.

[0206] Furthermore, during the period from time t44 to time t46, the output current I in one selected column OUT A current flows through each of the (N-1) nonselective columns, and a bypass current I Bypass Since current flows, the total current consumption is I OUT +(N-1)×I Bypass This is the result.

[0207] Once the P-phase signal has been read out, the D-phase signal is then read out.

[0208] Specifically, at time t47, the control signal SAMPLE_EN is simultaneously set to the H level in all columns, and switch 161 is turned on. At the following time t48, the control signal SAMPLE_EN is simultaneously set to the L level in all columns, and switch 161 is turned off, and the D-phase signal is sampled. These operations at times t47 and t48 are the same as the operations at times t26 and t27 in Figure 9.

[0209] Subsequently, during the period from time t49 to time t51, the control circuit 252 generates a control signal BUFSEL, and the same operation as in the period from time t44 to time t46 is performed. That is, each column is selected in order as a selected column, and the D-phase signal is output from the intermittently operating push-pull buffered S / H circuit 92 of the selected column to the ADC 251, and the AD conversion of that D-phase signal is performed.

[0210] Furthermore, in the logic circuit following the ADC251, processes such as CDS (Correlated Double Sampling) are performed to generate a luminance signal by calculating the difference between the P-phase signal and the D-phase signal, or the digital P-phase signal and D-phase signal are output directly.

[0211] For example, at time t49, only control signal BUFSEL_1 is set to the H level, while the other control signals BUFSEL_2 to BUFSEL_N are set to the L level. As a result, switch 176 of the intermittent push-pull buffered S / H circuit 92 of the first column is turned on, and a D-phase signal is output from output terminal OP11 to ADC251.

[0212] Furthermore, for example, at time t50, the control signal BUFSEL_1 is set to the L level, turning off the switch 176 of the first column, while the control signal BUFSEL_2 is set to the H level, turning on the switch 176 of the second column. As a result, the first column becomes a non-selected column, and the second column becomes a selected column. In other words, the selected column is switched, and a D-phase signal is output from the output terminal OP11 of the second column to the ADC251.

[0213] Subsequently, the same process is repeated until time t51, during which the D-phase signals from each column are read out and AD conversion is performed.

[0214] When the control signal BUFSEL_N is set to the L level at time t51 and the switch 176 of the Nth column is turned off, the reading of the D-phase signals from all columns is completed.

[0215] In the above, the period from time t46 to time t49 is the D-phase settling period, the period from time t49 to time t51 is the AD conversion period (readout period) of the D-phase signal, and the period from time t51 onwards is the idling period.

[0216] As shown by arrow Q31, in the period from time t46 to time t49, the total current consumption is N × I, similar to the period from time t41 to time t44. Bypass This is the result.

[0217] Furthermore, during the period from time t49 to time t51, the total current consumption is I, similar to the period from time t44 to time t46. OUT +(N-1)×I Bypass This is the result.

[0218] Thus, even with the configuration shown in Figure 10, it is possible to reduce the IR drop and decrease the power consumption during the bias voltage sampling period.

[0219] Furthermore, similar to the example in Figure 5, the response speed during signal readout in each column can be increased, thereby improving the intermittency ratio. Therefore, by connecting the intermittent operation push-pull buffer-equipped S / H circuits 92 of each column in parallel, high-speed multiplex operation (multiplex switching) can be achieved, and power consumption during signal readout can also be reduced.

[0220] <Regarding noise reduction> By the way, the circuit configuration shown in Figure 10 is susceptible to noise caused by power supply fluctuations and ground fluctuations.

[0221] Therefore, as shown in Figure 13, for example, by configuring the circuit that supplies the reference voltage (voltage signal) used as the reference voltage during AD conversion to the ADC 251 to be the same as the S / H circuit 92 with intermittent push-pull buffer and the reference bias circuit 91, the influence of noise can be reduced.

[0222] In Figure 13, the same reference numerals are used for parts corresponding to those in Figure 10, and their explanations are omitted as appropriate. Furthermore, in Figure 13, some reference numerals have been omitted for clarity. In subsequent figures, some reference numerals will also be omitted as appropriate for clarity.

[0223] In the example shown in Figure 13, N intermittent push-pull buffer S / H circuits 92 are connected in parallel to the ADC 251. These intermittent push-pull buffer S / H circuits 92 supply P-phase signals and D-phase signals to the ADC 251 as signal voltages to be converted to AD. Each intermittent push-pull buffer S / H circuit 92 is also connected to a reference bias circuit 91.

[0224] Furthermore, this example also includes a reference bias circuit 281 and an S / H circuit 282 with an intermittent push-pull buffer connected to the reference bias circuit 281.

[0225] The reference bias circuit 281 is a bias voltage source circuit with the same configuration as the reference bias circuit 91, and supplies a bias voltage to the S / H circuit 282 with an intermittently operating push-pull buffer.

[0226] The intermittently operating push-pull buffered S / H circuit 282 is a push-pull buffer circuit (S / H circuit) having the same configuration as the intermittently operating push-pull buffered S / H circuit 92, and supplies a reference voltage (reference voltage signal) to the ADC 251.

[0227] The intermittently operating push-pull buffered S / H circuit 282 includes a sample-and-hold circuit 291 (S / H circuit 291), a push-pull buffer circuit 292, an attenuation circuit 293, a capacitor 294, and a capacitor 295. These S / H circuits 291 to capacitor 295 correspond to the S / H circuits 151 to capacitor 155 in the intermittently operating push-pull buffered S / H circuit 92.

[0228] Furthermore, the intermittently operating push-pull buffered S / H circuit 282 has input terminals IP31, IP32, IP33, and output terminal OP31, which correspond to the input terminals IP11 to output terminal OP11 of the intermittently operating push-pull buffered S / H circuit 92.

[0229] Input terminal IP31 is connected to ground and S / H circuit 291, and the ground voltage level is input (supplied) to S / H circuit 291.

[0230] Terminal IP32 is connected to the reference bias circuit 281, and the bias voltage NGTE_BIAS from the reference bias circuit 281 is supplied to the push-pull buffer circuit 292 and capacitor 294 via terminal IP32.

[0231] Terminal IP33 is connected to the reference bias circuit 281, and the bias voltage PGTE_BIAS from the reference bias circuit 281 is supplied to the push-pull buffer circuit 292 and capacitor 295 via terminal IP33.

[0232] Output terminal OP31 is connected to ADC251 and supplies the output of the push-pull buffer circuit 292 to ADC251.

[0233] In the intermittently operating push-pull buffered S / H circuit 92, a signal (voltage signal) corresponding to the voltage level (potential) of the vertical signal line is supplied as a signal voltage from the output terminal OP11 to the ADC 251. In contrast, in the intermittently operating push-pull buffered S / H circuit 282, a signal corresponding to the voltage level (potential) of the ground is supplied as a reference voltage from the output terminal OP31 to the ADC 251. The ADC 251 performs AD conversion of the signal voltage, i.e., the signal supplied from the intermittently operating push-pull buffered S / H circuit 92, by comparing the supplied signal voltage with the reference voltage.

[0234] Furthermore, the reference bias circuit 91 and reference bias circuit 281 allow for adjustment of the output current and output voltage levels. In other words, the reference bias circuit 91 controls the output current I that flows through the push-pull buffer circuit 152 when a signal is output. OUT This determines the voltage level (output voltage) at the time of signal output. Similarly, the reference bias circuit 281 determines the output current I OUT Determine the corresponding output current and reference voltage.

[0235] Specifically, for example, by adjusting the reference current flowing from the current source 101 in the reference bias circuit 91, the output current I flowing through the push-pull buffer circuit 152 of the intermittently operating push-pull buffered S / H circuit 92 can be controlled. OUT The magnitude can be adjusted. Similarly, the output current can be adjusted in the reference bias circuit 281.

[0236] Furthermore, by adjusting the resistance value (magnitude of resistance) of resistor 106 in the reference bias circuit 91, for example, the voltage level of the signal voltage output (supplied) from the intermittently operating push-pull buffered S / H circuit 92 to the ADC 251, or more specifically, the reference voltage level of the signal voltage, can be adjusted. The reference voltage can also be adjusted in the same way in the reference bias circuit 281.

[0237] In the intermittently operating push-pull buffered S / H circuit 92, noise may be generated by parasitic capacitance between the gate and drain of transistor 174 due to power supply fluctuations (fluctuations in the self-power supply). In addition, noise may be generated in capacitor 173 (capacitor 162) due to ground fluctuations.

[0238] When such noise occurs, fluctuations in the signal voltage occur, as shown in Figure 14, for example. In other words, the signal voltage deteriorates due to the noise.

[0239] In Figure 14, the horizontal axis represents time, and the vertical axis represents voltage level. Curve L41 represents the signal voltage supplied from the intermittently operating push-pull buffered S / H circuit 92 to the ADC 251, and straight line L42 represents the reference voltage supplied from the intermittently operating push-pull buffered S / H circuit 282 to the ADC 251.

[0240] As mentioned above, the signal voltage contains noise caused by power supply fluctuations and ground fluctuations.

[0241] However, the reference bias circuit 281 and the S / H circuit 282 with intermittent push-pull buffer have the same configuration as the reference bias circuit 91 and the S / H circuit 92 with intermittent push-pull buffer.

[0242] Furthermore, the reference bias circuit 281 and the S / H circuit 282 with intermittent push-pull buffer, and the reference bias circuit 91 and the S / H circuit 92 with intermittent push-pull buffer will operate under similar conditions and in similar environments.

[0243] Therefore, the reference voltage also contains noise similar to that of the signal voltage, and the noise contained in the signal voltage and the noise contained in the reference voltage can be considered common-mode noise. Such common-mode noise is suppressed by the common-mode rejection ratio (CMRR) of the ADC251. In other words, a noise reduction effect due to the common-mode rejection ratio can be expected.

[0244] As described above, by using the same configuration for the reference bias circuit 91 and the S / H circuit 92 with intermittent push-pull buffer, and the same configuration for the reference bias circuit 281 and the S / H circuit 282 with intermittent push-pull buffer, noise caused by fluctuations in the power supply and ground can be reduced. In other words, resistance to fluctuations in the power supply and ground can be improved. The configuration shown in Figure 13 can also be applied when an ADC is connected after the S / H circuit 92 with intermittent push-pull buffer in the example shown in Figure 5.

[0245] <Example of a bypass current circuit> The bypass current circuit provided in the push-pull buffer circuit 152 can be any type as long as it can form a bypass current path when the signal output is paused. In other words, the bypass current circuit can be configured in any way as long as it can supply bypass current (subthreshold current) to transistors 174 and 175 when switch 176 is in the off state.

[0246] Figures 15 to 20 show examples of bypass current circuits. In Figures 15 to 20, the same reference numerals are used for parts corresponding to those in Figure 5, and their explanations are omitted as appropriate.

[0247] In all the examples shown in Figures 15 to 20, the bypass current circuit is located between transistors 174 and 175, which are connected in parallel. Additionally, two switches 176 are located between one end and the other end of the bypass current circuit.

[0248] In the example shown in Figure 15, a bypass current circuit is formed by transistors 311 and 312. In this example, transistor 311 is an N-channel transistor, and transistor 312 is a P-channel transistor.

[0249] The gate and drain of transistor 311 are connected between the source of transistor 174 and switch 176-1, and the source of transistor 311 is connected between the source of transistor 175 and switch 176-2. In addition, the back gate of transistor 311 is connected to the source of transistor 311.

[0250] The gate and drain of transistor 312 are connected between the source of transistor 175 and switch 176-2. Additionally, the gate and drain of transistor 312 are also connected to the source of transistor 311.

[0251] The source of transistor 312 is connected between the source of transistor 174 and switch 176-1. The source of transistor 312 is also connected to the gate and drain of transistor 311. Furthermore, the back gate of transistor 312 is connected to the source of transistor 312.

[0252] In this example, transistors 311 and 312 are shown in a self-bias configuration where the back gates and sources are connected, but a non-self-bias configuration is also possible. In such a case, for example, the back gate of transistor 311 is connected to ground, and the back gate of transistor 312 is connected to the power supply.

[0253] In the example shown in Figure 16, a P-channel transistor 341 is provided as a bypass current circuit.

[0254] In this example, the source of transistor 341 is connected between the source of transistor 174 and switch 176-1, and the gate and drain of transistor 341 are connected between the source of transistor 175 and switch 176-2.

[0255] Furthermore, although a self-bias configuration is shown here where the back gate and source of transistor 341 are connected, a non-self-bias configuration may also be used, as in the example in Figure 15.

[0256] In the example shown in Figure 17, a bypass current circuit is configured by two current sources 371 and 372.

[0257] In this example, the current source 371 is positioned between the source of transistor 174 and switch 176-1 and ground, and a bypass current flows from transistor 174 to the ground connected to the current source 371.

[0258] Furthermore, the current source 372 is positioned between the source of transistor 175 and switch 176-2 and the power supply, and a bypass current flows from the current source 372 through transistor 175 and switch 178 to ground.

[0259] In the example shown in Figure 18, resistor 401 is provided as a bypass current circuit.

[0260] In this example, one end of resistor 401 is connected between the source of transistor 174 and switch 176-1, and the other end of resistor 401 is connected between the source of transistor 175 and switch 176-2.

[0261] In the example shown in Figure 19, an N-channel transistor 177 is provided as a bypass current circuit. The configuration of the bypass current circuit shown in Figure 19 is the same as the example shown in Figures 5 and 10. In addition, in the example in Figure 19, the back gate and source of transistor 177 are connected in a self-bias configuration, but a non-self-bias configuration may also be used.

[0262] In the example shown in Figure 20, the current source 441 is provided as a bypass current circuit.

[0263] In this example, one end of the current source 441 is connected between the source of transistor 174 and switch 176-1, and the other end of the current source 441 is connected between the source of transistor 175 and switch 176-2.

[0264] <About the Attenuation Function> The attenuation circuit 153 provided in the S / H circuit 92 with intermittent operation push-pull buffer in the examples shown in Figures 5 and 10 will be described below. Specifically, the attenuation function by the attenuation circuit 153 will be described below with reference to Figures 21 and 22. Note that parts corresponding to those in Figure 5 are denoted by the same reference numerals in Figures 21 and 22, and their explanations will be omitted as appropriate.

[0265] When the attenuation function is off, i.e., in 0dB attenuation mode, switch 181 is in the ON state and switch 182 is in the OFF state, as shown in Figure 21.

[0266] In this case, for example, if the voltage level of the signal input from the vertical signal line to the S / H circuit 151 is 1V, then the signal voltage output from the push-pull buffer circuit 152 will also be 1V.

[0267] In contrast, when the attenuation function is ON, i.e., in 6dB attenuation mode, switch 181 is OFF and switch 182 is ON, as shown in Figure 22.

[0268] When the attenuation function is turned on, the two capacitors 172 are connected in series, and the gate of transistor 174 is connected between the two capacitors 172. Similarly, the two capacitors 173 are connected in series, and the gate of transistor 175 is connected between the two capacitors 173.

[0269] Here, we assume that the capacitances of the two capacitors 172 are equal, and the capacitances of the two capacitors 173 are also equal. In such a case, when the attenuation function is on, the signal voltage output from the push-pull buffer circuit 152 is attenuated by 6 dB compared to when the attenuation function is off. That is, an attenuation rate of -6 dB is achieved. Specifically, for example, if the voltage level of the signal input from the vertical signal line to the S / H circuit 151 is 1 V, the signal voltage output from the push-pull buffer circuit 152 will be 0.5 V.

[0270] By providing an attenuation circuit 153 to the intermittently operating push-pull buffered S / H circuit 92, the S / H circuit 151 can receive signals with a wider input amplitude (voltage range). In other words, it can output signal voltages with a wider amplitude.

[0271] Furthermore, in the attenuation circuit 153, various attenuation rates can be achieved by increasing the number of connected capacitors, that is, by increasing the number of divisions of the capacitance.

[0272] For example, if you use a binary-weighted configuration, you can increase the number of additional capacitors connected to capacitors 172 and 173, allowing you to switch between and use various attenuation levels of the signal voltage, i.e., various attenuation rates, such as 0dB, -6dB, -12dB, and so on.

[0273] Thus, in the attenuation circuit 153, the capacitors 172 and 173, and any additionally provided capacitors, may be configured to either connect to capacitor 162 or to ground directly or via other capacitors. By doing so, the attenuation circuit 153 can adjust (switch) the amount of attenuation of the signal (signal voltage) output from the push-pull buffer circuit 152 in multiple stages.

[0274] Furthermore, although the above describes an example in which an attenuation circuit 153 is provided in the intermittently operating push-pull buffered S / H circuit 92, the attenuation circuit 153 is not required to be provided in the intermittently operating push-pull buffered S / H circuit 92. In other words, the intermittently operating push-pull buffered S / H circuit 92 does not need to have an attenuation function.

[0275] In such cases, for example, the intermittently operating push-pull buffered S / H circuit 92 is configured as shown in Figure 23. Note that in Figure 23, the same reference numerals are used for parts corresponding to those in Figure 5, and their explanations are omitted as appropriate.

[0276] In the example shown in Figure 23, the intermittently operating push-pull buffered S / H circuit 92 includes an S / H circuit 151, a push-pull buffer circuit 152, a capacitor 154, and a capacitor 155.

[0277] The configuration of the intermittent push-pull buffered S / H circuit 92 shown in Figure 23 differs from the configuration of the intermittent push-pull buffered S / H circuit 92 shown in Figure 5 in that it does not have an attenuation circuit 153, but in other respects it is the same as the configuration shown in Figure 5.

[0278] However, in the intermittent push-pull buffered S / H circuit 92 shown in Figure 23, capacitors 172-2 and 173-2 are not provided in the push-pull buffer circuit 152.

[0279] Furthermore, one end of capacitor 172-1 is connected to the gate of transistor 174 and switch 171-1, and the other end of capacitor 172-1 is connected to switch 161 and capacitor 162. Similarly, one end of capacitor 173-1 is connected to the gate of transistor 175 and switch 171-2, and the other end of capacitor 173-1 is connected to switch 161 and capacitor 162.

[0280] The intermittent push-pull buffered S / H circuit 92 shown in Figure 23 operates in the same way as the intermittent push-pull buffered S / H circuit 92 shown in Figure 5, except that it lacks an attenuation function.

[0281] <Example of a reference bias circuit> The reference bias circuit 91 connected to the intermittently operating push-pull buffered S / H circuit 92 is not limited to the configuration shown in Figure 5, but can be any circuit that can supply a bias voltage to the intermittently operating push-pull buffered S / H circuit 92.

[0282] Figures 24 and 25 show other configuration examples of the reference bias circuit 91. Note that in Figure 24, parts corresponding to those in Figure 5 are denoted by the same reference numerals, and their explanations are omitted as appropriate.

[0283] In the example shown in Figure 24, the reference bias circuit 91 includes a current source 101, a transistor 102, a switch 103, a switch 104, a transistor 105, and a resistor 106.

[0284] The configuration of the reference bias circuit 91 shown in Figure 24 differs from the configuration of the reference bias circuit 91 shown in Figure 5 in that it does not include a transistor 107, but otherwise it is the same as the configuration of the reference bias circuit 91 shown in Figure 5.

[0285] In the example shown in Figure 24, the number of elements can be reduced compared to the reference bias circuit 91 with the configuration shown in Figures 5 and 10. However, discontinuities in the layout pattern and the presence or absence of bypass current may cause errors in the bias voltage.

[0286] The reference bias circuit 91 shown in Figure 25 includes a current source 481, a switch 482, a transistor 483, an operational amplifier 484, a stabilized reference voltage source 485, an operational amplifier 486, a transistor 487, a switch 488, and a current source 489.

[0287] In this example, a current source 481, a switch 482, and a P-channel transistor 483 are arranged in a row between the power supply and ground. The back gate and source of transistor 483 are also connected.

[0288] The inverting input terminal of operational amplifier 484 is connected between the current source 481 and the switch 482, and the non-inverting input terminal of operational amplifier 484 is connected to the non-inverting input terminal of operational amplifier 486 and the stabilized reference voltage source 485.

[0289] The output terminal of operational amplifier 484 is connected to the gate of transistor 483 and to terminal IP13 of the intermittently operating push-pull buffered S / H circuit 92. Operational amplifier 484 supplies the bias voltage PGTE_BIAS to terminal IP13 (push-pull buffer circuit 152).

[0290] The stabilized reference voltage source 485 is connected to the non-inverting input terminals of the operational amplifier 484 and the operational amplifier 486, and supplies (inputs) a predetermined reference voltage to the operational amplifiers 484 and 486.

[0291] The non-inverting input terminal of operational amplifier 486 is connected to the non-inverting input terminal of operational amplifier 484 and the stabilized reference voltage source 485, while the inverting input terminal of operational amplifier 486 is connected between switch 488 and current source 489.

[0292] The output terminal of the operational amplifier 486 is connected to the gate of transistor 487 and to terminal IP12 of the intermittently operating push-pull buffer S / H circuit 92. The operational amplifier 486 supplies the bias voltage NGTE_BIAS to terminal IP12 (push-pull buffer circuit 152).

[0293] Transistor 487 is an N-channel transistor located between the power supply and switch 488. The gate of transistor 487 is connected to the output terminal and terminal IP12 of op-amp 486, and the back gate of transistor 487 is connected to the source.

[0294] Switch 488 is positioned between the source of transistor 487 and the inverting input terminal of operational amplifier 486 and current source 489. One end of current source 489 is connected to switch 488 and the inverting input terminal of operational amplifier 486, and the other end of current source 489 is connected to ground.

[0295] In the example shown in Figure 25, although power consumption and area increase, the output voltage level can be stabilized regardless of the PVT conditions, and the accuracy of the bias voltage and the response speed of the bias voltage can be improved.

[0296] <Example of application to a CMOS image sensor> Referring to Figures 26 to 31, an example of the application of the intermittently operating push-pull buffered S / H circuit 92 to a CMOS image sensor will be described.

[0297] In Figures 26 to 31, parts corresponding to those in Figure 5 or Figure 10 are denoted by the same reference numerals, and their explanations are omitted as appropriate. Also, in Figures 26 to 31, parts corresponding to each other are denoted by the same reference numerals, and their explanations are omitted as appropriate. In addition, in the following, the push-pull buffer circuit 152 will be represented by a symbol that combines a buffer and a switch as appropriate.

[0298] For example, as shown in Figure 26, the switch 176 portion of the push-pull buffer circuit 152 may be composed of a combination of transistors.

[0299] Here, switch 176-1 is configured by an N-channel transistor 521 and a P-channel transistor 522. In particular, the source and drain of transistor 521 are connected to the drain and source of transistor 522.

[0300] Similarly, switch 176-2 is configured by an N-channel transistor 523 and a P-channel transistor 524. Furthermore, the source and drain of transistor 523 are connected to the drain and source of transistor 524.

[0301] The gates of transistors 521 and 523 are supplied with the control signal BUFSEL to control their on / off state, while the gates of transistors 522 and 524 are supplied with the control signal X_BUFSEL to control their on / off state.

[0302] The control signal X_BUFSEL is the inverted version of the control signal BUFSEL. Therefore, transistors 521 to 524 are turned on and off simultaneously. Note that the control signal BUFSEL does not necessarily have to be generated from Gray code.

[0303] When the switch 176 has such a configuration, examples of how multiple combinations of S / H circuit 151 and push-pull buffer circuit 152 are arranged in a CMOS image sensor can be considered, as shown in Figures 27 and 28.

[0304] Note that in the examples shown in Figures 27 and 28, the attenuation circuit 153 is not shown, but it may or may not be provided. Also, in Figures 27 and 28, some reference numerals have been omitted for clarity.

[0305] The example shown in Figure 27 is an example of a column ADC configuration. Specifically, the CMOS image sensor shown in Figure 27 has a pixel array section 561, unit AD circuits 562-1 to 562-K, and reference voltage supply circuits 563-1 to 563-3.

[0306] In the following, when there is no need to distinguish between unit AD circuits 562-1 to 562-K, they will simply be referred to as unit AD circuit 562. Similarly, when there is no need to distinguish between reference voltage supply circuits 563-1 to 563-3, they will simply be referred to as reference voltage supply circuit 563.

[0307] The pixel array 561 has multiple pixels arranged in a matrix. Each pixel has a pixel circuit that converts incident light into photoelectric energy and outputs a signal corresponding to the resulting charge. In addition, each pixel is provided with a color filter in an arbitrary arrangement, such as a Bayer array.

[0308] The unit AD circuit 562-1 includes S / H circuits 571-1 to 571-M, push-pull buffer circuits 572-1 to 572-M, and an ADC 573.

[0309] Hereafter, when there is no need to distinguish between S / H circuits 571-1 to 571-M, they will simply be referred to as S / H circuit 571. Similarly, when there is no need to distinguish between push-pull buffer circuits 572-1 to 572-M, they will simply be referred to as push-pull buffer circuit 572.

[0310] The S / H circuit 571 corresponds to the S / H circuit 151 described above, the push-pull buffer circuit 572 corresponds to the push-pull buffer circuit 152 described above, and the ADC 573 corresponds to the ADC 251 in Figure 10. In other words, the S / H circuit 571 has the same configuration as the S / H circuit 151, and the push-pull buffer circuit 572 has the same configuration as the push-pull buffer circuit 152.

[0311] The input side of the S / H circuit 571 is connected via vertical signal lines to pixels provided in the pixel array section 561, more specifically to each pixel in a pixel array consisting of multiple pixels arranged in the column direction, and the output side of the S / H circuit 571 is connected to a push-pull buffer circuit 572.

[0312] An S / H circuit 571 is connected to the input side of the push-pull buffer circuit 572, and an ADC 573 is connected to the output side of the push-pull buffer circuit 572.

[0313] In particular, in the unit AD circuit 562-1, multiple sets of S / H circuits 571 and push-pull buffer circuits 572 are connected in parallel, and all push-pull buffer circuits 572 are connected to one (same) ADC 573. Here, each set of S / H circuit 571 and push-pull buffer circuit 572 corresponds to a column.

[0314] By connecting multiple push-pull buffer circuits 572 to a single ADC 573, power consumption can be reduced compared to the case where one ADC is connected to one push-pull buffer circuit.

[0315] In addition, in the example shown in Figure 27, each unit AD circuit 562 has the same configuration, and multiple unit AD circuits 562 are arranged in a row.

[0316] The reference voltage supply circuit 563-1 includes S / H circuit 581-1, S / H circuit 581-2, push-pull buffer circuit 582-1, and push-pull buffer circuit 582-2.

[0317] Hereinafter, when there is no need to distinguish between S / H circuits 581-1 and 581-2, they will simply be referred to as S / H circuit 581, and when there is no need to distinguish between push-pull buffer circuits 582-1 and 582-2, they will simply be referred to as push-pull buffer circuit 582.

[0318] The S / H circuit 581 corresponds to the S / H circuit 291 shown in Figure 13, and the push-pull buffer circuit 582 corresponds to the push-pull buffer circuit 292 shown in Figure 13. In particular, in this example, the S / H circuit 581 has the same configuration as the S / H circuit 571, and the push-pull buffer circuit 582 has the same configuration as the push-pull buffer circuit 572.

[0319] Ground is connected to the input side of the S / H circuit 581, and a push-pull buffer circuit 582 is connected to the output side of the S / H circuit 581.

[0320] The S / H circuit 581 is connected to the input side of the push-pull buffer circuit 582, and the ADC 573 of each unit AD circuit 562 is connected to the output side of the push-pull buffer circuit 582.

[0321] In particular, in the reference voltage supply circuit 563-1, multiple sets of S / H circuits 581 and push-pull buffer circuits 582 are connected in parallel, and all push-pull buffer circuits 582 are connected to the ADC 573 of all unit AD circuits 562. That is, each push-pull buffer circuit 582 supplies a reference voltage to all ADC 573.

[0322] In addition, in the example shown in Figure 27, each reference voltage supply circuit 563 has the same configuration, and the reference voltage supply circuits 563 are positioned at both ends of the multiple AD circuits 562 arranged in a row.

[0323] Specifically, in the diagram of the multiple AD circuit units 562 arranged in a row, the reference voltage supply circuit 563-1 is located on the right side, and the reference voltage supply circuits 563-2 and 563-3 are located on the left side. By placing the reference voltage supply circuits 563 at both ends of the multiple AD circuit units 562 in this way, the effects of power supply fluctuations and ground fluctuations can be further reduced.

[0324] In this example, the reference voltage supply circuit 563-3 is a backup circuit and is not necessarily required. Also, although this example describes an example where the reference voltage supply circuit 563 is placed at both ends of multiple unit AD circuits 562, the reference voltage supply circuit 563 may be placed at only one end of the multiple unit AD circuits 562.

[0325] In the example shown in Figure 27, when the exposure operation is performed in the pixel array section 561, the same operation as described with reference to Figure 12 is performed.

[0326] When reading signals from pixels in the pixel array section 561, the signals output from each pixel circuit (pixel) are supplied to and held in the S / H circuit 571 via vertical signal lines.

[0327] Furthermore, when reading the signal, a multiplex operation is performed within the unit AD circuit 562 in which sets (columns) of S / H circuit 571 and push-pull buffer circuit 572 are selected in sequence.

[0328] The selected push-pull buffer circuit 572 outputs (supplies) a signal voltage corresponding to the signal held in the S / H circuit 571 to the ADC 573. The ADC 573 performs AD conversion of the signal voltage by comparing the signal voltage supplied from the push-pull buffer circuit 572 with the reference voltage supplied from the push-pull buffer circuit 582 of the reference voltage supply circuit 563.

[0329] The example shown in Figure 28 is an example of a big-little configuration.

[0330] The CMOS image sensor shown in Figure 28 includes a pixel array section 561, unit S / H circuits 611-1 to 611-W, reference voltage supply circuits 563-1 to 563-3, an AD conversion section 612, and an AD conversion section 613.

[0331] In the following, when there is no need to distinguish between unit S / H circuits 611-1 to 611-W, they will simply be referred to as unit S / H circuit 611.

[0332] The S / H circuit 611-1 unit includes S / H circuits 571-1 to 571-M, and push-pull buffer circuits 572-1 to 572-M. A set of S / H circuit 571 and push-pull buffer circuit 572 corresponds to a column.

[0333] Furthermore, in the example shown in Figure 28, each unit S / H circuit 611 has the same configuration, and multiple unit S / H circuits 611 are arranged in a row.

[0334] Reference voltage supply circuits 563 are provided at both ends of the multiple S / H circuit units 611 arranged in the same configuration as in the example in Figure 27. Specifically, in the diagram of the multiple S / H circuit units 611, reference voltage supply circuit 563-1 is located on the right side, and reference voltage supply circuits 563-2 and 563-3 are located on the left side. Alternatively, the reference voltage supply circuits 563 may be placed on only one end of the multiple S / H circuit units 611.

[0335] The AD conversion unit 612 consists of multiple ADCs 621-1 to ADC621-M. For example, ADCs 621-1 to ADC621-M are SAR ADCs, etc. Hereafter, when there is no need to distinguish between ADCs 621-1 to ADC621-M, they will simply be referred to as ADC621.

[0336] The AD conversion unit 613 is a column ADC consisting of multiple ADCs 631-1 to ADC631-Z (where Z = M × W). For example, ADCs 631-1 to ADC631-Z consist of different types of ADCs (AD conversion circuits) than ADC 621. As an example, ADCs 631-1 to ADC631-Z may be single-slope type ADCs. Hereafter, when there is no need to distinguish between ADCs 631-1 to ADC631-Z, they will simply be referred to as ADC631.

[0337] In the example shown in Figure 28, two ADC units, an AD conversion unit 612 and an AD conversion unit 613, are provided outside the unit S / H circuit 611.

[0338] In the unit S / H circuit 611, each pixel in the pixel array section 561 is connected to the input side of the S / H circuit 571 via a vertical signal line, and the push-pull buffer circuit 572 is connected to the output side of the S / H circuit 571.

[0339] An S / H circuit 571 is connected to the input side of the push-pull buffer circuit 572, and ADCs 621 and 631 are connected to the output side of the push-pull buffer circuit 572. That is, the signal output from one push-pull buffer circuit 572 is supplied to one ADC 621 that constitutes the AD conversion unit 612 and one ADC 631 that constitutes the AD conversion unit 613. In particular, each of the multiple push-pull buffer circuits 572 within the unit S / H circuit 611 is connected to each of the different ADCs 621 and ADCs 631.

[0340] In the AD conversion unit 612, each ADC 621 is connected to a different push-pull buffer circuit 572. In particular, in this example, one ADC 621 is connected to one push-pull buffer circuit 572 in each of the W unit S / H circuits 611. That is, one ADC 621 is connected to push-pull buffer circuits 572 provided in multiple different unit S / H circuits 611. In addition, each ADC 621 is connected to all push-pull buffer circuits 582 in all of the reference voltage supply circuits 563.

[0341] In the AD conversion unit 613, each of the multiple ADCs 631 is connected to each of the multiple push-pull buffer circuits 572, each being different from the others. In particular, in this example, one push-pull buffer circuit 572 is connected to each ADC 631. Also, in this example, each ADC 631 is not connected to the push-pull buffer circuit 582 of the reference voltage supply circuit 563.

[0342] In the example shown in Figure 28, the AD conversion can be switched depending on the application, either by the AD conversion unit 612 or by the AD conversion unit 613.

[0343] For example, when performing inference using an inference model such as a neural network, if an image is captured to serve as input to the inference model, AD conversion is performed by the AD conversion unit 612.

[0344] In this case, the same operation as in the example in Figure 27 is performed. That is, the signals output from each pixel circuit (pixel) of the pixel array unit 561 are supplied to and held in the S / H circuit 571 via the vertical signal line. Also, when reading out the signal, all sets of S / H circuit 571 and push-pull buffer circuit 572 provided in one of the W unit S / H circuits 611 are designated as selection columns, and a multiplex operation is performed in which the selection columns are switched sequentially. In other words, the unit S / H circuit 611 that reads out the signal is switched sequentially.

[0345] In the selection column, the push-pull buffer circuit 572 outputs a signal voltage corresponding to the signal held in the S / H circuit 571. Then, in the AD conversion unit 612, the ADC 621 performs AD conversion of the signal voltage by comparing the signal voltage supplied from the push-pull buffer circuit 572 with the reference voltage supplied from the push-pull buffer circuit 582 of the reference voltage supply circuit 563.

[0346] In contrast, when images are captured for recording or viewing purposes, for example, the AD conversion is performed by the AD conversion unit 613. In this case, the ADC 631 performs the AD conversion of the signal voltage supplied from the push-pull buffer circuit 572.

[0347] For example, as shown in Figure 29, if the switch 176 portion of the push-pull buffer circuit 152 is composed of a combination of transistors, the control circuit 252 can supply control signals BUFSEL and X_BUFSEL to those transistors.

[0348] In the example shown in Figure 29, similar to the example in Figure 26, switch 176-1 is composed of transistors 521 and 522, and switch 176-2 is composed of transistors 523 and 524.

[0349] Furthermore, the control circuit 252 generates the control signal BUFSEL and the control signal X_BUFSEL based on the input 5-bit Gray code. The control circuit 252 supplies the control signal BUFSEL to the gates of transistor 521 and transistor 523, and supplies the control signal X_BUFSEL to the gates of transistor 522 and transistor 524.

[0350] In this example, Gray code is used to select the column that outputs the signal. Since the change in Gray code at each timing is limited to one bit, using Gray code for column selection (switching the selected column) not only suppresses fluctuations (oscillations) in the power supply and ground due to signal changes, but also keeps the fluctuations in the power supply and ground constant regardless of which column is operating.

[0351] Furthermore, when using Gray code control, it is possible to control across the chip, and the control circuit 252 can be shared among the circuits of columns that are turned on and off simultaneously. By sharing the control circuit 252, fluctuations in the power supply and ground can be kept to a minimum, and power consumption can also be reduced.

[0352] When the switch 176 has the configuration shown in Figure 29, and a control signal is supplied to the switch 176 from the control circuit 252, examples of how multiple combinations of S / H circuits 151 and push-pull buffer circuits 152 are arranged in a CMOS image sensor can be considered, as shown in Figures 30 and 31.

[0353] Note that in the examples shown in Figures 30 and 31, the attenuation circuit 153 is not shown, but it may or may not be provided. Also, in Figures 30 and 31, some reference numerals have been omitted for clarity.

[0354] The example shown in Figure 30 is an example of a column ADC configuration. Specifically, the CMOS image sensor shown in Figure 30 has a pixel array section 561, unit AD circuits 562-1 to 562-K, and reference voltage supply circuits 563-1 to 563-3.

[0355] In this example, the arrangement and connection relationships of the pixel array section 561, the unit AD circuit 562, and the reference voltage supply circuit 563 are the same as those in the example shown in Figure 27. The example shown in Figure 30 differs from the example shown in Figure 27 only in that a control circuit corresponding to the control circuit 252 is provided within the push-pull buffer circuit 572.

[0356] The AD unit 562-1 includes S / H circuits 571-1 to 571-M, push-pull buffer circuits 572-1 to 572-M, and an ADC 573. The connection relationships of the S / H circuit 571, push-pull buffer circuit 572, and ADC 573 in the AD unit 562-1 are the same as in the example in Figure 27.

[0357] Push-pull buffer circuits 572-1 to 572-M are provided with control circuits 671-1 to 671-M, which correspond to control circuit 252. Hereafter, unless there is a need to distinguish between control circuits 671-1 to 671-M, they will simply be referred to as control circuit 671.

[0358] In this example, the push-pull buffer circuit 572 is also provided with a control circuit 671 in addition to the configuration shown in Figure 5. The control circuit 671 generates the control signal BUFSEL and the control signal X_BUFSEL based on the supplied Gray code and supplies them to the switch 176.

[0359] The AD units 562-2 through 562-K have the same configuration as AD unit 562-1.

[0360] In the example shown in Figure 30, the control circuits 671 of each push-pull buffer circuit 572 are not shared due to their placement. Also, all control circuits 671 in all unit AD circuits 562 are connected to the same signal line, and a 2-bit Gray code is supplied to all control circuits 671 via that signal line. Each control circuit 671 generates a control signal BUFSEL and a control signal X_BUFSEL based on the supplied Gray code.

[0361] Although not shown in the illustration, in the example of Figure 30, the CMOS image sensor is also provided with a REF control circuit, which is connected to all push-pull buffer circuits 582 of the entire reference voltage supply circuit 563 via a single signal line. Based on the supplied 1-bit Gray code, the REF control circuit generates a control signal to control the switch of the push-pull buffer circuit 582 corresponding to the switch 176, and supplies that control signal to the switch of each push-pull buffer circuit 582.

[0362] The example shown in Figure 31 is a big-little configuration.

[0363] The CMOS image sensor shown in Figure 31 includes a pixel array section 561, unit S / H circuits 611-1 to 611-W, reference voltage supply circuits 563-1 to 563-3, an AD conversion section 612, and an AD conversion section 613.

[0364] Note that in Figure 31, the AD conversion unit 613 is omitted from the illustration for clarity. Also, in this example, the arrangement and connection relationships of the pixel array unit 561, unit S / H circuit 611, reference voltage supply circuit 563, AD conversion unit 612, and AD conversion unit 613 are the same as those shown in Figure 28.

[0365] The example shown in Figure 31 differs from the example shown in Figure 28 only in that each unit S / H circuit 611 is provided with a control circuit corresponding to the control circuit 252.

[0366] The S / H circuit unit 611-1 includes S / H circuits 571-1 to 571-M, push-pull buffer circuits 572-1 to 572-M, and a control circuit 701. The connection relationships between each S / H circuit 571 and push-pull buffer circuit 572 in the S / H circuit unit 611-1 are the same as in the example in Figure 28.

[0367] The unit S / H circuit 611-1 is provided with a common control circuit 701 for all push-pull buffer circuits 572 within that unit S / H circuit 611. The control circuit 701 corresponds to the control circuit 252 shown in Figure 29, and generates the control signal BUFSEL and the control signal X_BUFSEL based on the supplied 5-bit Gray code, and supplies them to the switch 176 of each push-pull buffer circuit 572.

[0368] Unit S / H circuits 611-2 to 611-W have the same configuration as unit S / H circuit 611-1.

[0369] In the example shown in Figure 31, the Gray code for column selection, i.e., the Gray code for generating control signals such as BUFSEL, is supplied to the control circuit 701 of each unit S / H circuit 611 via the same signal line.

[0370] <Regarding power reduction through intermittent operation of Load MOS> When an intermittent push-pull buffered S / H circuit 92, as shown in Figure 5, is provided in a CMOS image sensor, it is possible to reduce power consumption by providing a Load MOS on the vertical signal to which the pixel circuit is connected, or more specifically, between the vertical signal and ground, and by making the Load MOS operate intermittently.

[0371] In such cases, it is conceivable to configure a part of the CMOS image sensor as shown in Figure 32, for example. In Figure 32, the same reference numerals are used for parts corresponding to those in Figure 5, and their explanations are omitted as appropriate. Also, although the attenuation circuit 153 is not shown in Figure 32, the attenuation circuit 153 may or may not be provided.

[0372] In the example shown in Figure 32, the CMOS image sensor is provided with a pixel circuit 741 that constitutes a pixel, a multiplexer circuit 742, a switch 743, a transistor 744, a vertical signal line 745, an S / H circuit 151, and a push-pull buffer circuit 152.

[0373] The pixel circuit 741 is connected to the vertical signal line 745 and includes a photodiode 811 as a photoelectric conversion element, a transfer transistor 812, an FD (Floating Diffusion) 813, a reset transistor 814, an amplification transistor 815, and a selection transistor 816.

[0374] The photodiode 811 converts light incident from an external source into photoelectricity, generating an electric charge (signal charge) corresponding to the amount of light received, and stores the generated charge. The photodiode 811 is connected to the FD 813 via a transfer transistor 812.

[0375] When the transfer transistor 812 is turned on by a control signal supplied to its gate, it transfers the charge stored in the photodiode 811 to the FD 813.

[0376] FD813 holds the charge transferred from photodiode 811. When reset transistor 814 is turned on by the supplied control signal, it resets the potential of FD813 by discharging the charge stored in FD813 to a constant voltage source.

[0377] The amplifying transistor 815 forms a source follower circuit with transistor 744, which is a constant current source connected via the vertical signal line 745, and outputs a signal corresponding to the potential of FD 813. That is, the amplifying transistor 815 outputs a signal indicating a level corresponding to the charge stored in FD 813 to the vertical signal line 745 via the selecting transistor 816.

[0378] The selection transistor 816 is turned on by the control signal. When the selection transistor 816 is turned on, the pixel is set to a selected state, and a signal is output from the amplification transistor 815 to the vertical signal line 745 via the selection transistor 816.

[0379] A multiplexer circuit 742 is located on the vertical signal line 745. For example, the multiplexer circuit 742 is connected to multiple vertical signal lines 745 and outputs the signal supplied from the pixel circuit 741 via one of these multiple vertical signal lines 745. Note that the multiplexer circuit 742 is not necessarily required.

[0380] The vertical signal line 745 is connected to the input terminal IP11 of the S / H circuit 92 with an intermittently operating push-pull buffer, i.e., the S / H circuit 151. Therefore, in this example, the signals output from the pixel circuit 741, i.e., the P-phase signal and D-phase signal, are supplied to the S / H circuit 151 via the multiplexer circuit 742 on the vertical signal line 745.

[0381] Furthermore, a switch 743 is connected to the vertical signal line 745, and a transistor 744 is provided between the switch 743 and ground.

[0382] Switch 743 is located between the vertical signal line 745 and the transistor 744, and controls the electrical connection between the transistor 744 and the vertical signal line 745 by turning it on and off in response to the control signal LM_Enable. In other words, switch 743 functions as a current control switch that controls whether or not a constant current flows through the vertical signal line 745 (transistor 744).

[0383] Transistor 744 is an NMOS transistor and functions as a current source circuit, or Load MOS, for supplying a constant current to the vertical signal line 745 in response to the drive of switch 743.

[0384] In the example shown in Figure 32, for example, the switch 743 is basically turned ON, and the vertical signal line 745 and the transistor 744 are electrically connected. In this state, a current I for source follower operation flows from the vertical signal line 745 through the transistor 744 to the ground. LM A constant current flows.

[0385] In contrast, when the signal output from the pixel circuit 741 is held (held) by the S / H circuit 151, current I is supplied to the vertical signal line 745. LM Since there is no need to run the current, switch 743 is turned off, and power consumption is reduced.

[0386] Please refer to Figure 33 for a specific example of operation.

[0387] In Figure 33, the horizontal axis represents time, and the vertical axis represents potential (voltage level). In Figure 33, the broken line L51 represents the control signal LM_Enable, and the curve L52 represents the potential of the vertical signal line 745, i.e., the input terminal IP11, at each time point.

[0388] Lines L53, L54, and L55 represent the control signals BIAS_EN, SAMPLE_EN, and BUFSEL, respectively. In particular, the upward-curving portions in the diagrams for each control signal indicate the H level.

[0389] Curve L56 shows the voltage level of the signal output from output terminal OP11, i.e., the potential of output terminal OP11. The section indicated by arrow Q51 shows the amount of current consumed at each time in the intermittently operating push-pull buffered S / H circuit 92, and the section indicated by arrow Q52 shows the amount of current consumed at each time in the transistor 744 (Load MOS) section.

[0390] In the example shown in Figure 33, the operation of the intermittently operating push-pull buffered S / H circuit 92 is the same as in the example shown in Figure 9. That is, the operation at times t71 to t73, t75 to t78, t80, and t81 in Figure 33 is the same as the operation at times t21 to t29 in Figure 9.

[0391] Furthermore, focusing on switch 743, at time t71, which is the start of the P-phase settling period, the control signal LM_Enable is set to the H level, and switch 743 is turned ON.

[0392] Then, at time t73, the signal is sampled, or sampled and held, by the S / H circuit 151. Subsequently, at time t74, the control signal LM_Enable is set to the L level, and the switch 743 is turned off.

[0393] Furthermore, at time t77, when the control signal SAMPLE_EN is set to the H level and the input of the signal from the pixel circuit 741 to the S / H circuit 151 begins, the control signal LM_Enable is set to the H level and switch 743 is turned on. Subsequently, similar to the case at time t74, at time t79 the control signal LM_Enable is set to the L level and switch 743 is turned off.

[0394] When the drive shown in Figure 33 is performed, the power consumption (current consumption) of the intermittent push-pull buffered S / H circuit 92 indicated by arrow Q51 is the same as in the example shown in Figure 9.

[0395] Focusing on the current consumption in the Load MOS section indicated by arrow Q52, the current I is always present between time t71 and time t74, and between time t77 and time t79. LM A current flows. However, between time t74 and time t77, and during the period from time t79 onwards, switch 743 is turned off, so current I LM No current flows. In other words, the amount of current consumed can be set to zero, and overall, power consumption can be reduced compared to when the switch 743 is not provided.

[0396] The intermittently operating push-pull buffered S / H circuit 92 has a sample-and-hold function, so when a signal is read (input) into the S / H circuit 151 and switch 161 is off, current I is supplied to the vertical signal line 745. LM There's no need to leave it running.

[0397] Therefore, in the example shown in Figure 32, a switch 743 is provided between the vertical signal line 745 and the transistor 744, and the switch 743 enables intermittent operation of the transistor 744 (Load MOS). By making the transistor 744 operate intermittently with the switch 743, current I is supplied only for the required period. LM Current control can be performed to allow the current to flow smoothly, thereby reducing power consumption. In other words, low power consumption can be achieved.

[0398] <Third Embodiment> When multiple combinations of S / H circuits and push-pull buffer circuits are arranged in a CMOS image sensor, for example, a configuration like the one shown in Figure 34 can be considered.

[0399] In the example shown in Figure 34, the CMOS image sensor includes an S / H circuit 841, a push-pull buffer circuit 842, S / H circuits 843-1 to 843-n, a push-pull buffer circuit 844-1 to 844-n, and an ADC 845.

[0400] In the following, when there is no need to distinguish between S / H circuits 843-1 to 843-n, they will simply be referred to as S / H circuit 843. Similarly, when there is no need to distinguish between push-pull buffer circuits 844-1 to 844-n, they will simply be referred to as push-pull buffer circuit 844.

[0401] S / H circuits 841 and 843 correspond to the S / H circuit 151 described above. Push-pull buffer circuits 842 and 844 correspond to the portion of the intermittently operating push-pull buffered S / H circuit 92 described above that consists of the push-pull buffer circuit 152 and the attenuation circuit 153. Furthermore, ADC 845 is an AD conversion circuit corresponding to the ADC 251 described above.

[0402] In this example, ground (GND) is connected to the input side of S / H circuit 841, and each of the input sides of S / H circuits 843-1 to 843-n is connected to a pixel circuit (pixel) via different vertical signal lines.

[0403] The S / H circuit 841 samples and holds the ground voltage level (a signal indicating the voltage level) in response to the supplied control signal SAMPLE_EN. The push-pull buffer circuit 842 outputs (supplies) a reference voltage (reference signal) corresponding to the signal (voltage level) held by the S / H circuit 841 to the ADC 845, particularly to the reference input terminal of the ADC 845.

[0404] The S / H circuit 843 samples and holds the signal supplied from the pixel circuit via the vertical signal line in accordance with the supplied control signal SAMPLE_EN. The push-pull buffer circuit 844 outputs (supplies) a signal voltage to the ADC 845 corresponding to the signal (voltage level) held by the S / H circuit 843.

[0405] In this example, n push-pull buffer circuits 844 are connected to the signal input terminal of the ADC 845. The CMOS image sensor is controlled so that, at a predetermined timing, the signal voltage from one of these n push-pull buffer circuits 844 is supplied to the ADC 845.

[0406] The ADC 845 consists of an A / D conversion circuit, such as a SAR ADC. The ADC 845 performs A / D conversion of the signal voltage based on the signal voltage supplied from the push-pull buffer circuit 844 and the reference voltage supplied from the push-pull buffer circuit 842, and outputs the resulting digital signal to the next stage.

[0407] In this example, the push-pull buffer circuits 842 and 844 have the same configuration, and the reference voltage signal and the pixel signal (signal voltage) are transmitted to the ADC 845 through these identical circuits. Therefore, power supply noise originating from the power supply that provides the bias voltage to the push-pull buffer circuits 842 and 844 can be removed (canceled) by the common-mode rejection function in the ADC 845.

[0408] On the other hand, when sampling the signal output from the pixel circuit, the power supply noise superimposed on the signal from that pixel circuit affects the signal column, i.e., the column having the S / H circuit 843 and the push-pull buffer circuit 844. In other words, the signal transmitted in the signal column is affected by the power supply noise. However, this power supply noise does not affect the reference column, i.e., the column having the S / H circuit 841 and the push-pull buffer circuit 842. Therefore, in the configuration of Figure 34, there is a risk that the PSRR (Power Supply Rejection Ratio) characteristics of the pixels will deteriorate.

[0409] Therefore, in this technology, by configuring the output of the pixel circuit of a light-shielded pixel, in which the light-receiving surface, i.e., the photoelectric conversion element (photoelectric conversion unit) that performs photoelectric conversion, is shielded from light, the degradation of the PSRR characteristics is suppressed, and better imaging characteristics with lower noise are achieved.

[0410] For example, a light-shielding pixel connected to an ADC is a light-shielding pixel located in the HOPB region, which is adjacent to the effective pixel region in the left-right direction, i.e., in the row direction, with respect to pixels whose light-receiving surface is not shielded (hereinafter also referred to as normal pixels).

[0411] In the following, light-shielding pixels located in the HOPB region will also be referred to as HOPB pixels. For example, the pixel circuit of a normal pixel and the pixel circuit of a HOPB pixel have basically the same configuration, differing only in whether or not the light-receiving surface is shielded from light. Furthermore, in the following, light-shielding pixels located in the VOPB region, which is adjacent to the effective pixel region in the vertical direction, i.e., in the column direction, will also be referred to as VOPB pixels.

[0412] <Example 1 of the Configuration of a CMOS Image Sensor> When this technology is applied to a CMOS image sensor, the configuration of a part of the CMOS image sensor, that is, the readout circuit part that reads out signals from pixel circuits, is as shown in, for example, FIG. 35. In FIG. 35, the parts corresponding to those in FIG. 34 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0413] In the example shown in FIG. 35, the CMOS image sensor 871 includes a power supply noise cancellation signal generation unit 881, an S / H circuit 841, a push-pull buffer circuit 842, an S / H circuit 882, a push-pull buffer circuit 883, S / H circuits 843-1 to S / H circuits 843-n, push-pull buffer circuits 844-1 to push-pull buffer circuits 844-n, and an ADC 845.

[0414] In this example, the power supply noise cancellation signal generation unit 881 is connected to the terminal on the reference input side of the ADC 845 via the S / H circuit 84 and the push-pull buffer circuit 842.

[0415] Also, the pixel circuit of the HOPB pixel is connected to the terminal on the signal input side of the ADC 845 via the S / H circuit 882 and the push-pull buffer circuit 883, and the pixel circuits of n normal pixels are connected to the terminal on the signal input side of the ADC 845 via the vertical signal line, the S / H circuit 843, and the push-pull buffer circuit 884.

[0416] The S / H circuit 882 corresponds to the above-described S / H circuit 151, and the push-pull buffer circuit 883 corresponds to the part including the push-pull buffer circuit 152 and the attenuation circuit 153 in the above-described S / H circuit with an intermittent operation push-pull buffer 92.

[0417] Incidentally, the push-pull buffer circuits 842, 844, and 883 may be configured without an attenuation circuit. That is, the push-pull buffer circuits 842, 844, and 883 may be the push-pull buffer circuit 152 itself.

[0418] The power supply noise cancellation signal generation unit 881 is connected to the pixel power supply to which the pixel circuits of the normal pixels and the pixel circuits of the HOPB pixels are connected. That is, the normal pixels, the HOPB pixels, and the power supply noise cancellation signal generation unit 881 are connected to the same pixel power supply. The power supply noise cancellation signal generation unit 881 generates a power supply noise cancellation signal based on the voltage (power supply voltage) supplied from the pixel power supply, and supplies it to the S / H circuit 841.

[0419] For example, the power supply noise cancellation signal is a signal for canceling the power supply noise caused by the pixel power supply that occurs in the pixel circuits of the normal pixels and the pixel circuits of the HOPB pixels. In other words, the power supply noise cancellation signal is the predicted result of the power supply noise caused by the pixel power supply that would occur in the normal pixels and the HOPB pixels.

[0420] In this example, the power supply noise cancellation signal generated by the power supply noise cancellation signal generation unit 881 is sampled and held by the S / H circuit 841, and the power supply noise cancellation signal held by the S / H circuit 841 is supplied to the terminal on the reference input side of the ADC 845 by the push-pull buffer circuit 842. In this case, the power supply noise cancellation signal is used as the reference voltage (reference signal) for AD conversion.

[0421] The S / H circuit 882 samples and holds the signal supplied from the pixel circuit of the HOPB pixel via the vertical signal line in response to the supplied control signal SAMPLE_EN. The push-pull buffer circuit 883 outputs (supplies) a signal voltage corresponding to the signal (voltage level) held by the S / H circuit 882 to the terminal on the signal input side of the ADC 845.

[0422] In this example, one push-pull buffer circuit 883 and n push-pull buffer circuits 844 are connected to the signal input terminal of the ADC 845. The CMOS image sensor 871 is controlled so that, at a predetermined timing, a signal voltage from one of these push-pull buffer circuits 883 and 844 is supplied to the ADC 845.

[0423] The ADC 845 performs AD conversion of the signal voltage based on the signal voltage supplied from the push-pull buffer circuit 883 or push-pull buffer circuit 844 and the reference voltage (power supply noise cancellation signal voltage) supplied from the push-pull buffer circuit 842, and outputs the resulting digital signal to the next stage. More specifically, the ADC 845 obtains a digital signal value by performing AD conversion on the difference between the signal voltage input from the signal input terminal and the reference voltage input from the reference input terminal.

[0424] In the CMOS image sensor 871 described above, the push-pull buffer circuits 842, 844, and 883 have the same circuit configuration. Therefore, in the CMOS image sensor 871, as in the case shown in Figure 34, power supply noise caused by the power supply for supplying the bias voltage can be removed by the common-mode rejection action of the ADC 845.

[0425] Furthermore, in the CMOS image sensor 871, the power supply noise cancellation signal generation unit 881 is connected to the same pixel power supply as the normal pixels and HOPB pixels, and generates a power supply noise cancellation signal equivalent to the power supply noise caused by the pixel power supply, which is superimposed on the signals obtained from those normal pixels and HOPB pixels. This power supply noise cancellation signal is sampled in a reference column having an S / H circuit 841 and a push-pull buffer circuit 842 and input to the ADC 845, so that the power supply noise generated in the normal pixels and HOPB pixels can be removed by common-mode rejection in the ADC 845. As a result, good noise characteristics can be obtained. In other words, the deterioration of the PSRR characteristics can be suppressed.

[0426] <Example of CMOS Image Sensor Configuration 2> In the example shown in Figure 35, the CMOS image sensor 871 is equipped with a power supply noise cancellation signal generation unit 881. The circuitry constituting this power supply noise cancellation signal generation unit 881 is relatively large in area, and the power consumption of the power supply noise cancellation signal generation unit 881 is not insignificant.

[0427] Therefore, for example, as shown in Figure 36, a configuration in which HOPB pixels are connected to a reference column having an S / H circuit 841 and a push-pull buffer circuit 842 may be used to achieve miniaturization of the CMOS image sensor and reduction of power consumption. In Figure 36, parts corresponding to those in Figure 34 or Figure 32 are denoted by the same reference numerals, and their explanations are omitted as appropriate.

[0428] Figure 36 shows the configuration of a part of a CMOS image sensor, namely a part including a pixel circuit and a readout circuit that reads signals from the pixel circuit. The CMOS image sensor 901 shown in Figure 36 has a HOPB pixel 911, an S / H circuit 841, a push-pull buffer circuit 842, normal pixels 912-1 to 912-n, S / H circuits 843-1 to 843-n, push-pull buffer circuits 844-1 to 844-n, and an ADC 845.

[0429] For the sake of simplicity, only one column of the HOPB pixel 911 and the reference column consisting of the S / H circuit 841 and the push-pull buffer circuit 842 is shown in this diagram. However, in more detail, the CMOS image sensor 901 is provided with multiple HOPB pixels 911 and reference columns, taking into account the lateral noise characteristics.

[0430] The HOPB pixel 911 includes a photodiode 941 as a photoelectric conversion element, a transfer transistor 942, an FD 943, a reset transistor 944, an amplification transistor 945, and a selection transistor 946 as components of the pixel circuit. The selection transistor 946 is also connected to the S / H circuit 841 via a vertical signal line.

[0431] The photodiodes 941 to the selection transistor 946 that constitute the HOPB pixel 911 correspond to the photodiodes 811 to the selection transistor 816 shown in Figure 32, and they operate in the same manner as those photodiodes 811 to the selection transistor 816. However, in the HOPB pixel 911, the light-receiving surface of the photodiode 941, which is the photoelectric conversion unit (photoelectric conversion element), is shielded from light, so no external light is incident on the photodiode 941.

[0432] The normal pixels 912-1 to 912-n correspond to pixels having the pixel circuit 741 shown in Figure 32, and are connected to S / H circuits 843-1 to 843-n via different vertical signal lines. Hereafter, when there is no need to distinguish between normal pixels 912-1 to 912-n, they will simply be referred to as normal pixels 912.

[0433] Each normal pixel 912 has a photodiode 811, a transfer transistor 812, an FD 813, a reset transistor 814, an amplification transistor 815, and a selection transistor 816 as components of the pixel circuit.

[0434] In the CMOS image sensor 901, the HOPB pixel 911 is connected to the reference input terminal of the ADC 845 via a vertical signal line, an S / H circuit 841, and a push-pull buffer circuit 842. That is, a signal voltage corresponding to the signal output from the HOPB pixel 911 is supplied to the ADC 845 as a reference voltage (reference signal).

[0435] Specifically, the S / H circuit 841 holds the signal output from the HOPB pixel 911 as a reference signal, and the push-pull buffer circuit 842 supplies the reference signal held by the S / H circuit 841 to the ADC 845.

[0436] Furthermore, each of the n normal pixels 912 is connected to the signal input terminal of the ADC 845 via a vertical signal line, an S / H circuit 843, and a push-pull buffer circuit 844. In particular, the CMOS image sensor 901 is controlled so that, at a predetermined timing, the signal voltage from one of these n push-pull buffer circuits 844 is supplied to the ADC 845.

[0437] In other words, a signal voltage corresponding to the signal output from any one of the multiple normal pixels 912 connected to each of the multiple vertical signal lines is supplied to the ADC 845. Specifically, the S / H circuit 843 holds the signal output from the normal pixel 912, and the push-pull buffer circuit 844 outputs a signal corresponding to the signal held by the S / H circuit 843, thereby supplying the signal from the normal pixel 912 to the ADC 845.

[0438] The ADC 845 performs AD conversion of the signal voltage corresponding to the signal from the normal pixel 912 based on the signal voltage supplied from the push-pull buffer circuit 844 and the signal voltage corresponding to the signal from the HOPB pixel 911 supplied from the push-pull buffer circuit 842, and outputs the resulting digital signal to the next stage. More specifically, the ADC 845 performs AD conversion of the difference between the signal voltage input from the signal input terminal and the reference voltage input from the reference input terminal corresponding to the signal from the HOPB pixel 911, and obtains a digital signal value.

[0439] In the CMOS image sensor 901, during imaging, i.e., when reading signals from the normal pixels 912, a control signal SAMPLE_EN, such as the broken line L71 in Figure 37, is supplied to the S / H circuits 841 and 843, and the P-phase signal and D-phase signal are read out. In Figure 37, the horizontal direction represents time, and the vertical direction represents potential (voltage level).

[0440] In the example shown in Figure 37, curve L72 represents the vertical signal line at each time step, i.e., the potential of the input terminal in the S / H circuit 843. When the P-phase and D-phase signals are read out in this manner, the degradation of the PSRR characteristics can be suppressed by the common-mode noise rejection function in the ADC 845. This is because the HOPB pixel 911 and the normal pixel 912 are connected to the same pixel power supply, and these pixels are connected to the ADC 845.

[0441] In other words, by using the signal from the HOPB pixel 911 as the input to the reference input terminal of the ADC 845, a black level reference signal including errors caused by the pixel power supply (PSRR-induced errors) can be maintained by simultaneous sampling of all columns of the P-phase and D-phase signals. In other words, the signal from the HOPB pixel 911 can be maintained as a black level reference signal.

[0442] The error contained in this reference signal can be considered to be in-mode noise with the error (PSRR-induced error) contained in the signal of the normal pixel 912. Therefore, the PSRR-induced error is compressed by the common-mode noise rejection characteristics of the ADC 845 (AD conversion). In other words, the PSRR-induced error can be corrected. In particular, since the circuit configuration from the normal pixel 912 to the signal input terminal and the circuit configuration from the HOPB pixel 911 to the reference input terminal are the same, the error can be compressed with higher precision.

[0443] Specifically, when reading out the P-phase signal, as shown by arrow Q71, both the signal voltage of the normal pixel 912 supplied to the signal input terminal of the ADC 845 and the signal voltage of the HOPB pixel 911 supplied to the reference input terminal of the ADC 845 contain power supply noise (errors caused by PSRR) originating from the same pixel power supply. Therefore, this power supply noise is removed by the common-mode noise rejection function during AD conversion in the ADC 845.

[0444] Similarly, when reading out the D-phase signal, as shown by arrow Q72, the signal voltage of the normal pixel 912 supplied to the signal input terminal of the ADC 845 contains power supply noise originating from the pixel power supply. Also, as shown by arrow Q73, the signal voltage of the HOPB pixel 911 supplied to the reference input terminal of the ADC 845 contains the same power supply noise originating from the pixel power supply as the normal pixel 912. Therefore, this power supply noise is removed by the common-mode noise rejection function during AD conversion in the ADC 845.

[0445] In this way, by connecting the normal pixel 912 to the signal input terminal of the ADC 845 and the HOPB pixel 911 to the reference input terminal of the ADC 845, and using the signal voltage of the HOPB pixel 911 as the reference voltage during AD conversion, it is possible to achieve a correction effect for errors caused by PSRR. In other words, the degradation of the PSRR characteristics can be suppressed.

[0446] Furthermore, in the CMOS image sensor 901, the push-pull buffer circuits 842 and 844 have the same circuit configuration as in the CMOS image sensor 871. Therefore, power supply noise caused by the power supply for supplying the bias voltage can be removed by the common-mode rejection function in the ADC 845.

[0447] Figure 38 shows a more detailed configuration example of the normal pixels 912, S / H circuit 843, and push-pull buffer circuit 844 in the CMOS image sensor 901. In Figure 38, parts corresponding to those in Figure 36 or Figure 5 are denoted by the same reference numerals, and their explanations are omitted as appropriate.

[0448] In the example shown in Figure 38, the S / H circuit 843 has a switch 161 and a capacitor 162, similar to the S / H circuit 151 shown in Figure 5. The end of the switch 161 opposite to the capacitor 162 is connected to the selection transistor 816 of the normal pixel 912 via the input terminal IP11 and the vertical signal line (VSL).

[0449] Also, a capacitor 162 and a push-pull buffer circuit 844 are connected to the end of the switch 161 on the side opposite to the input terminal IP11 side.

[0450] The push-pull buffer circuit 844 has a push-pull buffer circuit 152 and an attenuation circuit 153.

[0451] The push-pull buffer circuit 152 has, as in the case of FIG. 5, switches 171-1, 171-2, capacitors 172-1, 172-2, capacitors 173-1, 173-2, transistors 174, 175, switches 176-1, 176-2, transistor 177, and switch 178.

[0452] Also, an output terminal OP11 is connected between the switch 176-1 and the switch 176-2, and this output terminal OP11 is connected to the signal input side terminal of the ADC 845. The push-pull buffer circuit 152 outputs a signal with a voltage level corresponding to the signal held in the S / H circuit 843 from the output terminal OP11 and supplies it to the ADC 845.

[0453] The attenuation circuit 153 is provided between the S / H circuit 843 and the push-pull buffer circuit 152, and realizes an attenuation function for attenuating the signal output from the push-pull buffer circuit 152 (output terminal OP11).

[0454] The attenuation circuit 153 has, as in the case of FIG. 5, capacitors 172-1, 172-2, switches 181-1, 182-1, capacitors 173-1, 173-2, switches 181-2, and switches 182-2.

[0455] In particular, the capacitor 172-1, switch 181-1, switch 181-2, and capacitor 173-1 in the attenuation circuit 153 are connected to the switch 161 and the capacitor 162 of the S / H circuit 843.

[0456] Figure 39 shows a more detailed configuration example of the HOPB pixel 911, S / H circuit 841, and push-pull buffer circuit 842 in the CMOS image sensor 901. In Figure 39, parts corresponding to those in Figure 36 are denoted by the same reference numerals, and their explanations are omitted as appropriate.

[0457] In the example shown in Figure 39, the S / H circuit 841 has a switch 971 and a capacitor 972. These switches 971 and capacitor 972 correspond to the switches 161 and capacitor 162 in the S / H circuit 843. That is, the S / H circuit 841 has the same configuration as the S / H circuit 843 and operates in the same way as the S / H circuit 843 in response to the control signal SAMPLE_EN supplied to the switch 971.

[0458] The end of switch 971 opposite to the capacitor 972 is connected to the input terminal IP31 and the vertical signal line (VSL) to the selection transistor 946 of the HOPB pixel 911. The other end of switch 971 opposite to the input terminal IP31 is connected to the capacitor 972 and the push-pull buffer circuit 842.

[0459] The push-pull buffer circuit 842 includes a push-pull buffer circuit 981 and an attenuation circuit 982. These push-pull buffer circuits 981 and attenuation circuits 982 have the same configuration as the push-pull buffer circuit 152 and attenuation circuit 153 shown in Figure 38, and perform the same operation as those push-pull buffer circuits 152 and attenuation circuits 153.

[0460] In other words, the push-pull buffer circuit 981 includes switches 991-1 and 991-2, capacitors 992-1 and 992-2, capacitors 993-1 and 993-2, transistors 994 and 995, switches 996-1 and 996-2, transistor 997, and switch 998.

[0461] These switches 991-1 to 998 correspond to the switches 171-1 to 178 shown in Figure 38, and perform the same operations as those switches 171-1 to 178.

[0462] In particular, switch 991-1 is connected to a reference bias circuit (not shown) via terminal IP32. Switch 991-1 is supplied with a bias voltage NGTE_BIAS from the reference bias circuit via terminal IP32. Similarly, switch 991-2 is connected to a reference bias circuit (not shown) via terminal IP33. Switch 991-2 is supplied with a bias voltage PGTE_BIAS from the reference bias circuit via terminal IP33.

[0463] Hereafter, unless there is a need to distinguish between switches 991-1 and 991-2, they will simply be referred to as switch 991. Switch 991 turns on and off in response to the supplied control signal BIAS_EN, and controls the sampling of the bias voltage supplied from the reference bias circuit.

[0464] Furthermore, an output terminal OP31 is connected between switch 996-1 and switch 996-2, and this output terminal OP31 is connected to the reference input terminal of the ADC 845. Switches 996-1 and 996-2 are switched on and off in response to the supplied control signal REF_SEL, and function as switches for intermittent operation control, i.e., switches for intermittent signal output from the push-pull buffer circuit 981.

[0465] Hereafter, when there is no need to distinguish between switches 996-1 and 996-2, they will simply be referred to as switch 996. Furthermore, hereafter, when there is no need to distinguish between capacitors 992-1 and 992-2, they will simply be referred to as capacitor 992, and when there is no need to distinguish between capacitors 993-1 and 993-2, they will simply be referred to as capacitor 993.

[0466] The push-pull buffer circuit 981 outputs a signal with a voltage level corresponding to the signal held by the S / H circuit 841 from the output terminal OP31 and supplies it to the ADC 845.

[0467] The attenuation circuit 982 is located between the S / H circuit 841 and the push-pull buffer circuit 981, and provides an attenuation function that reduces the signal output from the push-pull buffer circuit 981 (output terminal OP31).

[0468] The attenuation circuit 982 includes capacitors 992-1 and 992-2, switch 1001-1, switch 1002-1, capacitor 993-1, capacitor 993-2, switch 1001-2, and switch 1002-2.

[0469] These capacitors 992-1 and switch 1002-2 correspond to the capacitors 172-1 and switch 182-2 shown in Figure 38, and perform the same operation as those capacitors 172-1 and switch 182-2.

[0470] In particular, capacitor 992-1, switch 1001-1, switch 1001-2, and capacitor 993-1 in the attenuation circuit 982 are connected to switch 971 and capacitor 972 in the S / H circuit 841.

[0471] Hereinafter, when there is no need to distinguish between switch 1001-1 and switch 1001-2, they will simply be referred to as switch 1001, and when there is no need to distinguish between switch 1002-1 and switch 1002-2, they will simply be referred to as switch 1002.

[0472] <Modified Configuration of CMOS Image Sensor> The CMOS image sensor 901 can also be configured as shown in Figures 40 to 42, for example. In Figures 40 to 42, the same reference numerals are used for parts corresponding to those in Figure 36, and their explanations are omitted as appropriate.

[0473] Furthermore, in Figures 40 to 42, the HOPB pixels 911 and normal pixels 912 are omitted from the illustration for clarity. Note that, as in the example in Figure 36, the HOPB pixels 911 are connected to the S / H circuit 841, and the normal pixels 912 are connected to the S / H circuit 843.

[0474] In the example shown in Figure 40, the CMOS image sensor 901 is further equipped with a gain adjustment unit 1031 in addition to the configuration shown in Figure 36. In particular, in this example, the gain adjustment unit 1031 is provided between the S / H circuit 841 and the push-pull buffer circuit 842.

[0475] The gain adjustment unit 1031 adjusts the gain of the signal voltage (reference signal) corresponding to the signal from the HOPB pixel 911, which is supplied from the S / H circuit 841, particularly from the capacitor 972 of the S / H circuit 841, based on a predetermined gain value. In other words, the gain adjustment unit 1031 amplifies or attenuates the signal voltage according to the predetermined gain value. The gain adjustment unit 1031 supplies the signal voltage (reference signal) after gain adjustment to the attenuation circuit 982 of the push-pull buffer circuit 842.

[0476] For example, the gain adjustment amount, i.e., the gain value, in the gain adjustment unit 1031 is a fixed value determined in advance by measurement or the like.

[0477] In the example shown in Figure 41, n normal pixels 912, i.e., n signal columns, are divided into two, and an ADC is provided for each of these divided signal columns.

[0478] Specifically, in this example, the CMOS image sensor 901 is equipped with an ADC 1061 in addition to the ADC 845. Like the ADC 845, the ADC 1061 consists of an AD conversion circuit such as a SAR ADC.

[0479] Furthermore, the n signal columns are divided into two groups of signal columns.

[0480] The first group of signal columns (hereinafter also referred to as the first group of signal columns) consists of n / 2 signal columns, from a signal column having an S / H circuit 843-1 and a push-pull buffer circuit 844-1 to a signal column having an S / H circuit 843-n / 2 and a push-pull buffer circuit 844-n / 2.

[0481] In contrast, the second group of signal columns (hereinafter also referred to as the second group of signal columns) consists of n / 2 signal columns, ranging from a signal column having an S / H circuit 843-n / 2+1 and a push-pull buffer circuit 844-n / 2+1 to a signal column having an S / H circuit 843-n and a push-pull buffer circuit 844-n.

[0482] The signal input terminal of the ADC 845 is connected to the push-pull buffer circuit 844 for each of the n / 2 signal columns belonging to the first signal column group, and the reference input terminal of the ADC 845 is connected to the push-pull buffer circuit 842 for the reference column. Therefore, the ADC 845 performs AD conversion of the signals obtained in the normal pixels 912 corresponding to the signal columns belonging to the first signal column group.

[0483] The signal input terminal of the ADC 1061 is connected to the push-pull buffer circuit 844 for each of the n / 2 signal columns belonging to the second signal column group, and the reference input terminal of the ADC 1061 is connected to the push-pull buffer circuit 842 for the reference column. Therefore, the ADC 1061 performs AD conversion of the signals obtained in the normal pixels 912 corresponding to the signal columns belonging to the second signal column group.

[0484] Thus, ADC 845 and ADC 1061 are connected to different push-pull buffer circuits 844, and ADC 845 and ADC 1061 are connected to the same push-pull buffer circuit 842.

[0485] By dividing n signal columns into multiple signal column groups and providing an ADC for each signal column group, AD conversion can be performed on multiple signal columns simultaneously, thereby achieving faster processing. While this example describes a case where the signal column group is divided into two, the number of divisions can be any number of three or more.

[0486] In each configuration example of the CMOS image sensor 901 described above, the HOPB pixels 911 are connected to the ADC 845 and ADC 1061 via a reference column. Furthermore, it is assumed that the CMOS image sensor 901 performs sampling twice, once for the P phase and once for the D phase.

[0487] In such cases, both the VSL signal, i.e., the signal from the normal pixel 912, and the reference signal, i.e., the signal from the HOPB pixel 911, are sampled twice, i.e., read out twice, so a P / D shift due to dark current occurs simultaneously. That is, a shift in the signal amount due to the dark current of the P-phase signal and the D-phase signal occurs simultaneously.

[0488] As a result, for each pixel row consisting of 912 pixels, an analog clamping function can be considered to have been implemented for each pixel row, enabling lower noise and better imaging characteristics. In addition, detection (signal readout) of VOPB pixels for analog clamping is unnecessary, allowing for miniaturization and lower power consumption of the CMOS image sensor 901. Moreover, since the clamping function can be implemented (completed) by calculations in the analog domain, no additional digital circuitry is required.

[0489] On the other hand, the pixel characteristics, such as dark current characteristics, of the pixels in the effective pixel region, i.e., the normal pixels 912, and the pixels in the HOPB region, i.e., the HOPB pixels 911, are not necessarily identical.

[0490] Therefore, as shown in Figure 42, for example, the difference in the amount of dark current shift may be absorbed by adjusting the reference voltage.

[0491] In the example shown in Figure 42, the CMOS image sensor 901 is further equipped with a control circuit 1091 and a reference voltage adjustment unit 1092 in addition to the configuration shown in Figure 36. In particular, in this example, the reference voltage adjustment unit 1092 is connected between the S / H circuit 841 and the push-pull buffer circuit 842 in the reference column, and the operation of the reference voltage adjustment unit 1092 is controlled by the control circuit 1091.

[0492] The control circuit 1091 controls the reference voltage adjustment unit 1092 so that, when reading the D-phase signal, more specifically during the D-phase settling period, within the period from when the control signal SAMPLE_EN falls to when the control signal REF_SEL rises, the signal voltage from the HOPB pixel 911 is adjusted (corrected).

[0493] The reference voltage adjustment unit 1092 consists of a circuit with high PSRR tolerance, for example, a BGR (Bandgap Reference) reference, and assists the analog clamping function. Specifically, the reference voltage adjustment unit 1092 adjusts the signal voltage from the HOPB pixel 911, which is supplied from the S / H circuit 841 to the push-pull buffer circuit 842 and becomes the reference voltage at the ADC 845, in accordance with the control of the control circuit 1091. In other words, the reference voltage adjustment unit 1092 adjusts the voltage level of the reference signal supplied from the S / H circuit 841 to the push-pull buffer circuit 842.

[0494] Figure 43 shows a more detailed example of the configuration of the reference voltage adjustment unit 1092. In Figure 43, parts corresponding to those in Figure 39 are denoted by the same reference numerals, and their explanations are omitted as appropriate. Also, in Figure 43, some reference numerals for the components of the push-pull buffer circuit 981 have been omitted for clarity.

[0495] In the example shown in Figure 43, the reference voltage adjustment unit 1092 includes capacitors 1121-1 to 1121-5 and switches 1122-1 to 1122-5.

[0496] In the following, capacitors 1121-1 to 1121-5 will simply be referred to as capacitor 1121 unless there is a need to distinguish between them. Similarly, switches 1122-1 to 1122-5 will simply be referred to as switch 1122 unless there is a need to distinguish between them.

[0497] One end of capacitor 1121 is connected to switch 1122, and the other end of capacitor 1121 is connected to capacitor 972, switch 1001, capacitor 992-1, and capacitor 993-1.

[0498] For example, capacitors 1121-1 to 1121-5 are capacitors with different capacitances, and they receive voltage from a predetermined voltage source via switches 1122-1 to 1122-5. The voltage source that supplies voltage to capacitor 1121 is, for example, a voltage source correlated with the full-scale voltage of the ADC 845.

[0499] Here, we will describe an example in which five capacitors 1121 are provided, but any number of capacitors 1121 may be provided. Also, any combination of capacitances of the capacitors 1121 is acceptable.

[0500] Switch 1122 switches the connection destination of capacitor 1121 according to the control of control circuit 1091. For example, control circuit 1091 switches between a state in which a predetermined voltage such as 40mV is supplied to capacitor 1121 from a voltage source, or a state in which a voltage of 0V is supplied to capacitor 1121.

[0501] In particular, each switch 1122 can be controlled independently. Therefore, at a given time, there may be capacitors 1121 that are supplied with a predetermined voltage such as 40mV and capacitors 1121 that are supplied with a voltage of 0V.

[0502] By switching the connection destination of each capacitor 1121 in this way, the signal voltage corresponding to the signal output from the HOPB pixel 911, supplied from the S / H circuit 841 to the push-pull buffer circuit 981, changes (attenuates) due to capacitance division. In this case, by appropriately selecting the combination of capacitors 1121 that supply the voltage, the signal voltage (reference signal) corresponding to the signal from the HOPB pixel 911 can be adjusted (corrected) by the desired amount.

[0503] <Example of CMOS Image Sensor Operation> An example of the operation of the CMOS image sensor 901 will be explained with reference to Figure 44. In Figure 44, the horizontal direction represents time, and the vertical direction represents potential (voltage level). In particular, the upward-convex portion of each control signal in the figure indicates the H level.

[0504] In Figure 44, curve L91 shows the potential of the vertical signal line, i.e., the input terminal IP11, at each time step. In particular, for clarity, the potential change is shown for only one column. Furthermore, the broken lines L92 and L93 represent the control signals BIAS_EN and SAMPLE_EN. Specifically, the control signals BIAS_EN and SAMPLE_EN are common to all columns.

[0505] The broken lines L94-1 to L94-n (however, broken lines L94-3 to L94-(n-1) are not shown) represent the control signal BUFSEL supplied to the push-pull buffer circuits 844-1 to 844-n. The broken line L95 represents the control signal REF_SEL supplied to the push-pull buffer circuit 981 of the reference column to which the HOPB pixel 911 is connected.

[0506] Curve L96 shows the potential at the signal input terminal of the ADC 845, i.e., the voltage level (signal voltage) corresponding to the signal output from the normal pixel 912. Curve L97 shows the potential at the reference input terminal of the ADC 845, i.e., the voltage level (signal voltage) corresponding to the signal output from the HOPB pixel 911.

[0507] First, at time t71, the control signals BIAS_EN and SAMPLE_EN are simultaneously set to the H level in all columns. As a result, in the signal column, switch 161 of the S / H circuit 843 is turned on, as well as switch 171 of the push-pull buffer circuit 152. Similarly, in the reference column, switch 971 of the S / H circuit 841 is turned on, as well as switch 991 of the push-pull buffer circuit 981.

[0508] At time t72, the control signals BIAS_EN and SAMPLE_EN are simultaneously set to L level in all columns.

[0509] As a result, in the signal column, switch 161 of the S / H circuit 843 is turned off, as is switch 171 of the push-pull buffer circuit 152. Consequently, the bias voltage is sampled and the P-phase signal is sampled in the same manner as in the example in Figure 12. That is, the S / H circuit 843 of each signal column connected to the ADC 845 simultaneously performs a sampling operation that normally samples the signal output from the pixel 912.

[0510] Similarly, in the reference column, switch 971 of the S / H circuit 841 is turned off, and switch 991 of the push-pull buffer circuit 981 is also turned off. As a result, the bias voltage is sampled, and the P-phase reference signal is sampled. That is, the S / H circuit 841 of the reference column connected to the ADC 845 performs a sampling operation to sample the signal output from the HOPB pixel 911.

[0511] Subsequently, the control signal BUFSEL is supplied to switch 176 of the push-pull buffer circuit 152 that constitutes the signal column, and similarly, the control signal REF_SEL is supplied to switch 996 of the push-pull buffer circuit 981 that constitutes the reference column.

[0512] As a result, from time t73 onward, each signal column is selected sequentially as a selected column, and a P-phase signal is output from the push-pull buffer circuit 152 of the selected column. At this time, at each timing, one of the total signal columns is designated as a selected column, and the P-phase signal is read out (output) from that selected column, while the remaining signal columns are designated as unselected columns, and the P-phase signals from those unselected columns are not read out.

[0513] On the other hand, from time t73 onward, the control signal REF_SEL supplied to the reference column, i.e., switch 996 of the push-pull buffer circuit 981, remains at the H level. Therefore, switch 996 remains ON, and the reference signal continues to be output from the push-pull buffer circuit 981 to the ADC 845.

[0514] Thus, during the period from time t73 to time t74, a multiplex operation is performed in which the P-phase signal is read out from the selected column while switching the selected column.

[0515] For example, at time t73, only the control signal BUFSEL_1 is set to the H level, turning on the switch 176 of the push-pull buffer circuit 152 for the first signal column, while the switches 176 of the push-pull buffer circuit 152 for the other signal columns are turned off.

[0516] In the first signal column, when switch 176 is turned on, the sampled P-phase signal is output from output terminal OP11 to ADC 845, similar to the case at time t24 in Figure 9. ADC 845 then performs A / D conversion of the P-phase signal from the signal column based on the reference signal from the reference column. Subsequently, the control signal BUFSEL_1 is set to a low level, turning off switch 176 for the first signal column, and the first signal column becomes a non-selected column. At the same time, the control signal BUFSEL_2 for the second signal column is set to a high level, making the second signal column a selected column.

[0517] Subsequently, the same process is repeated until time t74, during which the P-phase signals from each signal column are read out and AD conversion is performed.

[0518] At time t74, when the control signal BUFSEL_N is set to L level and the switch 176 of the Nth signal column is turned off, and the control signal REF_SEL is set to L level and the switch 996 of the reference column is turned off, the reading of the P-phase signals from all signal columns is completed.

[0519] Once the P-phase signal has been read out, the D-phase signal is then read out.

[0520] Specifically, at time t75, the control signal SAMPLE_EN is simultaneously set to the H level in all columns (reference column and signal column), turning on switches 971 and 161. At the following time t76, the control signal SAMPLE_EN is simultaneously set to the L level in all columns, turning off switches 971 and 161, and the D-phase signal is sampled. These operations at times t75 and t76 are the same as the operations at times t26 and t27 in Figure 9. At this time, similar to the signal column, the signal from the HOPB pixel 911 (reference signal) is also sampled by the S / H circuit 841 in the reference column.

[0521] Subsequently, during the period from time t77 to time t78, the same operations as in the period from time t73 to time t74 are performed. That is, the reference signal is continuously output from the push-pull buffer circuit 981 of the reference column to the ADC 845, and each signal column is selected in order as a selected column. The D-phase signal is then output from the push-pull buffer circuit 152 of the selected column to the ADC 845, and the A / D conversion of that D-phase signal is performed.

[0522] Furthermore, in the logic circuit following the ADC845, for example, CDS processing is performed to generate a luminance signal by calculating the difference between the P-phase signal and the D-phase signal, or processing is performed to output the digital P-phase signal and D-phase signal as they are.

[0523] When the control signal BUFSEL_N is set to the L level at time t78 and the switch 176 of the Nth signal column is turned off, the reading of the D-phase signals from all signal columns is completed.

[0524] For example, if the configuration of the CMOS image sensor 901 is as shown in Figure 42, the control circuit 1091 controls the switch 1122 of the reference voltage adjustment unit 1092 during the period from time t76 to time t77 to adjust the voltage level (reference voltage) of the reference signal. Specifically, for example, the voltage level of the reference signal is adjusted by switching from a state in which a voltage of 40mV is supplied to each capacitor 1121 to a state in which a voltage of 0V is supplied to one or more predetermined capacitors 1121.

[0525] In such cases, for example, if we enlarge the portion of curve L97, it will look like Figure 45. In this example, the difference between the voltage level of the P-phase reference signal and the voltage level of the D-phase reference signal is appropriately adjusted, and as a result, the assistance of the analog clamping function is realized.

[0526] Through the operation described above, the CMOS image sensor 901, as in the example in Figure 5, can increase the response speed during signal readout in each column and improve the intermittency ratio. This enables high-speed multiplex operation and reduces power consumption during signal readout. In particular, in this example, power consumption reduction through intermittent operation can be achieved not only for the normal pixels 912 (signal columns) but also for the HOPB pixels 911 (reference columns).

[0527] Furthermore, in the CMOS image sensor 901, connecting the HOPB pixels 911 to the reference column makes it possible to achieve lower noise and better imaging characteristics.

[0528] Specifically, for example, by sampling the power supply noise superimposed on the signal from the HOPB pixel 911 using a reference column, the power supply noise from the normal pixel 912 can be removed in the ADC 845 through common-mode rejection. In other words, the degradation of the PSRR characteristics can be suppressed.

[0529] Furthermore, since a similar signal shift occurs in the reference column in response to a signal shift due to dark current in the signal column, tracking is possible on the reference column side, enabling the realization of an analog clamp function (analog clamp correction). Moreover, in this case, since the analog clamp correction is performed in the analog domain, not only is additional digital circuitry unnecessary, but errors due to quantization, etc., as occur in processing in the digital domain, resulting in lower noise and better imaging characteristics.

[0530] Furthermore, the CMOS image sensor 901 does not require digital circuits such as the power supply noise cancellation signal generation unit 881 in the example of Figure 35, nor its adjustment valves. Therefore, the CMOS image sensor 901 can achieve miniaturization and reduced power consumption. Moreover, by connecting the HOPB pixel 911 to the reference column, the CMOS image sensor 901 eliminates the need to read signals from the HOPB pixel 911 separately at a different timing than the signal readout from the normal pixel 912, thereby shortening processing time and further reducing power consumption.

[0531] As an arrangement of HOPB pixels 911 in the CMOS image sensor 901, that is, the arrangement of the HOPB region, for example, the arrangement shown in Figure 46 is possible.

[0532] In Figure 46, the upper part of the figure shows the pixel arrangement on the subject-facing side (light-receiving surface) of the CMOS image sensor 901, while the lower part of the figure shows the circuit arrangement in the layer directly below the layer in which the pixels are arranged (hereinafter also referred to as the wiring layer).

[0533] The subject-facing side of the CMOS image sensor 901 is provided with an effective pixel area RG11, a HOPB area RG12-1, and a HOPB area RG12-2.

[0534] The effective pixel region RG11 is a region in which the effective pixels, i.e., normal pixels 912, that are the targets of signal (pixel value) readout are arranged in a matrix. For example, in the effective pixel region RG11, n normal pixels 912 are arranged in a row in the left-right direction (row direction) as shown in the figure.

[0535] HOPB regions RG12-1 and RG12-2 are HOPB regions in which HOPB pixels 911 are arranged in a matrix. In this example, when the light-receiving surface of the CMOS image sensor 901 is viewed from a direction perpendicular to the light-receiving surface, HOPB region RG12-1 is located adjacent to the left side of the effective pixel region RG11 in the diagram, and HOPB region RG12-2 is located adjacent to the right side of the effective pixel region RG11 in the diagram. In the diagram in Figure 46, the left-right direction is the row direction in which pixels constituting the pixel row are arranged.

[0536] Furthermore, a pixel region RG13-1 is provided between the effective pixel region RG11 and the HOPB region RG12-1, and a pixel region RG13-2 is provided between the effective pixel region RG11 and the HOPB region RG12-2. These pixel regions RG13-1 and RG13-2 are arranged with at least one of either normal pixels or light-shielding pixels (HOPB pixels). That is, pixel regions RG13-1 and RG13-2 may be provided with normal pixels or may be provided with HOPB pixels.

[0537] In the following, when there is no need to distinguish between HOPB region RG12-1 and HOPB region RG12-2, they will simply be referred to as HOPB region RG12. Similarly, when there is no need to distinguish between pixel region RG13-1 and pixel region RG13-2, they will simply be referred to as pixel region RG13.

[0538] In this example, one HOPB region RG12 has m × k HOPB pixels 911 arranged in a row direction.

[0539] In the CMOS image sensor 901, n signal columns are arranged in a row directly beneath the effective pixel area RG11 in the wiring layer. Here, one rectangle labeled "Signal Output" represents one signal column.

[0540] Furthermore, k reference columns are arranged in a row directly beneath the adjacent HOPB region RG12 and pixel region RG13 in the wiring layer. Here, one rectangle labeled "Reference Output" represents one reference column. In particular, in this example, a reference column is also located directly beneath the pixel region RG13.

[0541] In this pixel and circuit configuration, the CMOS image sensor 901 will have m × 2k HOPB pixels 911 and 2k reference columns in one pixel row. In this case, for example, as shown in Figure 47, the m HOPB pixels 911 in one pixel row can be connected to one reference column. Alternatively, for example, the outputs of multiple reference columns can be connected to the reference input terminal of a single ADC 845.

[0542] The CMOS image sensor 901 is equipped with push-pull buffer circuits 842 and 844, allowing for flexible selection (determination) of the arrangement of reference columns and signal columns. Furthermore, signals (reference signals) from multiple HOPB pixels 911 can be combined into a fixed number of columns by source follower addition. In other words, multiple HOPB pixels 911 can be connected to a single reference column. In addition, since the HOPB pixels 911 and the reference column can be arranged in an m:1 ratio, the value (constant) m that determines the number of HOPB pixels 911 can be flexibly selected, thereby achieving low noise.

[0543] For example, the power supply noise cancellation signal generation unit 881 described above only senses the pixel power supply, and therefore cannot respond to noise generated at locations other than the pixel power supply due to ground fluctuations, etc.

[0544] In contrast, the CMOS image sensor 901 allows for the parallel connection of multiple HOPB pixels 911 to a single reference column (S / H circuit 841), or the parallel connection of multiple reference columns (push-pull buffer circuits 842) to the reference input terminal of a single ADC 845. Therefore, for example, signals from multiple HOPB pixels 911 arranged to the left and right of the effective pixel area RG11 can be supplied to the ADC 845 as reference signals to average out random noise, reduce noise that depends on the position of the pixel row, i.e., noise that occurs only in a specific pixel row. In particular, it is possible to reduce lateral noise caused by ground potential fluctuations, etc.

[0545] Furthermore, the column arrangement in the CMOS image sensor 901 is not limited to the example shown in Figure 46; for example, the arrangement shown in Figure 48 may also be used. Note that in Figure 48, the parts corresponding to those in Figure 46 are denoted by the same reference numerals, and their explanations are omitted as appropriate.

[0546] In the example shown in Figure 48, k reference columns are arranged in a row directly beneath the HOPB region RG12 in the wiring layer. That is, no columns are placed directly beneath the pixel region RG13. Thus, the arrangement of the reference columns can be arbitrary.

[0547] <Example of Image Sensor Usage> Figure 49 shows an example of using an image sensor with this technology.

[0548] The image sensor using the above-described technology can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0549] - Devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions. - Devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. - Devices used in home appliances such as TVs, refrigerators, and air conditioners that capture user gestures and allow device operation according to those gestures. - Devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception. - Devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition. - Devices used for beauty purposes, such as skin measuring devices that capture images of skin and microscopes that capture images of the scalp. - Devices used for sports purposes, such as action cameras and wearable cameras for sports use. - Devices used for agriculture, such as cameras that monitor the condition of fields and crops.

[0550] In the example described above, an image sensor (solid-state imaging device) was described in which the first conductivity type was P-type and the second conductivity type was N-type, and electrons were used as the signal charge. However, this technology can also be applied to solid-state imaging devices that use holes as the signal charge. That is, a configuration in which the first conductivity type is N-type and the second conductivity type is P-type is possible.

[0551] <Examples of application to electronic devices> This technology is not limited to image sensors. That is, this technology can be applied to all electronic devices that use a solid-state imaging device in the image acquisition unit (photoelectric conversion unit), such as imaging devices such as digital still cameras and video cameras, portable terminal devices with imaging functions, and photocopiers that use a solid-state imaging device in the image reading unit. The solid-state imaging device may be formed as a single chip, or it may be in the form of a module with imaging functions in which the imaging unit and the signal processing unit or optical system are packaged together.

[0552] Figure 50 is a block diagram showing an example configuration of an imaging device as an electronic device to which this technology is applied.

[0553] The imaging device 1901 in Figure 50 comprises an optical unit 1911 consisting of a lens group and the like, a solid-state imaging device (imaging device) 1912 having an intermittent push-pull buffer S / H circuit 92 to which this technology is applied, and a DSP (Digital Signal Processor) circuit 1913 which is a camera signal processing circuit. The imaging device 1901 also includes a frame memory 1914, a display unit 1915, a recording unit 1916, an operation unit 1917, and a power supply unit 1918. The DSP circuit 1913, frame memory 1914, display unit 1915, recording unit 1916, operation unit 1917, and power supply unit 1918 are interconnected via a bus line 1919.

[0554] The optical unit 1911 captures incident light (image light) from the subject and forms an image on the imaging surface of the solid-state imaging device 1912. The solid-state imaging device 1912 converts the amount of light from the incident light formed on the imaging surface by the optical unit 1911 into an electrical signal on a pixel-by-pixel basis and outputs it as a pixel signal.

[0555] The display unit 1915 is composed of a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays moving images or still images captured by the solid-state imaging device 1912. The recording unit 1916 records the moving images or still images captured by the solid-state imaging device 1912 onto a recording medium such as a hard disk or semiconductor memory.

[0556] The control unit 1917 issues operation commands for various functions of the imaging device 1901 under the user's control. The power supply unit 1918 appropriately supplies various power sources to the DSP circuit 1913, frame memory 1914, display unit 1915, recording unit 1916, and control unit 1917.

[0557] <Examples of application to endoscopic surgical systems> The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be applied to endoscopic surgical systems.

[0558] Figure 51 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0559] Figure 51 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0560] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0561] An opening into which an objective lens is fitted is provided at the tip of the microscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the microscope tube by a light guide extending inside the microscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0562] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0563] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display an image based on that image signal.

[0564] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0565] The light source device 11203 is composed of a light source such as an LED (light-emitting diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0566] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various types of information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0567] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or blood vessel sealing. The insufflation device 11206 injects gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing a field of view by the endoscope 11100 and securing the operator's workspace. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0568] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0569] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0570] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue and irradiating with narrow-band light compared to the irradiation light used during normal observation (i.e., white light), so-called narrow-band imaging is performed to image predetermined tissues such as blood vessels on the surface of mucosa with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light is irradiated onto body tissue and fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated onto the body tissue to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0571] Figure 52 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 51.

[0572] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0573] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0574] The imaging unit 11402 may consist of one image sensor (a so-called single-chip type) or multiple image sensors (a so-called multi-chip type). If the imaging unit 11402 is configured as a multi-chip type, for example, each image sensor may generate image signals corresponding to RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each image sensor.

[0575] Furthermore, the imaging unit 11402 does not necessarily have to be located on the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0576] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0577] The communication unit 11404 is composed of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0578] Furthermore, the communication unit 11404 receives a control signal from the CCU 11201 to control the drive of the camera head 11102 and supplies it to the camera head control unit 11405. The control signal includes information about imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0579] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0580] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0581] The communication unit 11411 is comprised of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0582] Furthermore, the communication unit 11411 transmits a control signal to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0583] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0584] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates a control signal to control the driving of the camera head 11102.

[0585] Furthermore, the control unit 11413 displays the captured image showing the surgical area, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery reliably.

[0586] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0587] In the illustrated example, communication was performed via a wired connection using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0588] The above describes an example of an endoscopic surgical system to which the technology described herein may be applied. The technology described herein can be applied to, for example, the camera head 11102 of the configuration described above. By applying the technology described herein to the camera head 11102, power consumption can be reduced.

[0589] While an endoscopic surgical system has been described here as an example, the technology described herein may also be applied to other systems, such as microsurgical systems.

[0590] <Examples of application to mobile devices> The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0591] Figure 53 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0592] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 53, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0593] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0594] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0595] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0596] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0597] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0598] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0599] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0600] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0601] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 53, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0602] Figure 54 shows an example of the installation position of the imaging unit 12031.

[0603] In Figure 54, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0604] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0605] Figure 54 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0606] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0607] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0608] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0609] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0610] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 12031, for example, among the configurations described above. By applying the technology described herein to the imaging unit 12031, power consumption can be reduced.

[0611] Furthermore, this technology is applicable to semiconductor devices in general that have semiconductor integrated circuits.

[0612] The embodiments of this technology are not limited to those described above, and various modifications are possible without departing from the spirit of this technology.

[0613] For example, a combination of all or some of the above-described embodiments can be adopted.

[0614] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0615] Furthermore, this technology can also be configured as follows:

[0616] (1) An electronic circuit having a push-pull buffer circuit, wherein the push-pull buffer circuit has a switch for intermittent signal output and a bypass current circuit that forms a bypass current path when the signal output is paused. (2) The electronic circuit according to (1), further having a sample-and-hold circuit, wherein the push-pull buffer circuit outputs a signal in accordance with the signal held in the sample-and-hold circuit. (3) The electronic circuit according to (1) or (2), further having an attenuation circuit for attenuating the signal output from the push-pull buffer circuit. (4) The electronic circuit according to (3), wherein the attenuation circuit can adjust the amount of signal attenuation in multiple stages. (5) The electronic circuit according to any one of (1) to (4), further having a reference bias circuit that determines the output current flowing when the signal is output in the push-pull buffer circuit and the voltage level of the signal output. (6) The electronic circuit according to any one of (1) to (5), wherein the bypass current circuit is composed of a transistor, a resistor, or a current source. (7) The bypass current flowing through the bypass current path is a subthreshold current. The electronic circuit according to any one of (1) to (6). (8) The push-pull buffer circuit has a first conductivity type transistor and a second conductivity type transistor connected in parallel, and the switch is provided between the first conductivity type transistor and the second conductivity type transistor. The electronic circuit according to any one of (1) to (7). (9) The electronic circuit according to (8), where two switches are provided between the first conductivity type transistor and the second conductivity type transistor, and the signal output is provided from between the two switches. (10) The push-pull buffer circuit has a first conductivity type transistor and a second conductivity type transistor connected in parallel, and the bypass current circuit is connected between the first conductivity type transistor and the second conductivity type transistor. The electronic circuit according to any one of (1) to (9).(11) The push-pull buffer circuit has a current control switch provided on the bypass current path for controlling whether or not to flow a bypass current, the electronic circuit according to any one of (1) to (10). (12) A solid-state imaging device having a first push-pull buffer circuit having a switch for intermittent signal output and a bypass current circuit that forms a bypass current path when the signal output is paused, and a first AD conversion circuit connected to a plurality of the first push-pull buffer circuits and performing AD conversion of signals supplied from the first push-pull buffer circuits. (13) The solid-state imaging device according to (12), wherein, by controlling the switch, multiplex operation is possible in which signals are supplied sequentially to the first AD conversion circuit from each of the plurality of the first push-pull buffer circuits. (14) The solid-state imaging device according to (12) or (13), further having a sample-and-hold circuit for holding signals output from a pixel circuit, wherein the first push-pull buffer circuit performs the signal output according to the signal held in the sample-and-hold circuit. (15) The solid-state imaging apparatus according to (14), wherein each of the plurality of first push-pull buffer circuits connected to one of the first AD conversion circuits is connected to each of the plurality of sample-and-hold circuits, and the plurality of sample-and-hold circuits simultaneously perform the operation of sampling the signal output from the pixel circuit. (16) The solid-state imaging apparatus according to (14) or (15), further comprising a current source circuit for supplying a constant current to a vertical signal line to which the pixel circuit and the sample-and-hold circuit are connected, and a first current control switch provided between the vertical signal line and the current source circuit for controlling whether or not to supply the constant current. (17) The solid-state imaging apparatus according to any one of (12) to (16), further comprising a second push-pull buffer circuit having the same configuration as the first push-pull buffer circuit and supplying a reference voltage signal to the first AD conversion circuit. (18) The first AD conversion circuit is a SAR ADC. A solid-state imaging apparatus as described in any one of (12) to (17).(19) A solid-state imaging apparatus according to any one of (12) to (18), wherein a plurality of unit circuits are provided, each having one of the first AD conversion circuits and a plurality of the first push-pull buffer circuits connected to the one of the first AD conversion circuits. (20) A solid-state imaging apparatus according to any one of (12) to (18), wherein a plurality of unit circuits are provided, each having a plurality of the first push-pull buffer circuits connected to each of the plurality of the first AD conversion circuits, and the first AD conversion circuits are connected to the first push-pull buffer circuits of each of the plurality of the unit circuits. (21) A solid-state imaging apparatus according to (20), further comprising each of a plurality of second AD conversion circuits connected to each of the plurality of first push-pull buffer circuits. (22) A solid-state imaging apparatus according to any one of (12) to (21), further comprising an attenuation circuit for attenuating the signal output from the first push-pull buffer circuit. (23) The solid-state imaging apparatus according to (22), wherein the attenuation circuit is capable of adjusting the signal attenuation in multiple stages. (24) The solid-state imaging apparatus according to any one of (12) to (23), further comprising a reference bias circuit that determines the output current flowing when the signal is output and the voltage level of the signal output in the first push-pull buffer circuit. (25) The solid-state imaging apparatus according to any one of (12) to (24), wherein the bypass current circuit is composed of a transistor, a resistor, or a current source. (26) The solid-state imaging apparatus according to any one of (12) to (25), wherein the bypass current flowing through the bypass current path is a subthreshold current. (27) The solid-state imaging apparatus according to any one of (12) to (26), wherein the first push-pull buffer circuit has a first conductivity type transistor and a second conductivity type transistor connected in parallel, and the switch is provided between the first conductivity type transistor and the second conductivity type transistor. (28) The solid-state imaging apparatus according to (27), wherein two switches are provided between the first conductivity type transistor and the second conductivity type transistor, and the first AD conversion circuit is connected between the two switches.(29) The solid-state imaging apparatus according to any one of (12) to (28), wherein the first push-pull buffer circuit has a first conductivity type transistor and a second conductivity type transistor connected in parallel, and the bypass current circuit is connected between the first conductivity type transistor and the second conductivity type transistor. (30) The solid-state imaging apparatus according to any one of (12) to (29), wherein the first push-pull buffer circuit has a second current control switch provided on the bypass current path for controlling whether or not to allow bypass current to flow. (31) The solid-state imaging apparatus according to any one of (12) to (30), further comprising a control circuit that generates a control signal for controlling the operation of the switch based on a Gray code. (32) A readout circuit comprising an AD conversion circuit that performs AD conversion of a signal output from a pixel based on a signal output from any pixel among each of a plurality of pixels connected to each of a plurality of vertical signal lines and a reference signal. (33) The readout circuit according to (32), further comprising a first sample-and-hold circuit for holding a signal output from the pixel, and a first push-pull buffer circuit having a switch for intermittent signal output and for outputting a signal corresponding to the signal held in the first sample-and-hold circuit, wherein the AD conversion circuit is connected to a plurality of the first push-pull buffer circuits and performs AD conversion of a signal supplied from one of the first push-pull buffer circuits. (34) The readout circuit according to (33), wherein the AD conversion circuit performs AD conversion of the difference between a signal supplied from the first push-pull buffer circuit and the reference signal. (35) The readout circuit according to (33) or (34), wherein the AD conversion circuit is a SAR ADC. (36) A readout circuit according to any one of (33) to (35), further comprising a second sample-and-hold circuit for holding the reference signal, and a second push-pull buffer circuit having a switch for intermittent signal output and supplying the reference signal held by the second sample-and-hold circuit to the AD conversion circuit.(37) The readout circuit according to (36), further comprising a plurality of AD conversion circuits connected to the first push-pull buffer circuits which are different from each other, and the same second push-pull buffer circuit is connected to the plurality of AD conversion circuits. (38) The readout circuit according to (36), further comprising a power supply noise cancellation signal generation unit which generates a power supply noise cancellation signal, and the second sample-and-hold circuit holds the power supply noise cancellation signal as the reference signal. (39) The readout circuit according to (36), further comprising a second sample-and-hold circuit which holds a signal output from a light-shielded pixel whose light-receiving surface is shielded as the reference signal. (40) The readout circuit according to (39), further comprising a gain adjustment unit provided between the second sample-and-hold circuit and the second push-pull buffer circuit which adjusts the gain of the reference signal. (41) The readout circuit according to (39), further comprising a reference voltage adjustment unit connected between the second sample-and-hold circuit and the second push-pull buffer circuit which adjusts the voltage level of the reference signal. (42) The reference voltage adjustment unit adjusts the voltage level by capacitance division, the readout circuit as described in (41). (43) The readout circuit as described in any one of (39) to (42), wherein a plurality of light-shielding pixels are provided in regions adjacent in the pixel row direction to the effective pixel region on which the pixels are provided. (44) The readout circuit as described in any one of (39) to (43), wherein a plurality of light-shielding pixels are connected to the second sample-and-hold circuit. (45) The readout circuit as described in any one of (39) to (44), wherein a plurality of the second push-pull buffer circuits are connected to the AD conversion circuit.

[0617] 81 Electronic circuits, 91 Reference bias circuits, 92 Intermittent push-pull buffered S / H circuits, 151 S / H circuits, 152 Push-pull buffer circuits, 153 Attenuation circuits, 174 Transistors, 175 Transistors, 176-1, 176-2, 176 Switches, 177 Transistors, 178 Switches

Claims

1. An electronic circuit having a push-pull buffer circuit, wherein the push-pull buffer circuit includes a switch for intermittent signal output and a bypass current circuit that forms a bypass current path when the signal output is paused.

2. The electronic circuit according to claim 1, further comprising a sample-and-hold circuit, wherein the push-pull buffer circuit outputs the signal corresponding to the signal held by the sample-and-hold circuit.

3. The electronic circuit according to claim 1, further comprising an attenuation circuit for attenuating the signal output from the push-pull buffer circuit.

4. The electronic circuit according to claim 3, wherein the attenuation circuit is capable of adjusting the signal attenuation amount in multiple stages.

5. The electronic circuit according to claim 1, further comprising a reference bias circuit that determines the output current flowing when the signal is output and the voltage level of the signal output in the push-pull buffer circuit.

6. The electronic circuit according to claim 1, wherein the bypass current circuit is composed of a transistor, a resistor, or a current source.

7. The electronic circuit according to claim 1, wherein the bypass current flowing through the bypass current path is a subthreshold current.

8. The electronic circuit according to claim 1, wherein the push-pull buffer circuit has a first conductivity type transistor and a second conductivity type transistor connected in parallel, and the switch is provided between the first conductivity type transistor and the second conductivity type transistor.

9. The electronic circuit according to claim 8, wherein two switches are provided between the first conductivity type transistor and the second conductivity type transistor, and the signal output is generated from between the two switches.

10. The electronic circuit according to claim 1, wherein the push-pull buffer circuit has a first conductivity type transistor and a second conductivity type transistor connected in parallel, and the bypass current circuit is connected between the first conductivity type transistor and the second conductivity type transistor.

11. The electronic circuit according to claim 1, wherein the push-pull buffer circuit has a current control switch provided on the bypass current path for controlling whether or not to allow bypass current to flow.

12. A solid-state imaging device having a first push-pull buffer circuit having a switch for intermittent signal output and a bypass current circuit that forms a bypass current path when the signal output is paused, and a first AD conversion circuit connected to a plurality of the first push-pull buffer circuits and performing AD conversion of the signals supplied from the first push-pull buffer circuits.

13. The solid-state imaging apparatus according to claim 12, which enables multiplex operation in which signals are sequentially supplied to the first AD conversion circuit from each of the multiple first push-pull buffer circuits by controlling the switch.

14. The solid-state imaging apparatus according to claim 12, further comprising a sample-and-hold circuit for holding a signal output from a pixel circuit, wherein the first push-pull buffer circuit performs the signal output corresponding to the signal held in the sample-and-hold circuit.

15. The solid-state imaging apparatus according to claim 14, wherein each of the plurality of first push-pull buffer circuits connected to one of the first AD conversion circuits is connected to each of the plurality of sample-and-hold circuits, and the plurality of sample-and-hold circuits simultaneously perform the operation of sampling the signal output from the pixel circuit.

16. The solid-state imaging apparatus according to claim 14, further comprising: a current source circuit for supplying a constant current to a vertical signal line to which the pixel circuit and the sample-and-hold circuit are connected; and a first current control switch provided between the vertical signal line and the current source circuit for controlling whether or not to supply the constant current.

17. The solid-state imaging apparatus according to claim 12, further comprising a second push-pull buffer circuit having the same configuration as the first push-pull buffer circuit and supplying a reference voltage signal to the first AD conversion circuit.

18. The solid-state imaging apparatus according to claim 12, wherein the first AD conversion circuit is a SAR ADC.

19. The solid-state imaging apparatus according to claim 12, wherein a plurality of unit circuits are provided, each having one first AD conversion circuit and a plurality of first push-pull buffer circuits connected to the one first AD conversion circuit.

20. A solid-state imaging apparatus according to claim 12, wherein a plurality of unit circuits are provided, each having a plurality of first push-pull buffer circuits connected to each of the plurality of first AD conversion circuits, and the first AD conversion circuits are connected to the first push-pull buffer circuits of each of the plurality of unit circuits.

21. The solid-state imaging apparatus according to claim 20, further comprising each of a plurality of second AD conversion circuits connected to each of the plurality of first push-pull buffer circuits.

22. The solid-state imaging apparatus according to claim 12, further comprising an attenuation circuit for attenuating the signal output from the first push-pull buffer circuit.

23. The solid-state imaging apparatus according to claim 22, wherein the attenuation circuit is capable of adjusting the signal attenuation amount in multiple stages.

24. The solid-state imaging apparatus according to claim 12, further comprising a reference bias circuit that determines the output current flowing when the signal is output and the voltage level of the signal output in the first push-pull buffer circuit.

25. The solid-state imaging apparatus according to claim 12, wherein the bypass current circuit is composed of a transistor, a resistor, or a current source.

26. The solid-state imaging apparatus according to claim 12, wherein the bypass current flowing through the bypass current path is a subthreshold current.

27. The solid-state imaging apparatus according to claim 12, wherein the first push-pull buffer circuit has a first conductivity type transistor and a second conductivity type transistor connected in parallel, and the switch is provided between the first conductivity type transistor and the second conductivity type transistor.

28. The solid-state imaging apparatus according to claim 27, wherein two switches are provided between the first conductivity type transistor and the second conductivity type transistor, and the first AD conversion circuit is connected between the two switches.

29. The solid-state imaging apparatus according to claim 12, wherein the first push-pull buffer circuit has a first conductivity type transistor and a second conductivity type transistor connected in parallel, and the bypass current circuit is connected between the first conductivity type transistor and the second conductivity type transistor.

30. The solid-state imaging apparatus according to claim 12, wherein the first push-pull buffer circuit is provided on the bypass current path and has a second current control switch for controlling whether or not to allow bypass current to flow.

31. The solid-state imaging apparatus according to claim 12, further comprising a control circuit that generates a control signal for controlling the operation of the switch based on the Gray code.

32. A readout circuit comprising an AD conversion circuit that performs AD conversion of a signal output from a pixel based on a signal output from any of the pixels among a plurality of pixels connected to each of a plurality of vertical signal lines and a reference signal.

33. The readout circuit according to claim 32, further comprising: a first sample-and-hold circuit for holding a signal output from the pixel; and a first push-pull buffer circuit having a switch for intermittent signal output and for outputting a signal corresponding to the signal held by the first sample-and-hold circuit, wherein the AD conversion circuit is connected to a plurality of the first push-pull buffer circuits and performs AD conversion of a signal supplied from one of the first push-pull buffer circuits.

34. The readout circuit according to claim 33, wherein the AD conversion circuit performs AD conversion on the difference between the signal supplied from the first push-pull buffer circuit and the reference signal.

35. The readout circuit according to claim 33, wherein the AD conversion circuit is a SAR ADC.

36. The readout circuit according to claim 33, further comprising a second sample-and-hold circuit for holding the reference signal, and a second push-pull buffer circuit having a switch for intermittent signal output, which supplies the reference signal held by the second sample-and-hold circuit to the AD conversion circuit.

37. The readout circuit according to claim 36, comprising a plurality of AD conversion circuits connected to mutually different first push-pull buffer circuits, wherein the plurality of AD conversion circuits are connected to the same second push-pull buffer circuit.

38. The readout circuit according to claim 36, further comprising a power supply noise cancellation signal generation unit that generates a power supply noise cancellation signal, wherein the second sample-and-hold circuit holds the power supply noise cancellation signal as the reference signal.

39. The readout circuit according to claim 36, wherein the second sample-and-hold circuit holds the signal output from a light-shielded pixel whose light-receiving surface is shielded as the reference signal.

40. The readout circuit according to claim 39, further comprising a gain adjustment unit provided between the second sample-and-hold circuit and the second push-pull buffer circuit for adjusting the gain of the reference signal.

41. The readout circuit according to claim 39, further comprising a reference voltage adjustment unit connected between the second sample-and-hold circuit and the second push-pull buffer circuit, which adjusts the voltage level of the reference signal.

42. The readout circuit according to claim 41, wherein the reference voltage adjustment unit adjusts the voltage level by capacitance division.

43. The readout circuit according to claim 39, wherein a plurality of light-shielding pixels are provided in regions adjacent in the pixel row direction to the effective pixel region in which the pixels are provided.

44. The readout circuit according to claim 39, wherein a plurality of light-shielding pixels are connected to the second sample-and-hold circuit.

45. The readout circuit according to claim 39, wherein a plurality of the second push-pull buffer circuits are connected to the AD conversion circuit.

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