A frequency multiplier arrangement and an IQ-mixer arrangement comprising the multiplier arrangement

Abstract

A multiplier arrangement (1000) for receiving an input signal and for generating a frequency multiplied output signal with a controllable phase, and an IQ-mixer arrangement (1100) comprising a first and a second of said multiplier arrangement (1000). The multiplier arrangement (1000) comprises a frequency multiplier circuit (210, 810, 1010) and a control circuit (1080). The frequency multiplier circuit (210, 810, 1010) comprises a transistor (250) configured to receive a supply voltage (VCC), to receive a bias voltage (Vtune, Vtune_I, Vtune_Q, Vtune_1, Vtune_), and to multiply the input signal to provide the frequency multiplied output signal. The control circuit (1080) is configured to: obtain first data indicative of a first target phase of the frequency multiplied output signal; and provide a specific bias voltage (Vtune, Vtune_I, Vtune_Q, Vtune_1, Vtune_2) to the transistor (250) based on the obtained first data.

Description

[0001] A FREQUENCY MULTIPLIER ARRANGEMENT AND AN IQ-MIXER ARRANGEMENT COMPRISING THE MULTIPLIER ARRANGEMENT

[0002] TECHNICAL FIELD

[0003] The present disclosure relates a multiplier arrangement for receiving an input signal and for generating a frequency multiplied output signal with a controllable phase. The present disclosure also relates to an IQ-mixer arrangement comprising the multiplier arrangement. The present disclosure further relates to an apparatus for wireless communications, the apparatus comprising the multiplier arrangement and / or the IQ-mixer arrangement.

[0004] BACKGROUND

[0005] Bitrate demands in wireless communications networks continue to increase. To increase performance in wireless communications networks, network nodes (such as base stations) and wireless devices (such as user equipments, UEs) may be built with beam-steering capabilities. A radio with beam-steering capabilities is built up using multiple transmit and receive units, where the amplitude and / or phase of each unit may be controlled so that the antenna diagram may be optimized for a radio link between a wireless device and a network node. Thus, efficient and practical ways of controlling the phase of a unit is desired.

[0006] In some implementations, a radio comprises a respective mixer (often a respective in-phase quadrature, IQ, mixer) for each transmit and receive unit, where each mixer is provided a local oscillator (LO) signal. The phase of each unit may be controlled by varying the phase of each local oscillator signal associated with each unit. Often, for each unit, a separate phase shifter component controls the phase of the LO signal (relative to other LO signals for the other units) independently.

[0007] The chain of components between the LO and the input of a mixer may be called an LO-chain. The LO-chain comprises the phase shifter component. The LO-chain may further comprise one or more amplifiers. For high- frequency radios, e.g., above 100 GHz, the LO-chain sometimes also comprises one or more frequency multipliers circuits. However, frequency multipliers circuits may also be present in LO-chains for frequencies lower than 100 GHz. Including a frequency multipliers circuit may improve overall performance compared to omitting the frequency multipliers circuit and directly generate the desired LO signal at the frequency of the LO.

[0008] One example of a frequency multipliers circuit is the injection locked frequency multiplier. R. Gannedahl et. al. discloses one example in "An LO phase shifter with frequency tripling and phase detection in 28 nm FD-SOI CMOS for mm-wave 5G transceivers”, Analog Integr Circ Sig Process, 114, 1-11 (2023).

[0009] Another example of a frequency multipliers circuit is the harmonic amplification multiplier, see, e.g., US6066997A. In the harmonic amplification multiplier, the transistor's nonlinearity is utilized to generate harmonics. The input signal at a frequency (fjn) is applied at the base / gate, and the output signal at a frequency of Nfn is taken from the collector / drain, where N is an integer, and is the multiplication factor. Yet another example of a frequency multipliers circuit is the mixer-based multiplier, see, e.g., US11929723B2, where two input signals are mixed, obtaining an output signal at the frequency equal to the sum the frequencies of the two input signals.

[0010] Controlling phase is desired for other purposes than beam-steering as well. For example, a phase shifter component may be used in an IQ-mixer for compensation of the possible phase imbalance, due to, e.g., layout asymmetry and process variation. An IQ-mixer may comprise of two mixers, an amplifier, and a variable gain amplifier (VGA), as well as the phase shifter component. The VGA is used to compensate the variation of the output power of the phase shifter. The two mixers are driven by LO signals with a 90° phase shift relative to each other.

[0011] An IQ-mixer may be a sub-harmonic IQ-mixer. In that case, two sub-harmonic mixers are driven by LO signals at frequency that is half of LO frequency. However, the performance of a sub-harmonic mixer is often inferior to a conventional mixer, in terms of conversion gain and linearity. Therefore, an LO chain comprised of a phase shifter and a frequency multipliers circuit to drive a conventional mixer is often preferred (in case it is undesired to directly generate the signals driving the mixers by the LO).

[0012] Thus, in some cases, an IQ-mixer is combined with an LO-chain arrangement. The LO-chain arrangement comprises a 45° divider that splits a single-ended signal into two output signals which have a 45° phase difference. Each of the output signals from the divider is fed into a respective frequency doubler, which doubles the frequency of the respective signals and feed the frequency multiplied signal into one of the I and Q mixers. Furthermore, a phase shifter component is used before one of the frequency doublers to provide a 90° phase difference between the signals fed into the respective mixers.

[0013] A phase shifter component may have different kinds of topologies, such as switch-type, reflection-type, vector- sum-type phase shifter, as well as injection-locked phase shifter. However, the phase shifter components will occupy chip area, introduce losses, noise, etc. Therefore, a circuit merging a phase shifter and a frequency doubler is proposed in US11929723B2. The phase variable frequency multiplier proposed in US11929723B2 consists of two mixers, at least, one VGA, as well as one 90° hybrid. This arrangement is associated with some complexity. Furthermore, a relatively large chip area may be required, and a relatively large power consumption may be required.

[0014] There is a need for improved ways of enabling phase control, for various purposes, in an apparatus for wireless communications networks. Particularly for applications targeting high frequencies, such as above 100 GHz. Furthermore, for IQ-mixer arrangements, it is desired to provide a phase tuning range, Acp, larger than 90° with some margin. Here, the phase tuning range, Acp, is defined as the phase difference between the maximum phase value, (pmax, and the minimum phase value, (pmin, i.e., Acp = pmax- pmir

[0015] SUMMARY It is an object of the present disclosure to mitigate, alleviate or eliminate one or more of the above-identified deficiencies and disadvantages in the prior art and solve at least the above-mentioned problem. In particular, an object is to provide improved ways of enabling phase control in apparatuses for wireless communications networks. This object is attained at least in part by a multiplier arrangement for receiving an input signal and for generating a frequency multiplied output signal with a controllable phase. The multiplier arrangement comprises a frequency multiplier circuit and a control circuit. The frequency multiplier circuit comprises a transistor configured to receive a supply voltage, to receive a bias voltage, and to multiply the input signal to provide the frequency multiplied output signal. The control circuit is configured to obtain first data indicative of a first target phase of the frequency multiplied output signal. The control circuit is also configured to provide a specific bias voltage the transistor based on the obtained first data.

[0016] The disclosed multiplier arrangement enables controlling the phase of the frequency multiplied output signal (i.e., controlling a specific value of the first target phase). Thus, the disclosed multiplier arrangement provides both frequency multiplication and phase control without requiring any additional phase shift components. The disclosed multiplier arrangement provides both frequency multiplication and phase control with a relatively low complexity. In some embodiments, the disclosed multiplier arrangement provides both frequency multiplication and phase control with a relatively low requirement of chip area and DC power consumption.

[0017] The first target phase may be in relation to a reference signal of the same frequency as the frequency multiplied output signal (i.e., a frequency which is a desired overtone of the input signal). In that case, the control unit may provide the specific bias voltage to the transistor such a specific phase difference (i.e., the first target phase) between the frequency multiplied output signal and the refence signal is obtained. The reference signal may, e.g., be an I or Q channel in an IQ-mixer in a neighboring LO chain.

[0018] In some embodiments, the frequency multiplier circuit is configured to provide a controllable phase of the frequency multiplied output signal within a phase tuning range. In that case, the first target phase may be a value within the phase tuning range.

[0019] In some embodiments, the disclosed multiplier arrangement provides a relatively large phase tuning range, with a relatively low variation of the power of the multiplied signal, across a relatively wide fractional bandwidth of the frequency multiplied output signal.

[0020] In some embodiments, the frequency multiplied output signal comprises a harmonic frequency of at least two times the fundamental frequency of the input signal. In particular, the frequency multiplier circuit may be a frequency doubler.

[0021] In some embodiments, the frequency multiplier circuit comprises an input port configured to receive the input signal and an output port configured to provide the frequency multiplied output signal. In some embodiments, the frequency multiplier circuit is configured such that the fundamental frequency of the input signal is suppressed at the output port. Alternatively, or in combination, the frequency multiplier circuit is configured such that one or more undesired harmonics are suppressed at the output port. An undesired harmonic is a harmonic different from a desired harmonic of the frequency multiplied output signal. For example, if the frequency multiplier circuit is a frequency doubler, the desired harmonic is the second harmonic. In that case, an undesired harmonic could be the third harmonic.

[0022] In some embodiments, the frequency multiplier circuit comprises an input network, for impedance matching of the transistor, arranged at an input terminal of the transistor. In this way, the transistor's performance may be improved. In particular, the input network may be configured such that a desired source impedance is presented to the transistor, at least for a fundamental frequency of the input signal. The source impedance may be selected such that the disclosed multiplier arrangement provides a relatively large phase tuning range, with a relatively low variation of the power of the multiplied signal, across a relatively wide fractional bandwidth of the frequency multiplied output signal.

[0023] In some embodiments, the frequency multiplier circuit comprises an output network, for impedance matching of the transistor, arranged at an output terminal of the transistor. In this way, the transistor's performance may be improved. In particular, the output network may be configured such that a desired load impedance is presented to the transistor, at least for a harmonic of interest frequency (such as two times the fundamental frequency of the input signal when the frequency multiplier circuit is a frequency doubler). The load impedance may be selected such that the disclosed multiplier arrangement provides a relatively large phase tuning range, with a relatively low variation of the power of the multiplied signal, across a relatively wide fractional bandwidth of the frequency multiplied output signal.

[0024] In some embodiments, the output network is configured to suppress the fundamental frequency of the input signal. Note that the transistor itself may, in some cases, output a signal which comprises several tones (including the fundamental tone and / or other undesired harmonics of the input signal), and that it may be desired filter the output of the transistor such that the frequency multiplier circuit only outputs energy (of a significant level) at a single (desired) overtone at an output port of the frequency multiplier circuit. Such filtering may be provided by having the output network configured to suppress the fundamental frequency and / or other (undesired) harmonics of the input signal.

[0025] In some embodiments, the transistor is a first transistor configured to receive a first supply voltage, to receive a first bias voltage, and to multiply the input signal to provide a first frequency multiplied output signal. The frequency multiplier circuit further comprises a second transistor configured to receive a second supply voltage, to receive a second bias voltage, and to multiply the input signal to provide a second frequency multiplied output signal. The output network is arranged at respective output terminals of the first and the second transistors and is configured to combine the first and the second frequency multiplied output signals. The first and the second bias voltages may be the same value, but different values are possible. The first and the second supply voltages may be the same value, but different values are possible. The first and the second transistors may be the same type and size, but different sizes and types are possible. In some embodiments, the first and the second transistors are arranged in a push-push configuration. In this way, undesired harmonics are suppressed at the output port of the frequency multiplier circuit. When the frequency multiplier is a frequency doubler, the push-push configuration may suppress the fundamental frequency and other odd-order harmonics at the output port.

[0026] In some embodiments, the frequency multiplier circuit further comprises a splitter configured to receive a single- ended signal, to convert the single-ended signal to a differential signal, and to provide respective parts of the differential signal to respective input terminals of the first and the second transistors. The splitter may, e.g., be a balun.

[0027] In some embodiments, the control circuit is configured to obtain data indicative of a first target phase comprised in a first set of different phases, and wherein the control circuit is configured to provide the specific bias voltage from a second set of different bias voltages. For example, the control unit may store (or may be configured to obtain) a first list of discrete possible target phases, and the first data may be configured to point to one of the values in the list. Furthermore, the control circuit may be configured to provide the specific bias voltage from a second set of different bias voltages. For example, the control unit may store (or may be configured to obtain) a second list of discrete possible bias voltage values, and the control unit may be configured to provide one of the values in the second list based on the first data. In some embodiments, the control circuit is configured to provide the specific bias voltage based on a look-up-table comprising the first and the second sets.

[0028] In some embodiments, the control circuit comprises processing circuitry and a digital to analog converter, wherein the processing unit is configured to obtain the first data and to provide the specific bias via the digital to analog converter.

[0029] In some embodiments, the frequency multiplier circuit is configured to provide a controllable phase, of the frequency multiplied output signal, in a range of at least 90 degrees across a fractional bandwidth, of the frequency multiplied output signal, of at least 10%, and preferably 15%, when the control circuit provides a specific bias voltage comprised in in the second set.

[0030] In some embodiments, the frequency multiplier circuit is configured to provide a power variation, of the frequency multiplied output signal, less than 1 dB, preferably less than 0.5 dB, across a fractional bandwidth, of the frequency multiplied output signal, of at least 10%, and preferably 15%, when the control circuit provides a specific bias voltage comprised in the second set.

[0031] In some embodiments, the transistor is a field effect transistor or a heterojunction bipolar transistor.

[0032] In some embodiments, the frequency multiplier circuit comprises a bias feed network for receiving the specific bias voltage and providing the specific bias voltage to the transistor. In some embodiments, the frequency multiplier circuit comprises a supply feed network for receiving the supply voltage and providing the supply voltage to the transistor. In some embodiments, the multiplier arrangement comprises a plurality of cascaded frequency multiplier circuits. Each frequency multiplier circuit comprises a respective transistor configured to receive a respective supply voltage, to receive a respective bias voltage, and to multiply a respective input signal to provide a respective frequency multiplied output signal. The control circuit is configured to provide respective specific bias voltage to the plurality of cascaded frequency multiplier circuits based on the obtained first data. The plurality of cascaded frequency multiplier circuits increases the phase tuning range compared to if only a single frequency multiplier circuit is used. In addition, such an arrangement increases the multiplication factor, which is often desired for high frequency transceivers.

[0033] There is also disclosed herein an IQ-mixer arrangement comprising a first and a second multiplier arrangement according to the discussions above. The IQ-mixer arrangement is associated with the above-discussed advantages. The IQ-mixer further comprises a first branch for in-phase mixing. The first branch comprises a first mixer and a frequency multiplier circuit of the first multiplier arrangement. The frequency multiplier circuit of the first multiplier arrangement is configured to provide a frequency multiplied output signal to the first mixer. The IQ- mixer also comprises a second branch for quadrature mixing. The second branch comprises a second mixer and a frequency multiplier circuit of the second multiplier arrangement. The frequency multiplier circuit of the second multiplier arrangement is configured to provide a frequency multiplied output signal to the second mixer. The control circuits of the first and the second multiplier arrangements are configured to provide respective specific bias voltages to the frequency multiplier circuits of the first and the second multiplier arrangements such that a second target phase, between the respective frequency multiplied output signals of the frequency multiplier circuits of the first and the second multiplier arrangements, is provided by the frequency multiplier circuits of the first and the second multiplier arrangements.

[0034] The IQ-mixer arrangement enables control of the phase difference of the respective frequency multiplied output signals (i.e., controlling a specific value of the second target phase). Thus, the disclosed IQ-mixer arrangement provides IQ-mixing without requiring any additional phase shift components. Furthermore, in some embodiments, disclosed IQ-mixer arrangement provides IQ-mixing without requiring a 45° divider before the frequency multiplier circuits of the first and the second multiplier arrangements. The disclosed IQ-mixer arrangement provides IQ- mixing with a relatively low complexity. In some embodiments, the disclosed IQ-mixer arrangement provides IQ- mixing with a relatively low requirement of chip area and DC power consumption.

[0035] In some embodiments of the IQ-mixer arrangement, the second target phase is 90 degrees.

[0036] In some embodiments of the IQ-mixer arrangement, the control circuits of the first and the second multiplier arrangements are integrated in a single unit.

[0037] Some embodiments of the IQ-mixer arrangement comprise a feedback arrangement configured to receive portions of the respective frequency multiplied output signals of the frequency multiplier circuits of the first and the second multiplier arrangements. The feedback arrangement is also configured to provide a control signal to the control circuits of the first and the second multiplier arrangements based on the received portions. The control circuits of the first and the second multiplier arrangements are configured to provide the respective specific bias voltages based on the provided control signal. In this way, a desired phase difference (such as 90°) between the respective frequency multiplied output signals of the frequency multiplier circuits may be maintained more accurately (e.g., in an automatic fashion). This may, e.g., be desired for compensation of layout asymmetry and process variation.

[0038] In some embodiments of the IQ-mixer arrangement, the feedback arrangement comprises a filter arrangement and a third mixer, wherein the third mixer is configured to mix the portions of the respective frequency multiplied output signals of the frequency multiplier circuits of the first and the second multiplier arrangements to provide a mixed signal, and wherein the filter arrangement is configured to filter the mixed signal to provide the control signal.

[0039] Some embodiments of the IQ-mixer arrangement comprise a first amplifier arranged between the frequency multiplier circuit of the first multiplier arrangement and the first mixer, and a second amplifier arranged between the frequency multiplier circuit of the second multiplier arrangement and the second mixer. At least one of the first and the second amplifiers is a variable gain amplifier (VGA).

[0040] The VGA may reduce any variation between the respective output powers of the frequency multiplier circuits of the first and the second multiplier arrangements.

[0041] Some embodiments of the IQ-mixer arrangement comprise a third multiplier arrangement, where the last frequency multiplier circuit of a plurality of cascaded frequency multiplier circuits of the third multiplier arrangement is configured to provide a frequency multiplied output signal to the respective frequency multiplier circuits of the first and the second multiplier arrangements.

[0042] In some embodiments of the IQ-mixer arrangement, the control circuits of the third multiplier arrangement is configured to provide respective specific bias voltages, to the respective frequency multiplier circuits of the third multiplier arrangement such that a third target phase of any of the frequency multiplied output signal of the frequency multiplier circuits of the first and the second multiplier arrangements is provided. In this way, control of the third target phase is provided without having to include additional phase shift components, which is an advantage.

[0043] In some embodiments, the control units of the first, the second, and the third multiplier arrangements are integrated in a single unit.

[0044] There is also disclosed herein an apparatus for wireless communications. The apparatus comprising the multiplier arrangement and / or the IQ-mixer according to the discussions above. The apparatus is associated with the above-discussed advantages. The apparatus may, e.g., be a network node or a wireless device.

[0045] BRIEF DESCRIPTION OF THE DRAWINGS With reference to the appended drawings, below follows a more detailed description of embodiments of the present disclosure cited as examples. In the drawings:

[0046] Figure 1 is a schematic illustration of a wireless communications network in which embodiments may operate;

[0047] Figures 2a and 2b show example frequency multiplier circuits according to embodiments;

[0048] Figure 3 is a schematic illustration of the output of a transistor according to embodiments;

[0049] Figure 4a shows phase of the output signal versus frequency for different bias voltages, for a first load termination in a first frequency range of the output signal according to embodiments;

[0050] Figure 4b shows phase tuning range versus frequency, for the first load termination in the first frequency range of the output signal according to embodiments;

[0051] Figure 4c shows output power versus frequency for different bias voltages, for the first load termination in the first frequency range of the output signal according to embodiments;

[0052] Figure 5a shows phase of the output signal versus frequency for different bias voltages, for a second load termination in the first frequency range of the output signal according to embodiments;

[0053] Figure 5b shows phase tuning range versus frequency, for the second load termination in the first frequency range of the output signal according to embodiments;

[0054] Figure 5c shows output power versus frequency for different bias voltages, for the second load termination in the first frequency range of the output signal according to embodiments;

[0055] Figure 6a shows phase of the output signal versus frequency for different bias voltages, for a third load termination in a second frequency range of the output signal according to embodiments;

[0056] Figure 6b shows phase tuning range versus frequency, for the third load termination in the second frequency range of the output signal according to embodiments;

[0057] Figure 6c shows output power versus frequency for different bias voltages, for the third load termination in the second frequency range of the output signal according to embodiments;

[0058] Figure 7a shows phase of the output signal versus frequency for different bias voltages, for a fourth load termination in a third frequency range of the output signal according to embodiments;

[0059] Figure 7b shows phase tuning range versus frequency, for the fourth load termination in the third frequency range of the output signal according to embodiments;

[0060] Figure 7c shows output power versus frequency for different bias voltages, for the fourth load termination in the third frequency range of the output signal according to embodiments;

[0061] Figures 8a and 8b show example frequency multiplier circuits according to embodiments; Figure 9a shows phase of the output signal versus frequency for different bias voltages, for the frequency multiplier circuit of Figure 8b in the first frequency range of the output signal;

[0062] Figure 9b shows phase tuning range versus frequency, for the frequency multiplier circuit of Figure 8b in the first frequency range of the output signal;

[0063] Figure 9c shows output power versus frequency for different bias voltages, for the frequency multiplier circuit of Figure 8b in the first frequency range of the output signal;

[0064] Figures 10a and 10b show example multiplier arrangements according to embodiments;

[0065] Figures 11a, 11b, and 12 show example IQ-mixer arrangements according to embodiments; and

[0066] Figure 13 is a schematic diagram showing functional modules of a control unit according to embodiments.

[0067] DETAILED DESCRIPTION

[0068] The present disclosure is described below with reference to the accompanying drawings, in which certain aspects of the present disclosure are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments and aspects set forth herein; rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. The same features are denoted by the same reference signs throughout the description.

[0069] It is to be understood that the present disclosure is not limited to the embodiments described herein and illustrated in the drawings; rather, the skilled person will recognize that many changes and modifications may be made within the scope of the appended claims.

[0070] Figure 1 depicts a wireless communications network 100 in which embodiments herein may operate. In some embodiments, the wireless communications network 100 may be a radio communications network, such as, sixth generation (6G), New Radio (NR), or NR+ telecommunications network. However, the wireless communications network 100 may also employ technology of any one of third / fourth / fifth generation, Long Term Evolution (LTE), LTE-Advanced, Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Ultra Mobile Broadband (UMB), or any other similar network or system. The wireless communications network 100 may also employ technology transmitting on millimeter-waves (mmW), such as, e.g., an ultra-dense network (UDN). In some embodiments, the wireless communications network 100 may also employ transmissions supporting WiFi transmissions, e.g., the wireless communications standard IEEE 802.11 ad or similar, or other non-cellular wireless transmissions.

[0071] The wireless communications network 100 comprises a network node 110. The network node 110 may serve wireless devices in at least one cell 115, or coverage area. The network node 110 may correspond to any type of network node or radio network node capable of communicating with a wireless device and / or with another network node, such as, a base station (BS), a radio base station, gNB, eNB, eNodeB, a Home NodeB, a Home eNodeB, a femto BS, or a pico BS in the wireless communications network 100. Further examples of the network node 110 may be a node for wireless backhaul, wireless fronthaul, repeater, multi-standard radio (MSR) radio node such as MSR BS, network controller, radio network controller (RNC), base station controller (BSC), relay, donor node controlling relay, base transceiver station (BTS), access point (AP), transmission points, transmission nodes, a remote radio unit (RRU), a remote radio head (RRH), nodes in distributed antenna system (DAS), or core network node. The network node 110 may be arranged to communicate with a remote data processing unit 140, e.g., via a core network 150 of the wireless communications network 100. The remote data processing unit 140 may, for example, be a remote standalone server, a cloud-implemented server, a distributed server, dedicated data processing resources in a server farm, or similar.

[0072] As is also shown in Figure 1, a wireless device 121 is located within the cell 115. The wireless device 121 is configured to communicate within the wireless communications network 100 via the network node 110 over a radio link served by the network node 110. The wireless device 121 may transmit data over an air or radio interface to the network node 110 in uplink (UL), transmissions 132 and the radio base station may transmit data over an air or radio interface to the wireless device 121 in downlink (DL) transmissions 131. The wireless device 121 may refer to any type of wireless devices or user equipment (UE) communicating with a network node and / or with another wireless device in a cellular, mobile or radio communication network or system. Examples of such wireless devices are mobile phones, cellular phones, personal digital assistants (PDAs), smart phones, tablets, sensors equipped with a UE, laptop mounted equipment (LME) (e.g. universal serial bus, USB), laptop embedded equipment (LEE), machine type communication (MTC) devices, or machine to machine (M2M) device, customer premises equipment (CPE), target device, device-to-device (D2D) wireless device, wireless device capable of machine to machine (M2M) communication.

[0073] As mentioned, it is desired to provide improved ways of enabling phase control in apparatuses for wireless communications networks. Thus, there is disclosed herein a multiplier arrangement with a controllable (which may also be called "variable”) phase of a frequency multiplied output signal. The multiplier arrangement comprises a frequency multiplier circuit. The frequency multiplier circuit is an electronic circuit that generates an output signal, where the frequency of the output signal is a harmonic (multiple) of the frequency of the input signal. The frequency multiplier circuit comprises a transistor. The transistor may, e.g., be based on common- emitter / source configurated transistors, i.e., the harmonic amplification-type multiplier. The multiplier arrangement also comprises a control unit. The control unit, according to some aspects, acts as a voltage regulator and provides a tunable bias voltage, VtUne, to the base / gate of the transistor. The transistor may be a field-effect transistor (FET), which comprises a gate, a drain, and a source. Alternatively, the transistor may be a heterojunction bipolar transistor (HBT), which comprises a base, a collector, and an emitter. In some embodiments, the frequency multiplier circuit is configured to provide a controllable phase of the frequency multiplied output signal within a phase tuning range. Some embodiments disclosed herein present more than 100° phase tuning range by selectively changing the tunable bias voltage, Vtune, by the control unit. A particular bias voltage, Vtune, may, according to some aspects, be selected by the control unit based on look-up-table.

[0074] Figures 2a shows an example of a frequency multiplier circuit 210. The frequency multiplier circuit 210 comprises a single transistor 250. There is a first inductor L connected in parallel at the input port of the transistor 250 and second inductor L connected in parallel at the output port of the transistor 250. The first and the second inductors act as ideal bias feed networks, which present an open circuit for RF and a short circuit for DC. There is a first capacitor C connected in series at the input port of the transistor 250 and second capacitor C connected in series at the output port of the transistor 250. The first and the second capacitors act as ideal DC blocks, which present a short circuit for RF and an open circuit for DC. An input port 211 of the frequency multiplier circuit 210 has a resistive load termination Rs. There is also a reactance Xs connected in parallel with the load termination Rs. The impedance presented to the input of the transistor is thus Rs in parallel with Xs, which is denoted Rs II Xs. An output port 212 of the frequency multiplier circuit 210 has a resistive load termination RL. There is also a reactance XL connected in parallel with the load termination RL. The impedance presented to the output of the transistor is thus RL in parallel with XL, which is denoted RL II XL. The transistor 250 is provided with a supply voltage Vcc, which a DC voltage, via the second inductor L. In Figure 2A, the transistor 250 is provided with bias voltage VtUne, which a DC voltage, via the first inductor L.

[0075] Figure 2b shows a similar frequency multiplier circuit 210, where the first inductor L has been replaced with a via so called "current mirror”. The current mirror acts as a bias feed network, and includes a diode-connected transistor 251 (connected collector and base), a resistor R, as well as a transmission line TL at the emitter. The transmission line TL is used to increase the impedance at the diode branch to reduce the leakage of the input signal at the diode branch. In this case, the bias voltage VtUne is supplied via the resistor R.

[0076] The frequency multiplier circuit 210 (of Figure 2a and 2b) is configured to receive an input signal at the input port 211 , and to multiply the input signal to provide a frequency multiplied output signal at the output port 212. The input signal may be a single tone signal with a frequency fjn. The output signal comprises at least one (desired) overtone of the input signal. Thus, the output signal (at the output port 212) comprises at least a tone of frequency fout, which may be expressed as fout = nfin, where n is a natural number larger than one. Note that the transistor 250 itself may output a signal which comprises several tones (including the fundamental tone), and that it may be desired to filter the output of the transistor such that the frequency multiplier circuit 210 only outputs energy (of a significant level) at a single (desired) overtone at the output port 212. Different filtering arrangements and techniques for such purposes is discussed further below herein. The phase of the frequency component fout is denoted (pout. Figure 3 shows a schematic overview of a model of the output part 351 of the transistor 250, connected to the resistive load termination R and the reactance X . The output part 351 comprises a current source 352, which provides a current as a function of the signal at the input of the transistor. The output part 351 also comprises a parasitic capacitance Cpconnected in parallel to ground.

[0077] The phase (pout of the multiplier arrangement 210 may be tuned by selectively changing the value of the bias voltage VtUne. In other words, a particular value of VtUne results in a particular value of (pout. By changing the value of the bias voltage VtUne, the capacitive value of the transistor's parasitic capacitance Cpat its output (such as between collector and the ground) will be changed. This capacitive value affects the phase at the resistive load termination.

[0078] Below (in Figures 4-7), some performance metrics for multiplier arrangement 210 (as shown in Figure 2A), acting as a frequency doubler, are presented. These performance metrics are simulated using a model of a transistor in a 90 nm Heterojunction Bipolar Transistor (HBT) SIGe technology. In these simulations, it is assumed that the source / load impedance is the same for the fundamental frequency and all harmonics, but it is not a requirement. Note that in general, the impedance presented to the input of the transistor 250 is Rs II Xs at least for the fundamental frequency of the input signal. Also note that the impedance presented to the output of the transistor 250 is RL II XL at least for the harmonic of interest (i.e., fout = nfin).

[0079] Figures 4a, 4b, and 4c

[0080] Figures 4a-4c show simulations of different metrics versus frequency for different bias voltages, for a first load termination in a first frequency range of the output signal. In particular, Figure 4a shows phase of the output signal versus frequency for different bias voltages, Figure 4b shows phase tuning range versus frequency due to the variation of the different bias voltages, and Figure 4c shows output power versus frequency for different bias voltages.

[0081] In these simulations, the frequency of the input signal (fin) varies from 65-80 GHz, correspondingly, the frequency of the output signal (fout) changes from 130 - 160 GHz. The power of the input signal is 7.8 dBm. When targeting a maximum output power / gain of the particular transistor in the simulations, the following impedances are found

[0082] Rs=11.3 Q, Xs=4.26 Q and RL=51.5 Q, XL=21.1 Q (1)

[0083] Furthermore, in this example, the following voltage tuning range is identified for the bias voltage: a minimum value of Vtune, min = 791 mV to a maximum value of Vtune,max = 883 mV. This corresponds to a voltage tuning range of 93 mV. Figure 4a shows the phase ((pout) of the output signal for different bias voltages in the range of VtUne,min to Vtune, max. Even though the phase may be tuned continuously, Figure 4a plots phases for Vtune equal to 791 mV, 814 mV, 837 mV, 860 mV, and 884 mV (with a step of 23.2 mV) only. The DC collector current is varied from 51 mA to 75 mA. As can be seen in Figure 4b, within the frequency range from 130 GHz to 160 GHz, the phase tuning range varies from 104° to 117°. The average phase tuning range is 110.5°. This frequency doubler's output power depends on VtUne and frequency, as shown in Figure 4c. At an output frequency of 130 GHz, the output power changes between 5.68 and 8.08 dBm (AP=2.40 dB), and the conversion gain varies between -2.12 dB and 0.28 dB. At frequency of 160 GHz, the output power varies between 5.93 and 7.15 dBm (AP=1.22 dB), and the conversion gain varies between -1.87 dB and -0.65 dB. From 130 GHz to 160 GHz, as the frequency increasing, the average output power decreases from 7 dBm to 6.5 dBm, and the average conversion gain decreases from -0.8 dB to -1 .3 dB. This frequency doubler has an efficiency, defined as Equation (2) below, varying between 4.54% and 5.59%. where Poutand Pinare output power at the frequency of the second harmonic and input power at the fundamental frequency, respectively. PDCis the DC power consumption of the multiplier circuit.

[0084] It is possible to reduce the variation of the output power by reducing the voltage tuning range. However, this would lead to a reduction in the phase tuning range. Thus, different values of load and source terminations, as well as biases are explored below.

[0085] Figures 5a-5c show simulations of different metrics versus frequency for different bias voltages, for a second load termination in the first frequency range of the output signal. In particular, Figure 5a shows phase of the output signal versus frequency for different bias voltages, Figure 5b shows phase tuning range versus frequency due to the variation of the different bias voltages, and Figure 5c shows output power versus frequency for different bias voltages.

[0086] It is possible to search for source and load impedances (Rs, Xs, RL, and XL), as well as maximum and minimum values (extreme values) of bias tuning voltage (Vtune, min and VtUne,max), to make sure that the phase tuning range is kept (> 100°), but the variation of the output power is reduced, at a cost of decreasing the output power / conversion gain.

[0087] Similar to Figures 4a-4c, in these simulations, the frequency of the input signal (fn) varies from 65-80 GHz, correspondingly, the frequency of the output signal (fout) changes from 130 - 160 GHz. The power of the input signal is 7.8 dBm. Furthermore, the 93-mV voltage tuning range of the bias voltage is kept.

[0088] To find suitable impedances, a design procedure similar to a load-pull simulation in power amplifier (PA) design may be used, where the transistor's source and load impedances are swept. However, the targets in PA design are normally maximum output power at the fundamental frequency and highest possible power added efficiency (PAE). For the frequency multiplier circuit, however, the targets may be selected as the largest phase tuning range and the smallest variation of output power at the second harmonics (when the frequency multiplier circuit is a doubler). Besides, the extreme values of VtUne are swept too. All sweeps are performed within a certain frequency band of the output signal (130 GHz to 160 GHz). In the example of Figures 5a-5c, the obtained VtUne,min and Vtune.max are 620 mV and 714 mV, respectively, and the source / load impedance for the fundamental and harmonics are

[0089] Rs=15.8 Q, Xs=6.44 Q and RL=109.6 Q, XL=24.2 Q (3)

[0090] In the frequency range from 130 GHz to 160 GHz, the phase at different VtUne (620 mV, 644 mV, 667mV, 690 mV and 714 mV) is plotted in Figure 5a. As can be seen in Figure 5b, across the frequency band (130-160 GHz), the average phase tuning range is 107°. The variation of the phase tuning range is about 6 °, which is less than a half of that of the example of Figures 4a-4c. As can be seen in Figure 5c, the maximum variation of the output power occurs at output frequency of 130 GHz, the output power varies between 5.24 and 5.92 dBm (AP=0.68 dB), and the conversion gain changes between -2.56 dB and -1 .88 dB. The minimum variation of the output power occurs at frequency of 140 GHz, the output power varies between 5.48 and 5.73 dBm (AP=0.25 dB), and the conversion gain varies between -2.32 dB and -2.07 dB. Across frequency range from 130 GHz to 160 GHz, the average output power is about 5.6 dBm, and the average conversion gain is about -2.2 dB. The efficiency of this doubler varies between 4.7% and 11 .8%.

[0091] Compared to the example of Figures 4a-4c, the variation of the output power is shrunken significantly. The cost of minimizing the variations is that the average output power is reduced from 6.5 dBm-7 dBm to about 5.6 dBm.

[0092] The average conversion gain is reduced from -1.32 dB~-0.8 dB to about -2.2 dB.

[0093] The example of Figures 4a-4c provides a larger output power / gain than the example of Figures 5a-5c. However, the variation of the output power is larger for the example of Figures 4a-4c than for the example of Figures 5a-5c.

[0094] For the examples of Figures 4-5, the output frequency bandwidth is 30 GHz with a fractional bandwidth of 20.7%. Below, extending the bandwidth of the frequency multiplier circuit's output frequency to 50 GHz (from 120 GHz to 170 GHz), with a fractional bandwidth of 34.5%, is presented.

[0095] Fiqures 6a, 6b, and 6c

[0096] Figures 6a-6c show simulations of different metrics versus frequency for different bias voltages, for a third load termination in a second frequency range of the output signal. In particular, Figure 6a shows phase of the output signal versus frequency for different bias voltages, Figure 6b shows phase tuning range versus frequency due to the variation of the different bias voltages, and Figure 6c shows output power versus frequency for different bias voltages.

[0097] In these simulations, the frequency of the input signal (fin) varies from 60-85 GHz, correspondingly, the frequency of the output signal (fout) changes from 120 - 170 GHz. The power of the input signal is 7.8 dBm. When targeting a largest possible phase tuning range and smallest variation of output power at the second, for the frequency range 120 - 170 GHz, the following impedances are found

[0098] Rs=10.74 Q, Xs=9.34 Q and RL=124.3 Q, XL=24.5 Q (4) The voltage tuning range is 135 mV which is larger than that of the examples of Figures 4-5. Figure 6a plots the phase of the wide-bandwidth doubler at different Vtune. As can be seen in Figure 6b, from 120 GHz to 170 GHz, the phase tuning range varies between 101.8° and 107.5°, and the average phase tuning range is 104.5 °, which is comparable to the narrow-bandwidth doubler of Figure 5. But, as shown in Figure 6c, the variation of the output power increases, they are 0.89 dB and 0.77 dB, at 120 GHz and 170 GHz, respectively. Across the frequency range from 120 GHz to 170 GHz, the average output power varies between 4.4 dBm and 4.8 dBm, and the average conversion gain varies between -3.4 dB and -3.0 dB, which is lower than that of -2.2 dB for the example of Figures 5a-5c. The efficiency of the wideband doubler varies between 3.85% and 9.80%.

[0099] The frequency doublers mentioned above (Figures 4-6) operate with an input frequency of 65-80 GHz (which is doubled). Below, a phase variable frequency doubler operating at an input frequency of 16.25 to 20 GHz, and an output frequency of 32.5 to 40 GHz (a fractional bandwidth of 20.7%) is demonstrated.

[0100] Figures 7a-7c show simulations of different metrics versus frequency for different bias voltages, for a fourth load termination in a third frequency range of the output signal. In particular, Figure 7a shows phase of the output signal versus frequency for different bias voltages, Figure 7b shows phase tuning range versus frequency due to the variation of the different bias voltages, and Figure 7c shows output power versus frequency for different bias voltages.

[0101] When optimal VtUne,min and VtUne,maxare equal to 590 mV and 697 mV, respectively, and the source / load impedance for the fundamental and harmonics are equal to

[0102] Rs=6.7 Q, Xs=6.3 Q and RL=76 Q, XL=40.8 Q (5) and the input power of the frequency doubler is 5.8 dBm, this frequency doubler has a similar performance to a frequency doubler operating at input frequency of 65-80 GHz, but has a better conversion gain.

[0103] As can be seen in Figures 7a and 7b, the phase tuning range is changed from 103° to 110° across the output frequency range from 32.5 to 40 GHz. The average phase tuning range is 106.5°. As can be seen in Figure 7c the maximum variation of the output power is 0.6 dB, which occurs at output frequency equal to 32.5 GHz. The average output power is 5.6 dBm, and the average gain is -0.2 dB which is 2 dB higher than the example of Figures 5a-5c. The efficiency increases from 7.6% to 20% when the VtUne decreases from 697 mV to 590 mV.

[0104] Figures 8a and 8b

[0105] Figures 8a and 8b show examples of frequency multiplier circuits 810 comprising two transistors 250-1, 250-2 in a push-push configuration. These example circuits are frequency doublers and operate with an output frequency range from 130 to 160 GHz. The push-push configuration suppresses undesired fundamental and other odd-order harmonics at the output port 212. In Figures 8a and 8b, a balun (called "balun” in both figures, and has the reference number 873 in Figure 8b) transfers a single-ended input signal into two differential signals to drive two transistors 250-1, 250-2 separately. The outputs from two transistor's 250-1, 250-2 are connected, forming a single-ended output. The odd-order harmonics at the two transistor outputs have the same amplitude but have a 180° phase difference. Consequently, the fundamental and the odd-order harmonics will be cancelled at the output of the frequency multiplier circuit 810. In contrast, the even-order harmonics generated by two transistors have the same amplitude and the same phase, thus, the even-order harmonics are added constructively.

[0106] For a frequency doubler, the fundamental and the third harmonic are the undesired harmonics with a relatively large power, and these frequency components are the neighboring harmonics of the second harmonic (i.e., the desired harmonic for a frequency doubler). Fortunately, both the fundamental and the third harmonic may be cancelled in the push-push configuration, and the remaining 4thharmonic and other higher-order harmonics have a lower amplitude and at frequencies above the doubler's output frequency band. Thus, any filter at the output may be omitted thanks to the push-push configuration.

[0107] In Figure 8a, the frequency multiplier circuit 810 comprises two transistors 250-1, 250-2. For each transistor 250- 1, 250-2, there is a first inductor L connected in parallel at the input port of the transistor and second inductor L connected in parallel at the output port of the transistor. The first and the second inductors act as ideal bias feed networks, which present an open circuit for RF and a short circuit for DC. For each transistor 250-1, 250-2, there is a first capacitor C connected in series at the input port of the transistor and second capacitor C connected in series at the output port of the transistor. The first and the second capacitors act as ideal DC blocks, which present a short circuit for RF and an open circuit for DC. Each transistor 250-1, 250-2 is provided with a supply voltage Vcc, which a DC voltage, via the respective second inductor L. Each transistor is 250 is provided with bias voltage VtUne, which a DC voltage, via the respective first inductor L. Normally, each transistor 250-1, 250-2 may be supplied with the same supply voltage Vcc. However, the transistor 250-1, 250-2 alternatively be supplied with different supply voltages. Normally, each transistor 250-1, 250-2 may be provided with the same bias voltage However, the transistor 250-1, 250-2 alternatively be provided with different bias voltages.

[0108] In Figure 8a, an input port 211 of the frequency multiplier circuit 810 has a resistive source termination 811 of 50 Ohm. The balun provides respective parts of a differential signal to respective input terminals of the transistors 250-1, 250-2. Furthermore, there are two respective input matching networks (IMNs) for each transistor 250-1, 250-2. However, these two IMNs may be combined into a single network. The respective IMNs are configured such that the impedance presented to the input of each transistor 250-1, 250-2 is Rs II Xs. Furthermore, in Figure 8a, an output port 212 of the frequency multiplier circuit 810 has a resistive load termination of 50 Ohm. There are two respective output matching networks (OMNs) for each transistor 250-1, 250-2. However, these two OMNs may be combined into a single network. The respective OMNs are configured such that the impedance presented to the output of each transistor 250-1, 250-2 is RL II XL. The output of each OMN is combined and provided to the output port 212. The frequency multiplier circuit 810 is configured to receive an input signal at the input port 211 , and to multiply the input signal to provide a frequency multiplied output signal at the output port 212. The input signal may be a single tone signal with a frequency fin. The output signal comprises at least one (desired) overtone of the input signal, which is an even-order harmonic. Thus, the output signal comprises at least a tone of frequency fout, which may be expressed as fout = 2nfjn, where n is a natural number equal or larger than one. Note that the transistors 250-1, 250-2 may output respective signal which comprises even-order harmonics, and that it may be desired filter the output of the transistor such that the frequency multiplier circuit 210 only outputs energy (of a significant level) at a single even-order harmonic. As mentioned, the push-push configuration suppresses the fundamental and odd-order harmonics at the output port 212, and the energy of the 4thharmonic and higher even-order harmonics is relatively low.

[0109] Figure 8b shows a similar topology as Figure 8a, where the balun, the IMNs, the OMNs, biasing networks, and supply networks have been replaced with practical components. The OMNs are combined into a single structure, and comprises transmission lines (TLci, TLC2, TLca) and a capacitor (Cout), and is configured to present RL II XL at the output of each transistor 250-1 , 250-2. The IMNs are combined into a single structure, and comprises transmission lines (TLbi, TLb2, TUa) and two capacitors (Cbi and Cb2), and is configured to present Rs II Xs at the input of each transistor 250-1, 250-2. Each transistor 250-1 , 250-2 is provided with a supply voltage Vcc, which is a DC voltage, via the respective transmission line TLb2. Each transistor 250 is provided with bias voltage VtUne, which is a DC voltage, via the respective transmission line TLbi.

[0110] Below, different performance metrics for the frequency multiplier circuit of Figure 8b are presented.

[0111] Figures 9a, 9b, and 9c

[0112] Figures 9a-9c show simulations of different metrics versus frequency for different bias voltages, for the frequency multiplier circuit of Figure 8b. In particular, Figure 9a shows phase of the output signal versus frequency for different bias voltages, Figure 9b shows phase tuning range versus frequency due to the variation of the different bias voltages, and Figure 9c shows output power versus frequency for different bias voltages.

[0113] The frequency multiplier 810 acts as a frequency doubler. Similar to the examples of Figures 4-7, the performance metrics are simulated using a model of a transistor in a 90 nm Heterojunction Bipolar Transistor (HBT) SiGe technology. In these simulations, the frequency of the input signal (fn) varies from 65-80 GHz, correspondingly, the frequency of the output signal (fout) changes from 130 - 160 GHz. The input power is 11 dBm and the bias voltage Vtune is swept from 554 mV to 684 mV.

[0114] At the output port 812, the power of the fourth-order harmonic is at least 12 dB lower than the second harmonic. The phase of the output signal at different Vtune is plotted in Figure 9a, and the phase tuning range versus output frequency (130 GHz to 160 GHz) is shown in Figure 9b. The average phase tuning range is 106° which is similar to the performance of the example of Figures 5a-5c. The phase tuning range varies from 102° to 110° in the frequency band of 130 GHz to 160 GHz. Meanwhile, the maximum variation of the output power due to changing Vtune is 0.4 dB at 130 GHz and 160 GHz, as shown in Figure 9c, which is less than that for the example of Figures 5a-5c. Across the frequency range from 130 GHz to 160 GHz, the average output power changes from 8.75 dBm to 8.95 dBm, correspondingly, the average conversion gain varies from -2.25 dB to -2.05 dB. The efficiency varies between 3.5% and 5.5%.

[0115] Figure 10a

[0116] As is shown in Figures 4-9, a frequency multiplier circuit comprising a transistor may provide a controllable phase of the frequency multiplied output signal. Thus, with reference to the example of Figure 10a, there is disclosed herein a multiplier arrangement 1000 for receiving an input signal and for generating a frequency multiplied output signal with a controllable phase. The multiplier arrangement 1000 comprises a frequency multiplier circuit 1010 and a control circuit 1080. In Figure 10a, the there is a frequency multiplier circuit 1010. However, the frequency multiplier circuit 210 or 810, or other frequency multiplier circuits, could alternatively be used. In general, the frequency multiplier circuit comprises a transistor 250 configured to receive a supply voltage Vcc, to receive a bias voltage VtUne, and to multiply the input signal to provide the frequency multiplied output signal. In general, the frequency multiplier circuit comprises one or more transistors 250. The transistor 250 may for example be a field effect transistor or a heterojunction bipolar transistor.

[0117] The frequency multiplier circuit 210, 810, 1010 is configured to receive the input signal at the input port 211 , and to multiply the input signal to provide the frequency multiplied output signal at the output port 212. The input signal may be a single tone signal with a frequency fjn. The output signal at the output port 212 comprises at least one (desired) overtone of the input signal. Thus, the output signal comprises at least a tone of frequency fout, which may be expressed as fout = nfin, where n is a natural number larger than one. In other words, according to some aspects, the frequency multiplied output signal comprises a harmonic frequency of at least two times the fundamental frequency of the input signal. The phase of the frequency component fout is denoted (pout.

[0118] In Figure 10a, the input port 211 of the frequency multiplier circuit 1010 has a resistive load termination 811 of 50 Ohm and output port 212 of the frequency multiplier circuit 1010 has a resistive load termination 812 of 50 Ohm. In general, however, other port impedances are possible.

[0119] As is shown in Figure 10a, the frequency multiplier circuit 1010 may comprise an input network 1022, for impedance matching of the transistor 250, arranged at an input terminal of the transistor 250. The input network 1022 may be an IMN. The input network 1022 may be arranged such that a specific impedance is presented to the input of the transistor 250, such as RsII Xs, at least for the fundamental frequency of the input signal.

[0120] In Figure 10a, there is a first inductor L connected in parallel at the input port of the transistor 250. The first inductor acts as an ideal bias feed network, which presents an open circuit for RF and a short circuit for DC. There is a first capacitor C connected in series at the input port of the transistor 250. The first capacitor acts as an ideal DC block, which presents a short circuit for RF and an open circuit for DC. In general, however, the frequency multiplier circuit 210, 810, 1010 may comprise a bias feed network for receiving the specific bias voltage Vtune and providing the specific bias voltage VtUne to the transistor 250. The bias feed network may be implemented by the first inductor L in Figure 10a. However, other implementations are also possible, such as the bias feed network shown in Figure 8b. Also note that an ideal DC block is not required; a practical implementation is also possible (such as a capacitor component). Furthermore, the bias feed network may be implemented as a separate network as the input network 1022, or be integrated into a single network together with the input network 1022.

[0121] As is shown in Figure 10a, the frequency multiplier circuit 1010 may comprise an output network 1021, for impedance matching of the transistor 250, arranged at an output terminal of the transistor 250. The output network 1021 may be an OMN. The output network 1021 may be arranged such that a specific impedance is presented to the output of the transistor 250, such as R II X , at least for the harmonic frequency of interest (such as the second harmonic of the input signal when the frequency multiplier circuit is a frequency doubler).

[0122] The transistor 250 itself may output a signal which comprises several tones (including the fundamental tone), and that it may be desired suppress the output of the transistor such that the frequency multiplier circuit 210 only outputs energy (of a significant level) at a single (desired) overtone at the output port 212. Thus, the output network 1021 may be configured to suppress a fundamental frequency of the input signal. In other words, the output network 1021 may comprise or act as a filter. The filter may be configured to suppress a fundamental frequency of the input signal and possibly also other undesired harmonics. For example, if the frequency multiplier circuit 210, 810, 1010 is a frequency doubler, the filter may be configured to suppress the fundamental and / or third harmonic (and possibly also higher harmonics than the third harmonic). Furthermore, the filter may be implemented as a separate network as the output network 1021 , or be integrated into a single network together with the output network 1021. In the example of Figure 10a, the output network 1021 is a single network providing output matching and filtering.

[0123] In Figure 10a, there is a second inductor L connected in parallel at the output port of the transistor 250. The second inductor acts as ideal bias feed network, which presents an open circuit for RF and a short circuit for DC. There is a second capacitor C connected in series at the output port of the transistor 250. The second capacitor acts as an ideal DC block, which presents a short circuit for RF and an open circuit for DC.

[0124] In general, however, the frequency multiplier circuit 210, 810, 1010 may supply feed network for receiving the supply voltage Vcc and providing the supply voltage Vcc to the transistor 250. The supply feed network may be implemented by the second inductor L in Figure 10a. However, other implementations are also possible, such as the supply feed network shown in Figure 8b. Also note that an ideal DC block is not required; a practical implementation is also possible (such as a capacitor component). Furthermore, the supply feed network may be implemented as a separate network as the output network 1021 , or be integrated into a single network together with the output network 1021. As mentioned, the multiplier arrangement 1000 comprises a control circuit 1080 (called "CTRL” in Figure 10a). The control circuit 1080 is configured to obtain first data indicative of a first target phase of the frequency multiplied output signal. The control circuit 1080 is also configured to provide a specific bias voltage VtUne to the transistor 250 based on the obtained first data. In other words, the control unit 1080 receives data, which may indicate a specific value of (pout , and subsequently provides a specific value of VtUne to the transistor 250 based on the specific value of (pout ■ Different hardware implementations of the control unit are discussed below in connection to Figure 13.

[0125] The first target phase may be in relation to a reference signal of the same frequency as the frequency multiplied output signal (i.e., a frequency which is a desired overtone of the input signal). In that case, the control unit 1080 may provide the specific bias voltage VtUne to the transistor 250 such a specific phase difference (i.e., the first target phase) between the frequency multiplied output signal and the refence signal is obtained.

[0126] In some embodiments, the frequency multiplier circuit 210, 810, 1010 is configured to provide a controllable phase of the frequency multiplied output signal within a phase tuning range. In that case, the first target phase may be a value within the phase tuning range.

[0127] When the transistor is provided with a first value of the bias voltage, the phase of the frequency multiplied output signal (at a frequency which is a desired overtone of the input signal) has a first value. When the transistor is provided with a second value of the bias voltage, which is different from the first value of the bias voltage, the phase of the frequency multiplied output signal (at the frequency which is the desired overtone of the input signal) has a second value, which is different from the first value of the phase. Thus, in some embodiments, the control unit 1080 may provide the specific bias voltage Vtune to the transistor 250 such a specific phase difference (i.e., the first target phase) between the frequency multiplied output signal when specific bias voltage VtUne is provided compared to when a previous value of the bias voltage was provided.

[0128] In some embodiments, the control circuit 1080 is configured to obtain data indicative of a first target phase comprised in a first set of different phases. For example, the control unit may store (or may be configured to obtain) a first list of discrete possible target phases, and the first data may be configured to point to one of the values in the list. The first set of different phases may, e.g., be in relation to each other within the phase tuning range. For example, one of the values may be a reference phase, and the other values may be phases in relation to that reference.

[0129] Furthermore, the control circuit 1080 may be configured to provide the specific bias voltage Vtune from a second set of different bias voltages. For example, the control unit may store (or may be configured to obtain) a second list of discrete possible bias voltage values, and the control unit may be configured to provide one of the values in the second list based on the first data. In some embodiments, the control circuit 1080 is configured to provide the specific bias voltage VtUne based on a look-up-table comprising the first and the second sets.

[0130] In some embodiments, the frequency multiplier circuit 210, 810, 1010 is configured to provide a controllable phase, of the frequency multiplied output signal, in a range of at least 90 degrees across a fractional bandwidth, of the frequency multiplied output signal (i.e. , fout), of at least 10%, and preferably 15%, when the control circuit 1080 provides a specific bias voltage Vtune comprised in in the second set.

[0131] In some embodiments, the frequency multiplier circuit 210, 810, 1010 is configured to provide a power variation, of the frequency multiplied output signal, less than 1 dB, preferably less than 0.5 dB, across a fractional bandwidth, of the frequency multiplied output signal, of at least 10%, and preferably 15%, when the control circuit 1080 provides a specific bias voltage VtUne comprised in the second set.

[0132] As mentioned, frequency multiplier circuit may comprise two transistors. For example, the frequency multiplier circuit may comprise transistors in a push-push configuration according to any of the examples in Figures 8a and 8b. In general, in some embodiments of the multiplier arrangement 1000, the transistor according to the discussions above is a first transistor 250-1 configured to receive a first supply voltage Vcc, to receive a first bias voltage Vtune, and to multiply the input signal to provide a first frequency multiplied output signal. Furthermore, the frequency multiplier circuit 210, 810, 1010 also comprises a second transistor 250-2 configured to receive a second supply voltage Vcc, to receive a second bias voltage VtUne, and to multiply the input signal to provide a second frequency multiplied output signal. The first and the second bias voltages may be the same value (provided by the control unit 1080), but different values are possible. The first and the second supply voltages may be the same value, but different values are possible. The first and the second transistors may be the same type and size, but different sizes and types are possible. In addition, the output network 821 is arranged at respective output terminals of the first and the second transistors 250-1 , 250-2 and is configured to combine the first and the second frequency multiplied output signals. Optionally, the first and the second transistors 250-1 , 250-2 are arranged in a push-push configuration. Optionally, the frequency multiplier circuit 210, 810, 1010 further comprises a splitter 873 configured to receive a single-ended signal, to convert the single-ended signal to a differential signal, and to provide respective parts of the differential signal to respective input terminals of the first and the second transistors 250-1 , 250-2. The splitter 873 may, e.g., comprise a balun.

[0133] Figure 10b

[0134] Figure 10b shows a multiplier arrangement 1000b where a multiplier circuit 1010-1 has been cascaded with a multiplier circuit 1010-2. In Figure 10b, the frequency multiplier circuits 1010-1 , 1010-2 may, e.g., be the frequency multiplier circuit 210, 810, or 1010. In general, the multiplier arrangement 1000b may comprise a plurality of cascaded frequency multiplier circuits (such as 1010-1 , 1010-2), where each frequency multiplier circuit comprises a respective transistor 250 configured to receive a respective supply voltage Vcc, to receive a respective bias voltage Vtune_i, VtUne_2, and to multiply a respective input signal to provide a respective frequency multiplied output signal. In that case, the control circuit 1080 is configured to provide respective specific bias voltage Vtune_i, VtUne_2 to the plurality of cascaded frequency multiplier circuits 1010-1 , 1010-2 based on the obtained first data. Figure 10b shows an input port 1051 (called "in” in the figure) and an output port 1053 (called "out” in the figure). There is a node 1052 between the frequency multiplier circuit 1010-1 and the frequency multiplier circuit 1010-2.

[0135] The frequency multiplier circuit 1010-1 is configured to receive the input signal at the input port 1051 , and to multiply the input signal to provide the frequency multiplied output signal at the node 1052. The frequency multiplier circuit 1010-2 is configured to receive the signal from the node 1052, and to multiply the input signal to provide a frequency multiplied output signal to the output port 1053. The input signal may be a single tone signal with a frequency fin. The signal at the node 1052 comprises a (desired) overtone of the input signal, i.e., fnOde = mfin, where m is a natural number larger than one. The number m may be called multiplication factor 1. The signal at the output port 1053 comprises a (desired) overtone of the signal at the node 1052, i.e., fout = n2fnOde, where n2 is a natural number larger than one. The number n2 may be called multiplication factor 2. In some embodiments, ni = n2 = 2. The phase of the overtone at the node 1052 is denoted (pi, and the phase of the overtone at output port 1053 is denoted q>2.

[0136] Furthermore, Aq>i and Aq>2 represent respective individual phase tuning ranges for each frequency multiplier circuit 1010-1 , 1010-2. When each frequency multiplier circuit 1010-1 , 1010-2 is a respective frequency doubler, the phase q>2 ,has a phase tuning range of (2Acpi+ Aq>2). Thus, a 180° tuning range of q>2 may be obtained if the phase tuning range of A(pi and A(p2, respectively, is at least 60° (i.e., A(pi = Aq>2 = 60°). Note that A(pi does not have to be equal to Aq>2. In another example, A(pi=40° and Atp2=100°, which gives a 180° phase tuning range (of 2A(pi+ Aq>2).

[0137] The control circuit 1080 provide the respective specific bias voltage Vtune_i, VtUne_2 to frequency multiplier circuits 1010-1, 1010-2. This increases the phase tuning range compared to if only a single frequency multiplier circuit is used. Simultaneously, the multiplier factor (of the whole frequency multiplier circuit) is increased to ni x n2. The control unit receives data, which may indicate a specific value of q>2 and subsequently provides respective specific bias voltage Vtune_i, VtUne_2 based on the specific value of q>2. For each frequency multiplier circuit 1010-1, 1010-2, the control unit may store (or may be configured to obtain) a first list of discrete possible target phases and a second list of discrete possible bias voltage values. In some embodiments, the control circuit 1080 is configured to provide the respective specific bias voltage Vtune_i, VtUne_2 based on a look-up-table.

[0138] Figures 11 a and 11 b

[0139] With reference to Figures 11 a and 11 b, there is also disclosed herein an IQ-mixer arrangement 1100 comprising a first and a second multiplier arrangement 1000 according to the discussions above. The IQ-mixer arrangement 1100 comprises a first branch for in-phase mixing. The first branch comprises a first mixer 1111 and a frequency multiplier circuit 1010-3 of the first multiplier arrangement 1000. The frequency multiplier circuit 1010-1 of the first multiplier arrangement 1000 is configured to provide a frequency multiplied output signal to the first mixer 1111. The IQ-mixer arrangement 1100 also comprises a second branch for quadrature mixing. The second branch comprises a second mixer 1112 and a frequency multiplier circuit 1010-4 of the second multiplier arrangement 1000. The frequency multiplier circuit 1010-4 of the second multiplier arrangement 1000 is configured to provide a frequency multiplied output signal to the second mixer 1112.

[0140] In Figure 11a and 11b, the frequency multiplier circuits 1010-3, 1010-4 may, e.g., be the frequency multiplier circuit 210, 810, or 1010. The frequency multiplier circuits 1010-3, 1010-4 may, e.g., be respective frequency doublers.

[0141] Figures 11a and 11b show an input port 1121 where an input signal is provided. The input signal may be a single tone signal with a frequency (denoted LO / N in the figure, where N is a natural number larger than one) that is a fraction of a desired LO frequency. The input signal is split into the respective inputs of the frequency multiplier circuits 1010-3, 1010-4. Each of the frequency multiplier circuits 1010-3, 1010-4 is configured to receive the input signal at the input port 1121, and to multiply the input signal to provide a frequency multiplied output signal, which is provided to the corresponding mixer 1111, 1112. The frequency multiplied output signal provided by each frequency multiplier circuit 1010-3, 1010-4 comprises one overtone of the input signal, of a multiple N times the frequency of the input signal. The phase difference between the overtone of the respective outputs of the frequency multiplier circuits 1010-3, 1010-4 is 90° in the figures. Furthermore, in the figures, the phase of the overtone of the frequency multiplier circuits 1010-3 is denoted 0° and the phase of the overtone of the frequency multiplier circuits 1010-4 is denoted 90°. In general, however, different phase differences than 90° are possible.

[0142] Figures 11a and 11b also show a power amplifier (PA) 1113 and a variable gain amplifier (VGA) 1114, which are optional components. In general, the IQ-mixer arrangement 1100 may comprising a first amplifier (such as the PA 1113 or the VGA 1114) arranged between the frequency multiplier circuit 1010-3 of the first multiplier arrangement 1000 and the first mixer 1111, and a second amplifier (such as the PA 1113 or the VGA 1114) arranged between the frequency multiplier circuit 1010-4 of the second multiplier arrangement 1000 and the second mixer 1112, where at least one of the first and the second amplifiers (1113, 1114) is a VGA. The first and the second amplifiers enable a higher power of the signals provided to the mixers 1111, 1112. Furthermore, the IQ-mixer arrangement 1100 (and / or the control circuit 1080) may be configured to control the VGA such that the power of the signals provided to the mixers 1111 , 1112 is equal, or at least more similar.

[0143] In Figures 11a and 11b, the IQ-mixer arrangement 1100 is for up-conversion. Thus, an in-phase baseband signal (BB_I) is provided to the mixer 1111, and a quadrature baseband signal (BB_Q) is provided to the mixer 1112. Both mixers 1111, 1112 provide respective RF signals, which are combined and provided to an output port 1122. The signal at the output port may be provided to an antenna element (possibly via further amplification)

[0144] Alternatively, the IQ-mixer arrangement 1100 is for down-conversion. In that case, an RF signal (e.g., received by an antenna element (possibly via further amplification) is provided to the mixer 1111, 1112, separately. The frequency multipliers to generate LO signals (inputs to the mixers) are the same as those in the up-conversion IQ- mixer. The mixer 1111 outputs an in-phase baseband signal (BB_I) to, e.g., an analog to digital converter circuit, and the mixer 1112 outputs a quadrature baseband signal (BB_Q) to, e.g., an analog to digital converter circuit. The control circuits 1080 of the first and the second multiplier arrangements 1000 are configured to provide respective specific bias voltages Vtune_i, Vtune_o to the frequency multiplier circuits 1010-3, 1010-4 of the first and the second multiplier arrangements 1000 such that a second target phase, between the respective frequency multiplied output signals of the frequency multiplier circuits 1010-3, 1010-4 of the first and the second multiplier arrangements 1000, is provided by the frequency multiplier circuits 1010-3, 1010-4 of the first and the second multiplier arrangements 1000. The second target phase may, e.g., be 90 degrees.

[0145] As is shown in Figures 11a and 11 b, the control circuits 1080 of the first and the second multiplier arrangements 1000 may be integrated in a single unit. Alternatively, the control circuits 1080 of the first and the second multiplier arrangements 1000 may be arranged as separate units.

[0146] The control circuits 1080 of the first and the second multiplier arrangements 1000 provide the respective specific bias voltage VtUnej, Vtune_Q to frequency multiplier circuits 1010-3, 1010-4. This enables obtaining the 90° phase difference in the I- and Q-branches without having to include a separate phase shifter component, which is an advantage. The control units may receive data, which may, e.g., indicate a specific value of the phase provided by the frequency multiplier circuit 1010-3 and a specific value of the phase provided by the frequency multiplier circuit 1010-4, and subsequently provides respective specific bias voltage VtUnej, VtUne_Q based on said specific values of the phases. For each frequency multiplier circuit 1010-3, 1010-4, the control unit may store (or may be configured to obtain) a first list of discrete possible target phases and a second list of discrete possible bias voltage values. In some embodiments, the control circuit 1080 is configured to provide the respective specific bias voltage VtUnej, VtUne_Q based on a look-up-table. In other words, in some embodiments, the control circuits 1080 of the first and the second multiplier arrangements 1000 may be configured to receive second data indicative of the second target phase, and to provide respective specific bias voltage VtUnej, Vtune_Q based on the obtained second data. In some embodiments, control circuits 1080 of the first and the second multiplier arrangements 1000 may be configured to provide respective specific bias voltage VtUnej, VtUne_Q based on the obtained second data.

[0147] As is shown in Figure 11 b, the IQ-mixer arrangement 1100 may comprise a feedback arrangement 1131 , 1132, 1133, 1134, 1135 configured to receive portions of the respective frequency multiplied output signals of the frequency multiplier circuits 1010-1 , 1010-2 of the first and the second multiplier arrangements 1000, and to provide a control signal to the control circuits 1080 of the first and the second multiplier arrangements 1000 based on the received portions. In that case, the control circuits 1080 of the first and the second multiplier arrangements 1000 are configured to provide the respective specific bias voltages Vtune_i, Vtune_o based on the provided control signal.

[0148] Furthermore, the feedback arrangement may comprise a filter arrangement 1134 and a third mixer 1133. The filter 1134 may be a low-pass filter. The low-pass filter may be configured to suppress frequencies other than DC. The third mixer 1133 is configured to mix the portions of the respective frequency multiplied output signals of the frequency multiplier circuits 1010-3, 1010-4 of the first and the second multiplier arrangements 1000 to provide a mixed signal. The filter arrangement 1134 is configured to filter the mixed signal to provide the control signal. In this way, a desired phase difference (such as 90°) between the respective frequency multiplied output signals of the frequency multiplier circuits 1010-3, 1010-4 may be maintained more accurately. This may, e.g., be desired for compensation of layout asymmetry and process variation.

[0149] Assuming that the output signals (V and Q) of the frequency multiplier circuits 1010-3, 1010-4 are sinusoidal waves with the same amplitude with different phases, the following expressions are obtained

[0150] Vj = V cos(&jLOt + <pz) (6a)

[0151] VQ= F eos (a)LOt + <pQ) (6b)

[0152] Where V is an amplitude of a voltage, a>L0is the angular frequency of the frequency multiplied output signal of frequency multiplier circuits 1010-3, 1010-4, t is time, <pj is the phase of the tone of the frequency multiplied output signal of frequency multiplier circuit 1010-3, <pQis the phase of the tone of the frequency multiplied output signal of frequency multiplier circuit 1010-4.

[0153] The output of the mixer 1133, after mixing, is

[0154] The filtered signal after the filter 1134 (being a low-pass filter) is

[0155] This voltage, VPD, is a function of the phase difference. For example, when <p, - <pQ= 0°, then VPD= 0. The voltage VPDis fed to the control unit 1080, which is configured to adjust the specific values of VtUnej, VtUne_Q based on the provided voltage VPD.

[0156] The control signal (such as the voltage VPD) may constitute the first and / or second data, or be comprised in the first and / or second data.

[0157] Figure 12

[0158] Figure 12 shows an example of the IQ-mixer arrangement 1100 that additionally comprises the multiplier arrangement 1000b of Figure 10b. In general, the IQ-mixer arrangement 1100 may comprise a third multiplier arrangement 1000b, which comprises a plurality of cascaded frequency multiplier circuits (such as 1010-1, 1010- 2). In that case, the last frequency multiplier circuit 1010-2 of the plurality of cascaded frequency multiplier circuits of the third multiplier arrangement 1000b is configured to provide a frequency multiplied output signal to the respective frequency multiplier circuits 1010-3, 1010-4 of the first and the second multiplier arrangements 1000.

[0159] In the example of Figure 12, each frequency multiplier circuit 1010-1, 1010-2, 1010-3, 1010-4 is a frequency doubler. However, other multiples of frequency multiplication are possible. Figure 12 shows an input port 1252, where an input signal is provided. The input signal may be a single tone signal with a frequency (denoted LO / 8 in the figure) that is a fraction of a desired LO frequency. The input signal is provided to the frequency multiplier circuit 1010-1 , which doubles the frequency and provides the doubled frequency (LO / 4) to the frequency multiplier circuit 1010-2 (via node 1251). The frequency multiplier circuit 1010-2 doubles the frequency again and provides the quadrupled frequency (LO / 2) to each of the frequency multiplier circuits 1010-3, 1010-4 (via node 1121). Each of the frequency multiplier circuits 1010-3, 1010-4 doubles the frequency again, and provides respective signals (with a frequency 8 times the input signal at the port 1052, i.e., LO) to the respective mixers 1111 , 1112.

[0160] In Figure 12, the phase of the overtone at node 1251 is denoted (pi, the phase of the overtone at node 1121 is denoted q)2, the phase of the overtone provided by the frequency multiplier circuit 1010-3 is denoted q)3-i, and the phase of the overtone provided by the frequency multiplier circuit 1010-4 is denoted (P3-2.

[0161] Furthermore, Acpi, Aq>2, A(ps-i, and Aq>3-1 represent respective individual phase tuning ranges for each frequency multiplier circuit 1010-1 , 1010-2, 1010-3, 1010-4. When each frequency multiplier circuit 1010-1, 1010-2, 1010-3, 1010-4 is a respective frequency doubler, the phase q>2 has a phase tuning range of 2Acpi+ A(p2, and the phase (P3-1 has a tuning range of 2(2Acpi+ Aq>2) + Acps-i, and the phase (P3.2 has a tuning range of 2(2Acpi+ Aq>2) + Arp^. Thus, a 360° phase tuning range of (P3-1 and (P3-2 may be obtained if the phase tuning range of q>2 is 180°. The 180° phase tuning range of q>2 can, e.g., be obtained if the phase tuning range of A(pi and Aq>2, respectively, is at least 60°. Note that specific values in the ranges Aq>3-1 and Aq>3-2, may be selected such that (P3-1 - (P3-2 = 90°.

[0162] The control circuit 1080 of the third multiplier arrangement 1000b is configured to provide respective specific bias voltages Vtune_i, VtUne_2, to the respective frequency multiplier circuits 1010-1 , 1010-2 of the third multiplier arrangement 1000b such that a third target phase of any of the frequency multiplied output signal of the frequency multiplier circuits 1010-3, 1010-4 of the first and the second multiplier arrangements 1000 is provided.

[0163] In this way, control of the third target phase is provided without having to include additional phase shift components, which is an advantage.

[0164] The third target phase may be in relation to a reference signal of the same frequency as the frequency multiplied output signal of any of the frequency multiplier circuits 1010-3, 1010-4 (i.e., a frequency which is a desired overtone of the input signal). In that case, the control unit 1080 of the third multiplier arrangement 1000b may provide the specific bias voltage Vtune_i, VtUne_2 such a specific phase difference (i.e., the third target phase) between the frequency multiplied output signal (of 1010-1 or 1010-2) and the refence signal is obtained. When the phase (P3-1 is tuned in the range 2(2Acpi+ Aq>2) + Aq>3-1 and the phase (P3-2 is tuned in the range 2(2Acpi+ Aq>2) + A(p3-2, the third target phase may be a specific value in the range 2(2Acpi + Aq>2) in relation to the reference signal.

[0165] As is shown in Figure 12, the control circuits 1080 of the first, the second, and the third multiplier arrangements 1000, 1000b may be integrated in a single unit. Alternatively, the control circuits 1080 may be arranged as separate units.

[0166] In some embodiments, the control circuit 1080 of the third multiplier arrangement 1000b may be configured to receive third data indicative of the third target phase, and to provide respective specific bias voltage Vtune_i, VtUne_2 to the plurality of cascaded frequency multiplier circuits 1010-1 , 1010-2 based on the obtained third data. In some embodiments, the IQ-mixer arrangement 1100 provides a 360° phase tuning range of the third target phase.

[0167] There is also disclosed herein an apparatus for wireless communications. The apparatus comprises the multiplier arrangement 1000 according to the discussions above and / or the IQ-mixer 1100 according to the discussions above. The apparatus may be a network node 110 or a wireless device 121, as discussed in connection to Figure 1.

[0168] Figure 13 schematically illustrates the components of a control unit 1080 according to an embodiment. The control unit 1080 may comprise processing circuitry 1310 and a storage medium 1330. It should be noted that some or all the functionality described in the embodiments above as being performed by the multiplier arrangement 1000, the IQ-mixer arrangement 1100, and / or the control unit 1080 may be provided by the processing circuitry 1310 executing instructions stored on a computer-readable medium, such as, e.g., the storage medium 1330 shown in Figure 13. The storage medium 1330 may, e.g., comprise any of the look-up tables mentioned above. Alternative embodiments of the control unit 1080 may comprise additional components, such as, a digital to analog converter 1340, an analog to digital converter 1350, and a communications interface 1320.

[0169] In some embodiments, the processing unit 1310 is configured to obtain the first data and to provide the specific bias voltage (such as one or more of VtUne, Vtunej, VtUne_Q, Vtunej, VtUne_2) via the digital to analog converter 1340. In other words, the specific bias voltage is provided by an output of the digital to analog converter 1340, where the specific output provided by the digital to analog converter 1340 is controlled by the processing unit 1310.

[0170] Any of the first, second or third data (or any data indicating a target phase) may be provided to the control unit in different ways. In some examples, such data is provided via the communications interface 1320.

[0171] In some embodiments, the control unit 1080 comprises the analog to digital converter 1350. The analog to digital converter 1350 may, e.g., be configured to receive the filtered signal from the filter arrangement 1134, or an analog signal indicative of a desired phase . In that case, the processing unit 1310 may be configured to control the output of the digital to analog converter 1340 based on the signal received by the analog to digital converter 1350.

[0172] Those skilled in the art will also appreciate that the processing circuitry 1310 and the storage medium 1330 described above may refer to a combination of analog and digital circuits, and / or one or more processors configured with software and / or firmware, e.g., stored in a memory, that when executed by the one or more processors such as the processing circuitry 1310 perform as described above. One or more of these processors, as well as the other digital hardware, may be included in a single application-specific integrated circuit (ASIC), or several processors and various digital hardware may be distributed among several separate components, whether individually packaged or assembled into a system-on-a-chip (SoC).

[0173] The description of the example embodiments provided herein have been presented for purposes of illustration. The description is not intended to be exhaustive or to limit example embodiments to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of various alternatives to the provided embodiments. The examples discussed herein were chosen and described to explain the principles and the nature of various example embodiments and its practical application to enable one skilled in the art to utilize the example embodiments in various manners and with various modifications as are suited to the particular use contemplated. The features of the embodiments described herein may be combined in all possible combinations of methods, apparatus, modules, systems, computer programs, and computer program products. It should be appreciated that the example embodiments presented herein may be practiced in any combination with each other.

[0174] It should be noted that the word "comprising” does not necessarily exclude the presence of other elements or steps than those listed and the words "a” or "an” preceding an element do not exclude the presence of a plurality of such elements. It should further be noted that any reference signs do not limit the scope of the claims, that the example embodiments may be implemented at least in part by means of both hardware and software, and that several "means”, "units” or "devices” may be represented by the same item of hardware.

[0175] The embodiments herein are not limited to the above-described preferred embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be construed as limiting.

Claims

29CLAIMS1. A multiplier arrangement (1000) for receiving an input signal and for generating a frequency multiplied output signal with a controllable phase, wherein the multiplier arrangement (1000) comprises a frequency multiplier circuit (210, 810, 1010) and a control circuit (1080), wherein the frequency multiplier circuit (210, 810, 1010) comprises a transistor (250) configured to receive a supply voltage (Vcc), to receive a bias voltage (Vtune, Vtunej, VtUne_Q, Vtune_i, VtUne_2), and to multiply the input signal to provide the frequency multiplied output signal, wherein the control circuit (1080) is configured to: obtain first data indicative of a first target phase of the frequency multiplied output signal; and provide a specific bias voltage (Vtune, Vtunej, Vtune_Q, Vtune_i , VtUne_2) to the transistor (250) based on the obtained first data.

2. The multiplier arrangement (1000) according to claim 1, wherein the frequency multiplier circuit (210, 810, 1010) comprises an input network (822, 1022), for impedance matching of the transistor (250), arranged at an input terminal of the transistor (250).

3. The multiplier arrangement (1000) according to claim 1 or 2, wherein the frequency multiplier circuit (210, 810, 1010) comprises an output network (821, 1021), for impedance matching of the transistor (250), arranged at an output terminal of the transistor (250).

4. The multiplier arrangement (1000) according to claim 3, wherein the output network (821, 1021) is configured to suppress a fundamental frequency of the input signal.

5. The multiplier arrangement (1000) according to claim 3 or 4, wherein the transistor (250) is a first transistor (250-1) configured to receive a first supply voltage (Vcc), to receive a first bias voltage (Vtune, Vtunej, Vtune_Q, Vtunej, Vtunej), and to multiply the input signal to provide a first frequency multiplied output signal, wherein the frequency multiplier circuit (210, 810, 1010) further comprises a second transistor (250-2) configured to receive a second supply voltage (Vcc), to receive a second bias voltage (Vtune, Vtune_i, Vtune ), Vtune_i, Vtunej), and to multiply the input signal to provide a second frequency multiplied output signal, and wherein the output network (821) is arranged at respective output terminals of the first and the second transistors (250-1, 250-2) and is configured to combine the first and the second frequency multiplied output signals.

6. The multiplier arrangement (1000) according to claim 5, wherein the first and the second transistors (250-1, 250-2) are arranged in a push-push configuration.

307. The multiplier arrangement (1000) according to claim 5 or 6, wherein the frequency multiplier circuit (210, 810, 1010) further comprises a splitter (873) configured to receive a single-ended signal, to convert the single-ended signal to a differential signal, and to provide respective parts of the differential signal to respective input terminals of the first and the second transistors (250-1, 250-2).

8. The multiplier arrangement (1000) according to any previous claim, wherein the control circuit (1080) is configured to obtain data indicative of a first target phase comprised in a first set of different phases, and wherein the control circuit (1080) is configured to provide the specific bias voltage (Vtune, Vtunej, VtUne_Q, Vtune_i, VtUne_2) from a second set of different bias voltages.

9. The multiplier arrangement (1000) according to claim 8, wherein the control circuit (1080) is configured to provide the specific bias voltage (Vtune, Vtunej, VtUne_Q, Vtune_i, VtUne_2) based on a look-up-table comprising the first and the second sets.

10. The multiplier arrangement (1000) according to any previous claim, wherein the control circuit comprises processing circuitry (1310) and a digital to analog converter (1340), wherein the processing unit (1310) is configured to obtain the first data and to provide the specific bias voltage (Vtune, VtUne_i, Vtune_o, Vtune_i, VtUne_2) via the digital to analog converter (1340).

11. The multiplier arrangement (1000) according to any previous claim when dependent on claim 8, wherein the frequency multiplier circuit (210, 810, 1010) is configured to provide a controllable phase, of the frequency multiplied output signal, in a range of at least 90 degrees across a fractional bandwidth, of the frequency multiplied output signal, of at least 10%, and preferably 15%, when the control circuit (1080) provides a specific bias voltage (VtUne, Vtunej, Vtune_Q,, Vtune_i, Vtune.2) comprised in in the second set.

12. The multiplier arrangement (1000) according to any previous claim when dependent on claim 8, wherein the frequency multiplier circuit (210, 810, 1010) is configured to provide a power variation, of the frequency multiplied output signal, less than 1 dB, preferably less than 0.5 dB, across a fractional bandwidth, of the frequency multiplied output signal, of at least 10%, and preferably 15%, when the control circuit (1080) provides a specific bias voltage (Vtune, Vtunej, VtUne_Q,, Vtunej, Vtunej) comprised in the second set.

13. The multiplier arrangement (1000) according to any previous claim, wherein the frequency multiplied output signal comprises a harmonic frequency of at least two times the fundamental frequency of the input signal.

14. The multiplier arrangement (1000) according to any previous claim, wherein the transistor (250) is a field effect transistor or a heterojunction bipolar transistor.

15. The multiplier arrangement (1000) according to any previous claim, wherein the frequency multiplier circuit (210, 810, 1010) comprises a bias feed network for receiving the specific bias voltage (Vtune, Vtunej, VtUne_Q,, Vtune , Vtunej) and providing the specific bias voltage (Vtune, Vtunej, VtUne_Q,, Vtunej, Vtunej) to the transistor (250), and wherein the frequency multiplier circuit (210, 810, 1010) comprises a supply feed network for receiving the supply voltage (Vcc) and providing the supply voltage (Vcc) to the transistor (250).

16. The multiplier arrangement (1000b) according to any previous claim, comprising a plurality of cascaded frequency multiplier circuits (1010-1, 1010-2), wherein each frequency multiplier circuit (1010-1 , 1010-2) comprises a respective transistor (250) configured to receive a respective supply voltage (VCc), to receive a respective bias voltage (Vtune_i, VtUne_2), and to multiply a respective input signal to provide a respective frequency multiplied output signal, wherein the control circuit (1080) is configured to: provide respective specific bias voltage (Vtune_i, Vtunej) to the plurality of cascaded frequency multiplier circuits (1010-1 , 1010-2) based on the obtained first data.

17. An IQ-mixer arrangement (1100) comprising a first and a second multiplier arrangement (1000) according to any of claims 1-15, the IQ-mixer arrangement (1100) further comprising: a first branch for in-phase mixing, the first branch comprising a first mixer (1111) and a frequency multiplier circuit (1010-3) of the first multiplier arrangement (1000), wherein the frequency multiplier circuit (1010-1) of the first multiplier arrangement (1000) is configured to provide a frequency multiplied output signal to the first mixer (1111); and a second branch for quadrature mixing, the second branch comprising a second mixer (1112) and a frequency multiplier circuit (1010-4) of the second multiplier arrangement (1000), wherein the frequency multiplier circuit (1010-4) of the second multiplier arrangement (1000) is configured to provide a frequency multiplied output signal to the second mixer (1112); and wherein the control circuits (1080) of the first and the second multiplier arrangements (1000) are configured to: provide respective specific bias voltages (Vtune_i, Vtune_Q) to the frequency multiplier circuits (1010-3, 1010-4) of the first and the second multiplier arrangements (1000) such that a second target phase, between the respective frequency multiplied output signals of the frequency multiplier circuits (1010-3, 1010-4) of the first and the second multiplier arrangements (1000), is provided by the frequency multiplier circuits (1010-3, 1010-4) of the first and the second multiplier arrangements (1000).

18. The IQ-mixer arrangement (1100) according to claim 17, wherein the control circuits (1080) of the first and the second multiplier arrangements (1000) are integrated in a single unit.

19. The IQ-mixer arrangement (1100) according to any of claims 17-18, wherein the second target phase is 90 degrees.

20. The IQ-mixer arrangement (1100) according to any of claims 17-19, comprising a feedback arrangement (1131, 1132, 1133, 1134, 1135) configured to receive portions of the respective frequency multiplied output signals of the frequency multiplier circuits (1010-3, 1010-4) of the first and the second multiplier arrangements (1000), and to provide a control signal to the control circuits (1080) of the first and the second multiplier arrangements (1000) based on the received portions,and wherein the control circuits (1080) of the first and the second multiplier arrangements (1000) are configured to provide the respective specific bias voltages (Vtune_i, Vtune_Q) based on the provided control signal.

21. The IQ-mixer arrangement (1100) according to claim 20, wherein the feedback arrangement (1131 , 1132, 1133, 1134, 1135) comprises a filter arrangement (1134) and a third mixer (1 133), wherein the third mixer (1133) is configured to mix the portions of the respective frequency multiplied output signals of the frequency multiplier circuits (1010-3, 1010-4) of the first and the second multiplier arrangements (1000) to provide a mixed signal, and wherein the filter arrangement (1134) is configured to filter the mixed signal to provide the control signal.

22. The IQ-mixer arrangement (1100) according to any of claims 17-21 , comprising a first amplifier (1113) arranged between the frequency multiplier circuit (1010-3) of the first multiplier arrangement (1000) and the first mixer (1111), and a second amplifier (1114) arranged between the frequency multiplier circuit (1010-4) of the second multiplier arrangement (1000) and the second mixer (1111), wherein at least one of the first and the second amplifiers (11 13, 1114) is a variable gain amplifier.

23. The IQ-mixer arrangement (1100) according to any of claims 17-22, comprising a third multiplier arrangement (1000b) according to claim 16, wherein the last frequency multiplier circuit (1010-2) of the plurality of cascaded frequency multiplier circuits of the third multiplier arrangement (1000b) is configured to provide a frequency multiplied output signal to the respective frequency multiplier circuits (1010-3, 1010-4) of the first and the second multiplier arrangements (1000).

24. The IQ-mixer arrangement (1100) according to claim 23, wherein the control circuit (1080) of the third multiplier arrangement (1000b) is configured to: provide respective specific bias voltages (Vtune_i, Vtune_2), to the respective frequency multiplier circuits (1010-1 , 1010-2) of the third multiplier arrangement (1000b) such that a third target phase of the frequency multiplied output signal of any of the frequency multiplier circuits (1010-3, 1010-4) of the first and the second multiplier arrangements (1000) is provided.

25. An apparatus (110, 121) for wireless communications, the apparatus comprising the multiplier arrangement (1000) according to any of claims 1-16 and / or the IQ-mixer arrangement (1100) according to any of claims 17-24.

26. The apparatus (110, 121) according to claim 25, wherein the apparatus is a network node (110) or a wireless device (121).

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