Nitride semiconductor device

Abstract

This nitride semiconductor device (1) comprises a power FET (11), an ESD protection FET (12), a diode (13), and a resistor element (14). A gate structure (50G) of the power FET (11) includes a p-type semiconductor layer (52G) and a gate electrode (54G) that is Schottky-connected to the p-type semiconductor layer (52G). An anode structure (50A) of the diode (13) includes a p-type semiconductor layer (52A). The gate structure (50G), a drain structure (51D) of the ESD protection FET (12), and the anode structure (50A) are electrically connected to each other. A source structure (50S) of the power FET (11), a source structure (51S) of the ESD protection FET (12), and a terminal structure (50R) of the resistor element (14) are electrically connected to each other. A gate structure (51G) of the ESD protection FET (12), a cathode structure (50K) of the diode (13), and a terminal structure (51R) of the resistor element (14) are electrically connected to each other.

Description

Nitride semiconductor equipment

[0001] This disclosure relates to nitride semiconductor devices.

[0002] Patent Document 1 discloses an ESD (Electrostatic Discharge) protection circuit provided between the gate and source of a power FET (Field Effect Transistor). The ESD protection circuit includes a diode array containing a plurality of diodes connected in series, a resistor connected in series with the diode array, and an ESD protection FET connected in parallel with the series circuit of the diode array and the resistor. The gate of the ESD protection FET is connected to the connection point of the diode array and the resistor, and its source and drain are connected to the gate and source of the power FET, respectively. Patent Document 1 also discloses a configuration in which a plurality of transistors with their gates and drains short-circuited are provided instead of a plurality of diodes.

[0003] Strength Patent No. 11699899

[0004] Conventional ESD protection circuits use a configuration in which multiple Schottky diodes with low forward voltage or gate-source short FET diodes are connected in series, resulting in a large circuit area. Furthermore, the characteristics of gate-source short FET diodes vary greatly within the wafer surface, leading to large variations in the characteristics of the ESD protection circuit.

[0005] Therefore, the present disclosure aims to provide a nitride semiconductor device that can reduce variations in circuit area and circuit characteristics.

[0006] A nitride semiconductor device according to one aspect of the present disclosure comprises a substrate, a semiconductor laminate containing a two-dimensional electron gas provided above the substrate, the semiconductor laminate including a first region, a second region, a third region and a fourth region that do not overlap with each other in a plan view, a first transistor provided on the first region including a first source structure, a first drain structure and a first gate structure, a second transistor provided on the second region including a second source structure, a second drain structure and a second gate structure, a first diode provided on the third region including a first anode structure and a first cathode structure, and a resistive element provided on the fourth region including a first terminal structure and a second terminal structure, wherein the first gate structure is a first p-type The first gate structure includes a semiconductor layer and a first metal layer provided above the first p-type semiconductor layer, the second gate structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer, the first anode structure includes a third p-type semiconductor layer and a third metal layer provided above the third p-type semiconductor layer, the first metal layer is Schottky connected to the first p-type semiconductor layer, the first gate structure, the second drain structure and the first anode structure are electrically connected to each other, the first source structure, the second source structure and the first terminal structure are electrically connected to each other, and the second gate structure, the first cathode structure and the second terminal structure are electrically connected to each other.

[0007] A nitride semiconductor device according to one aspect of the present disclosure comprises a substrate, a semiconductor laminate containing a two-dimensional electron gas provided above the substrate, the semiconductor laminate including a first region, a second region, a third region and a fourth region that do not overlap with each other in a plan view, a first transistor provided on the first region including a first source structure, a first drain structure and a first gate structure, a second transistor provided on the second region including a second source structure, a second drain structure and a second gate structure, a plurality of diodes provided on the third region each including an anode structure and a cathode structure, and a resistive element provided on the fourth region including a first terminal structure and a second terminal structure, wherein the first gate structure includes a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer, and the The second gate structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer, the first metal layer being Schottky connected to the first p-type semiconductor layer, the second metal layer being ohmic connected to the second p-type semiconductor layer, the anode structure being Schottky connected to the semiconductor stack, the plurality of diodes being connected in series in the forward direction to form a diode array, the first gate structure, the second drain structure, and the anode structure corresponding to the anode end of the diode array being electrically connected to each other, the first source structure, the second source structure, and the first terminal structure being electrically connected to each other, and the second gate structure, the cathode structure corresponding to the cathode end of the diode array, and the second terminal structure being electrically connected to each other.

[0008] According to this disclosure, variations in circuit area and circuit characteristics can be reduced.

[0009] Figure 1 is a circuit diagram of a nitride semiconductor device according to Embodiment 1. Figure 2 is a plan view of the nitride semiconductor device according to Embodiment 1. Figure 3 is a cross-sectional view of the nitride semiconductor device according to Embodiment 1. Figure 4A is a cross-sectional view of a power FET according to Embodiment 1. Figure 4B is a cross-sectional view of an ESD protection FET according to Embodiment 1. Figure 4C is a cross-sectional view of a diode according to Embodiment 1. Figure 4D is a cross-sectional view of a resistive element according to Embodiment 1. Figure 5A is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. Figure 5B is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. Figure 5C is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. Figure 5D is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. Figure 5E is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. Figure 5F is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. Figure 5G is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. Figure 5H is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. Figure 5I is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. Figure 5J is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. Figure 6 is a cross-sectional view of a nitride semiconductor device according to Modification 1 of Embodiment 1. Figure 7 is a cross-sectional view of a diode according to Modification 1 of Embodiment 1. Figure 8A is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Modification 1 of Embodiment 1. Figure 8B is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Modification 1 of Embodiment 1. Figure 8C is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Modification 1 of Embodiment 1. Figure 8D is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Modification 1 of Embodiment 1. Figure 8E is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Modification 1 of Embodiment 1.Figure 9 is a cross-sectional view of a nitride semiconductor device according to a modification 2 of Embodiment 1. Figure 10 is a cross-sectional view of an ESD-protected FET according to a modification 2 of Embodiment 1. Figure 11A is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to a modification 2 of Embodiment 1. Figure 11B is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to a modification 2 of Embodiment 1. Figure 11C is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to a modification 2 of Embodiment 1. Figure 11D is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to a modification 2 of Embodiment 1. Figure 11E is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to a modification 2 of Embodiment 1. Figure 12 is a cross-sectional view of a nitride semiconductor device according to a modification 3 of Embodiment 1. Figure 13A is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to a modification 3 of Embodiment 1. Figure 13B is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to a modification 3 of Embodiment 1. Figure 13C is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to a modification 3 of Embodiment 1. Figure 13D is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to a modification 3 of Embodiment 1. Figure 13E is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to a modification 3 of Embodiment 1. Figure 14 is a circuit diagram of a nitride semiconductor device according to Embodiment 2. Figure 15 is a plan view of a nitride semiconductor device according to Embodiment 2. Figure 16 is a cross-sectional view of a Schottky diode according to Embodiment 2. Figure 17 is a circuit diagram of a nitride semiconductor device according to Embodiment 3. Figure 18 is a plan view of a nitride semiconductor device according to Embodiment 3. Figure 19 is a cross-sectional view of a nitride semiconductor device according to Embodiment 3. Figure 20A is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 3. Figure 20B is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 3. Figure 20C is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 3. Figure 20D is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 3.Figure 20E is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 3. Figure 20F is a cross-sectional view illustrating one step in the manufacturing method of a nitride semiconductor device according to Embodiment 3.

[0010] (Summary of the Disclosure) A nitride semiconductor device according to a first aspect of the Disclosure comprises a substrate, a semiconductor laminate containing a two-dimensional electron gas provided above the substrate, the semiconductor laminate including a first region, a second region, a third region and a fourth region that do not overlap with each other in a plan view, a first transistor provided on the first region including a first source structure, a first drain structure and a first gate structure, a second transistor provided on the second region including a second source structure, a second drain structure and a second gate structure, a first diode provided on the third region including a first anode structure and a first cathode structure, and a resistive element provided on the fourth region including a first terminal structure and a second terminal structure, wherein the first gate structure is a first p The first gate structure includes a p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer, the second gate structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer, the first anode structure includes a third p-type semiconductor layer and a third metal layer provided above the third p-type semiconductor layer, the first metal layer is Schottky connected to the first p-type semiconductor layer, the first gate structure, the second drain structure and the first anode structure are electrically connected to each other, the first source structure, the second source structure and the first terminal structure are electrically connected to each other, and the second gate structure, the first cathode structure and the second terminal structure are electrically connected to each other.

[0011] As a result, the first diode becomes a pn diode with a third p-type semiconductor layer and a two-dimensional electron gas (2DEG). Therefore, the forward voltage of the first diode is higher than that of a Schottky diode, allowing for a reduction in the number of first diodes. This reduces the circuit area. Furthermore, because the forward characteristics have less variation within the wafer plane than gate-source short FET diodes, the variations in circuit characteristics can be reduced.

[0012] A nitride semiconductor device according to a second aspect of this disclosure is a nitride semiconductor device according to a first aspect, wherein the second metal layer is ohmic-connected to the second p-type semiconductor layer.

[0013] This reduces the forward voltage drop at the gate of the ESD protection FET, allowing it to operate at a lower gate voltage. As a result, the saturation current of the ESD protection FET increases, and the area of ​​the ESD protection FET can be reduced.

[0014] A nitride semiconductor device according to a third aspect of the present disclosure is a nitride semiconductor device according to the first or second aspect, wherein the second metal layer is an alloy layer containing Ti and Al, and includes an alloy layer in contact with the second p-type semiconductor layer, and the second p-type semiconductor layer is a group III nitride semiconductor layer.

[0015] As a result, the alloy layer is connected to the second p-type semiconductor layer with low resistance, allowing the ESD protection FET to operate at a low gate voltage. This allows for a higher saturation current of the ESD protection FET and a smaller area of ​​the ESD protection FET.

[0016] A nitride semiconductor device according to a fourth aspect of this disclosure is a nitride semiconductor device according to any one of the first to third aspects, wherein the third metal layer is ohmic-connected to the third p-type semiconductor layer.

[0017] This reduces the contact resistance of the anode of the first diode, thereby reducing the variation in the forward voltage characteristics of the first diode.

[0018] A nitride semiconductor device according to a fifth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to fourth aspects, wherein the third metal layer is an alloy layer containing Ti and Al, and includes an alloy layer in contact with the third p-type semiconductor layer, and the third p-type semiconductor layer is a group III nitride semiconductor layer.

[0019] As a result, the alloy layer is connected to the third p-type semiconductor layer with low resistance, which reduces variations in the forward voltage characteristics of the first diode.

[0020] A nitride semiconductor device according to a sixth aspect of this disclosure is a nitride semiconductor device according to a first aspect, wherein the second metal layer is Schottky connected to the second p-type semiconductor layer.

[0021] This reduces the forward gate current of the ESD protection FET, thereby reducing the leakage current when the ESD protection circuit is off.

[0022] A nitride semiconductor device according to a seventh aspect of this disclosure is a nitride semiconductor device according to a first or sixth aspect, wherein the second metal layer includes a TiN layer in contact with the second p-type semiconductor layer, and the second p-type semiconductor layer is a group III nitride semiconductor layer.

[0023] This increases the contact resistance between the TiN layer and the second p-type semiconductor layer, thereby reducing the forward gate current of the ESD protection FET and lowering the leakage current when the ESD protection circuit is off.

[0024] A nitride semiconductor device according to the eighth aspect of this disclosure is a nitride semiconductor device according to any one of the first to third aspects, sixth aspect, and seventh aspect, wherein the third metal layer is Schottky connected to the third p-type semiconductor layer.

[0025] This reduces the leakage current flowing through the first diode.

[0026] A nitride semiconductor device according to the ninth aspect of this disclosure is a nitride semiconductor device according to any one of the first to third aspects or the sixth to eighth aspects, wherein the third metal layer includes a TiN layer in contact with the third p-type semiconductor layer, and the third p-type semiconductor layer is a group III nitride semiconductor layer.

[0027] This increases the contact resistance between the TiN layer and the third p-type semiconductor layer, thereby reducing the forward current of the first diode and lowering the leakage current when the ESD protection circuit is off.

[0028] The nitride semiconductor device according to the 10th aspect of the present disclosure is a nitride semiconductor device according to any one of the 1st to 9th aspects, wherein the semiconductor laminate includes a 5th region that does not overlap with any of the 1st region, the 2nd region, the 3rd region, and the 4th region, and the nitride semiconductor device further includes a 2nd diode including a 2nd anode structure and a 2nd cathode structure provided on the 5th region. The 2nd anode structure is Schottky-connected to the semiconductor laminate, and the 2nd diode is connected in series in the forward direction to the 1st diode on the path connecting the 1st gate structure and the 2nd gate structure.

[0029] As a result, the 2nd diode is a Schottky diode and has a lower forward voltage than the 1st diode. Therefore, when the forward voltage required for the clamp diode to turn off the ESD protection FET during the normal operation of the power FET is insufficient with only the 1st diode, it can be adjusted by the forward voltage of the 2nd diode.

[0030] The nitride semiconductor device according to the 11th aspect of the present disclosure is a nitride semiconductor device according to the 10th aspect, wherein the 3rd metal layer is ohmic-connected to the 3rd p-type semiconductor layer.

[0031] As a result, the contact resistance of the anode of the 1st diode can be reduced, and the variation in the forward voltage characteristics of the 1st diode can be reduced.

[0032] The nitride semiconductor device according to the 12th aspect of the present disclosure is a nitride semiconductor device according to the 10th or 11th aspect, wherein the 3rd metal layer is an alloy layer containing Ti and Al, includes an alloy layer in contact with the 3rd p-type semiconductor layer, and the 3rd p-type semiconductor layer is a group III nitride semiconductor layer.

[0033] As a result, the alloy layer is connected to the 3rd p-type semiconductor layer with low resistance, and the variation in the forward voltage characteristics of the 1st diode can be reduced.

[0034] The nitride semiconductor device according to the 13th aspect of the present disclosure is a nitride semiconductor device according to the 10th aspect, wherein the 3rd metal layer is Schottky-connected to the 3rd p-type semiconductor layer.

[0035] This reduces the forward current of the first diode, thereby lowering the leakage current when the ESD protection circuit is off.

[0036] A nitride semiconductor device according to a fourteenth aspect of this disclosure is a nitride semiconductor device according to a tenth or thirteenth aspect, wherein the third metal layer includes a TiN layer in contact with the third p-type semiconductor layer, and the third p-type semiconductor layer is a group III nitride semiconductor layer.

[0037] This increases the contact resistance between the TiN layer and the third p-type semiconductor layer, reducing the forward current of the first diode and thus lowering the leakage current when the ESD protection circuit is off.

[0038] A nitride semiconductor device according to a 15th aspect of the present disclosure comprises a substrate, a semiconductor laminate containing a two-dimensional electron gas provided above the substrate, the semiconductor laminate including a first region, a second region, a third region and a fourth region that do not overlap with each other in a plan view, a first transistor provided on the first region including a first source structure, a first drain structure and a first gate structure, a second transistor provided on the second region including a second source structure, a second drain structure and a second gate structure, a plurality of diodes provided on the third region each including an anode structure and a cathode structure, and a resistive element provided on the fourth region including a first terminal structure and a second terminal structure, wherein the first gate structure includes a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer, The second gate structure includes a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer, wherein the first metal layer is Schottky connected to the first p-type semiconductor layer, the second metal layer is ohmic connected to the second p-type semiconductor layer, the anode structure is Schottky connected to the semiconductor stack, the plurality of diodes are connected in series in the forward direction to form a diode array, the first gate structure, the second drain structure, and the anode structure corresponding to the anode end of the diode array are electrically connected to each other, the first source structure, the second source structure, and the first terminal structure are electrically connected to each other, and the second gate structure, the cathode structure corresponding to the cathode end of the diode array, and the second terminal structure are electrically connected to each other.

[0039] This reduces the forward voltage drop at the gate of the ESD protection FET, allowing it to operate at a lower gate voltage. As a result, the saturation current of the ESD protection FET increases, and the area of ​​the ESD protection FET can be reduced. Therefore, according to this embodiment, the circuit area of ​​the nitride semiconductor device can be reduced. In addition, since multiple diodes have less variation in forward characteristics within the wafer plane than gate-source short FET diodes, the variation in circuit characteristics can be reduced.

[0040] A nitride semiconductor device according to a sixteenth aspect of the present disclosure is a nitride semiconductor device according to a fifteenth aspect, wherein the second metal layer is an alloy layer containing Ti and Al, and includes an alloy layer in contact with the second p-type semiconductor layer, and the second p-type semiconductor layer is a group III nitride semiconductor layer.

[0041] As a result, the alloy layer is connected to the second p-type semiconductor layer with low resistance, allowing the ESD protection FET to operate at a low gate voltage. This allows for a higher saturation current of the ESD protection FET and a smaller area of ​​the ESD protection FET.

[0042] The embodiments will be described in detail below with reference to the drawings.

[0043] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, any components in the following embodiments that are not described in an independent claim will be described as optional components.

[0044] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily match in each figure. Also, in each figure, substantially identical components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0045] Furthermore, in this specification, terms indicating relationships between elements such as parallel and perpendicular, terms indicating the shape of elements, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0046] Furthermore, in this specification, the terms "up" and "down" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather are used as terms defined by the relative positional relationship based on the stacking order in a stacked configuration. In addition, the terms "up" and "down" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close contact with each other and are in contact. In this specification, the direction in which the gate electrode is provided is considered "up" with respect to the substrate.

[0047] Furthermore, in this specification, "plan view" means a view taken from a direction perpendicular to the top or bottom surface of the substrate, unless otherwise specified.

[0048] Furthermore, in this specification, a nitride semiconductor is a group III nitride semiconductor containing one or more group III elements and nitrogen. Group III elements include, for example, aluminum (Al), gallium (Ga), and indium (In). Examples of group III nitride semiconductors include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. A group III nitride semiconductor may also contain one or more elements other than group III, such as silicon (Si), phosphorus (P), and magnesium (Mg). In the following description, unless otherwise specified, when AlInGaN is used, it means that the group III nitride semiconductor contains Al, In, Ga, and N. The same applies to other notations such as AlGaN and GaN.

[0049] Furthermore, in this specification, the composition ratio of Group III elements in a nitride semiconductor (layer) refers to the ratio of the number of atoms of the target Group III element among the multiple Group III elements contained in the nitride semiconductor. For example, if the nitride semiconductor layer is Al ａ In ｂ Ga ｃ When N consists of elements N(a+b+c=1, a≧0, b≧0, c≧0), the Al composition ratio of the nitride semiconductor layer can be expressed as a / (a+b+c). Similarly, the In composition ratio and Ga composition ratio can be expressed as b / (a+b+c) and c / (a+b+c), respectively.

[0050] Furthermore, in this specification, n-type and p-type refer to the conductivity types of semiconductors, and they are conductivity types with opposite polarities. Also, i-type typically represents an undoped state in which no n-type or p-type dopants (impurities) are added. In addition, an i-type semiconductor layer may have an n-type or p-type dopant added, as long as the n-type or p-type dopant is not activated. Furthermore, an i-type semiconductor layer may have impurities other than n-type and p-type dopants added. As the n-type dopant for nitride semiconductors, Si is used, but Ge and the like may also be used. As the p-type dopant for nitride semiconductors, Mg is used, but Be, Zn, and the like may also be used.

[0051] Furthermore, in this specification, the term "metal layer" refers not only to a conductive layer mainly composed of a metal or alloy, but also to a conductive layer mainly composed of a metal compound. For example, a layer mainly composed of conductive metal nitrides such as TiN and TaN is also considered an example of a metal layer.

[0052] Furthermore, in this specification, "main component" refers to the component with the highest content among all components constituting the material. For example, a component with a content of 50% or more is the main component. Components include materials, elements, or compounds.

[0053] Furthermore, in this specification, two or more elements being electrically connected to one another means that the two or more elements are connected in such a way that current can flow in at least one direction through a conductor such as wiring. For example, when two or more elements are electrically connected to one another, this also includes cases where other elements such as resistors or diodes are connected between the two or more elements.

[0054] (Embodiment 1) [Circuit Configuration] First, the circuit configuration of the nitride semiconductor device according to Embodiment 1 will be explained using Figure 1. Figure 1 is a circuit diagram of the nitride semiconductor device 1 according to this embodiment.

[0055] As shown in Figure 1, the nitride semiconductor device 1 comprises a power FET 11, an ESD protection FET 12, a diode 13, and a resistor 14. The ESD protection FET 12, diode 13, and resistor 14 are provided for ESD protection of the power FET 11.

[0056] Power FET 11 is an example of a first transistor and is an enhancement-type (normally off) FET. Power FET 11 is a HEMT that uses 2DEG as the channel.

[0057] The ESD protection FET 12 is an example of a second transistor and is an enhancement-type (normally off) FET. The ESD protection FET 12 is connected between the gate and source of the power FET 11. Specifically, the drain of the ESD protection FET 12 is connected to the gate of the power FET 11, and the source of the ESD protection FET 12 is connected to the source of the power FET 11 and one end of the resistor 14. The gate of the ESD protection FET 12 is connected to the cathode of the diode 13 and the other end of the resistor 14.

[0058] Diode 13 is an example of a first diode. Diode 13 and resistor 14 are connected in series between the gate and source of power FET 11. Specifically, the anode of diode 13 is connected to the gate of power FET 11, and the cathode of diode 13 is connected to the other end of resistor 14.

[0059] Power FET 11 may be subjected to momentary surges. The gate-source junction has low ESD immunity, and it is desirable to protect the power FET 11 from ESD currents flowing from gate to source or from source to gate.

[0060] When a surge is applied to the gate of the power FET 11, the current flowing through the diode 13 and the resistor 14 causes the gate potential of the ESD protection FET 12 to rise. As a result, the gate-source voltage of the ESD protection FET 12 exceeds the threshold voltage, causing the ESD protection FET 12 to turn on (conduct), and an ESD current flows from the drain to the source of the ESD protection FET 12. This prevents a large current from flowing from the gate to the source of the power FET 11, thus protecting the power FET 11.

[0061] When a surge is applied to the source of the power FET 11, the gate of the ESD protection FET 12 is connected to the source of the power FET 11 via the resistor element 14, causing the source potential and gate potential of the ESD protection FET 12 to rise. As a result, the drain-gate voltage of the ESD protection FET 12 exceeds the threshold voltage, causing the ESD protection FET 12 to turn on (conduct), and an ESD current flows from the source to the drain of the ESD protection FET 12. This prevents a large current from flowing from the source to the gate of the power FET 11, thus protecting the power FET 11.

[0062] [Configuration] Next, the specific configuration of the nitride semiconductor device 1 will be explained using Figures 2 and 3. Figure 2 is a plan view of the nitride semiconductor device 1 according to this embodiment. Figure 3 is a cross-sectional view of the nitride semiconductor device 1 according to this embodiment. In Figure 3, some of the components of the nitride semiconductor device 1 are shown as schematic blocks and thick solid lines. Also, Figure 2 is a simplified plan view mainly to explain the positional relationship of electrodes, wiring and pads, and does not represent an accurate plan view in relation to the cross-sectional view in Figure 3. For example, it can be seen from the cross-sectional view in Figure 3 that the source wiring 70S is provided so as to cover the gate electrode 54G, but in Figure 2, the source wiring 70S and the gate electrode 54G are shown so as not to overlap. The same applies to the relationship between the source wiring 71S and the gate electrode 55G.

[0063] As shown by the dashed rectangle in Figure 2, the nitride semiconductor device 1 includes four active regions 21, 22, 23, and 24 that do not overlap with each other in a plan view of the substrate 30. The four active regions 21, 22, 23, and 24 are included in the semiconductor laminate 40 and are regions where 2DEG 43 can occur. The nitride semiconductor device 1 comprises the substrate 30 and the semiconductor laminate 40.

[0064] The active regions 21-24 are spatially separated in a plan view. "Spatial separation" means that two or more regions are provided without overlap or mixing with each other. The active regions 21-24 are spatially separated by the provision of inactive regions 25 between each region.

[0065] The active region 21 is an example of a first region and corresponds to the region through which the drain current of the power FET 11 flows. The source structure 50S, drain structure 50D, and gate structure 50G of the power FET 11 are provided on the active region 21.

[0066] The active region 22 is an example of a second region and corresponds to the region through which the ESD current of the ESD protection FET 12 flows. The source structure 51S, drain structure 51D, and gate structure 51G of the ESD protection FET 12 are provided on the active region 22.

[0067] The active region 23 is an example of a third region and corresponds to the region through which the forward current of the diode 13 flows. The anode structure 50A and cathode structure 50K of the diode 13 are provided on the active region 23.

[0068] The active region 24 is an example of the fourth region and corresponds to the region through which current flows in the resistive element 14. The terminal structures 50R and 51R included in the resistive element 14 are provided on the active region 24. In Figure 2, the active region 24 is represented by a dashed rectangular region, but a part of this dashed rectangular region is deactivated, and 2DEG does not occur. In effect, the active region 24 is formed in a stripe shape. Further details will be explained later along with the configuration of the resistive element 14.

[0069] When comparing the areas of active regions 21 to 24, active region 21 has the largest area, followed by active region 22. The areas of active regions 23 and 24 may be larger or equal. For example, if the area of ​​the substrate 30 is 1940 μm × 1873 μm, the area of ​​active region 21 can be 1300 μm × 1600 μm, the area of ​​active region 22 can be 350 μm × 1200 μm, the area of ​​active region 23 can be 50 μm × 150 μm, and the area of ​​active region 24 can be 100 μm × 200 μm. Note that these area values ​​are merely examples and are not limiting.

[0070] The substrate 30 is a semiconductor substrate such as a Si substrate, but it may also be a substrate including an insulating part such as an SOI (Silicon On Insulator) substrate, or it may be an insulating substrate. For example, the substrate 30 may be a substrate mainly composed of SiC, sapphire, diamond, GaN, or AlN.

[0071] The semiconductor laminate 40 is provided above the substrate 30. Specifically, the semiconductor laminate 40 contacts and covers the upper surface of the substrate 30. The semiconductor laminate 40 has a laminated structure of nitride semiconductor layers. Specifically, as shown in Figure 3, the semiconductor laminate 40 includes a channel layer 41 and a barrier layer 42. The semiconductor laminate 40 also includes a 2DEG 43. Furthermore, the semiconductor laminate 40 includes an impurity region 44.

[0072] The channel layer 41 is a layer mainly composed of a nitride semiconductor, for example, an undoped GaN layer or an undoped InGaN layer. The thickness of the channel layer 41 is, for example, 100 nm or more and 200 nm or less, and is 150 nm or 200 nm as an example. The channel layer 41 includes 2DEG 43.

[0073] The barrier layer 42 is a layer mainly composed of a nitride semiconductor and is provided above the channel layer 41. For example, the barrier layer 42 contacts and covers the upper surface of the channel layer 41. The barrier layer 42 has a larger band gap than the channel layer 41. The barrier layer 42 is, for example, an undoped AlGaN layer. The thickness of the barrier layer 42 is, for example, 40 nm to 80 nm, and 60 nm as an example. The barrier layer 42 functions as an electron source for 2DEG 43.

[0074] 2DEG43 is generated near the interface between the channel layer 41 and the barrier layer 42. The channel layer 41 and the barrier layer 42 are formed using different types of materials, and the interface between the channel layer 41 and the barrier layer 42 is called a heterointerface. For example, if the channel layer 41 is a GaN layer and the barrier layer 42 is an AlGaN layer, electrons generated due to piezoelectric polarization caused by the difference in lattice constants between GaN and AlGaN, and due to spontaneous polarization, move to the channel layer 41, which has a smaller band gap, and are confined in the thickness direction near the heterointerface. Electrons gathered near the heterointerface can move laterally (in the direction parallel to the main surface of the substrate 30). In this way, 2DEG43 is formed within the channel layer 41, near the interface between the channel layer 41 and the barrier layer 42.

[0075] In this embodiment, the 2DEG43 generated within the active region 21 functions as a path (channel) for the drain current flowing through the power FET 11. The 2DEG43 generated within the active region 22 functions as a path for the ESD current flowing through the ESD protection FET 12. The 2DEG43 generated within the active region 23 functions as a path for the forward current flowing through the diode 13. The 2DEG43 generated within the active region 24 functions as a path for the current flowing through the resistive element 14. Since the 2DEG43 has high electron mobility and high concentration, a high-speed, high-current power FET 11 can be realized.

[0076] The impurity region 44 is part of the barrier layer 42 and the channel layer 41, and is a region in which impurities (e.g., boron) for inactivating 2DEG 43 are implanted. The impurity region 44 is also called the ion implantation region or the device isolation region. The impurity region 44 corresponds to the inert region 25 in which 2DEG 43 is not generated. By providing the impurity region 44, 2DEG 43 can be electrically isolated between the active regions 21 to 24. In Figure 3, the impurity region 44 is also provided on the substrate 30, but it does not have to be provided on the substrate 30.

[0077] Furthermore, it is sufficient that 2DEG43 can be separated, and instead of the impurity region 44, a groove may be provided in the inert region 25 that penetrates the barrier layer 42 and removes a portion of the channel layer 41. An insulating layer may also be embedded in the groove.

[0078] Furthermore, the semiconductor laminate 40 may further include other nitride semiconductor layers, such as a buffer layer. For example, the buffer layer is a nitride semiconductor layer provided between the substrate 30 and the channel layer 41. The buffer layer is provided to mitigate lattice mismatch between the channel layer 41 and the substrate 30. The buffer layer is a single layer of AlN or a laminated structure of AlN and AlGaN layers, but is not particularly limited.

[0079] [Power FET] Next, the configuration of the power FET 11 will be explained using Figure 4A with reference to Figures 2 and 3. Figure 4A is a cross-sectional view of the power FET 11 according to this embodiment. Figure 4A is a simplified cross-sectional view of the configuration of the power FET 11 shown in Figure 3.

[0080] The power FET 11 includes multiple source structures 50S, drain structures 50D, and gate structures 50G. As shown in Figure 2, each of the source structures 50S, drain structures 50D, and gate structures 50G has an elongated shape in one direction. The source structures 50S and drain structures 50D are arranged alternately in a repeating pattern, with a gate structure 50G placed between each source structure 50S and drain structure 50D. Figures 3 and 4A show cross-sections perpendicular to the longitudinal direction (cross-sections parallel to the short direction) of the source structures 50S, drain structures 50D, and gate structures 50G.

[0081] The source structure 50S is an example of a first source structure and functions as a source for the power FET 11. As shown in Figures 2 and 3, the source structure 50S is electrically connected to the source structure 51S of the ESD protection FET 12 and the terminal structure 50R of the resistive element 14 via source wiring 70S and wirings 70 and 71. The source structure 50S is also electrically connected to the source pad 90S.

[0082] The source structure 50S includes a conductive source electrode 54S. The source electrode 54S is electrically connected to the 2DEG 43 within the active region 21. Specifically, the source electrode 54S is provided on the active region 21 of the semiconductor laminate 40 and is ohmic connected to the 2DEG 43 within the active region 21.

[0083] As shown in Figure 4A, the source electrode 54S includes a laminated structure of a TiAl alloy layer 56S and an Al layer 58S. The TiAl alloy layer 56S is in contact with the upper surface of the semiconductor laminate 40 (the upper surface of the barrier layer 42) through an opening 60S provided in the insulating layer 60. The TiAl alloy layer 56S is a conductive layer mainly composed of an alloy of Ti and Al, for example, an alloy layer substantially composed only of TiAl alloy. The thickness of the TiAl alloy layer 56S is 10 nm to 40 nm, and is 20 nm as an example. The Al layer 58S is in contact with and covers the upper surface of the TiAl alloy layer 56S. The Al layer 58S is a conductive layer mainly composed of Al, for example, a single-metal layer substantially composed only of Al. The thickness of the Al layer 58S is 200 nm to 600 nm, and is 200 nm or 400 nm as an example.

[0084] The drain structure 50D is an example of a first drain structure and functions as a drain for the power FET 11. As shown in Figures 2 and 3, the drain structure 50D is electrically connected to the drain pad 90D. As shown in Figure 4A, the drain structure 50D includes a p-type semiconductor layer 52D and a conductive drain electrode 54D.

[0085] The p-type semiconductor layer 52D is provided on the active region 21. Specifically, the p-type semiconductor layer 52D is in contact with the upper surface within the active region 21 of the semiconductor laminate 40 (barrier layer 42). The p-type semiconductor layer 52D contains a p-type nitride semiconductor as a main component. For example, the p-type semiconductor layer 52D has a single-layer or laminated structure such as a p-type GaN layer or a p-type InGaN layer. For example, Mg is added to the p-type semiconductor layer 52D as a p-type impurity. The p-type impurity concentration of the p-type semiconductor layer 52D is 1×10 １７ cm －３ or more and 1×10 １８ cm －３ or less, and as an example, it is 2×10 １７ cm －３ . The thickness of the p-type semiconductor layer 52D is, for example, 100 nm or more and 300 nm or less, and as an example, it is 180 nm.

[0086] The drain electrode 54D is electrically connected to the 2DEG 43 within the active region 21. Specifically, the drain electrode 54D is provided on the active region 21 of the semiconductor laminate 40 and is in ohmic contact with the 2DEG 43 within the active region 21.

[0087] The drain electrode 54D includes a laminated structure of a TiAl alloy layer 56D and an Al layer 58D. The TiAl alloy layer 56D is in contact with the upper surface of the semiconductor laminate 40 (the upper surface of the barrier layer 42) through an opening 60D provided in the insulating layer 60. The TiAl alloy layer 56D is a conductive layer containing an alloy of Ti and Al as a main component, and for example, it is an alloy layer containing substantially only the TiAl alloy. The thickness of the TiAl alloy layer 56D is 10 nm or more and 40 nm or less, and as an example, it is 20 nm. The Al layer 58D covers and contacts the upper surface of the TiAl alloy layer 56D. The Al layer 58D is a conductive layer containing Al as a main component, and for example, it is a single-metal layer containing substantially only Al. The thickness of the Al layer 58D is 200 nm or more and 600 nm or less, and as an example, it is 200 nm or 400 nm.

[0088] In this embodiment, the drain electrode 54D is electrically connected to the p-type semiconductor layer 52D. Specifically, the drain electrode 54D is in contact with the side and top surfaces of the p-type semiconductor layer 52D. The p-type semiconductor layer 52D is positioned between at least a portion of the drain electrode 54D and the gate structure 50G. Specifically, the p-type semiconductor layer 52D is positioned between the portion of the drain electrode 54D that contacts the top surface of the semiconductor laminate 40 and the gate structure 50G. The drain electrode 54D is in contact with the side surface of the p-type semiconductor layer 52D opposite to the gate structure 50G. The p-type semiconductor layer 52D has a hole injection effect when connected to the drain electrode 54D. Electrons trapped on the surface of the barrier layer 42 during operation of the power FET 11 can be neutralized by holes, thereby suppressing current collapse. The p-type semiconductor layer 52D is not required.

[0089] The gate structure 50G is an example of a first gate structure and functions as the gate of the power FET 11. The gate structure 50G is provided between the source structure 50S and the drain structure 50D. As shown in Figures 2 and 3, the gate structure 50G is electrically connected to the drain structure 51D of the ESD protection FET 12 and the anode structure 50A of the diode 13 via gate wiring 70G and wiring 72. The gate structure 50G is also electrically connected to the gate pad 90G.

[0090] As shown in Figure 4A, the gate structure 50G includes a p-type semiconductor layer 52G and a conductive gate electrode 54G.

[0091] The p-type semiconductor layer 52G is an example of a first p-type semiconductor layer and is provided on the active region 21. Specifically, the p-type semiconductor layer 52G is in contact with the upper surface within the active region 21 of the semiconductor laminate 40 (barrier layer 42). The p-type semiconductor layer 52G mainly contains a p-type nitride semiconductor. For example, the p-type semiconductor layer 52G has a single-layer or multi-layer structure such as a p-type GaN layer or a p-type InGaN layer. For example, Mg is added to the p-type semiconductor layer 52G as a p-type impurity. The p-type impurity concentration of the p-type semiconductor layer 52G is 1 × 10⁻⁶. １７ cm －３ The above 1 x 10 １８cm －３ The following is an example: 2 x 10 １７ cm －３ The thickness of the p-type semiconductor layer 52G is, for example, 100 nm to 300 nm, and is 180 nm as an example. By providing the p-type semiconductor layer 52G, the depletion layer from the p-type semiconductor layer 52G extends to the region where 2DEG43 is formed, and when the p-type semiconductor layer 52G is at 0V, 2DEG43 below the p-type semiconductor layer 52G is blocked. This makes it possible to realize normally-off operation (enhancement type) of the power FET 11.

[0092] The gate electrode 54G is an example of a first metal layer and is located above the p-type semiconductor layer 52G. Specifically, the gate electrode 54G is in contact with the upper surface of the p-type semiconductor layer 52G through an opening 62G provided in the insulating layer 60. The gate electrode 54G is electrically connected to the p-type semiconductor layer 52G. Specifically, the gate electrode 54G is Schottky connected to the p-type semiconductor layer 52G. This reduces gate leakage current.

[0093] The gate electrode 54G includes a laminated structure of a TiN layer 56G and an Al layer 58G. The TiN layer 56G is in contact with the upper surface of the p-type semiconductor layer 52G through an opening 62G provided in the insulating layer 60. The TiN layer 56G is a conductive layer mainly composed of TiN, for example, a conductive metal nitride layer substantially composed of only TiN. The thickness of the TiN layer 56G is 10 nm to 40 nm, and is 20 nm as an example. The Al layer 58G is in contact with and covers the upper surface of the TiN layer 56G. The Al layer 58G is a conductive layer mainly composed of Al, for example, a single-metal layer substantially composed of only Al. The thickness of the Al layer 58G is 200 nm to 600 nm, and is 400 nm or 450 nm as an example.

[0094] In the power FET 11, as shown in Figure 4A, the distance between the gate structure 50G and the drain structure 50D (gate-drain distance) is longer than the distance between the gate structure 50G and the source structure 50S (gate-source distance). This allows for a higher breakdown voltage of the power FET 11.

[0095] [ESD Protection FET] Next, the configuration of the ESD protection FET 12 will be described using Figure 4B with reference to Figures 2 and 3. Figure 4B is a cross-sectional view of the ESD protection FET 12 according to this embodiment. Figure 4B is a simplified cross-sectional view of the configuration of the ESD protection FET 12 shown in Figure 3.

[0096] The ESD protection FET 12 includes multiple source structures 51S, drain structures 51D, and gate structures 51G. As shown in Figure 2, each of the source structures 51S, drain structures 51D, and gate structures 51G has an elongated shape in one direction. The source structures 51S and drain structures 51D are arranged alternately in a repeating pattern, with a gate structure 51G placed between each source structure 51S and drain structure 51D. Figures 3 and 4B show cross-sections perpendicular to the longitudinal direction (cross-sections parallel to the short direction) of the source structures 51S, drain structures 51D, and gate structures 51G.

[0097] The source structure 51S is an example of a second source structure and functions as a source for the ESD protection FET 12. As shown in Figures 2 and 3, the source structure 51S is electrically connected to the source structure 51S of the power FET 11 and the terminal structure 50R of the resistive element 14 via source wirings 70S and 71S and wirings 70 and 71. The source structure 51S is also electrically connected to the source pad 90S.

[0098] The source structure 51S includes a conductive source electrode 55S. The source electrode 55S is electrically connected to the 2DEG 43 in the active region 22. Specifically, the source electrode 55S is provided on the active region 22 of the semiconductor laminate 40 and is ohmic connected to the 2DEG 43 in the active region 22.

[0099] As shown in Figure 4B, the source electrode 55S includes a laminated structure of a TiAl alloy layer 57S and an Al layer 59S. The TiAl alloy layer 57S is in contact with the upper surface of the semiconductor laminate 40 (the upper surface of the barrier layer 42) through an opening 61S provided in the insulating layer 60. The TiAl alloy layer 57S is a conductive layer mainly composed of an alloy of Ti and Al, for example, an alloy layer substantially composed only of TiAl alloy. The thickness of the TiAl alloy layer 57S is 10 nm to 40 nm, and is 20 nm as an example. The Al layer 59S is in contact with and covers the upper surface of the TiAl alloy layer 57S. The Al layer 59S is a conductive layer mainly composed of Al, for example, a single-metal layer substantially composed only of Al. The thickness of the Al layer 59S is 200 nm to 600 nm, and is 200 nm or 400 nm as an example.

[0100] The drain structure 51D is an example of a second drain structure and functions as a drain for the ESD protection FET 12. As shown in Figures 2 and 3, the drain structure 51D is electrically connected to the gate structure 50G of the power FET 11 and the anode structure 50A of the diode 13 via gate wiring 70G and wiring 72. The drain structure 51D includes a conductive drain electrode 55D.

[0101] The drain electrode 55D is electrically connected to the 2DEG 43 within the active region 22. Specifically, the drain electrode 55D is provided on the active region 22 of the semiconductor laminate 40 and is ohmic connected to the 2DEG 43 within the active region 22.

[0102] As shown in Figure 4B, the drain electrode 55D includes a laminated structure of a TiAl alloy layer 57D and an Al layer 59D. The TiAl alloy layer 57D is in contact with the upper surface of the semiconductor laminate 40 (the upper surface of the barrier layer 42) through an opening 61D provided in the insulating layer 60. The TiAl alloy layer 57D is a conductive layer mainly composed of an alloy of Ti and Al, for example, an alloy layer substantially composed only of TiAl alloy. The thickness of the TiAl alloy layer 57D is 10 nm to 40 nm, and is 20 nm as an example. The Al layer 59D is in contact with and covers the upper surface of the TiAl alloy layer 57D. The Al layer 59D is a conductive layer mainly composed of Al, for example, a single-metal layer substantially composed only of Al. The thickness of the Al layer 59D is 200 nm to 600 nm, and is 200 nm or 400 nm as an example.

[0103] The gate structure 51G is an example of a second gate structure and functions as the gate of the ESD protection FET 12. The gate structure 51G is provided between the source structure 51S and the drain structure 51D. As shown in Figures 2 and 3, the gate structure 51G is electrically connected to the cathode structure 50K of the diode 13 and the terminal structure 51R of the resistive element 14 via wiring 73.

[0104] As shown in Figure 4B, the gate structure 51G includes a p-type semiconductor layer 53G and a conductive gate electrode 55G.

[0105] The p-type semiconductor layer 53G is an example of a second p-type semiconductor layer and is provided on the active region 22. Specifically, the p-type semiconductor layer 53G is in contact with the upper surface within the active region 22 of the semiconductor laminate 40 (barrier layer 42). The p-type semiconductor layer 53G mainly contains a p-type nitride semiconductor. For example, the p-type semiconductor layer 53G has a single-layer or multi-layer structure such as a p-type GaN layer or a p-type InGaN layer. For example, Mg is added to the p-type semiconductor layer 53G as a p-type impurity. The p-type impurity concentration of the p-type semiconductor layer 53G is 1 × 10⁻⁶. １７ cm －３ The above 1 x 10 １８ cm －３ The following is an example: 2 x 10 １７ cm －３The thickness of the p-type semiconductor layer 53G is, for example, 100 nm to 300 nm, and is 180 nm as an example. By providing the p-type semiconductor layer 53G, the depletion layer from the p-type semiconductor layer 53G extends to the region where the 2DEG 43 is formed, and when the p-type semiconductor layer 53G is at 0V, the 2DEG 43 below the p-type semiconductor layer 53G is blocked. This makes it possible to realize normally-off operation (enhancement type) of the ESD protection FET 12.

[0106] The gate electrode 55G is an example of a second metal layer and is provided above the p-type semiconductor layer 53G. Specifically, the gate electrode 55G is in contact with the upper surface of the p-type semiconductor layer 53G through an opening 61G provided in the insulating layer 60. The gate electrode 55G is electrically connected to the p-type semiconductor layer 53G. Specifically, the gate electrode 55G is ohmic connected to the p-type semiconductor layer 53G. This reduces the forward voltage drop of the ESD protection FET 12, allowing it to operate at a low gate voltage. As a result, the saturation current of the ESD protection FET 12 increases, and the area of ​​the ESD protection FET 12 can be reduced.

[0107] The gate electrode 55G includes a laminated structure of a TiAl alloy layer 57G and an Al layer 59G. The TiAl alloy layer 57G is in contact with the upper surface of the p-type semiconductor layer 53G through an opening 61G provided in the insulating layer 60. The TiAl alloy layer 57G is a conductive layer mainly composed of an alloy of Ti and Al, for example, an alloy layer substantially composed only of TiAl alloy. The thickness of the TiAl alloy layer 57G is 10 nm to 40 nm, and is 20 nm as an example. The Al layer 59G is in contact with and covers the upper surface of the TiAl alloy layer 57G. The Al layer 59G is a conductive layer mainly composed of Al, for example, a single-metal layer substantially composed only of Al. The thickness of the Al layer 59G is 200 nm to 600 nm, and is 200 nm or 400 nm as an example.

[0108] In the ESD protection FET 12, as shown in Figure 4B, the distance between the gate structure 51G and the drain structure 51D (gate-drain distance) may be the same as the distance between the gate structure 51G and the source structure 51S (gate-source distance). For example, the ESD protection FET 12 may be formed symmetrically in cross-sectional view. Similar to the power FET 11, the distance between the gate structure 51G and the drain structure 51D (gate-drain distance) may be longer than the distance between the gate structure 51G and the source structure 51S (gate-source distance). Note that the breakdown voltage required for the ESD protection FET 12 is lower than that required for the power FET 11. Therefore, the drain-source distance of the ESD protection FET 12 may be shorter than the drain-source distance of the power FET 11. This makes it possible to reduce the area of ​​the ESD protection FET 12 (area of ​​the active region 22), enabling miniaturization of the nitride semiconductor device 1.

[0109] The contact portion between the gate electrode 55G and the p-type semiconductor layer 53G (the bottom surface of the opening 61G) is, for example, 0.8 μm wide and 800 μm long. The gate electrode 55G has a margin of, for example, 0.4 μm from the bottom surface of the opening 61G. The p-type semiconductor layer 53G also has a margin of, for example, 0.4 μm from the bottom surface of the opening 61G. The contact portion between the source electrode 55S and the semiconductor laminate 40 (the bottom surface of the opening 61S) is, for example, 3 μm wide and 800 μm long. The source electrode 55S has a margin of, for example, 1 μm from the bottom surface of the opening 61S. The contact portion between the drain electrode 55D and the semiconductor laminate 40 (the bottom surface of the opening 61D) is, for example, 3 μm wide and 800 μm long. The drain electrode 55D has a margin of, for example, 1 μm from the bottom surface of the opening 61D. The distance between the gate electrode 55G and the source electrode 55S is, for example, 0.9 μm. The distance between the gate electrode 55G and the drain electrode 55D is, for example, 4.5 μm. Note that these dimensions are merely examples and are not limiting.

[0110] [Diode] Next, the configuration of the diode 13 will be explained using Figure 4C with reference to Figures 2 and 3. Figure 4C is a cross-sectional view of the diode 13 according to this embodiment. Figure 4C is a simplified cross-sectional view of the configuration of the diode 13 shown in Figure 3.

[0111] The diode 13 includes two anode structures 50A and one cathode structure 50K. In this embodiment, the cathode structure 50K is positioned between the two anode structures 50A. As shown in Figure 2, each of the anode structures 50A and cathode structures 50K has an elongated shape in one direction. Figures 3 and 4C show cross-sections of the anode structures 50A and cathode structures 50K perpendicular to their longitudinal directions (cross-sections parallel to their short directions).

[0112] The number of anode structures 50A and cathode structures 50K included in the diode 13 is not particularly limited and may be one of each or multiple of each. When multiple anode structures 50A and cathode structures 50K are included, the anode structures 50A and cathode structures 50K are arranged alternately one at a time.

[0113] The anode structure 50A is an example of a first anode structure and functions as the anode of the diode 13. As shown in Figures 2 and 3, the anode structure 50A is electrically connected to the gate structure 50G of the power FET 11 and the drain structure 51D of the ESD protection FET 12 via wiring 72 and gate wiring 70G. As shown in Figure 4C, the anode structure 50A includes a p-type semiconductor layer 52A and a conductive anode electrode 54A.

[0114] The p-type semiconductor layer 52A is an example of a third p-type semiconductor layer and is provided on the active region 23. Specifically, the p-type semiconductor layer 52A is in contact with the upper surface within the active region 23 of the semiconductor laminate 40 (barrier layer 42). The p-type semiconductor layer 52A mainly contains a p-type nitride semiconductor. For example, the p-type semiconductor layer 52A has a single-layer or multi-layer structure such as a p-type GaN layer or a p-type InGaN layer. For example, Mg is added to the p-type semiconductor layer 52A as a p-type impurity. The p-type impurity concentration of the p-type semiconductor layer 52A is 1 × 10⁻⁶. １７ cm－３ The above 1 x 10 １８ cm －３ The following is an example: 2 x 10 １７ cm －３ The thickness of the p-type semiconductor layer 52A is, for example, 100 nm to 300 nm, and is 180 nm as an example. The p-type semiconductor layer 52A forms a pn junction with the 2DEG 43. In other words, the diode 13 is a pn diode formed by the p-type semiconductor layer 52A and the 2DEG 43.

[0115] The anode electrode 54A is an example of a third metal layer and is provided above the p-type semiconductor layer 52A. Specifically, the anode electrode 54A is in contact with the upper surface of the p-type semiconductor layer 52A through an opening 60A provided in the insulating layer 60. The anode electrode 54A is electrically connected to the p-type semiconductor layer 52A. Specifically, the anode electrode 54A is ohmic connected to the p-type semiconductor layer 52A. This reduces the contact resistance of the anode structure 50A of the diode 13, thereby reducing the variation in the forward voltage characteristics of the diode 13.

[0116] The anode electrode 54A includes a laminated structure of a TiAl alloy layer 56A and an Al layer 58A. The TiAl alloy layer 56A is in contact with the upper surface of the p-type semiconductor layer 52A through an opening 60A provided in the insulating layer 60. The TiAl alloy layer 56A is a conductive layer mainly composed of an alloy of Ti and Al, for example, an alloy layer substantially composed only of TiAl alloy. The thickness of the TiAl alloy layer 56A is 10 nm to 40 nm, and is 20 nm as an example. The Al layer 58A is in contact with and covers the upper surface of the TiAl alloy layer 56A. The Al layer 58A is a conductive layer mainly composed of Al, for example, a single-metal layer substantially composed only of Al. The thickness of the Al layer 58A is 200 nm to 600 nm, and is 200 nm or 400 nm as an example.

[0117] The cathode structure 50K is an example of a first cathode structure and functions as the cathode of the diode 13. As shown in Figures 2 and 3, the cathode structure 50K is electrically connected to the gate structure 51G of the ESD protection FET 12 and the terminal structure 51R of the resistive element 14 via wiring 73. The cathode structure 50K includes a conductive cathode electrode 54K. The cathode electrode 54K is electrically connected to 2DEG 43 in the active region 23. Specifically, the cathode electrode 54K is provided on the active region 23 of the semiconductor laminate 40 and is ohmic connected to 2DEG 43 in the active region 23.

[0118] As shown in Figure 4C, the cathode electrode 54K includes a laminated structure of a TiAl alloy layer 56K and an Al layer 58K. The TiAl alloy layer 56K is in contact with the upper surface of the semiconductor laminate 40 (the upper surface of the barrier layer 42) through an opening 60K provided in the insulating layer 60. The TiAl alloy layer 56K is a conductive layer mainly composed of an alloy of Ti and Al, for example, an alloy layer substantially composed only of TiAl alloy. The thickness of the TiAl alloy layer 56K is 10 nm to 40 nm, and is 20 nm as an example. The Al layer 58K is in contact with and covers the upper surface of the TiAl alloy layer 56K. The Al layer 58K is a conductive layer mainly composed of Al, for example, a single-metal layer substantially composed only of Al. The thickness of the Al layer 58K is 200 nm to 600 nm, and is 200 nm or 400 nm as an example.

[0119] The contact portion between the anode electrode 54A and the p-type semiconductor layer 52A (the bottom surface of the opening 60A) is, for example, 10 μm wide and 50 μm or 100 μm long. The anode electrode 54A has a margin of, for example, 0.4 μm from the bottom surface of the opening 60A. The p-type semiconductor layer 52A also has a margin of, for example, 0.6 μm from the bottom surface of the opening 60A. The contact portion between the cathode electrode 54K and the semiconductor laminate 40 (the bottom surface of the opening 60K) is, for example, 10 μm wide and 50 μm long. The cathode electrode 54K has a margin of, for example, 0.4 μm from the bottom surface of the opening 60K. The distance between the anode electrode 54A and the cathode electrode 54K is, for example, 5 μm. These dimensions are merely examples and are not limiting.

[0120] [Resistor Element] Next, the configuration of the resistor element 14 will be explained using Figure 4D with reference to Figures 2 and 3. Figure 4D is a cross-sectional view of the resistor element 14 according to this embodiment. Figure 4D is a simplified cross-sectional view of the configuration of the resistor element 14 shown in Figure 3.

[0121] The resistive element 14 includes two terminal structures 50R and 51R. The resistive element 14 is configured such that current flows through the active region 24 between terminal structures 50R and 51R. In this embodiment, as shown in Figure 2, the active region 24 includes a region (2DEG region) where three linear 2DEGs extending in one direction are generated. The three linear 2DEG regions 24a, 24b, and 24c are electrically connected by connecting wires 70R and 71R so that current flows sequentially between terminal structures 50R and 51R. The connecting wires 70R and 71R are electrically connected to the 2DEG regions 24a to 24c by terminal structures similar to those of terminal structure 50R or 51R, respectively. Note that the terminal structure 50R and terminal structure 51R may be electrically connected only by the 2DEG regions without providing the connecting wires 70R and 71R. Note that the number of 2DEG regions may be one or less, and is not particularly limited.

[0122] The terminal structure 50R is an example of a first terminal structure and functions as one end of the resistive element 14. The terminal structure 50R is electrically connected to the source structure 50S of the power FET 11 and the source structure 51S of the ESD protection FET 12 via wirings 71 and 72 and source wirings 70S and 71S. The terminal structure 50R includes a conductive terminal electrode 54R. The terminal electrode 54R is electrically connected to the 2DEG 43 in the active region 24. Specifically, the terminal electrode 54R is provided on the active region 24 of the semiconductor laminate 40 and is ohmic connected to the 2DEG 43 in the active region 24.

[0123] As shown in Figure 4D, the terminal electrode 54R includes a laminated structure of a TiAl alloy layer 56R and an Al layer 58R. The TiAl alloy layer 56R is in contact with the upper surface of the semiconductor laminate 40 (the upper surface of the barrier layer 42) through an opening 60R provided in the insulating layer 60. The TiAl alloy layer 56R is a conductive layer mainly composed of an alloy of Ti and Al, for example, an alloy layer containing substantially only TiAl alloy. The thickness of the TiAl alloy layer 56R is 10 nm to 40 nm, and is 20 nm as an example. The Al layer 58R is in contact with and covers the upper surface of the TiAl alloy layer 56R. The Al layer 58R is a conductive layer mainly composed of Al, for example, a single-metal layer containing substantially only Al. The thickness of the Al layer 58R is 200 nm to 600 nm, and is 200 nm or 400 nm as an example.

[0124] The terminal structure 51R is an example of a second terminal structure and functions as the other end of the resistive element 14. As shown in Figures 2 and 3, the terminal structure 51R is electrically connected to the gate structure 51G of the ESD protection FET 12 and the cathode structure 50K of the diode 13 via wiring 73. The terminal structure 51R includes a conductive terminal electrode 55R. The terminal electrode 55R is electrically connected to the 2DEG 43 in the active region 24. Specifically, the terminal electrode 55R is provided on the active region 24 of the semiconductor laminate 40 and is ohmic connected to the 2DEG 43 in the active region 24.

[0125] As shown in Figure 4D, the terminal electrode 55R includes a laminated structure of a TiAl alloy layer 57R and an Al layer 59R. The TiAl alloy layer 57R is in contact with the upper surface of the semiconductor laminate 40 (the upper surface of the barrier layer 42) through an opening 61R provided in the insulating layer 60. The TiAl alloy layer 57R is a conductive layer mainly composed of an alloy of Ti and Al, for example, an alloy layer substantially composed only of TiAl alloy. The thickness of the TiAl alloy layer 57R is 10 nm to 40 nm, and is 20 nm as an example. The Al layer 59R is in contact with and covers the upper surface of the TiAl alloy layer 57R. The Al layer 59R is a conductive layer mainly composed of Al, for example, a single-metal layer substantially composed only of Al. The thickness of the Al layer 59R is 200 nm to 600 nm, and is 200 nm or 400 nm as an example.

[0126] In this embodiment, the source structure 50S, source structure 51S, drain structure 51D, cathode structure 50K, terminal structure 50R, and terminal structure 51R have the same layer configuration. Also, the gate structure 51G and anode structure 50A have the same layer configuration. "Same layer configuration" means that one or more layers constituting the two structures are formed in the same film deposition process. Layers formed in the same film deposition process will have the same composition, impurity concentration, and film thickness. However, after being formed in the same film deposition process, other processes such as ion implantation or etching may be performed on only one of the structures. If other processes are performed, even if the "layer configuration" is the same, the impurity concentration and film thickness may differ.

[0127] Furthermore, for example, the source electrodes 54S and 55S, drain electrodes 54D and 55D, gate electrode 55G, anode electrode 54A, cathode electrode 54K, and terminal electrodes 54R and 55R have the same layer structure. Therefore, these electrodes can be formed in the same film deposition process. Specifically, the TiAl alloy layers 56S, 56D, 57S, 57D, 57G, 56A, 56K, 56R, and 57R have the same layer structure and can be formed in the same film deposition process. The Al layers 58S, 58D, 59S, 59D, 59G, 58A, 58K, 58R, and 59R have the same layer structure and can be formed in the same film deposition process. Also, the p-type semiconductor layers 52D, 52G, 53G, and 52A have the same layer structure and can be formed in the same film deposition process.

[0128] [Other Configurations] As shown in Figure 3, the nitride semiconductor device 1 further comprises insulating layers 60, 62, and 64, source wiring 70S and 71S, drain wiring 70D and 71D, insulating layer 80, source pad 90S, drain pad 90D, and gate pad 90G. Note that the insulating layers 60, 62, 64, and 80 are not shown in Figure 2. Also, as shown in Figure 2, the nitride semiconductor device 1 comprises gate wiring 70G and a plurality of wirings 70, 71, 72, and 73 for electrically connecting elements to each other.

[0129] The insulating layer 60 is an insulating protective layer that covers the upper surface of the semiconductor laminate 40. Specifically, the insulating layer 60 covers the upper surface of the semiconductor laminate 40 and the upper and side surfaces of the p-type semiconductor layers 52D, 52G, 53G, and 52A. The insulating layer 60 is, for example, a single-layer structure of a SiN film, but SiO ２ The structure may also include a film-based laminated structure. The thickness of the insulating layer 60 is 100 nm to 200 nm, and is 140 nm as an example.

[0130] Furthermore, the insulating layer 60 is provided with openings 60S, 60D, 62G, 61S, 61D, 61G, 60A, 60K, 60R, and 61R, as shown in Figures 4A to 4D. In Figure 3, the notation of reference numerals has been omitted.

[0131] As shown in Figure 4A, the opening 60S is provided to electrically connect the source electrode 54S and the 2DEG 43, and the barrier layer 42 is exposed on the bottom surface of the opening 60S. The opening 60D is provided to electrically connect the drain electrode 54D and the 2DEG 43, and the barrier layer 42 is exposed on the bottom surface of the opening 60D. The opening 62G is provided to electrically connect the gate electrode 54G and the p-type semiconductor layer 52G, and the p-type semiconductor layer 52G is exposed on the bottom surface of the opening 62G.

[0132] As shown in Figure 4B, the opening 61S is provided to electrically connect the source electrode 55S and the 2DEG 43, and the barrier layer 42 is exposed on the bottom surface of the opening 61S. The opening 61D is provided to electrically connect the drain electrode 55D and the 2DEG 43, and the barrier layer 42 is exposed on the bottom surface of the opening 61D. The opening 61G is provided to electrically connect the gate electrode 55G and the p-type semiconductor layer 53G, and the p-type semiconductor layer 53G is exposed on the bottom surface of the opening 61G.

[0133] As shown in Figure 4C, the opening 60K is provided to electrically connect the cathode electrode 54K and the 2DEG 43, and the barrier layer 42 is exposed on the bottom surface of the opening 60K. The opening 60A is provided to electrically connect the anode electrode 54A and the p-type semiconductor layer 52A, and the p-type semiconductor layer 52A is exposed on the bottom surface of the opening 60A.

[0134] As shown in Figure 4D, the opening 60R is provided to electrically connect the terminal electrode 54R and the 2DEG 43, and the barrier layer 42 is exposed on the bottom surface of the opening 60R. The opening 61R is provided to electrically connect the terminal electrode 55R and the 2DEG 43, and the barrier layer 42 is exposed on the bottom surface of the opening 61R.

[0135] The insulating layer 62 covers the upper and side surfaces of each of the source electrode 54S, drain electrode 54D, source electrode 55S, drain electrode 55D, gate electrode 55G, anode electrode 54A, cathode electrode 54K, terminal electrode 54R, and terminal electrode 55R, as well as the upper surface of the insulating layer 60. The insulating layer 62 does not cover the upper surface of the gate electrode 54G. A portion of the insulating layer 62 is located between a portion of the gate electrode 54G and the p-type semiconductor layer 52G. The insulating layer 64 is, for example, a SiN film or SiO ２ The film has a single-layer or multi-layer structure. The thickness of the insulating layer 64 is, for example, 120 nm.

[0136] The insulating layer 64 covers the upper and side surfaces of the gate electrode 54G and the upper surface of the insulating layer 62. The insulating layer 64 is, for example, a SiN film or SiO ２ The film has a single-layer or multi-layer structure. The thickness of the insulating layer 64 is, for example, 300 nm.

[0137] The insulating layers 62 and 64 are provided with openings for connecting electrodes and wiring. Specifically, the insulating layers 62 and 64 are provided with openings for electrically connecting the source electrode 54S and the source wiring 70S. The insulating layers 62 and 64 are provided with openings for electrically connecting the drain electrode 54D and the drain wiring 70D. The insulating layers 62 and 64 are provided with openings for electrically connecting the source electrode 55S and the source wiring 71S. The insulating layers 62 and 64 are provided with openings for electrically connecting the drain electrode 55D and the drain wiring 71D.

[0138] The source wiring 70S is a conductive wiring electrically connected to a plurality of source electrodes 54S. As shown in Figure 2, the source wiring 70S is formed in a comb-like shape to cover the plurality of source electrodes 54S, and the finger portions of the comb are connected to the plurality of source electrodes 54S arranged in a stripe pattern. A source pad 90S is provided so as to overlap the common portion that bundles the finger portions of the source wiring 70S. The source pad 90S is electrically connected to the source wiring 70S through an opening provided in the insulating layer 80 (see Figure 3). Both the source wiring 70S and the source pad 90S are formed using a conductive material such as metal. For example, the source wiring 70S and the source pad 90S have a single-layer or multi-layer structure of a metal layer mainly composed of Ti, Al, Au, etc. The thickness of the source wiring 70S is, for example, 470 nm. The source wiring 70S and the source pad 90S may be formed in the same layer.

[0139] As shown in Figure 3, the source wiring 70S is provided so as to cover the gate electrode 54G. In other words, in a plan view of the substrate 30, a portion of the source wiring 70S overlaps with the gate electrode 54G. As a result, a portion of the source wiring 70S functions as a source field plate, which can mitigate the electric field between the gate and drain. Note that, as in the example shown in Figure 2, the source wiring 70S and the gate electrode 54G do not necessarily have to overlap.

[0140] The drain wiring 70D is a conductive wiring electrically connected to a plurality of drain electrodes 54D. As shown in Figure 2, the drain wiring 70D is formed in a comb-like shape to cover the plurality of drain electrodes 54D, and the finger portions of the comb are connected to the plurality of drain electrodes 54D which are arranged in a stripe pattern. A drain pad 90D is provided so as to overlap the common portion that bundles the finger portions of the drain wiring 70D. The drain pad 90D is electrically connected to the drain wiring 70D through an opening provided in the insulating layer 80 (see Figure 3). Both the drain wiring 70D and the drain pad 90D are formed using a conductive material such as metal. For example, the drain wiring 70D and the drain pad 90D have a single-layer or multi-layer structure of a metal layer mainly composed of Ti, Al, Au, etc. The thickness of the drain wiring 70D is, for example, 470 nm. The drain wiring 70D and the drain pad 90D may be formed in the same layer.

[0141] The gate wiring 70G is a conductive wiring electrically connected to a plurality of gate electrodes 54G. As shown in Figure 2, the gate wiring 70G is connected to each end of the plurality of gate electrodes 54G. The gate wiring 70G is further electrically connected to a plurality of drain electrodes 55D of the ESD protection FET 12. A gate pad 90G is provided so as to overlap a portion of the gate wiring 70G. The gate pad 90G is electrically connected to the gate wiring 70G through an opening provided in the insulating layer 80 (see Figure 3). Both the gate wiring 70G and the gate pad 90G are formed using a conductive material such as metal. For example, the gate wiring 70G and the gate pad 90G have a single-layer or multi-layer structure of a metal layer mainly composed of Ti, Al, Au, etc. Note that the gate wiring 70G and the gate pad 90G may be formed in the same layer. Note that a portion of the gate wiring 70G may be formed in a comb-like shape so as to cover the gate electrodes 54G.

[0142] The source wiring 71S is a conductive wiring electrically connected to a plurality of source electrodes 55S. As shown in Figure 2, the source wiring 71S is formed in a comb-like shape to cover the plurality of source electrodes 55S, and the finger portions of the comb are connected to the plurality of source electrodes 55S arranged in a stripe pattern. The common portion that bundles the finger portions of the source wiring 70S is connected to the wiring 70. The source wiring 71S is formed using a conductive material such as metal. For example, the source wiring 71S has a single-layer or multi-layer structure of a metal layer mainly composed of Ti, Al, Au, etc. The thickness of the source wiring 71S is, as an example, 470 nm.

[0143] As shown in Figure 3, the source wiring 71S is provided so as to cover the gate electrode 55G. In other words, in a plan view of the substrate 30, a portion of the source wiring 71S overlaps with the gate electrode 55G. As a result, a portion of the source wiring 71S functions as a source field plate, which can mitigate the electric field between the gate and drain. Note that, as in the example shown in Figure 2, the source wiring 71S and the gate electrode 55G do not necessarily have to overlap.

[0144] The drain wiring 71D is a conductive wiring electrically connected to a plurality of drain electrodes 55D. As shown in Figure 2, the drain wiring 71D is formed in a comb-like shape to cover the plurality of drain electrodes 55D, and the finger portions of the comb are connected to the plurality of drain electrodes 55D arranged in a stripe pattern. The common portion that bundles the finger portions of the drain wiring 71D is part of the gate wiring 70G. The drain wiring 71D is formed using a conductive material such as metal. For example, the drain wiring 71D has a single-layer or multi-layer structure of a metal layer mainly composed of Ti, Al, Au, etc. The thickness of the drain wiring 71D is, as an example, 470 nm.

[0145] Wiring 70 is a conductive wiring provided in a rectangular ring shape along the outer circumference of the substrate 30. Wiring 70 is connected to source wirings 70S and 71S and wiring 71. Wiring 71 is a conductive wiring electrically connected to terminal electrode 54R and wiring 70. Wirings 70 and 71 are wirings that electrically connect the source of power FET 11, the source of ESD protection FET 12, and one end of resistive element 14. Both wirings 70 and 71 are formed using a conductive material such as metal. For example, both wirings 70 and 71 have a single-layer or multi-layer structure of a metal layer mainly composed of Ti, Al, Au, etc. The thickness of wirings 70 and 71 is, as an example, 470 nm. Wirings 70 and 71 are formed, for example, in the same process, but may be formed in different processes.

[0146] The wiring 72 is a conductive wiring electrically connected to the gate wiring 70G and the anode electrode 54A. As shown in Figure 2, the wiring 72 electrically connects the gate of the power FET 11, the drain of the ESD protection FET 12, and the anode of the diode 13. The wiring 72 is formed using a conductive material such as metal. For example, the wiring 72 has a single-layer or multi-layer structure of a metal layer mainly composed of Ti, Al, Au, etc. The thickness of the wiring 72 is, as an example, 470 nm. A portion of the wiring 72 may be formed in a comb-like shape to cover the anode electrode 54A.

[0147] The wiring 73 is a conductive wire electrically connected to the cathode electrode 54K, the terminal electrode 55R, and the gate electrode 55G. As shown in Figure 2, the wiring 73 electrically connects the gate of the ESD protection FET 12, the cathode of the diode 13, and the other end of the resistive element 14. The wiring 73 is formed using a conductive material such as metal. For example, the wiring 73 has a single-layer or multi-layer structure of a metal layer mainly composed of Ti, Al, Au, etc. The thickness of the wiring 73 is, as an example, 470 nm. A portion of the wiring 73 may be formed in a comb-like shape so as to cover the cathode electrode 54K.

[0148] The insulating layer 80 covers the upper and side surfaces of the source wiring 70S and 71S, the drain wiring 70D and 71D, and the upper surface of the insulating layer 64. The insulating layer 80 is, for example, a SiN film or SiO ２ The film has a single-layer or multi-layer structure. Although not shown in Figure 3, the insulating layer 80 is provided with openings for electrically connecting the wiring and the pads. The thickness of the insulating layer 80 is, for example, 1000 nm.

[0149] [Effects, etc.] As described above, in the nitride semiconductor device 1 according to this embodiment, the gate electrode 55G and the p-type semiconductor layer 53G are connected with low resistance in the gate structure 51G of the ESD protection FET 12. Specifically, the TiAl alloy layer 57G of the gate electrode 55G is in contact with the p-type semiconductor layer 53G, resulting in lower resistance than when the TiN layer is in contact with the p-type semiconductor layer 53G. For example, the TiN layer is Schottky connected to the p-type semiconductor layer 53G, whereas the gate electrode 55G and the p-type semiconductor layer 53G are ohmic connected.

[0150] This reduces the voltage drop across the gate structure 51G, allowing the ESD protection FET 12 to be driven with a lower gate voltage. As a result, the drain current flowing through the ESD protection FET 12 increases. In other words, a large ESD current can be passed through the ESD protection FET 12 even with a smaller area. Therefore, the area of ​​the ESD protection FET 12 can be reduced.

[0151] Furthermore, in the nitride semiconductor device 1, the ESD protection FET 12 must be in the off state during normal operation. When the gate operating voltage of the power FET 11 is a maximum of 6V, the gate voltage of the power FET 11 must be 6V, and the gate voltage of the ESD protection FET 12 must be below the threshold voltage of the ESD protection FET 12 (approximately 1.5V).

[0152] In this embodiment, since the anode structure 50A of the diode 13 includes a p-type semiconductor layer 52A, the diode 13 becomes a pn diode including a pn junction between the p-type semiconductor layer 52A and the 2DEG43 of the semiconductor laminate 40. For this reason, the forward voltage of the diode 13 is higher than that of a Schottky barrier diode having a configuration in which the anode electrode 54A is in contact with the semiconductor laminate 40. For example, the forward voltage of the diode 13 is approximately 7V. Even when a voltage of 6V is applied between the anode structure 50A and the cathode structure 50K of the diode 13, the current flowing is less than 1μA, and when the resistive element is 250kΩ, the gate voltage of the ESD protection FET 12 is 1μA × 250kΩ = 0.25V, the threshold voltage is approximately 1.5V or less, and the ESD protection FET 12 remains in the off state. For this reason, ESD protection can be performed with only one diode 13 without interfering with the operation of the power FET 11. The gate breakdown voltage of power FET 11 is approximately 14V.

[0153] In this way, the number of diodes 13 can be reduced, thus reducing the circuit area of ​​the nitride semiconductor device 1. Furthermore, since the diodes 13 have less variation in forward characteristics across the wafer plane than gate-source short FET diodes, the variation in the circuit characteristics of the nitride semiconductor device 1 can be reduced.

[0154] [Manufacturing Method] Next, the manufacturing method of the nitride semiconductor device 1 according to this embodiment will be explained using Figures 5A to 5J. Figures 5A to 5J are cross-sectional views illustrating each step of the manufacturing method of the nitride semiconductor device 1 according to this embodiment.

[0155] First, as shown in Figure 5A, a laminated structure of nitride semiconductors is formed on the substrate 30 by an epitaxial growth method such as MOCVD (Metal Organic Chemical Vapor Deposition). Specifically, a semiconductor laminate 40 and a p-type semiconductor layer 52 are formed sequentially on the substrate 30. The semiconductor laminate 40 consists of a buffer layer (not shown), a channel layer 41, and a barrier layer 42, which are formed sequentially. A 2DEG 43 is generated between the channel layer 41 and the barrier layer 42. The semiconductor laminate 40 and the p-type semiconductor layer 52 are formed over the entire main surface of the substrate 30. The p-type semiconductor layer 52 is the base layer for the p-type semiconductor layers 52D, 52G, 53G, and 52A.

[0156] Next, as shown in Figure 5B, an impurity region 44 is formed within the semiconductor laminate 40. Specifically, the impurity region 44 is formed by implanting impurities such as boron by ion implantation. With the formation of the impurity region 44, the active regions 21, 22, 23 and 24 are spatially separated by the inactive region 25, as shown in Figure 5B. The impurity region 44 is also formed in the substrate 30, but it is not required to be formed in the substrate 30.

[0157] Next, a portion of the p-type semiconductor layer 52 is removed by lithography and etching. This forms p-type semiconductor layers 52D, 52G, 53G, and 52A, as shown in Figure 5C.

[0158] Next, as shown in Figure 5D, after forming the insulating layer 60, a portion of it is removed to form the openings 60D, 60S, 61D, 61S, 61G, 60A, 60K, 60R, and 61R. For example, after forming the insulating layer 60 over the entire surface by plasma CVD (Chemical Vapor Deposition), a portion of the formed insulating layer 60 is removed by lithography and etching. In this step, the opening 62G that exposes the p-type semiconductor layer 52G is not formed. The top surface of the barrier layer 42 is exposed at the bottom of each of the openings 60D, 60S, 61D, 61S, 60K, 60R, and 61R. The top and side surfaces of the p-type semiconductor layer 52D are also exposed at the opening 60D. The top surface of the p-type semiconductor layer 53G is exposed at the bottom of the opening 61G. The top surface of the p-type semiconductor layer 52A is exposed at the bottom of the opening 60A.

[0159] Next, a metal film is formed to cover the openings 60D, 60S, 61D, 61S, 61G, 60A, 60K, 60R, and 61R. For example, sputtering or vapor deposition can be used to form the metal film. Specifically, after forming the Ti layer 56 and the Al layer 58 in this order, a portion of each of the Ti layer 56 and Al layer 58 is removed by lithography and etching. As a result, as shown in Figure 5E, a laminated structure of Ti layer 56 and Al layer 58 is formed in the openings 60D, 60S, 61D, 61S, 61G, 60A, 60K, 60R, and 61R, respectively.

[0160] Next, a heat treatment is performed to alloy Ti and Al. The heat treatment is carried out, for example, by laser annealing. Specifically, the heat treatment is performed using an RTA (Rapid Thermal Annealing) furnace at 535°C for 60 seconds. The time and temperature of the heat treatment can be appropriately changed depending on the type of metal and film thickness. Through the heat treatment, the Ti layer 56 and Al layer 58 formed in each opening are alloyed, changing into TiAl alloy layers 56D, 56S, 57D, 57S, 57G, 56A, 56K, 56R and 57R, and Al layers 58D, 58S, 59D, 59S, 59G, 58A, 58K, 58R and 59R.

[0161] As a result, as shown in Figure 5F, the drain electrode 54D, source electrode 54S, drain electrode 55D, source electrode 55S, gate electrode 55G, anode electrode 54A, cathode electrode 54K, terminal electrode 54R, and terminal electrode 55R are formed. The drain electrode 54D, source electrode 54S, drain electrode 55D, source electrode 55S, cathode electrode 54K, terminal electrode 54R, and terminal electrode 55R are all ohmic connected to 2DEG43. The gate electrode 55G is ohmic connected to the p-type semiconductor layer 53G. The anode electrode 54A is ohmic connected to the p-type semiconductor layer 52A.

[0162] Next, as shown in Figure 5G, an opening 62G is formed by removing a portion of the insulating layer 62 after it has been formed. For example, after forming the insulating layer 62 over the entire surface by plasma CVD, an opening 62G is formed by removing a portion of the formed insulating layer 62 by lithography and etching. The opening 62G penetrates not only the insulating layer 62 but also the insulating layer 60. A p-type semiconductor layer 52G is exposed at the bottom surface of the opening 62G. After forming the opening 62G, a gate electrode 54G is formed. Specifically, a TiN layer and an Al layer are formed in this order by sputtering or the like, and then a portion of each of the TiN layer and Al layer is removed by lithography and etching. As a result, a gate electrode 54G including a stacked structure of a TiN layer 56G and an Al layer 58G is formed so as to cover the opening 62G.

[0163] Next, as shown in Figure 5H, an opening is formed by removing a portion of the insulating layer 64 after it has been formed. For example, after forming the insulating layer 64 over the entire surface by plasma CVD, a portion of the formed insulating layer 64 is removed by lithography and etching. The opening is formed so as to expose the upper surfaces of the source electrode 54S, drain electrode 54D, source electrode 55S, and drain electrode 55D.

[0164] Next, as shown in Figure 5I, source wiring 70S, drain wiring 70D, source wiring 71S, and drain wiring 71D are formed. Specifically, first, a metal film is formed to cover the openings formed in the insulating layer 64. For example, sputtering or vapor deposition can be used to form the metal film. Specifically, after forming the Ti layer and the Al layer in this order, a portion of each of the Ti layer and Al layer is removed by lithography and etching. As a result, as shown in Figure 5I, source wiring 70S, drain wiring 70D, source wiring 71S, and drain wiring 71D are formed. In addition, the wirings 70, 71, 72, and 73 shown in Figure 2 can also be formed at the same time as the source wiring 70S, etc.

[0165] Next, as shown in Figure 5J, an insulating layer 80 is formed. For example, the insulating layer 80 is formed over the entire surface by plasma CVD. Then, openings (not shown) are formed by removing a portion of the formed insulating layer 80 by lithography and etching. After forming a metal layer to cover the formed openings by sputtering, plating, etc., a portion of each of the metal layers is removed by lithography and etching. As a result, the source pad 90S, drain pad 90D, and gate pad 90G are formed, as shown in Figure 2.

[0166] The nitride semiconductor device 1 according to this embodiment can be manufactured through the above steps. The order in which various wirings are formed may be modified as appropriate. Furthermore, multiple layers formed in the same process may be formed in different processes.

[0167] (Modification 1 of Embodiment 1) Next, Modification 1 of Embodiment 1 will be described. In this modification, the layer configuration of the diode anode structure is different from that of Embodiment 1. In the following, the differences from Embodiment 1 will be explained, and the explanation of the common points will be omitted or simplified.

[0168] [Configuration] First, the configuration of the nitride semiconductor device 101 according to Modification 1 will be explained using Figure 6. Figure 6 is a cross-sectional view of the nitride semiconductor device 101 according to this modification. The plan view of the nitride semiconductor device 101 is the same as the plan view shown in Figure 2.

[0169] As shown in Figure 6, the nitride semiconductor device 101 has a diode 113 instead of diode 13, compared to the nitride semiconductor device 1. Since the configuration other than diode 113 is the same as that of the nitride semiconductor device 1, the configuration of diode 113 will be described below.

[0170] Figure 7 is a cross-sectional view of the diode 113 according to this modified example. Compared to the diode 13 shown in Figure 4C, the layer configuration of the anode electrode 54A of the diode 113 is different. Specifically, the anode electrode 54A of the diode 113 according to this modified example includes a TiN layer 156A instead of a TiAl alloy layer 56A. In other words, the anode electrode 54A of the diode 113 includes a laminated structure of a TiN layer 156A and an Al layer 58A.

[0171] The TiN layer 156A is in contact with the upper surface of the p-type semiconductor layer 52A through an opening 162A provided in the insulating layer 60. The TiN layer 156A is a conductive layer mainly composed of TiN, and is, for example, a conductive metal nitride layer substantially containing only TiN. The thickness of the TiN layer 156A is 10 nm to 40 nm, and is 20 nm as an example.

[0172] In this modified example, the anode structure 50A and the gate structure 50G have the same layer configuration. For example, the anode electrode 54A and the gate electrode 54G have the same layer configuration and can be formed in the same film deposition process. Specifically, the TiN layers 156A and 56G have the same layer configuration and can be formed in the same film deposition process. The Al layers 58A and 58G have the same layer configuration and can be formed in the same film deposition process.

[0173] In the nitride semiconductor device 101, the anode electrode 54A of the diode 113 is Schottky connected to the p-type semiconductor layer 52A. This reduces the leakage current flowing through the diode 113. For example, the TiN layer 156A is connected to the p-type semiconductor layer 52A with a contact resistance higher than that of the TiAl alloy layer. Therefore, the leakage current flowing through the diode 113 can be reduced.

[0174] [Manufacturing Method] Next, the manufacturing method of the nitride semiconductor device 101 according to this modified example will be explained using Figures 8A to 8E. Figures 8A to 8E are cross-sectional views illustrating each step of the manufacturing method of the nitride semiconductor device 101 according to this modified example.

[0175] First, as explained using Figures 5A to 5C, the following steps are performed: forming a semiconductor laminate 40 on a substrate 30, forming impurity regions 44 for spatially separating the active regions 21 to 24, and forming p-type semiconductor layers 52D, 52G, 53G, and 52A.

[0176] Next, as shown in Figure 8A, after forming the insulating layer 60, openings 60D, 60S, 61D, 61S, 61G, 60K, 60R, and 61R are formed by removing a portion of it. In this step, the opening 62G that exposes the p-type semiconductor layer 52G and the opening 162A that exposes the p-type semiconductor layer 52A are not formed. In other words, the p-type semiconductor layers 52G and 52A remain covered by the insulating layer 60.

[0177] Next, a metal film is formed to cover the openings 60D, 60S, 61D, 61S, 61G, 60K, 60R, and 61R. For example, sputtering or vapor deposition can be used to form the metal film. Specifically, after forming the Ti layer 56 and the Al layer 58 in this order, a portion of each of the Ti layer 56 and Al layer 58 is removed by lithography and etching. As a result, as shown in Figure 8B, a laminated structure of Ti layer 56 and Al layer 58 is formed in the openings 60D, 60S, 61D, 61S, 61G, 60K, 60R, and 61R, respectively.

[0178] Next, heat treatment is performed to alloy Ti and Al. Through heat treatment, the Ti layer 56 and Al layer 58 formed in each opening are alloyed, transforming into TiAl alloy layers 56D, 56S, 57D, 57S, 57G, 56K, 56R, and 57R, and Al layers 58D, 58S, 59D, 59S, 59G, 58K, 58R, and 59R. As a result, as shown in Figure 8C, the drain electrode 54D, source electrode 54S, drain electrode 55D, source electrode 55S, gate electrode 55G, cathode electrode 54K, terminal electrode 54R, and terminal electrode 55R are formed.

[0179] Next, as shown in Figure 8D, after forming the insulating layer 62, openings 62G and 162A are formed by removing a portion of it. For example, after forming the insulating layer 62 over the entire surface by plasma CVD, openings 62G and 162A are formed by removing a portion of the formed insulating layer 62 by lithography and etching. Both openings 62G and 162A penetrate not only the insulating layer 62 but also the insulating layer 60. The bottom surface of opening 62G exposes the p-type semiconductor layer 52G. The bottom surface of opening 162A exposes the p-type semiconductor layer 52A. After forming openings 62G and 162A, the gate electrode 54G and anode electrode 54A are formed. Specifically, after forming a TiN layer and an Al layer in that order by sputtering or the like, a portion of each of the TiN layer and Al layer is removed by lithography and etching. As a result, a gate electrode 54G including a stacked structure of TiN layer 56G and Al layer 58G is formed so as to cover opening 62G. An anode electrode 54A is formed so as to cover the opening 162A, and includes a laminated structure of a TiN layer 156A and an Al layer 58A.

[0180] Next, as shown in Figure 8E, after forming the insulating layer 64, an opening is formed by removing a portion of it. For example, after forming the insulating layer 64 over the entire surface by plasma CVD, a portion of the formed insulating layer 64 is removed by lithography and etching. The opening is formed so as to expose the upper surfaces of the source electrode 54S, drain electrode 54D, source electrode 55S, and drain electrode 55D.

[0181] Subsequently, as explained using Figures 5I and 5J, the following steps are performed: forming wiring such as source wiring 70S, forming an insulating layer 80, and forming pads such as source pads 90S.

[0182] By following the above steps, the nitride semiconductor device 101 according to this modified example can be manufactured. The order in which various wirings are formed may be modified as appropriate. Furthermore, multiple layers formed in the same process may be formed in different processes.

[0183] (Modification 2 of Embodiment 1) Next, Modification 2 of Embodiment 1 will be described. In this modification, the layer configuration of the gate structure of the ESD protection FET differs from that of Embodiment 1. In the following, the differences from Embodiment 1 will be explained, and the explanation of the common points will be omitted or simplified.

[0184] [Configuration] First, the configuration of the nitride semiconductor device 102 according to the modified example 2 will be explained using Figure 9. Figure 9 is a cross-sectional view of the nitride semiconductor device 102 according to this modified example. The plan view of the nitride semiconductor device 102 is the same as the plan view shown in Figure 2.

[0185] As shown in Figure 9, the nitride semiconductor device 102, compared to the nitride semiconductor device 1, is equipped with an ESD protection FET 112 instead of an ESD protection FET 12. Since the configuration other than the ESD protection FET 112 is the same as that of the nitride semiconductor device 1, the configuration of the ESD protection FET 112 will be described below.

[0186] Figure 10 is a cross-sectional view of the ESD-protected FET 112 according to this modified example. The ESD-protected FET 112 differs from the ESD-protected FET 12 shown in Figure 4B in the layer configuration of the gate electrode 55G. Specifically, the gate electrode 55G of the ESD-protected FET 112 according to this modified example includes a TiN layer 157G instead of a TiAl alloy layer 57G. In other words, the gate electrode 55G of the ESD-protected FET 112 includes a laminated structure of a TiN layer 157G and an Al layer 59G.

[0187] The TiN layer 157G is in contact with the upper surface of the p-type semiconductor layer 53G through an opening 162G provided in the insulating layer 60. The TiN layer 157G is a conductive layer mainly composed of TiN, and is, for example, a conductive metal nitride layer substantially containing only TiN. The thickness of the TiN layer 157G is 10 nm to 40 nm, and is 20 nm as an example.

[0188] In this modified example, the gate structure 51G of the ESD protection FET 112 and the gate structure 50G of the power FET 11 have the same layer configuration. For example, the gate electrode 55G and the gate electrode 54G have the same layer configuration and can be formed in the same film deposition process. Specifically, the TiN layers 157G and 56G have the same layer configuration and can be formed in the same film deposition process. The Al layers 59G and 58G have the same layer configuration and can be formed in the same film deposition process.

[0189] In the nitride semiconductor device 102, the gate electrode 55G of the ESD protection FET 112 is Schottky connected to the p-type semiconductor layer 53G. This reduces the forward gate current of the ESD protection FET 112. For example, the TiN layer 157G is connected to the p-type semiconductor layer 53G with a contact resistance higher than that of the TiAl alloy layer. As a result, the forward gate current of the ESD protection FET 112 is reduced, and the leakage current when the ESD protection circuit is off can be reduced.

[0190] [Manufacturing Method] Next, the manufacturing method of the nitride semiconductor device 102 according to this modified example will be explained using Figures 11A to 11E. Figures 11A to 11E are cross-sectional views illustrating each step of the manufacturing method of the nitride semiconductor device 102 according to this modified example.

[0191] First, as explained using Figures 5A to 5C, the following steps are performed: forming a semiconductor laminate 40 on a substrate 30, forming impurity regions 44 for spatially separating the active regions 21 to 24, and forming p-type semiconductor layers 52D, 52G, 53G, and 52A.

[0192] Next, as shown in Figure 11A, after forming the insulating layer 60, openings 60D, 60S, 61D, 61S, 60A, 60K, 60R, and 61R are formed by removing a portion of it. In this step, the opening 62G that exposes the p-type semiconductor layer 52G and the opening 162G that exposes the p-type semiconductor layer 53G are not formed. In other words, the p-type semiconductor layers 52G and 53G remain covered by the insulating layer 60.

[0193] Next, a metal film is formed to cover the openings 60D, 60S, 61D, 61S, 60A, 60K, 60R, and 61R. For example, sputtering or vapor deposition can be used to form the metal film. Specifically, after forming the Ti layer 56 and the Al layer 58 in this order, a portion of each of the Ti layer 56 and Al layer 58 is removed by lithography and etching. As a result, as shown in Figure 11B, a laminated structure of Ti layer 56 and Al layer 58 is formed in the openings 60D, 60S, 61D, 61S, 60A, 60K, 60R, and 61R, respectively.

[0194] Next, heat treatment is performed to alloy Ti and Al. Through heat treatment, the Ti layer 56 and Al layer 58 formed in each opening are alloyed, transforming into TiAl alloy layers 56D, 56S, 57D, 57S, 56A, 56K, 56R and 57R, and Al layers 58D, 58S, 59D, 59S, 58A, 58K, 58R and 59R. As a result, as shown in Figure 11C, the drain electrode 54D, source electrode 54S, drain electrode 55D, source electrode 55S, anode electrode 54A, cathode electrode 54K, terminal electrode 54R and terminal electrode 55R are formed.

[0195] Next, as shown in Figure 11D, after forming the insulating layer 62, openings 62G and 162G are formed by removing a portion of it. For example, after forming the insulating layer 62 over the entire surface by plasma CVD, openings 62G and 162G are formed by removing a portion of the formed insulating layer 62 by lithography and etching. Both openings 62G and 162G penetrate not only the insulating layer 62 but also the insulating layer 60. The bottom surface of opening 62G exposes the p-type semiconductor layer 52G. The bottom surface of opening 162G exposes the p-type semiconductor layer 53G. After forming openings 62G and 162G, gate electrodes 54G and 55G are formed. Specifically, after forming a TiN layer and an Al layer in that order by sputtering or the like, a portion of each of the TiN layer and Al layer is removed by lithography and etching. As a result, a gate electrode 54G including a stacked structure of a TiN layer 56G and an Al layer 58G is formed so as to cover opening 62G. A gate electrode 55G is formed so as to cover the opening 162G, and includes a laminated structure of a TiN layer 157G and an Al layer 59G.

[0196] Next, as shown in Figure 11E, an opening is formed by removing a portion of the insulating layer 64 after it has been formed. For example, after forming the insulating layer 64 over the entire surface by plasma CVD, a portion of the formed insulating layer 64 is removed by lithography and etching. The opening is formed so as to expose the upper surfaces of the source electrode 54S, drain electrode 54D, source electrode 55S, and drain electrode 55D.

[0197] Subsequently, as explained using Figures 5I and 5J, the following steps are performed: forming wiring such as source wiring 70S, forming an insulating layer 80, and forming pads such as source pads 90S.

[0198] By following the above steps, the nitride semiconductor device 102 according to this modified example can be manufactured. The order in which various wirings are formed may be modified as appropriate. Furthermore, multiple layers formed in the same process may be formed in different processes.

[0199] (Modification 3 of Embodiment 1) Next, Modification 3 of Embodiment 1 will be described. This modification has a configuration that combines Modification 1 and Modification 2 of Embodiment 1. In the following, the differences from Embodiment 1 will be explained, and the explanation of the common points will be omitted or simplified.

[0200] [Configuration] First, the configuration of the nitride semiconductor device 103 according to the modified example 3 will be explained using Figure 12. Figure 12 is a cross-sectional view of the nitride semiconductor device 103 according to this modified example. The plan view of the nitride semiconductor device 103 is the same as the plan view shown in Figure 2.

[0201] As shown in Figure 12, the nitride semiconductor device 103, compared to the nitride semiconductor device 1, is equipped with an ESD protection FET 112 instead of an ESD protection FET 12, and a diode 113 instead of a diode 13. The ESD protection FET 112 is the same as the ESD protection FET 112 shown in Modification 2 in Figure 10. The diode 113 is the same as the diode 113 shown in Modification 1 in Figure 7.

[0202] In this modified example, the gate structure 51G of the ESD protection FET 112, the gate structure 50G of the power FET 11, and the anode structure 50A of the diode 113 have the same layer configuration. For example, the gate electrode 55G, gate electrode 54G, and anode electrode 54A have the same layer configuration and can be formed in the same film deposition process. Specifically, the TiN layers 157G, 56G, and 156A have the same layer configuration and can be formed in the same film deposition process. The Al layers 59G, 58G, and 58A have the same layer configuration and can be formed in the same film deposition process.

[0203] According to the nitride semiconductor device 103, the forward gate current of the ESD protection FET 112 is reduced, and the leakage current when the ESD protection circuit is off can be reduced. In addition, the leakage current of the diode 113 can be reduced.

[0204] [Manufacturing Method] Next, the manufacturing method of the nitride semiconductor device 103 according to this modified example will be explained using Figures 13A to 13E. Figures 13A to 13E are cross-sectional views illustrating each step of the manufacturing method of the nitride semiconductor device 103 according to this modified example.

[0205] First, as explained using Figures 5A to 5C, the following steps are performed: forming a semiconductor laminate 40 on a substrate 30, forming impurity regions 44 for spatially separating the active regions 21 to 24, and forming p-type semiconductor layers 52D, 52G, 53G, and 52A.

[0206] Next, as shown in Figure 13A, after forming the insulating layer 60, openings 60D, 60S, 61D, 61S, 60K, 60R, and 61R are formed by removing a portion of it. In this step, the opening 62G that exposes the p-type semiconductor layer 52G, the opening 162G that exposes the p-type semiconductor layer 53G, and the opening 162A that exposes the p-type semiconductor layer 52A are not formed. In other words, the p-type semiconductor layers 52G, 53G, and 52A remain covered by the insulating layer 60.

[0207] Next, a metal film is formed to cover the openings 60D, 60S, 61D, 61S, 60K, 60R, and 61R. For example, sputtering or vapor deposition can be used to form the metal film. Specifically, after forming the Ti layer 56 and the Al layer 58 in this order, a portion of each of the Ti layer 56 and Al layer 58 is removed by lithography and etching. As a result, as shown in Figure 13B, a laminated structure of Ti layer 56 and Al layer 58 is formed in the openings 60D, 60S, 61D, 61S, 60K, 60R, and 61R, respectively.

[0208] Next, a heat treatment is performed to alloy Ti and Al. Through the heat treatment, the Ti layer 56 and Al layer 58 formed in each opening are alloyed, transforming into TiAl alloy layers 56D, 56S, 57D, 57S, 56K, 56R and 57R, and Al layers 58D, 58S, 59D, 59S, 58K, 58R and 59R. As a result, as shown in Figure 13C, the drain electrode 54D, source electrode 54S, drain electrode 55D, source electrode 55S, cathode electrode 54K, terminal electrode 54R and terminal electrode 55R are formed.

[0209] Next, as shown in Figure 13D, after forming the insulating layer 62, openings 62G, 162G, and 162A are formed by removing a portion of it. For example, after forming the insulating layer 62 over the entire surface by plasma CVD, openings 62G, 162G, and 162A are formed by removing a portion of the formed insulating layer 62 by lithography and etching. Openings 62G, 162G, and 162A all penetrate not only the insulating layer 62 but also the insulating layer 60. The bottom surface of opening 62G exposes the p-type semiconductor layer 52G. The bottom surface of opening 162G exposes the p-type semiconductor layer 53G. The bottom surface of opening 162A exposes the p-type semiconductor layer 52A. After forming openings 62G, 162G, and 162A, gate electrodes 54G and 55G and an anode electrode 54A are formed. Specifically, after forming the TiN layer and Al layer in this order by sputtering or the like, a portion of each of the TiN and Al layers is removed by lithography and etching. As a result, a gate electrode 54G including a stacked structure of TiN layer 56G and Al layer 58G is formed so as to cover the opening 62G. A gate electrode 55G including a stacked structure of TiN layer 157G and Al layer 59G is formed so as to cover the opening 162G. An anode electrode 54A including a stacked structure of TiN layer 156A and Al layer 58A is formed so as to cover the opening 162A.

[0210] Next, as shown in Figure 13E, an opening is formed by removing a portion of the insulating layer 64 after it has been formed. For example, after forming the insulating layer 64 over the entire surface by plasma CVD, a portion of the formed insulating layer 64 is removed by lithography and etching. The opening is formed so as to expose the upper surfaces of the source electrode 54S, drain electrode 54D, source electrode 55S, and drain electrode 55D.

[0211] Subsequently, as explained using Figures 5I and 5J, the following steps are performed: forming wiring such as source wiring 70S, forming an insulating layer 80, and forming pads such as source pads 90S.

[0212] By following the above steps, the nitride semiconductor device 103 according to this modified example can be manufactured. The order in which various wirings are formed may be modified as appropriate. Furthermore, multiple layers formed in the same process may be formed in different processes.

[0213] (Embodiment 2) Next, Embodiment 2 will be described. Embodiment 2 differs from Embodiment 1 in that it further includes a Schottky diode. In the following, the differences from Embodiment 1 will be explained, and the explanation of the common points will be omitted or simplified.

[0214] [Circuit Configuration] First, the circuit configuration of the nitride semiconductor device according to this embodiment will be explained using Figure 14. Figure 14 is a circuit diagram of the nitride semiconductor device 201 according to this embodiment.

[0215] As shown in Figure 14, the nitride semiconductor device 201 further includes a Schottky diode 213 compared to the nitride semiconductor device 1 shown in Figure 1. The Schottky diode 213 is an example of a second diode and is connected in forward series with diode 13. Specifically, the cathode of the Schottky diode 213 is connected to the anode of diode 13. The anode of the Schottky diode 213 is connected to the gate of the power FET 11 and the drain of the ESD protection FET 12.

[0216] Note that the Schottky diode 213 and diode 13 may be connected in reverse. Specifically, the anode of Schottky diode 213 may be connected to the cathode of diode 13, and the cathode of Schottky diode 213 may be connected to the gate of ESD protection FET 12 and the other end of the resistive element 14.

[0217] Furthermore, the nitride semiconductor device 201 according to this embodiment may be equipped with an ESD protection FET 112 according to modification 2 or 3 of Embodiment 1 instead of the ESD protection FET 12. Also, the nitride semiconductor device 201 may be equipped with a diode 113 according to modification 1 or 3 of Embodiment 1 instead of the diode 13.

[0218] [Configuration] Next, the specific configuration of the nitride semiconductor device 201 will be explained using Figure 15. Figure 15 is a plan view of the nitride semiconductor device 201 according to this embodiment.

[0219] As shown by the dashed rectangle in Figure 15, the nitride semiconductor device 201 includes five active regions 21, 22, 23, 24, and 225 that do not overlap with each other in a plan view of the substrate 30. The active regions 21, 22, 23, 24, and 225 are spatially separated by an inactive region 25.

[0220] The active region 225 is an example of a fifth region, is included in the semiconductor laminate 40, and is a region where 2DEG 43 can occur. The active region 225 corresponds to the region through which the forward current of the Schottky diode 213 flows. The anode structure 250A and cathode structure 250K included in the Schottky diode 213 are provided on the active region 225.

[0221] The cross-sectional view of the nitride semiconductor device 201 is the same as the cross-sectional view of the nitride semiconductor device 1 shown in Figure 3, except for the Schottky diode 213. The cross-sectional view of the Schottky diode 213 will be explained using Figure 16. Figure 16 is a cross-sectional view of the Schottky diode 213 according to this embodiment.

[0222] The Schottky diode 213 includes two anode structures 250A and one cathode structure 250K. In this embodiment, the cathode structure 250K is positioned between the two anode structures 250A. As shown in Figure 15, each of the anode structures 250A and cathode structures 250K has an elongated shape in one direction. Figure 16 shows a cross-section of the anode structures 250A and cathode structures 250K perpendicular to the longitudinal direction (a cross-section parallel to the short direction).

[0223] The number of anode structures 250A and cathode structures 250K included in the Schottky diode 213 is not particularly limited and may be one of each or multiple of each. When multiple anode structures 250A and cathode structures 250K are included, the anode structures 250A and cathode structures 250K are arranged alternately one at a time.

[0224] The anode structure 250A is an example of a second anode structure and functions as the anode of the Schottky diode 213. The anode structure 250A is electrically connected to the gate structure 50G of the power FET 11 and the drain structure 50D of the ESD protection FET 12. The anode structure 250A includes a conductive anode electrode 254A.

[0225] The anode electrode 254A is an example of a fourth metal layer, and is Schottky connected to the semiconductor laminate 40. Specifically, the anode electrode 254A is provided on the active region 225 of the semiconductor laminate 40 and is Schottky connected to 2DEG 43 within the active region 225.

[0226] The anode electrode 254A includes a laminated structure of a TiN layer 256A and an Al layer 258A. The TiN layer 256A is in contact with the upper surface of the semiconductor laminate 40 (the upper surface of the barrier layer 42) through an opening 262A provided in the insulating layer 60. The TiN layer 256A is a conductive layer mainly composed of TiN, for example, a conductive metal nitride layer substantially composed of only TiN. The thickness of the TiN layer 256A is 10 nm to 40 nm, with 20 nm as an example. The Al layer 258A is in contact with and covers the upper surface of the TiN layer 256A. The Al layer 258A is a conductive layer mainly composed of Al, for example, a single metal layer substantially composed of only Al. The thickness of the Al layer 258A is 200 nm to 600 nm, with 200 nm or 400 nm as an example.

[0227] The cathode structure 250K is an example of a second cathode structure and functions as the cathode of the Schottky diode 213. The cathode structure 250K is electrically connected to the anode structure 50A of the diode 13. The cathode structure 250K includes a conductive cathode electrode 254K. The cathode electrode 254K is electrically connected to 2DEG 43 in the active region 225. Specifically, the cathode electrode 254K is provided on the active region 225 of the semiconductor laminate 40 and is ohmic connected to 2DEG 43 in the active region 225.

[0228] The cathode electrode 254K includes a laminated structure of a TiAl alloy layer 256K and an Al layer 258K. The TiAl alloy layer 256K is in contact with the upper surface of the semiconductor laminate 40 (the upper surface of the barrier layer 42) through an opening 260K provided in the insulating layer 60. The TiAl alloy layer 256K is a conductive layer mainly composed of an alloy of Ti and Al, for example, an alloy layer substantially composed only of TiAl alloy. The thickness of the TiAl alloy layer 256K is 10 nm to 40 nm, with 20 nm as an example. The Al layer 258K is in contact with and covers the upper surface of the TiAl alloy layer 256K. The Al layer 258K is a conductive layer mainly composed of Al, for example, a single-metal layer substantially composed only of Al. The thickness of the Al layer 258K is 200 nm to 600 nm, with 200 nm or 400 nm as an example.

[0229] In this embodiment, the source structure 50S, source structure 51S, drain structure 51D, cathode structure 50K, cathode structure 250K, terminal structure 50R, and terminal structure 51R have the same layer configuration. For example, the source electrodes 54S and 55S, drain electrodes 54D and 55D, gate electrode 55G, anode electrode 54A, cathode electrodes 54K and 254K, and terminal electrodes 54R and 55R have the same layer configuration. Therefore, these electrodes can be formed in the same film deposition process. Specifically, the TiAl alloy layers 56S, 56D, 57S, 57D, 57G, 56A, 56K, 256K, 56R, and 57R have the same layer configuration and can be formed in the same film deposition process. The Al layers 58S, 58D, 59S, 59D, 59G, 58A, 58K, 258K, 58R, and 59R have the same layer structure and can be formed using the same film deposition process.

[0230] [Effects, etc.] As described above, in the nitride semiconductor device 201 according to this embodiment, a Schottky diode 213 is connected in forward series with the diode 13. The forward voltage of the Schottky diode 213 is lower than the forward voltage of the diode 13. For example, the forward voltage of the Schottky diode 213 is less than 1V.

[0231] This allows the forward voltage of the Schottky diode 213 to be adjusted if the forward voltage required for the clamp diode to keep the ESD protection FET 12 off during the normal operation of the power FET 11 is insufficient with diode 13 alone. For example, although diode 13 is a pn diode, the carrier concentration of the p-type semiconductor layer 52A of the anode structure 50A is susceptible to manufacturing variations, which may cause the forward voltage to be lower than expected. To address this, providing the Schottky diode 213 enables ESD protection without interfering with the normal operation of the power FET 11. The nitride semiconductor device 201 may also include two or more Schottky diodes 213 connected in series in the forward direction.

[0232] Furthermore, in the nitride semiconductor device 201 according to this embodiment, the number of diodes can be reduced compared to the case where all clamp diodes are formed from Schottky diodes, thus reducing the circuit area of ​​the nitride semiconductor device 201. Diodes 13 and Schottky diode 213 have less variation in forward characteristics within the wafer plane than gate-source short FET diodes, thus reducing the variation in the circuit characteristics of the nitride semiconductor device 201.

[0233] The manufacturing method for the nitride semiconductor device 201 according to this embodiment is a combination of the manufacturing method according to Embodiment 3, which will be described next, and the manufacturing method according to Embodiment 1 and its modified form. Therefore, the explanation will be omitted here.

[0234] (Embodiment 3) Next, Embodiment 3 will be described. Embodiment 3 differs from Embodiment 1 in that it is equipped with multiple Schottky diodes instead of pn diodes as clamp diodes. In the following, the differences from Embodiment 1 will be explained, and the explanation of the common points will be omitted or simplified.

[0235] [Circuit Configuration] First, the circuit configuration of the nitride semiconductor device 301 according to this embodiment will be explained using Figure 17. Figure 17 is a circuit diagram of the nitride semiconductor device 301 according to this embodiment.

[0236] As shown in Figure 17, the nitride semiconductor device 301, compared to the nitride semiconductor device 1 shown in Figure 1, includes multiple Schottky diodes 213 instead of diode 13. The multiple Schottky diodes 213 are connected in series in the forward direction to form a diode array. The anode terminal of the diode array is connected to the gate of the power FET 11 and the drain of the ESD protection FET 12. The cathode terminal of the diode array is connected to the gate of the ESD protection FET 12 and the other terminal of the resistor element 14. The number of Schottky diodes 213 constituting the diode array is nine, but is not limited to this.

[0237] [Configuration] Next, the specific configuration of the nitride semiconductor device 301 will be described using Figures 18 and 19. Figure 18 is a plan view of the nitride semiconductor device 301 according to this embodiment. Figure 19 is a cross-sectional view of the nitride semiconductor device 301 according to this embodiment.

[0238] As shown by the dashed rectangle in Figure 18, the nitride semiconductor device 301 includes four active regions 21, 22, 323, and 24 that do not overlap with each other in a plan view of the substrate 30. The active regions 21, 22, 323, and 24 are spatially separated by an inactive region 25.

[0239] The active region 323 is an example of a third region, is included in the semiconductor stack 40, and is a region where 2DEG 43 can occur. The anode structure 250A and cathode structure 250K included in each of the multiple Schottky diodes 213 are provided on the active region 323. In Figure 18, the active region 323 is represented by a dashed rectangular region, but a part of this dashed rectangular region is deactivated and 2DEG does not occur there. In substance, the active region 323 contains nine 2DEG regions where 2DEG can occur, and these nine 2DEG regions are arranged in a 3x3 grid.

[0240] The nine Schottky diodes 213 have the same configuration as each other. Specifically, each of the nine Schottky diodes 213 includes two anode structures 250A and one cathode structure 250K. In this embodiment, the cathode structure 250K is positioned between the two anode structures 250A. As shown in Figure 18, each of the anode structures 250A and cathode structures 250K has an elongated shape in one direction. Figure 19 shows a cross-section of the anode structures 250A and cathode structures 250K perpendicular to the longitudinal direction (a cross-section parallel to the short direction).

[0241] The nine Schottky diodes 213 are electrically connected to each other via wiring, with their anode structure 250A and cathode structure 250K being connected to one another. This connects the nine Schottky diodes 213 in series in the forward direction. Note that the wiring example shown in Figure 18 is just one example and is not limited to this.

[0242] The contact portion between the anode electrode 254A and the semiconductor laminate 40 (the bottom surface of the opening 262A) is, for example, 0.8 μm in width and 10 μm in length. The contact portion between the cathode electrode 254K and the semiconductor laminate 40 (the bottom surface of the opening 260K) is, for example, 4.2 μm in width and 10 μm in length. The distance between the anode electrode 254A and the cathode electrode 254K is, for example, 1.65 μm. These dimensions are merely examples and are not limiting.

[0243] Figure 19 shows one of the nine Schottky diodes 213, which includes an anode structure 250A corresponding to the anode end of the diode array. The cross-sectional structure of the Schottky diode 213 is the same as the cross-sectional structure shown in Figure 16.

[0244] In the nitride semiconductor device 301 according to this embodiment, the gate electrode 55G and the p-type semiconductor layer 53G are connected with low resistance in the gate structure 51G of the ESD protection FET 12. Specifically, the TiAl alloy layer 57G of the gate electrode 55G is in contact with the p-type semiconductor layer 53G, resulting in lower resistance than when the TiN layer is in contact with the p-type semiconductor layer 53G. For example, the TiN layer is Schottky connected to the p-type semiconductor layer 53G, whereas the gate electrode 55G and the p-type semiconductor layer 53G are ohmic connected.

[0245] This reduces the voltage drop across the gate structure 51G, allowing the ESD protection FET 12 to be driven with a lower gate voltage. As a result, the drain current flowing through the ESD protection FET 12 increases. In other words, a large ESD current can be passed through the ESD protection FET 12 even with a smaller area. Therefore, the area of ​​the ESD protection FET 12 can be reduced.

[0246] [Manufacturing Method] Next, the manufacturing method of the nitride semiconductor device 301 according to this embodiment will be described using Figures 20A to 20F. Figures 20A to 20F are cross-sectional views illustrating each step of the manufacturing method of the nitride semiconductor device 301 according to this embodiment.

[0247] First, as explained using Figures 5A and 5B, the process involves forming a semiconductor laminate 40 on a substrate 30 and forming impurity regions 44 for spatially separating the active regions 21, 22, 23, and 24.

[0248] Next, a portion of the p-type semiconductor layer 52 is removed by lithography and etching. This forms p-type semiconductor layers 52D, 52G, and 53G, as shown in Figure 20A. In this embodiment, the p-type semiconductor layer 52 is completely removed from the region where the Schottky diode 213 is formed (active region 323). The same procedure is followed for the region where the Schottky diode 213 is formed (active region 225) in Embodiment 2.

[0249] Next, as shown in Figure 20B, after forming the insulating layer 60, openings 60D, 60S, 61D, 61S, 61G, 260K, 60R, and 61R are formed by removing a portion of it. In this step, no opening 62G is formed that exposes the p-type semiconductor layer 52G. In other words, the p-type semiconductor layer 52G remains covered by the insulating layer 60.

[0250] Next, a metal film is formed to cover the openings 60D, 60S, 61D, 61S, 61G, 260K, 60R, and 61R. For example, sputtering or vapor deposition can be used to form the metal film. Specifically, after forming the Ti layer 56 and the Al layer 58 in this order, a portion of each of the Ti layer 56 and Al layer 58 is removed by lithography and etching. As a result, as shown in Figure 20C, a laminated structure of Ti layer 56 and Al layer 58 is formed in the openings 60D, 60S, 61D, 61S, 61G, 260K, 60R, and 61R, respectively.

[0251] Next, a heat treatment is performed to alloy Ti and Al. Through the heat treatment, the Ti layer 56 and Al layer 58 formed in each opening are alloyed, transforming into TiAl alloy layers 56D, 56S, 57D, 57S, 57G, 256K, 56R, and 57R, and Al layers 58D, 58S, 59D, 59S, 59G, 258K, 58R, and 59R. As a result, as shown in Figure 20D, the drain electrode 54D, source electrode 54S, drain electrode 55D, source electrode 55S, gate electrode 55G, cathode electrode 254K, terminal electrode 54R, and terminal electrode 55R are formed.

[0252] Next, as shown in Figure 20E, after forming the insulating layer 62, openings 62G and 262A are formed by removing a portion of it. For example, after forming the insulating layer 62 over the entire surface by plasma CVD, openings 62G and 262A are formed by removing a portion of the formed insulating layer 62 by lithography and etching. Both openings 62G and 262A penetrate not only the insulating layer 62 but also the insulating layer 60. The p-type semiconductor layer 52G is exposed at the bottom of opening 62G. The semiconductor laminate 40 (barrier layer 42) is exposed at the bottom of opening 262A. After forming openings 62G and 262A, the gate electrode 54G and anode electrode 254A are formed. Specifically, after forming the TiN layer and Al layer in this order by sputtering or the like, a portion of each of the TiN layer and Al layer is removed by lithography and etching. As a result, a gate electrode 54G including a stacked structure of a TiN layer 56G and an Al layer 58G is formed so as to cover the opening 62G. An anode electrode 254A including a stacked structure of a TiN layer 256A and an Al layer 258A is formed so as to cover the opening 262A.

[0253] Next, as shown in Figure 20F, an opening is formed by removing a portion of the insulating layer 64 after it has been formed. For example, after forming the insulating layer 64 over the entire surface by plasma CVD, a portion of the formed insulating layer 64 is removed by lithography and etching. The opening is formed so as to expose the upper surfaces of the source electrode 54S, drain electrode 54D, source electrode 55S, and drain electrode 55D.

[0254] Subsequently, as explained using Figures 5I and 5J, the following steps are performed: forming wiring such as source wiring 70S, forming an insulating layer 80, and forming pads such as source pads 90S.

[0255] By following the above steps, the nitride semiconductor device 301 according to this modified example can be manufactured. The order in which various wirings are formed may be modified as appropriate. Furthermore, multiple layers formed in the same process may be formed in different processes.

[0256] (Other Embodiments) Although nitride semiconductor devices according to one or more embodiments have been described above based on embodiments, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to these embodiments that a person skilled in the art could conceive of, and forms constructed by combining components from different embodiments are also included within the scope of this disclosure.

[0257] For example, in the above embodiment, the p-type semiconductor layer 52G and the gate electrode 54G are in contact in the gate structure 50G, but this is not limited to this. The gate structure 50G may include another nitride semiconductor layer, such as an i-type nitride semiconductor layer, between the p-type semiconductor layer 52G and the gate electrode 54G. The same applies to the gate structure 51G and the anode structure 50A. Examples of the i-type nitride semiconductor layer are i-type GaN, i-type AlGaN, etc. By providing an i-type nitride semiconductor layer, the gate leakage current or the anode leakage current can be reduced.

[0258] Furthermore, for example, if an i-type nitride semiconductor layer is included, a portion of the i-type nitride semiconductor layer may be converted to p-type by ion implantation or the like. The carrier concentration in the p-type portion may be higher than the carrier concentration in the p-type semiconductor layer. This can reduce contact resistance.

[0259] Furthermore, each of the above embodiments may be modified, replaced, added, or omitted in various ways within the scope of the claims or equivalent thereof.

[0260] This disclosure can be used, for example, in power amplifiers for high-power or high-frequency applications, wireless communication base stations or terminal equipment in which such power amplifiers are used, or wireless power supply devices that perform power transmission using microwaves.

[0261] 1, 101, 102, 103, 201, 301 Nitride semiconductor device 11 Power FET 12, 112 ESD protection FET 13, 113 Diode 14 Resistor Element 21, 22, 23, 24, 225, 323 Active Region 24a, 24b, 24c 2DEG Region 25 Inactive Region 30 Substrate 40 Semiconductor Laminate 41 Channel Layer 42 Barrier Layer 43 2DEG 44 Impurity Region 50A, 250A Anode Structure 50D, 51D Drain Structure 50G, 51G Gate Structure 50K, 250K Cathode Structure 50R, 51R Terminal Structure 50S, 51S Source Structure 52, 52A, 52D, 52G, 53G p-type Semiconductor Layer 54A, 254A Anode electrode 54D, 55D Drain electrode 54G, 55G Gate electrode 54K, 254K Cathode electrode 54R, 55R Terminal electrode 54S, 55S Source electrode 56 Ti layer 56A, 56D, 56K, 56R, 56S, 57D, 57G, 57R, 57S, 256K TiAl alloy layer 56G, 156A, 157G, 256A TiN layer 58, 58A, 58D, 58G, 58K, 58R, 58S, 59D, 59G, 59R, 59S, 258A, 258K Al layer 60, 62, 64, 80 Insulating layer 60A, 60D, 60K, 60R, 60S, 61D, 61G, 61R, 61S, 62G, 162A, 162G, 260K, 262A Opening 70, 71, 72, 73 Wiring 70D, 71D Drain Wiring 70G Gate Wiring 70R, 71R Connection Wiring 70S, 71S Source Wiring 90D Drain Pad 90G Gate Pad 90S Source Pad 213 Schottky Diode

Claims

1. A semiconductor laminate comprising: a substrate; a semiconductor laminate containing a two-dimensional electron gas provided above the substrate, comprising a first region, a second region, a third region and a fourth region that do not overlap with each other in a plan view; a first transistor provided on the first region, comprising a first source structure, a first drain structure and a first gate structure; a second transistor provided on the second region, comprising a second source structure, a second drain structure and a second gate structure; a first diode provided on the third region, comprising a first anode structure and a first cathode structure; and a resistive element provided on the fourth region, comprising a first terminal structure and a second terminal structure, wherein the first gate structure comprises a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer; and the second gate structure comprises a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer. The first anode structure includes a third p-type semiconductor layer and a third metal layer provided above the third p-type semiconductor layer, the first metal layer being Schottky connected to the first p-type semiconductor layer, the first gate structure, the second drain structure and the first anode structure being electrically connected to each other, the first source structure, the second source structure and the first terminal structure being electrically connected to each other, and the second gate structure, the first cathode structure and the second terminal structure being electrically connected to each other, wherein the nitride semiconductor device.

2. The nitride semiconductor device according to claim 1, wherein the second metal layer is ohmic-connected to the second p-type semiconductor layer.

3. The nitride semiconductor device according to claim 1, wherein the second metal layer is an alloy layer containing Ti and Al, and includes an alloy layer in contact with the second p-type semiconductor layer, and the second p-type semiconductor layer is a group III nitride semiconductor layer.

4. The nitride semiconductor device according to any one of claims 1 to 3, wherein the third metal layer is ohmic connected to the third p-type semiconductor layer.

5. The nitride semiconductor device according to any one of claims 1 to 3, wherein the third metal layer is an alloy layer containing Ti and Al, and includes an alloy layer in contact with the third p-type semiconductor layer, and the third p-type semiconductor layer is a group III nitride semiconductor layer.

6. The nitride semiconductor device according to claim 1, wherein the second metal layer is Schottky connected to the second p-type semiconductor layer.

7. The nitride semiconductor device according to claim 1, wherein the second metal layer includes a TiN layer in contact with the second p-type semiconductor layer, and the second p-type semiconductor layer is a group III nitride semiconductor layer.

8. The nitride semiconductor device according to any one of claims 1 to 3, 6 and 7, wherein the third metal layer is Schottky connected to the third p-type semiconductor layer.

9. The nitride semiconductor device according to any one of claims 1 to 3, 6 and 7, wherein the third metal layer includes a TiN layer in contact with the third p-type semiconductor layer, and the third p-type semiconductor layer is a group III nitride semiconductor layer.

10. The nitride semiconductor device according to any one of claims 1 to 3, 6 and 7, wherein the semiconductor laminate includes a fifth region that does not overlap with any of the first, second, third, and fourth regions, and the nitride semiconductor device further comprises a second diode provided on the fifth region, including a second anode structure and a second cathode structure, the second anode structure is Schottky connected to the semiconductor laminate, and the second diode is forward-series connected to the first diode on a path connecting the first gate structure and the second gate structure.

11. The nitride semiconductor device according to claim 10, wherein the third metal layer is ohmic-connected to the third p-type semiconductor layer.

12. The nitride semiconductor device according to claim 10, wherein the third metal layer is an alloy layer containing Ti and Al, and includes an alloy layer in contact with the third p-type semiconductor layer, and the third p-type semiconductor layer is a group III nitride semiconductor layer.

13. The nitride semiconductor device according to claim 10, wherein the third metal layer is Schottky connected to the third p-type semiconductor layer.

14. The nitride semiconductor device according to claim 10, wherein the third metal layer includes a TiN layer in contact with the third p-type semiconductor layer, and the third p-type semiconductor layer is a group III nitride semiconductor layer.

15. A semiconductor laminate comprising: a substrate; a semiconductor laminate containing a two-dimensional electron gas provided above the substrate, comprising a first region, a second region, a third region and a fourth region that do not overlap with each other in a plan view; a first transistor provided on the first region, comprising a first source structure, a first drain structure and a first gate structure; a second transistor provided on the second region, comprising a second source structure, a second drain structure and a second gate structure; a plurality of diodes provided on the third region, each comprising an anode structure and a cathode structure; and a resistive element provided on the fourth region, comprising a first terminal structure and a second terminal structure, wherein the first gate structure comprises a first p-type semiconductor layer and a first metal layer provided above the first p-type semiconductor layer; the second gate structure comprises a second p-type semiconductor layer and a second metal layer provided above the second p-type semiconductor layer; and the first metal layer is Schottky connected to the first p-type semiconductor layer. A nitride semiconductor device wherein the second metal layer is ohmic-connected to the second p-type semiconductor layer, the anode structure is Schottky-connected to the semiconductor laminate, the plurality of diodes are connected in series in the forward direction to form a diode array, the first gate structure, the second drain structure, and the anode structure corresponding to the anode end of the diode array are electrically connected to each other, the first source structure, the second source structure, and the first terminal structure are electrically connected to each other, and the second gate structure, the cathode structure corresponding to the cathode end of the diode array, and the second terminal structure are electrically connected to each other.

16. The nitride semiconductor device according to claim 15, wherein the second metal layer is an alloy layer containing Ti and Al, and includes an alloy layer in contact with the second p-type semiconductor layer, and the second p-type semiconductor layer is a group III nitride semiconductor layer.

Images