Heterojunction solar cell and preparation method therefor, and photovoltaic module

AU2026204267A1Pending Publication Date: 2026-07-23CANADIAN SOLAR SUNENERGY (JIAXING) CO LTD
View PDF 0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
AU · AU
Patent Type
Applications
Current Assignee / Owner
CANADIAN SOLAR SUNENERGY (JIAXING) CO LTD
Filing Date
2026-01-07
Publication Date
2026-07-23

AI Technical Summary

Technical Problem

Existing heterojunction solar cells have problems with tunneling contacts and edge short circuits or leakage, which affect cell performance and thermal degradation reliability.

Method used

By setting a composite film structure with multiple intrinsic back layers and doped layers on the surface and sidewalls of the silicon substrate, the stability and insulation effect of the tunneling contact are ensured. Specific film deposition sequence and process parameters are used to avoid damage and improve the photoelectric conversion efficiency of the cell.

Benefits of technology

This resulted in improved insulation performance, superior tunneling contact, enhanced thermal decay reliability, and significantly improved photoelectric conversion efficiency in heterojunction solar cells.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure 00000056_0000
    Figure 00000056_0000
  • Figure 00000056_0001
    Figure 00000056_0001
  • Figure 00000057_0000
    Figure 00000057_0000
Patent Text Reader

Abstract

Provided in the present disclosure are a heterojunction solar cell and a preparation method therefor, and a photovoltaic module. The heterojunction solar cell comprises a silicon substrate and a first intrinsic layer. The silicon substrate has a first surface, a second surface opposite the first surface, and a sidewall surface connecting the first surface and the second surface, wherein at least one back intrinsic layer, a back doped layer, a second transparent oxide conductive layer and a second electrode are stacked in sequence on the first surface; a back doped layer is further disposed on the sidewall surface; at least one front intrinsic layer, a front doped layer, a first transparent oxide conductive layer and a first electrode are stacked in sequence on the second surface; and a front doped layer is configured to be further disposed on the sidewall surface. The first intrinsic layer is disposed between the front doped layer and the back doped layer on the sidewall surface.
Need to check novelty before this filing date? Find Prior Art