A clock phase detection system

Abstract

The present application provides a clock phase detection system, including a first sampling unit for receiving a first clock signal and sampling the first clock signal, a second sampling unit for receiving a second clock signal and sampling the second clock signal, a phase detector connected to the first sampling unit and the second sampling unit at the same time, and used to obtain the phase difference between the first clock signal and the second clock signal according to the first sampling information sent by the first sampling unit and the second sampling information sent by the second sampling unit, and a sampling control unit connected to the phase detector, the first sampling unit, and the second sampling unit respectively, and used to send a third clock signal to the first sampling unit and the second sampling unit according to the phase difference output by the phase detector, so that the first sampling unit and the second sampling unit use the frequency of the third clock signal as the sampling frequency to work. The present application can obtain a high-precision clock phase difference value.

Description

Technical Field

[0001] The present application relates to the technical field of phase detection, and in particular to a clock phase detection system. Background Art

[0002] Phase detectors are used to detect the phase difference between two signals. In clock signal processing, phase detection plays an important role and has been widely used in communications and phase-locked loops.

[0003] Current phase detectors such as Figure 1 As shown, the first latch 10 and the control circuit 20 are composed. The control circuit 20 includes a control logic 21 and a second latch 22.

[0004] In a specific application process, in response to the phase difference Φ between the first input signal S1 and the second input signal S2, the first latch 10 generates a first output signal P1 and a second output signal P2. The first output signal P1 and the second output signal P2 both contain first phase information Φ1 and second phase information Φ2 of the phase difference Φ. Further, the control logic 21 filters out the second phase information Φ2 from the first output signal P1 and filters out the second phase information Φ2 from the second output signal P2 to generate a first filtered signal q1 and a second filtered signal q2. The second latch 22 generates a phase indication signal PD based on the first filtered signal q1 and the second filtered signal q2.

[0005] It can be seen that the existing phase detector first obtains the phase information of the two input signals by using the first latch 10, and then filters the two output signals respectively by using the control logic 21, and then performs phase comparison by using the second latch 22.

[0006] Regarding the existing phase detector, the applicant of the present application found that although the existing phase detector can realize phase detection, it can only provide the phase leading / lagging result, but cannot provide a high-precision phase difference value. Therefore, how to obtain a high-precision clock phase difference value is a technical problem that urgently needs to be solved. Summary of the invention

[0007] In view of this, the present application provides a clock phase detection system, which can obtain a high-precision clock phase difference value. The technical solution is as follows:

[0008] The present application provides a clock phase detection system, comprising:

[0009] A first sampling unit configured to receive a first clock signal and sample the first clock signal;

[0010] a second sampling unit configured to receive a second clock signal and sample the second clock signal;

[0011] A phase detector connected to the first sampling unit and the second sampling unit at the same time, and used to obtain a phase difference between the first clock signal and the second clock signal according to the first sampling information sent by the first sampling unit and the second sampling information sent by the second sampling unit;

[0012] A sampling control unit is respectively connected to the phase detector, the first sampling unit, and the second sampling unit, and is used to send a third clock signal to the first sampling unit and the second sampling unit according to the phase difference output by the phase detector, so that the first sampling unit and the second sampling unit use the frequency of the third clock signal as the sampling frequency for sampling.

[0013] Optionally, the system further comprises:

[0014] a first sampling processing unit located between the first sampling unit and the phase detector;

[0015] A second sampling processing unit is located between the second sampling unit and the phase detector.

[0016] Optionally, the first sampling processing unit and the second sampling processing unit both include:

[0017] A second processor is configured to obtain the first sampling information or the second sampling information based on an averaging algorithm.

[0018] Optionally, the phase detector comprises a digital phase detector.

[0019] Optionally, when the phase difference between the first clock signal and the second clock signal is N, the sampling control unit adjusts the frequency of the third clock signal so that the phase difference between the first clock signal and the second clock signal changes from N to N+1 or N-1, where N is a positive number.

[0020] The clock phase detection system provided by the present application includes a first sampling unit, a second sampling unit, a phase detector and a sampling control unit. In the application process of the present application, the phase detector obtains the phase difference between the first clock signal and the second clock signal based on the first sampling information sent by the first sampling unit and the second sampling information sent by the second sampling unit. The sampling control unit further sends a third clock signal to the first sampling unit and the second sampling unit based on the phase difference output by the phase detector, so that the first sampling unit and the second sampling unit use the frequency of the third clock signal as the sampling frequency to work. The present application can obtain an accurate phase difference value by using the phase detector, and further uses the sampling control unit to implement feedback adjustment based on the phase difference, forming a feedback loop, and further ensuring the accuracy of the phase difference value output by the phase detector. The clock phase detection system provided by the present application can obtain a high-precision clock phase difference value. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0022] Figure 1 It is a structural schematic diagram of a phase detector in the prior art;

[0023] Figure 2 A schematic diagram of the structure of a clock phase detection system provided by the present application;

[0024] Figure 3 A schematic diagram of the structure of another clock phase detection system provided by the present application;

[0025] Figure 4 Schematic diagram of the structure of the sampling processing unit in this application. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] like Figure 2As shown, the clock phase detection system provided by the present application includes: a first sampling unit 100, a second sampling unit 200, a phase detector 300 and a sampling control unit 400. The first sampling unit 100 and the second sampling unit 200 are respectively connected to the phase detector 300, the phase detector 300 is connected to the sampling control unit 400, and the sampling control unit 400 is respectively connected to the first sampling unit 100 and the second sampling unit 200.

[0028] Specifically in the present application, the first sampling unit 100 is used to receive a first clock signal Clk1 and sample the first clock signal Clk1 to obtain first sampling information P1. The second sampling unit 200 is used to receive a second clock signal Clk2 and sample the second clock signal Clk2 to obtain second sampling information P2.

[0029] In the present application, the first sampling information P1 includes the phase information, frequency information, amplitude information, etc. of the first clock signal Clk1, and the second sampling information P2 may include the phase information, frequency information, amplitude information, etc. of the second clock signal Clk2. In the present application, preferably, the first sampling information P1 includes the phase information of the first clock signal Clk1, and the second sampling information P2 includes the phase information of the second clock signal Clk2.

[0030] The phase detector 300 is connected to the first sampling unit 100 and the second sampling unit 200 at the same time, and is used to receive the first sampling information P1 sent by the first sampling unit 100 and the second sampling information P2 sent by the second sampling unit 200. The phase detector 300 can obtain the phase difference F0 between the first clock signal Clk1 and the second clock signal Clk2 based on the received first sampling information P1 and second sampling information P2, and then the phase detector 300 continues to send the obtained phase difference F0 to the sampling control unit 400.

[0031] The sampling control unit 400 in the present application is connected to the first sampling unit 100 and the second sampling unit 200 at the same time, and obtains a third clock signal Sample_clk according to the received phase difference F0 output by the phase detector 300, and then the sampling control unit 400 sends the third clock signal Sample_clk to the first sampling unit 100 and the second sampling unit 200 respectively. After receiving the third clock signal Sample_clk, the first sampling unit 100 and the second sampling unit 200 use the frequency of the third clock signal Sample_clk as the sampling frequency, and continue to perform sampling at the sampling frequency.

[0032] In the embodiment of the present application, the frequency of the third clock signal Sample_clk is known. The sampling control unit 400 can know how many clock cycles of the third clock signal Sample_clk are separated from the positions of the rising edges of the first clock signal Clk1 and the second clock signal Clk2 (i.e., the phase difference) according to the phase difference F0 output by the phase detector 300 and the frequencies of the first clock signal Clk1 and the second clock signal Clk2. Assuming that they are separated by N clock cycles, N is a positive number, the sampling control unit 400 can adjust the frequency of the third clock signal Sample_clk according to the parameter N. For example, the frequency of the adjusted clock signal Sample_clk increases (or decreases) compared to the frequency of the clock signal Sample_clk before adjustment, so that the phase difference between the first clock signal Clk1 and the second clock signal Clk2 changes from N to N+1 (or N-1). When N changes to N+1 (N-1), the corresponding number of cycles of the third clock signal Sample_clk is the accurate phase difference.

[0033] After the third clock signal Sample_clk is sent to the first sampling unit 100 and the second sampling unit 200, the first sampling unit 100 and the second sampling unit 200 continue to perform sampling using the frequency of the third clock signal Sample_clk as the sampling frequency, thereby achieving flexible adjustment of the sampling frequencies of the first sampling unit 100 and the second sampling unit 200, thereby ensuring the accuracy of the phase difference F0 output by the phase detector 300.

[0034] The clock phase detection system provided by the present application includes a first sampling unit 100, a second sampling unit 200, a phase detector 300 and a sampling control unit 400. In the application process of the present application, the phase detector 300 obtains the phase difference F0 between the first clock signal Clk1 and the second clock signal Clk2 according to the first sampling information P1 sent by the first sampling unit 100 and the second sampling information P2 sent by the second sampling unit 200. Further, the sampling control unit 400 sends the third clock signal Sample_clk to the first sampling unit 100 and the second sampling unit 200 based on the phase difference F0 output by the phase detector 300, so that the first sampling unit 100 and the second sampling unit 200 use the frequency of the third clock control signal Sample_clk as the sampling frequency for sampling. The present application can obtain an accurate phase difference value by using the phase detector 300, and further realizes feedback adjustment based on the phase difference by using the sampling control unit 400, forming a feedback loop, and further ensuring the accuracy of the phase difference value output by the phase detector 300. The clock phase detection system provided by the present application can obtain a high-precision clock phase difference value.

[0035] Based on the clock phase detection system provided by the embodiment of the previous application, Figure 3As shown, the present application also provides another clock phase detection system. Based on the structure of the clock phase detection system provided in the above embodiment, it also includes a first sampling processing unit 500 located between the first sampling unit 100 and the phase detector 300, and a second sampling processing unit 600 located between the second sampling unit 200 and the phase detector 300.

[0036] Specifically, the first sampling unit 100 is connected to the first sampling processing unit 500 , which is connected to the phase detector 300 . The second sampling unit 200 is connected to the second sampling processing unit 600 , which is connected to the phase detector 300 .

[0037] Specifically in the present application, the first sampling unit 100 is used to receive a first clock signal Clk1 and sample the first clock signal Clk1 to obtain first sampling information P1. The second sampling unit 200 is used to receive a second clock signal Clk2 and sample the second clock signal Clk2 to obtain second sampling information P2.

[0038] Further, the first sampling unit 100 sends the obtained first sampling information P1 to the first sampling processing unit 500 , and the second sampling unit 200 sends the obtained second sampling information P2 to the second sampling processing unit 600 .

[0039] The first sampling processing unit 500 processes the first sampling information P1 by a preset method to obtain third sampling information P1', and sends the third sampling information P1' to the phase detector 300. The second sampling processing unit 600 processes the second sampling information P2 by a preset method to obtain fourth sampling information P2', and sends the fourth sampling information P2' to the phase detector 300.

[0040] Specifically, Figure 4 As shown, the first sampling processing unit 500 and the second sampling processing unit 600 in the present application may both include: a second processor 720 .

[0041] The second processor 720 in the first sampling processing unit 500 can obtain the third sampling information P1' based on an averaging algorithm, and the second processor 720 in the second sampling processing unit 600 can obtain the fourth sampling information P2' based on an averaging algorithm. The averaging algorithm includes, for example, removing the maximum value and the minimum value of the received multiple sampling information, and obtaining the average value of the remaining multiple sampling information. The present application does not limit the specific implementation method of the averaging algorithm.

[0042] After receiving the third sampling information P1′ sent by the first sampling processing unit 500 and the fourth sampling information P2′ sent by the second sampling processing unit 600, the phase detector 300 obtains the phase difference F0′ between the first clock signal Clk1 and the second clock signal Clk2 based on the third sampling information P1′ and the fourth sampling information P2′, and then the phase detector 300 continues to send the obtained phase difference F0′ to the sampling control unit 400.

[0043] The sampling control unit 400 is connected to the first sampling unit 100 and the second sampling unit 200 at the same time, and obtains the third clock signal Sample_clk' according to the phase difference F0' received from the output of the phase detector 300, and then the sampling control unit 400 sends the third clock signal Sample_clk' to the first sampling unit 100 and the second sampling unit 200 respectively, so that the first sampling unit 100 and the second sampling unit 200 continue sampling with the frequency of the third clock signal Sample_clk' as the sampling frequency.

[0044] The clock phase detection system provided by the present application includes a first sampling unit 100, a second sampling unit 200, a phase detector 300, a sampling control unit 400, a first sampling processing unit 500, and a second sampling processing unit 600. In the application process of the present application, the first sampling processing unit 500 first processes the first sampling information P1 sent by the first sampling unit 100 by a preset method to obtain the third sampling information P1', and the second sampling processing unit 600 processes the second sampling information P2 sent by the second sampling unit 200 by a preset method to obtain the fourth sampling information P2', thereby ensuring the accuracy of the phase information. Then, the phase detector 300 obtains the phase difference F0' between the first clock signal Clk1 and the second clock signal Clk2 according to the third sampling information P1' and the fourth sampling information P2'. Further, the sampling control unit 400 sends the third clock signal Sample_clk' to the first sampling unit 100 and the second sampling unit 200 based on the phase difference F0' output by the phase detector 300, so that the first sampling unit 100 and the second sampling unit 200 use the frequency of the third clock signal Sample_clk as the sampling frequency for sampling. The present application uses the first sampling processing unit 500 and the second sampling processing unit 600 to preliminarily process the first sampling information P1 and the second sampling information P2, thereby ensuring the accuracy of the phase information. Further, the phase detector 300 can be used to obtain a more accurate phase difference value, and the sampling control unit 400 is used to implement feedback adjustment based on the phase difference, thereby forming a feedback loop, thereby further ensuring the accuracy of the phase difference value output by the phase detector 300. The clock phase detection system provided by the present application can obtain a high-precision clock phase difference value.

[0045] In the above embodiments of the present application, the phase detector 300 is preferably a digital phase detector.

[0046] The above is a detailed introduction to a clock phase detection system provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A clock phase detection system, characterized in that: include: A first sampling unit configured to receive a first clock signal and sample the first clock signal; a second sampling unit configured to receive a second clock signal and sample the second clock signal; A phase detector connected to the first sampling unit and the second sampling unit at the same time, and used to obtain a phase difference between the first clock signal and the second clock signal according to the first sampling information sent by the first sampling unit and the second sampling information sent by the second sampling unit; A sampling control unit is respectively connected to the phase detector, the first sampling unit, and the second sampling unit, and is used to send a third clock signal to the first sampling unit and the second sampling unit according to the phase difference output by the phase detector, so that the first sampling unit and the second sampling unit use the frequency of the third clock signal as the sampling frequency for sampling.

2. The clock phase detection system according to claim 1, characterized in that: The clock phase detection system also includes: a first sampling processing unit located between the first sampling unit and the phase detector; A second sampling processing unit is located between the second sampling unit and the phase detector.

3. The clock phase detection system according to claim 2, characterized in that: The first sampling processing unit and the second sampling processing unit both include: A second processor is configured to obtain the first sampling information or the second sampling information based on an averaging algorithm.

4. The clock phase detection system according to any one of claims 1 to 3, characterized in that: The phase detector comprises a digital phase detector.

5. The clock phase detection system according to claim 1, characterized in that: When the phase difference between the first clock signal and the second clock signal is N, the sampling control unit adjusts the frequency of the third clock signal so that the phase difference between the first clock signal and the second clock signal changes from N to N+1 or N-1, where N is a positive number.

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