Delay locked loop circuit

Abstract

The invention relates to a delay locked loop circuit comprising: a voltage controlled delay line (VCDL); a phase detector circuit configured to process the first and last output signals of the VCDL to provide: i) an uplink pulse signal; and ii) a downlink pulse signal; a charge pump configured to provide a feedback voltage signal based on the uplink pulse signal and the downlink pulse signal; a phase signal processor configured to process the uplink pulse signal and the downlink pulse signal to provide a delay code lock signal representing whether the first output signal is out of phase with the last output signal by 2 [pi] radian; and a delay code setter configured to provide a delay code setting signal representing one candidate delay code in the sequence of different candidate delay codes. When the delay locked loop circuit is in a calibration operation mode: the fixed voltage source provides a fixed voltage signal as a control voltage signal of the voltage controlled delay line; when the delay code lock signal indicates that the first output signal and the last output signal have no out-of-phase 2 [pi] radians: the delay code setter applies a delay code setting signal to the VCDL such that the delay code setter sequentially applies different candidate delay codes to the voltage controlled delay line until a selected delay code is allocated; and when the delay locked loop circuit is in an active operation mode: the charge pump provides a feedback voltage signal as a control voltage signal of the voltage controlled delay line; and the VCDL uses the selected delay code as the delay code.

Description

Technical Field

[0001] The present disclosure relates to a delay locked loop circuit. Background Art

[0002] According to a first aspect of the present disclosure, there is provided a delay locked loop circuit, the delay locked loop circuit comprising:

[0003] A voltage controlled delay line, the voltage controlled delay line comprising one or more variable components, wherein the voltage controlled delay line is configured to:

[0004] Receive a clock input signal;

[0005] Receive a control voltage signal; and

[0006] Apply a time delay to the clock input signal so as to provide a first output signal and a last output signal, wherein the magnitude of the time delay is based on the control voltage signal and a delay code, and wherein the delay code defines the value of the one or more variable components in the voltage controlled delay line;

[0007] A phase detector circuit, the phase detector circuit being configured to process the first output signal and the last output signal to provide: i) an up pulse signal; and ii) a down pulse signal, wherein the difference between the width of the up pulse signal and the width of the down pulse signal represents the phase difference between the first output signal and the last output signal;

[0008] A charge pump, the charge pump being configured to provide a feedback voltage signal based on the up pulse signal and the down pulse signal;

[0009] A phase signal processor, the phase signal processor being configured to process the up pulse signal and the down pulse signal to provide a delay code lock signal, the delay code lock signal indicating whether the first output signal is out of phase by 2Π radians with the last output signal;

[0010] A delay code setter, the delay code setter being configured to provide a delay code setting signal representing one candidate delay code in a sequence of different candidate delay codes;

[0011] A fixed voltage source, the fixed voltage source being configured to provide a fixed voltage signal; and

[0012] A switch circuit, the switch circuit being configured to place the delay locked loop circuit in an active operation mode or a calibration operation mode, wherein:

[0013] When the delay locked loop circuit is in the calibration operation mode:

[0014] The fixed voltage source is configured to provide the fixed voltage signal as the control voltage signal of the voltage-controlled delay line;

[0015] When the delay code lock signal indicates that the first output signal and the last output signal are not out of phase by 2Π radians: the delay code setter is configured to apply the delay code setting signal to the voltage-controlled delay line such that the delay code setter sequentially applies different candidate delay codes as the active delay code to the voltage-controlled delay line; and

[0016] When the delay code lock signal indicates that the first output signal and the last output signal are out of phase by 2Π radians: the delay code setter is configured to assign the active candidate delay code as the selected delay code; and

[0017] When the delay lock loop circuit is in the active operation mode:

[0018] The charge pump is configured to provide the feedback voltage signal as the control voltage signal of the voltage-controlled delay line; and

[0019] The voltage-controlled delay line is configured to use the selected delay code as the delay code.

[0020] In one or more embodiments, the delay code setter is configured to apply the delay code setting signal to the voltage-controlled delay line such that the delay code setter applies a sequence of candidate delay codes in which the value of the delay code gradually increases until the last output signal is out of phase with the first output signal by at least 2Π radians.

[0021] In one or more embodiments, the phase signal processor includes a D-type flip-flop having: a data input terminal, a clock input terminal, and an output terminal, where:

[0022] The data input terminal is configured to receive one of the up pulse signal and the down pulse signal;

[0023] The clock input terminal is configured to receive the other of the up pulse signal and the down pulse signal;

[0024] And

[0025] The output terminal is configured to provide the delay code lock signal.

[0026] In one or more embodiments, the D-type flip-flop further includes an enable input terminal, and where:

[0027] The enable input terminal is configured to receive an enable input signal when the delay lock loop circuit is in the calibration operation mode; and

[0028] The enabled input terminal is configured to receive a disable input signal when the delay locked loop circuit is in the active operation mode.

[0029] In one or more embodiments, the phase detector is a proportional phase detector.

[0030] In one or more embodiments, the delay locked loop circuit further includes:

[0031] A reset generator configured to ensure that the delay code setter receives a first rising edge of the last output signal before a corresponding rising edge of the first output signal, before the delay code setter sequentially applies the different candidate delay codes to the voltage controlled delay line.

[0032] In one or more embodiments, the voltage controlled delay line includes:

[0033] A delay line biasing circuit, wherein:

[0034] The delay line biasing circuit includes a resistor bank;

[0035] The resistor bank includes a plurality of resistors connected in series between a resistor bank connection node and a ground terminal, wherein the resistor bank has a resistance value that affects the magnitude of the time delay imposed by the voltage controlled delay line;

[0036] The delay line biasing circuit includes a plurality of bypass switches, each bypass switch being associated with a resistor in the resistor bank;

[0037] Each bypass switch is configured to selectively include or exclude its associated resistor arranged in series between the resistor bank connection node and the ground terminal, so as to set the resistance value of the resistor bank based on a resistance code signal; and

[0038] The delay line biasing circuit includes a controller that provides the resistance code signal for each of the bypass switches based on the received delay code.

[0039] In one or more embodiments:

[0040] The voltage controlled delay line includes a plurality of delay buffers connected in series to continuously impose a time delay on the clock input signal;

[0041] The output of the first delay buffer is the first output signal;

[0042] The output of the last delay buffer is the last output signal; and

[0043] The magnitude of the time delay imposed by each delay buffer is based on a bias voltage signal;

[0044] The delay line biasing circuit further includes a calibration transistor;

[0045] The resistance value of the resistor bank is configured to set the current passing through the calibration transistor; and

[0046] The delay line biasing circuit is configured to set the bias voltage signal based on the current passing through the calibration transistor.

[0047] In one or more embodiments:

[0048] The voltage-controlled delay line includes a plurality of delay buffers connected in series to continuously impose a time delay on the clock input signal;

[0049] Each of the plurality of delay buffers has:

[0050] An input terminal;

[0051] An output terminal;

[0052] An intermediate terminal; and

[0053] A duty cycle distortion reduction circuit connected in series between the intermediate terminal and the output terminal;

[0054] The duty cycle distortion reduction circuit includes:

[0055] An AC-coupled capacitor and an inverter, the capacitor and the inverter being connected in series between the intermediate terminal and the output terminal, wherein the inverter has an inverter input terminal and an inverter output terminal;

[0056] A feedback resistor connected in series between the inverter input terminal and the inverter output terminal.

[0057] In one or more embodiments, the duty cycle distortion reduction circuit further includes:

[0058] A first enable switch connected in series with the feedback resistor between the inverter input terminal and the inverter output terminal; and

[0059] A second enable switch connected in series between the inverter output terminal and the ground terminal.

[0060] While the present disclosure admits of various modifications and alternative forms, specific details have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that there may be other embodiments beyond the specific embodiments described. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also covered.

[0061] The foregoing discussion is not intended to present every example embodiment or every implementation within the scope of the current or future claim sets. The drawings and the following detailed description also illustrate various example embodiments. The various example embodiments can be more fully understood by considering the following detailed description in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] One or more embodiments will now be described by way of example with respect to the drawings, in which:

[0063] Figure 1 An example embodiment of a delay locked loop (DLL) circuit according to the present disclosure is shown;

[0064] Figure 2 Another example of a DLL circuit according to the present disclosure is shown;

[0065] Figure 3 A flowchart of a calibration sequence that can be performed by the Figure 2 DLL circuit is shown;

[0066] Figure 4 is a flowchart that more particularly illustrates the Figure 3 function of step 335;

[0067] Figure 5 A timing diagram that illustrates the function of a flowchart that further illustrates the Figure 4 is shown;

[0068] Figure 6 A graph is shown that plots the candidate delay code index (load_cal<3:0>) on the horizontal axis against the time delay on the vertical axis;

[0069] Figure 7 An example embodiment of a VCDL 701 according to the present disclosure is shown;

[0070] Figure 8 Additional details of a delay line biasing circuit (such as the Figure 7 delay line biasing circuit shown) according to an embodiment of the present disclosure are shown; and

[0071] Figure 9 An example embodiment of a delay buffer according to the present disclosure is shown. DETAILED DESCRIPTION

[0072] A delay - locked loop (DLL) circuit includes a delay chain that applies a time delay to an input clock signal. The DLL circuit also includes a feedback circuit that phase - locks the final output signal to the input clock signal, such that it is delayed by 2Π radians relative to the input clock signal. The feedback circuit can include a phase detector and a charge pump. The delay chain can include a VCDL (voltage - controlled delay line). The magnitude of the time delay applied by the VCDL is affected by a control voltage signal. Due to limitations related to the supply voltage and the overdrive voltage of the charge pump, the VCDL may have a limited range of acceptable control voltages. Thus, if the control voltage (vcntrl) of the DLL exceeds the safely - specified range, the DLL will be locked at an incorrect phase alignment. That is, the final output signal of the DLL will not be delayed by 2Π radians relative to the input reference clock of the DLL.

[0073] Figure 1 An example embodiment of a delay - locked loop (DLL) circuit 100 according to the present disclosure is shown. As will be discussed below, the DLL circuit 100 can be placed in an active operation mode or a calibration operation mode. In the calibration operation mode, the voltage - controlled delay line (VCDL) 101 is calibrated such that when the DLL circuit 100 is in the active operation mode, the control voltage signal 103 applied to the VCDL 101 is expected to have a value that reduces the likelihood of it exceeding the range of acceptable values, which would result in incorrect operation of the DLL circuit 100. For example, the VCDL 101 can be calibrated such that when the DLL circuit is in the active operation mode, the control voltage signal 103 is expected to have a value in the middle of the range of acceptable values. Thus, if any situation occurs that causes the control voltage signal 103 to increase or decrease (e.g., a temperature change in the DLL circuit 100), the control voltage signal 103 can increase or decrease with the maximum margin while still having a value that enables the DLL circuit 100 to apply the correct phase delay.

[0074] Now turning more specifically to Figure 1 , the VCDL 101 receives a clock input signal 102 and a control voltage signal 103. The VCDL 101 applies a time delay to the clock input signal 102 to provide a first output signal (PH<0>) 104 and a final output signal (PH <n>)105. In some examples, the first output signal (PH<0>) 104 can be the same signal as the clock input signal 102, such that the VCDL 101 applies zero time delay when providing the first output signal (PH<0>) 104. When the DLL circuit 100 is in the active operation mode, the last output signal (PH <n>)105 should be delayed relative to the first output signal (PH<0>) 104 such that there is a 2Π radian phase difference between the signals. Additionally, as Figure 2 shown, the VCDL 101 can also provide one or more intermediate output signals PH<1> to PH <n-1>( Figure 1 not shown), and these intermediate output signals are phase-shifted by less than 2Π radians with respect to the first output signal (PH<0>) 104.

[0075] The magnitude of the time delay imposed by the VCDL 101 is based on the control voltage signal 103 and also on the delay code. The delay code defines the value of one or more variable components in the VCDL 101. In this way, the value of one or more variable components affects the magnitude of the time delay imposed by the VCDL 101. As will be described below, the variable components may include variable resistors and / or variable capacitors, but it should be understood that any type of variable component that affects the time delay may be used.

[0076] The DLL circuit 100 further includes a phase detector 115 and a charge pump 116, and the phase detector 115 and the charge pump 116 are based on the first output signal (PH<0>) 104 and the last output signal (PH <n>)A phase difference between 105 provides a feedback voltage signal 107. In this example, the phase detector 115 is a proportional phase detector. As is known in the art, the phase detector 115 processes the first output signal (PH<0>) 104 and the last output signal (PH <n>)105 to provide: i) an up-pulse signal 106; and ii) a down-pulse signal 117. The time difference between the rising edge of the up-pulse signal 106 and the rising edge of the down-pulse signal 117 reflects the first output signal (PH<0>) 104 and the last output signal (PH <n>)The phase difference between 105. The charge pump provides a feedback voltage signal 107 based on the up-pulse signal 106 and the down-pulse signal 117.

[0077] The DLL circuit 100 further includes a fixed voltage source 110 that provides a fixed voltage signal 111. As will be discussed below: when the DLL circuit 100 is in the calibration operation mode, the fixed voltage signal 111 is provided as the control voltage signal 103; and when the DLL circuit 100 is in the active operation mode, the feedback voltage signal 107 is provided as the control voltage signal 103. In this way, the DLL circuit 100 is in an open-loop configuration when in the calibration operation mode and in a closed-loop configuration when in the active operation mode.

[0078] The DLL circuit 100 further includes a delay code setter 108 that provides a delay code setting signal 109 to the VCDL 101. At any time when the DLL circuit 100 is in the calibration operation mode, the delay code setting signal 109 represents one candidate delay code in a sequence of different candidate delay codes. The delay code setter 108 is used to calibrate the VCDL 101 when the DLL circuit 100 is in the calibration operation mode.

[0079] As Figure 1 shown, the DLL circuit 100 further includes a switch circuit 112. The switch circuit 112 is used to place the DLL circuit 100 in the active operation mode or the calibration operation mode. In Figure 1 one, the switch circuit 112 is implemented as a single switch. However, in other examples including Figure 2 the examples of, more than one switch component can be used to control the operation mode of the DLL circuit 100.

[0080] When the DLL circuit 100 is in the calibration operation mode, the switch circuit 112 connects the fixed voltage source 110 to the VCDL 101. The switch circuit 112 also disconnects the charge pump 116 from the VCDL 101. In this way, the fixed voltage source 110 provides the fixed voltage signal 111 as the control voltage signal 103 for the VCDL 101. As will be discussed below, in one example, the fixed voltage signal 111 can have a value in the middle of the voltage value range that enables the DLL circuit 100 to operate correctly. This can be implemented by providing a plurality of voltage signals close to the middle of the power supply voltage, as shown by the resistor divider in Figure 2 one.

[0081] The delay code setter 108 is used to sequentially apply different candidate delay codes to the VCDL 101 until a last output signal (PH <n>)A candidate delay code that is out of phase by 2Π radians with the first output signal (PH<0>) 104. As will be discussed in detail below, in one example, the delay code setter 108 applies a sequence of candidate delay codes for which the value of the delay code is incremented. The value of the applied delay code is incremented until the final output signal (PH <n>)105 is out of phase with the first output signal (PH<0>) 104 by at least 2Π radians. This function can be performed in combination with a reset generator that ensures that the delay code setter 108 captures PH before the corresponding rising edge of PH<0> <n>The first rising edge. In this way, since the rising edge of the downlink pulse signal 117 provided by the phase detector 115 precedes the uplink pulse signal 106, the pulse width in the downlink pulse signal 117 will increase to be greater than the pulse width in the uplink pulse signal 106. Now, if the delay code setter 108 increases the delay, then ph <n>will be delayed more; that is, it will move in the 2Π phase shift direction relative to ph<0>. Therefore, the rising edge of the downlink pulse signal 117 will move toward the rising edge of the uplink pulse signal 106. This means that as a higher delay is applied by the delay code setter 108, the pulse width in the downlink pulse signal 117 will decrease. At a specific delay setter value during increment, due to the higher delay applied in the VCDL 101, PH <n>The rising edge of will just pass through the rising edge of PH<0>. At this time, the pulse width in the downlink pulse signal 117 will be smaller than the pulse width in the uplink pulse signal 106.

[0082] In Figure 1 the phase signal processor 113 is used to provide a delay code locking signal 114 to the delay code setter 108, and the delay code locking signal 114 indicates whether the first output signal (PH<0>) 104 is the same as the last output signal (PH <n>)105 The out-of-phase is 2Π radians. The phase signal processor 113 processes the up pulse signal 106 and the down pulse signal 117 to provide a delay code lock signal 114. This can be considered advantageous because the signals generated during the active operation mode are reused, and thus only minimal additional processing is required to implement the calibration operation mode.

[0083] More specifically, when the DLL circuit 100 is in the calibration operation mode:

[0084] · When the delay code lock signal 114 indicates that the first output signal (PH<0>) 104 and the last output signal (PH <n>)When there is no phase difference of 2Π radians in 105, the delay code setter 108 applies a delay code setting signal 109 to the VCDL 101, such that the delay code setter 108 sequentially applies one or more candidate delay codes from a sequence of different candidate delay codes as the active delay code to the voltage controlled delay line; and

[0085] · When the delay code lock signal 114 indicates that the first output signal (PH<0>) 104 and the last output signal (PH <n>)When the phase difference is 2π radians, the delay code setter 108 assigns the active candidate delay code as the selected delay code.

[0086] When the DLL circuit 100 is in the active operation mode, the switch circuit 112 connects the charge pump 116 to the VCDL 101. The switch circuit 112 also disconnects the fixed voltage source 110 from the VCDL 101. In this way, the charge pump 116 provides the feedback voltage signal 107 as the control voltage signal 103 of the VCDL 101.

[0087] In addition, when the DLL circuit 100 is in the active operation mode, the VCDL 101 uses the selected delay code (i.e., the delay code determined during the calibration operation mode) as the delay code. That is, the variable components in the VCDL 101 are set such that they have the same delay as the one identified during the calibration operation mode to make the final output signal (PH <n>)A value that is in phase opposition by 2Π radians to the first output signal (PH<0>) 104. Subsequently, the DLL circuit 100 can operate in a closed-loop configuration in the active operation mode such that the value of the feedback voltage signal 107 is expected to have the same value as the fixed voltage signal 111, so as to make the first output signal (PH<0>) 104 and the final output signal (PH <n>)An expected phase difference of 2Π radians is achieved between 105. Then, if there are any temperature variations during the operation of the DLL circuit 100 in the active operating mode, the DLL circuit 100 is well placed to accommodate any associated variations in the feedback voltage signal 107 that occur due to the closed-loop configuration without saturating the control of the VCDL 101.

[0088] Advantageously, Figure 1 Examples of can limit the control voltage signal 103 when there are PVT (process, voltage, temperature) variations. In this example, this can be achieved by calibrating the RC delay (by applying a candidate delay code) to maintain the control voltage signal at an intermediate value of the supply voltage (e.g., VDD / 2) when the charge pump 116 is disabled or disconnected. In other examples, the control voltage signal can be maintained at a different value, which may or may not be close to VDD / 2. Such a control voltage can be provided by a resistive voltage divider (such as Figure 2 shown) or any biasing generating voltage source. Either way, the DLL circuit 100 can change the RC delay of the VCDL 101 until the final output signal 105 of the DLL is 2Π radians apart from the first output signal 104. Once the calibrated RC value is determined, the DLL circuit enters the closed-loop operating mode (referred to above as the active operating mode) using the final calibrated RC value of the VCDL 101 to lock near a fixed value of the control voltage signal used in the calibration mode, which can be VDD / 2.

[0089] Figure 2 Another example of a DLL circuit 200 according to the present disclosure is shown. Figure 2 The features of are also shown in Figure 1 and corresponding reference numerals are given in the 200 series, which will not necessarily be described again here. As will be discussed below, the DLL circuit 200 includes a calibration mode enable signal (Oploop_en) 222, which is set to high when the DLL circuit 200 is to be placed in the calibration operating mode; and low when the DLL circuit 200 is to be placed in the active operating mode. The DLL circuit 200 also generates and uses the inverse signal of the calibration mode enable signal (Oploop_enb) 223.

[0090] In this example, the VCDL 201 is implemented as a chain of N+2 delay buffers connected in series with each other. The first buffer in the chain receives the clock input signal 202 as an input signal and provides a first output signal (PH<0>) 204 as its output signal. The penultimate buffer in the chain provides the final output signal (PH <n>)205 as its output signal. As Figure 2 shown, variable capacitors are respectively connected between the output terminal and the ground terminal of each of the first to the penultimate buffers. In the same manner as described above with reference to Figure 1 the method, the value of the variable capacitor is set by the delay code. Thus, a variable component (in this example, a variable capacitor, but the variable component can also be a variable resistor or any other suitable type of variable component) is associated with each buffer, thereby contributing to defining the magnitude of the time delay imposed by each buffer in the VCDL 201.

[0091] In this example, each of the first to the penultimate buffers provides an output signal that is a phase-shifted version of the clock input signal 202. Since each of the buffers in this example imposes the same amount of delay, the phase of each of the output signals is equally offset relative to the earlier output signal in the phase, and if the DLL circuit 200 operates correctly, the last output signal 205 is phase-shifted by 2Π radians relative to the first output signal 204.

[0092] In this example, the DLL circuit 200 includes a phase detector 215 and a charge pump 216. The phase detector 215 compares the first output signal (PH<0>) 204 and the last output signal (PH <n>)Compare with 205, and depending on the comparison result, set the widths of the up-pulse signal 206 and the down-pulse signal 217 such that they represent the phase difference between the first output signal 204 and the last output signal 205. As is known in the art, the up-pulse signal 206 and the down-pulse signal 217 are used to control the charge pump 216 such that the charge pump 216 increases or decreases the feedback voltage signal 207 provided as the output signal of the charge pump 216. In this way, when the DLL circuit 200 is in the active operation mode, the charge pump 216 sets the feedback voltage signal 207 such that the first output signal (PH<0>) 204 and the last output signal (PH <n>)205 are in phase with each other. Due to the time delay imposed by VCDL 201, this should mean that the final output signal (PH <n>)205 is phase-shifted by 2Π radians relative to the first output signal (PH<0>) 204.

[0093] In this example, the fixed voltage source 210 is configurable such that the voltage level of the fixed voltage signal 211 can be set by the user. In Figure 2 the fixed voltage source 210 includes a potentiometer 227 (which can also be referred to as a resistive voltage divider). It should be understood that in other examples, the fixed voltage source 210 can be implemented differently and can include any bias voltage design. The fixed voltage source 210 receives a calibration voltage control signal 239, which defines the required level of the voltage of the fixed voltage signal 211. In this example, the DLL circuit 200 converts the calibration voltage control signal 239 into four binary signals 226 for controlling four corresponding switches. Each of these four switches is connected to a different node in the potentiometer 227 such that different voltage levels can be tapped and connected to the input terminal of an operational amplifier (op-amp) 228. The op-amp 228 is configured as a unity-gain amplifier such that the output signal of the op-amp 228 is the fixed voltage signal 211.

[0094] Figure 2 The DLL circuit 200 of includes a control voltage connection switch 212, which is part of a switch circuit for controlling the operation mode of the DLL circuit 200. Similar to Figure 1 the same, the control voltage connection switch 212 provides either the fixed voltage signal 211 or the feedback voltage signal 207 as the control voltage signal 203 for the VCDL 201.

[0095] Figure 2 The delay code setter block 208 of is implemented as an RTL (resistor transistor logic) circuit. The delay code setter block 208 provides a delay code setting signal (load_cal <n:0>)209, the delay code setting signal (load_cal <n:0>)209 applies the next candidate delay code in the sequence to the VCDL 201 periodically. In this example, the delay code setter block 208 starts with the lowest candidate delay code and gradually increments the value of the candidate delay code until the last output signal (PH <n>)A code that is out of phase by 2Π radians with the first output signal (PH<0>) 204. As will be discussed below, the phase signal processor 213 processes the uplink pulse signal 206 and the downlink pulse signal 217 to provide a delay code lock signal 214 to the delay code setter block 208, and the delay code lock signal 214 indicates the last output signal (PH <n>)When does 205 have a phase difference of 2Π radians from the first output signal (PH<0>) 204?

[0096] In this example, the phase signal processor includes a D-type flip-flop 213. The D-type flip-flop 213 has a data input terminal, a clock input terminal, and an output terminal. The data input terminal receives the downlink pulse signal 217, and the clock input terminal receives the uplink pulse signal 206. The output terminal provides a delayed code lock signal 214. In this way, the downlink pulse signal 217 is sampled with respect to the uplink pulse signal 206 such that: when the first output signal (PH<0>) 204 and the last output signal (PH <n>)When out of phase by 205, the delayed code lock signal 214 has a value of 1; and when the first output signal (PH<0>) 204 and the last output signal (PH <n>)When 205 is in phase, the delayed code lock signal 214 has a value of 0. An example waveform illustrating this function is described below with respect to Figure 5 Description of the example waveform illustrating this function.

[0097] It should be understood that the signal provided to the input of the D-type flip-flop 213 can be inverted so that the same function can be achieved together with the corresponding changes of other components of the DLL circuit 200. The value of the delayed code lock signal 214 will be at the desired delayed code (i.e., when PH <n>When the phase difference with PH<0> will be 2Π radians, switch 1-->0 or 0-->1, depending on which signal is provided to which input terminal of the D-type flip-flop 213.

[0098] The D-type flip-flop 213 also includes an enable input terminal. When the DLL circuit 200 is in the calibration operation mode, the enable input terminal receives the enable input signal 222. When the DLL circuit 200 is in the active operation mode, the enable input signal 222 represents a disable input signal. In this way, when the DLL circuit 200 is in the calibration operation mode, the D-type flip-flop 213 samples the downlink pulse signal 217 only with respect to the uplink pulse signal 206.

[0099] Figure 3 Shown can be Figure 2 The flowchart of the calibration sequence that can be executed by the DLL circuit. Figure 3 The names of the signals included in Figure 2 are also shown in

[0100] In step 330, the DLL circuit is enabled by setting the DLL_EN signal to logic 1. As can be seen from Figure 2 setting this signal in this way disconnects a switch and disconnects the control voltage signal 203 from the VDD power supply.

[0101] Also in step 330, the calibration mode enable signal (Oploop_en) 222 is set to a logic high value. As discussed in detail above, this causes the DLL circuit 200 to enter the calibration operation mode. When the calibration mode enable signal (Oploop_en) 222 is set to a high value:

[0102] ● The fixed voltage signal 211 is provided as the control voltage signal 203 of the VCDL 201; and

[0103] ● The D-type flip-flop 213 associated with the delay code setter 208 is triggered.

[0104] In addition, when the calibration mode enable signal (Oploop_en) 222 is set to a logic high value, the harmonic detector 220 is disconnected from the phase detector 215. Since the function of the harmonic detector 220 is not the core of the calibration function of the present disclosure, it will not be described in further detail here.

[0105] In this way, in step 330, the loop filter is disconnected from the power supply, and the DLL circuit 200 enters the calibration operation mode, which is the open-loop mode in this example.

[0106] Then, in step 331, the calibration sequence waits until the control voltage signal 203 is charged to VDD / 2 or another predetermined voltage provided by the fixed voltage source 210.

[0107] Figure 2 The DLL circuit 200 also includes a reset generator 221 known in the art. The operation of the reset generator 221 will be briefly described with respect to Figure 3 steps 332 - 334.

[0108] In step 332, the Reset_sw signal changes from a logic low value to a logic high value. As can be seen from Figure 2 this closes the switch between the reset generator 221 and the phase detector 215. When this switch is closed, the reset generator 221 is enabled such that it generates the RSTP LOW signal to reset the phase detector 215 until the phase detector 215 detects PH before PH<0> <n>The first rising edge, which means that in step 333, the width of the downlink pulse signal 217 is greater than the width of the uplink pulse signal 206. That is, until the final output signal (PH <n>)The phase of 205 leads the phase of the first output signal (PH<0>) 204. Then, the Reset_sw signal changes from a logic high value to a logic low value to indicate the end of the reset operation. It should be understood from the following description that this represents a suitable starting point for starting to increment the delay code. This is because the next first output signal (PH<0>) 204 and the last output signal (PH <n>)When 205 are in phase with each other, the final output signal (PH <n>)205 will be phase-delayed by 2Π radians with respect to the first output signal (PH<0>) 204.

[0109] In step 335, when the delay code lock signal 214 is triggered, the delay code setter block 208 determines the selected delay code as load_cal <n:0>value. The following describes in reference to Figure 4 the function of step 335 in more detail.

[0110] In step 336, the calibration mode enable signal (Oploop_en) 222 is set to a logic low value, causing the DLL circuit 200 to enter the active closed-loop operation mode, and:

[0111] ● The feedback voltage signal 207 is provided as the control voltage signal 203 for the VCDL 201;

[0112] ● The D flip-flop 213 associated with the delay code setter 208 is disabled; and

[0113] ● The VCDL 201 uses the selected delay code.

[0114] In step 337, the DLL circuit is disabled by setting the DLL_EN signal to logic 0, causing the control voltage signal 203 to tend towards the power supply voltage VDD. Then, the flowchart waits for the control voltage signal 203 to reach the power supply voltage VDD, and in step 338, the DLL circuit is re-enabled by setting the DLL_EN signal to logic 1. Also in step 338, the Reset_sw signal changes from a logic low value to a logic high value.

[0115] The DLL circuit 200 is now calibrated and in the active operation mode. Thus, in the closed-loop active operation mode, the DLL circuit 200 will be locked such that the selected control voltage signal (vcntrl) 203 has a value similar to the value (e.g., VDD / 2) used in the open-loop calibration operation mode by maintaining the same delay code (load_cal) value for which the delay code lock signal (cal_lock) 214 switches from high to low. As described above, the value of cal_lock 214 switches depending on the UP and DOWN pulses at the input of the D flip-flop 213.

[0116] Figure 4 is a flowchart that illustrates in more detail Figure 3 the function of step 335. Thus, Figure 4 illustrates Figure 2 how the delay code setter block 208 of

[0117] Figure 4 The flowchart includes an initial step of checking whether the calibration mode enable signal (Oploop_en) 222 has a logic high value, where a logic high value indicates that the DLL circuit 200 is in the calibration operation mode. If the calibration mode enable signal (Oploop_en) 222 does have a logic high value, the flowchart proceeds to: step 440, where the Reset_sw signal changes from a logic low value to a logic high value; and step 441, where it is initialized by setting the delay code setting signal (load_cal<n:0>) 209 to a first candidate delay code. In this example, the first candidate delay code is zero.

[0118] Then, the flowchart waits for a period of time until the down pulse width is greater than the up pulse width, after which the flowchart proceeds. In this case, at step 442, the Reset_sw signal changes from a logic high value to a logic low value.

[0119] At step 443, the delay code setter 208 increments the delay code setting signal (load_cal <n:0>)209, such that it represents the next candidate delay code in the sequence. As described above, this represents incrementing the delay code setting signal (load_cal <n:0>)The value of 209.

[0120] Although the delay code lock signal (cal_lock) 214 has not been switched yet, which means that the first output signal (PH<0>) 204 and the last output signal (PH <n>) 205 has no phase difference of 2Π radians, but the flowchart returns to step 443 to increment the delay code setting signal (load_cal) periodically <n:0>) 209, so that it represents the next candidate delay code in the sequence. In this way, the delay code setter 208 sequentially applies the sequence of different candidate delay codes as the active delay code to the VCDL 201.

[0121] This continues until the delay code lock signal (cal_lock) 214 switches from 0 -> 1 or 1 -> 0 (depending on how the signal is connected to the input of the D-type flip-flop 213), which indicates that the first output signal (PH<0>) and the last output signal (PH <n>)Out-of-phase 2Π radians. At this time, the flowchart proceeds to step 444, where the delay code setter 208 stores the delay code setting signal (load_cal <n:0>)209 effectively allocates the active candidate delay code as the selected delay code.

[0122] As described above, the VCDL 201 will use this selected delay code in the active operation mode.

[0123] Figure 5 Illustrated for further explanation Figure 4 The timing diagram of the function of the flowchart shown.

[0124] Figure 5 The topmost curve in is the first output signal (PH<0>) 504, which, as described above, is one of the input signals of the phase detector 215.

[0125] Figure 5 The second, third, and fourth curves in represent Figure 2 The operation of the DLL circuit when receiving the delay code setting signal 209 with a value representing the first candidate delay code (i.e., load_cal = 0). The second curve is the final output signal (PH <n>)505a, the final output signal (PH <n>)505a is another input signal of the phase detector 215. The third curve graph is the downlink pulse signal 517a, and the downlink pulse signal 517a is the output signal of the phase detector 215 and also one of the input signals of the D flip-flop 213. The fourth curve graph is the uplink pulse signal 506a, and the uplink pulse signal 506a is another output signal of the phase detector 215 and also another input signal of the D flip-flop 213.

[0126] Figure 5 The first and second curve graphs in <n>)505a is not sufficiently delayed relative to the first output signal (PH<0>) 504 because they are not out of phase by 2Π radians with respect to each other. It can also be seen that when the D flip-flop 213 samples the down pulse signal 517a using the up pulse signal 506a as a clock signal, the output signal of the D flip-flop 213 will have a logic high signal. This is because the down pulse signal 517a has a logic high value at the rising edge of the up pulse signal 506a.

[0127] Figure 5 The fifth and sixth graphs in Figure 2 show the operation of the DLL circuit when receiving a delay code setting signal 209, which represents a delay code between a first candidate delay code and the delay code that will become the selected delay code; i.e., load_cal = x, as Figure 5 shown. That is to say, the fifth and sixth graphs show the operation of the DLL circuit during the calibration operation mode, which is later in time than the operations represented by the second, third, and fourth graphs. The fifth graph is the final output signal (PH <n>)505b. The sixth curve graph is the down pulse signal 517b. Figure 5 The first and fifth curve graphs in <n>)505b is still not sufficiently delayed with respect to the first output signal (PH<0>) 504 because they are not out of phase by 2Π radians with respect to each other. When the D flip-flop 213 samples the down pulse signal 517b that appears when load_cal = x using the up pulse signal 506a as the clock signal, the output signal of the D flip-flop 213 will still have a logic high signal.

[0128] Figure 5 The seventh, eighth, and ninth graphs in Figure 2 show the operation of the DLL circuit in Figure 5 when it receives a delay code setting signal 209 having a value representing a selected delay code (i.e., load_cal = locking load_cal, as Figure 5 shown). The operations represented by the seventh, eighth, and ninth graphs in

[0129] are later in time than the operations represented by the fifth and sixth graphs. <n>)505c. The eighth curve graph is the downlink pulse signal 517c. The ninth curve graph is the uplink pulse signal 506c. Figure 5 The first and seventh curve graphs in <n>)505a is now sufficiently delayed relative to the first output signal (PH<0>) 504, as they are out of phase with each other by slightly more than 2Π radians. It can also be seen that when the D flip-flop 213 samples the down pulse signal 517c using the up pulse signal 506c as the clock signal, the output signal of the D flip-flop 213 will have a logic low signal. This is because the down pulse signal 517a has a logic low value at the rising edge of the up pulse signal 506c. Therefore, the candidate delay codes used in generating the seventh, eighth, and ninth curves in Figure 5 represent the desired active delay codes.

[0130] Summarizing the aspects disclosed above, during the calibration operation mode, vcntrl remains close to VDD / 2, and load_cal <n:0>Varying from 0 until the cal_lock signal changes from high to low. While increasing the load_cal value, the DOWN pulse width will decrease. When the refclk and the feedback clk are 360 degrees apart, load_cal <n:0>Further incrementing of causes the DOWN pulse to overlap with the UP pulse. Thus, we can say that the feedback clk is close to the refclk, and once the feedback clk crosses the refclk it means that the feedback clk is 360 degrees away from the refclk and the UP pulse width > DOWN pulse width. This is the locking condition for this particular process. The cal_lock signal will switch the value ph <n>will be delayed by nearly one cycle relative to ph<0>. Thus, on the conversion code, ph <n>It will be delayed close to Tclk relative to ph<0>.

[0131] Figure 6 A graph showing candidate delay code indices (load_cal<3:0>) on the horizontal axis, where each index represents a different candidate delay code in the sequence. In this example, a sequence of 16 candidate delay codes is shown. The vertical axis shows the time delay of the entire VCDL in seconds.

[0132] For Figure 6 the graph, the fourth candidate delay code is identified as the selected delay code, corresponding to a time delay of 1.3333 ns.

[0133] Figure 7 An example embodiment of VCDL 701 according to the present disclosure is shown.

[0134] VCDL 701 includes a chain of delay buffers connected in series with each other. The chain includes:

[0135] ● A first virtual delay buffer 751 that receives a clock input signal (refclk) 702 and provides an output signal that is a delayed version of the clock input signal (refclk) 702;

[0136] ● N delay buffers 752 - 753 that are connected in series to continuously apply a delay to the output signal from the first virtual delay buffer 751. Each of the N delay buffers 752 - 753 provides an output signal that is a phase-delayed version of the clock input signal (refclk) 702. The output of the first delay buffer 752 is the first output signal (PH<0>) 704. The output of the last, the Nth delay buffer 753 is the last output signal (PH <n>)705; and

[0137] ● The last virtual delay buffer 754, which receives the last output signal (PH from the last Nth delay buffer 753 <n>)705。

[0138] Due to the matching fan-in / fan-out, the first virtual delay buffer 751 and the last virtual delay buffer 754 are used to reduce the phase detector inputs (i.e., PH<0> and PH <n>) skew between.

[0139] Figure 7 It shows that each of the delay buffers receives a cap_code<2 n :1> signal, which may be referred to as a capacitance code signal. Lock the delay code signal (load_cal received from the delay code setter block) <n:0>Set cap_code < 2 for the signal n : The value of the signal > 1. ( Figure 7 The res_cap_code shown in <n:1>The signal is the above load_cal <n:0>Another name for the signal.) In this example, this includes using an n to 2^n thermometric decoder to res_cap_code <n:1>The signal is converted into cap_code<2 n :1> signal. Each of the delay buffers includes a variable capacitor ( Figure 8 An example is marked with reference numeral 862 in the figure), and the capacitance value of each variable capacitor is based on cap_code<2 n :1> signal (capacitance code signal).

[0140] Figure 7 The delay line bias circuit 750 is also shown. The delay line bias circuit 750 receives the control voltage signal 703 and provides a first bias voltage signal (VBP) 755 and a second bias voltage signal (VBN) 756 to each of the delay buffers. In this example, the first bias voltage signal (VBP) 755 is provided for the PMOS transistor, and the second bias voltage signal (VBN) 756 is provided for the NMOS transistor. The delay line bias circuit 750 sets the values of the first bias voltage signal (VBP) 755 and the second bias voltage signal (VBN) 756 based on the res_code<2 n :1> signal, and the res_code<2 n :1> signal can be referred to as a resistance code signal and will be described with respect to Figure 8 The res_code<2 n :1> signal in this example is obtained by converting res_cap_code <n:1>n to 2 of the signal n provided by a binary decoder, such as Figure 8 shown.

[0141] res_cap_code <n:1>The signal is used for cross - process and variation calibration purposes to limit the control voltage signal (vcntrl) 703 in both the delay - line biasing circuit 750 and the delay buffer, and is also used to control the current and capacitance values in the delay buffer.

[0142] Figure 8 Additional details of a delay - line biasing circuit 850 according to an embodiment of the present disclosure are shown (e.g., Figure 7 the delay - line biasing circuit shown).

[0143] As Figure 8 shown, the delay - line biasing circuit 850 includes a resistor bank 860. The resistor bank 860 includes a plurality of resistors connected in series between a resistor - bank connection node (V1) 863 and a ground terminal 864. As will be discussed below, the resistor bank 860 has a resistance value that affects the magnitude of the time delay imposed by the VCDL.

[0144] The delay - line biasing circuit 850 also includes a plurality of bypass switches, each bypass switch being associated with a resistor in the resistor bank 860. Each bypass switch is configured to selectively include or exclude its associated resistor arranged in series between the resistor - bank connection node (V1) 861 and the ground terminal 864. In this example, each bypass switch selectively connects the node between adjacent resistors to the ground terminal 864. The bypass switches can be opened and closed according to a resistor - code signal (res_code<2 n :1>) to set the resistance value of the resistor bank 860.

[0145] The delay - line biasing circuit 850 also includes a controller 865 that provides a resistor - code signal (res_code<2 n :1>) for each of the bypass switches based on the received delay code. In this example, the controller 865 is an n - to - 2 n binary decoder.

[0146] The delay - line biasing circuit 850 also includes a calibration transistor (MN1) 861. As Figure 8 shown, the resistance value of the resistor bank 860 is set by the current through the calibration transistor (MN1) 861. The delay - line biasing circuit sets a first bias - voltage signal (VBP) 855 and a second bias - voltage signal (VBN) 856 based on the current through the calibration transistor (MN1) 861. It should be understood that this function can be implemented in a variety of different ways, and the circuit shown Figure 8 is a non - limiting example of a suitable implementation.

[0147] Recall Figure 7 It can be seen that the VCDL includes a plurality of delay buffers connected in series to continuously apply a time delay to the clock input signal. The magnitude of the time delay applied by each delay buffer is based on the first bias voltage signal (VBP) 855 and the second bias voltage signal (VBN) 856. An example of the delay buffer 851 is as Figure 8 shown. Figure 8 The delay buffer 851 shown illustrates how the first bias voltage signal (VBP) 855 and the second bias voltage signal (VBN) 856 affect the time delay applied by the delay buffer 851. If the series resistance value is increased from low to high by enabling the switch <2^n:1>, the current through MN1 will change from high to low, and the currents through MN2 and MP3 will also change from high to low. Since MN2 and MP3 are diode-connected, the voltage on VBN will change from high to low, and the voltage on VBP will change from low to high. Therefore, the Ron resistances of MP3 and MN2 will increase from low to high, such that this increase in the Ron resistances of MP3 and MN3 will cause more delay in each delay buffer in the VCDL. This will result in PH <n>Is delayed more and thus is offset from PH<0> towards 2Π radians.

[0148] In this manner, the resistor bank 860 can be used to control the current across process and voltage and local mismatch during calibration by calibrating the (MN1) transistor 861. This calibrated current generates calibrated voltage signals (VBN and VBP) 855, 856 for the nmos and pmos devices in the delay buffer respectively. This in turn controls the Ron resistance of MN2 and MP2. (As is known in the art, "Ron" is the resistance of a FET when it is turned on.) Controlling the Ron resistance in this manner changes the time delay imposed by the delay buffer during calibration.

[0149] Figure 9 An example embodiment of a delay buffer 977 according to the present disclosure is shown. Figure 9 The delay buffer 977 can be used in any DLL circuit disclosed herein.

[0150] The delay buffer 977 has: an input terminal 970; an output terminal 971; and an intermediate terminal (Vc) 972.

[0151] The delay buffer 977 also has a duty cycle distortion reduction circuit 973 connected in series between the intermediate terminal (Vc) 972 and the output terminal 971. The duty cycle distortion reduction circuit 973 includes an ac-coupled capacitor 978, an inverter 974, and a feedback resistor 975. The ac-coupled capacitor 978 and the inverter 974 are each connected in series between the intermediate terminal (Vc) 972 and the output terminal 971. The inverter 974 has an inverter input terminal and an inverter output terminal. The feedback resistor 975 is connected in series between the inverter input terminal and the inverter output terminal.

[0152] If there is a high RC load under lock conditions (i.e., when the delay code setter applies the selected delay code to the VCDL), the voltage swing at the intermediate node (Vc) 972 may be reduced to such an extent that the DC voltage at the intermediate node (Vc) 972 may deviate from the switching threshold due to process variations. This reduced swing and the offset DC voltage at the intermediate node (Vc) 972 may result in severe duty cycle distortion at the output terminal 972 of the delay buffer 971, or even no switching at all. When the pulse changes from PH<0> to PH <n>These problems (i.e., distorted and / or failed clocks) may be more severe when

[0153] A distorted duty cycle clock may introduce jitter in the VCDL and / or it may increase the likelihood of failed clock outputs on multiple phases.

[0154] This problem can be solved by introducing Figure 9 a duty cycle distortion reduction circuit 971. The duty cycle distortion reduction circuit 971 may be referred to as an AC-coupled resistor feedback circuit, and it can achieve an improved DC bias at the input of the inverter 974, which enables the inverter 974 to amplify the signal with reduced duty cycle distortion.

[0155] In Figure 9 the example of Figure 9 the duty cycle distortion reduction circuit 971 also includes two enabling circuits operated by a signal labeled DLL_EN in Figure 2 which is described in detail above. The first enabling switch 976 is serially disposed between the inverter input and the inverter output in series with the feedback resistor 975. The second enabling switch 979 is serially disposed between the inverter output and the ground terminal 981. These two switches 976, 979 can reduce the noise amplification of the inverter 974. Otherwise, even if the DLL is disabled (power-down mode), the inverter 974 may act as a ring oscillator and generate all phases ph<0> to ph <n>In addition, even when the DLL is disabled, the VCDL still consumes power.

[0156] One or more examples described in this document may provide the following advantages:

[0157] ● Vcntrl can be restricted by using the built-in DLL sub-blocks (i.e., delay buffer / line and phase detector).

[0158] ● Multiple frequencies of the same DLL can be supported.

[0159] ● Since built-in sub-blocks are used for calibration, no additional power is consumed during normal operation.

[0160] ● Less jitter compared to the prior art.

[0161] ● If highly precise Vcntrl is required, there may be no impact or a minimal impact on power and jitter.

[0162] The examples described in this document may relate to one or more of the following aspects:

[0163] 1. Before starting to change the RC delay in the VCDL during open-loop calibration ( Figure 2 ), RSTGEN can first be enabled by setting reset_sw = 0 --> 1 until the DOWN width > UP width, thereby keeping the control voltage vcntrl at VDD / 2 or any predetermined fixed voltage, and then RSTGEN is disabled again.

[0164] 2. To achieve a good vcntrl range for temperature (again as Figure 2 shown), calibration can be performed by fixing the control voltage at VDD / 2 or any predetermined fixed voltage, and then multiple RC delays are applied in the delay line (VCDL) by using a resistor divider biased by the delay line ( Figure 8 ) until the UP width of the phase detector in the open loop > DOWN width. Therefore, calibration for process, power supply voltage, and local mismatch can be achieved by using the calibration circuit ( Figure 2 ) plus the built-in DLL sub-blocks (delay line bias + VCDL + PD).

[0165] 3. Vcntrl will be locked very close to the predetermined fixed voltage in the closed loop for process, power supply, and local mismatch variations to generate multiple equally spaced phases within one clk period. Therefore, the vcntrl range can provide a wide range of temperature tracking in closed-loop operation.

[0166] 4. Therefore, one or more calibration examples described in this document can support DLLs with a wide frequency range.

[0167] In addition to the calibration outlined above, the present disclosure also relates to:

[0168] 1. A delay line biasing circuit ( Figure 8 ), which is used in calibration (open loop) to generate multiple delays in a VCDL by changing resistor calibration, and is also used in closed loop to control temperature delay by changing vcntrl using a charge pump and a phase detector when entering normal function.

[0169] 2. A duty - cycle - free delay cell, which is implemented by using a resistor - feedback AC - coupled inverter, helping to reduce jitter caused by duty - cycle distortion and even reducing the probability of a failed clock if a high delay is required between consecutive phases ( Figure 9 ).

[0170] The present disclosure describes an efficient, accurate, and novel method for delay - line gain calibration.

[0171] Advantageously, the DLL circuit described herein can provide precise calibration for the control voltage signal by changing the RC delay between process, voltage, and local mismatch during the calibration operation mode before entering the locked condition in the closed - loop configuration during the active operation mode. Since the range of the control voltage signal (Vcntrl) is limited, for example, it cannot fall outside the range defined by ground and the supply voltage (VDD), the value of the control voltage signal applied to the voltage - controlled delay line should remain within these limits within the expected PVT variations.

[0172] Unless a specific order is explicitly stated, the instructions and / or flowchart steps in the above schema can be executed in any order. Moreover, those skilled in the art will recognize that although one example instruction set / method has been discussed, the materials in this specification can be combined in many ways to produce other examples, and should be understood within the context provided in this detailed description.

[0173] In some example embodiments, the above - described instruction set / method steps are implemented as functions and software instructions embodied in an executable instruction set, which is implemented on a computer or a machine programmed and controlled by the executable instructions. Such instructions are loaded for execution on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor can refer to a single component or multiple components.

[0174] In other examples, the instruction sets / methods shown herein, as well as the data and instructions associated therewith, are stored in corresponding storage devices, which are implemented as one or more non-transitory machine or computer-readable or computer-usable storage media. These computer-readable or machine-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture may refer to any single manufactured component or multiple components. As defined herein, non-transitory machine or computer-usable media do not include signals, but such media may be capable of receiving and processing information from signals and / or other transitory media.

[0175] Example embodiments of the materials discussed in this specification may be implemented, in whole or in part, via a network, computer, or data-based device and / or service. These may include the cloud, the Internet, an intranet, mobile devices, desktop computers, processors, lookup tables, microcontrollers, consumer devices, infrastructure, or other enabling devices and services. As used herein and in the claims, the following non-exclusive definitions are provided.

[0176] In one example, one or more of the instructions or steps discussed herein are automated. The term automated or automatic (and its similar variants) means the use of a computer and / or mechanical / electrical device to control the operation of a device, system, and / or process without human intervention, observation, effort, and / or decision-making.

[0177] It should be understood that any components that are alleged to be coupled may be directly or indirectly coupled or connected. In the case of indirect coupling, additional components may be located between the two components that are alleged to be coupled.

[0178] In this specification, example embodiments have been presented in accordance with a selected set of details. However, those of ordinary skill in the art will understand that many other example embodiments may be practiced that include different selected sets of these details. It is intended that the appended claims cover all possible example embodiments.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A delay locked loop circuit, characterized in that: include: A voltage controlled delay line comprising one or more variable components, wherein the voltage controlled delay line is configured to: receiving a clock input signal; receiving a control voltage signal; and applying a time delay to the clock input signal to provide a first output signal and a last output signal, wherein a magnitude of the time delay is based on the control voltage signal and a delay code, and wherein the delay code defines a value of the one or more variable components in the voltage-controlled delay line; a phase detector circuit configured to process the first output signal and the final output signal to provide: i) an up pulse signal; and ii) a downlink pulse signal, wherein the difference between the width of the uplink pulse signal and the width of the downlink pulse signal represents a phase difference between the first output signal and the last output signal; a charge pump, the charge pump being configured to provide a feedback voltage signal based on the up pulse signal and the down pulse signal; a phase signal processor configured to process the uplink pulse signal and the downlink pulse signal to provide a delayed code lock signal, wherein the delayed code lock signal indicates whether the first output signal is 2Π radians out of phase with the last output signal; a delay code setter configured to provide a delay code setting signal representing a candidate delay code in a sequence of different candidate delay codes; a fixed voltage source configured to provide a fixed voltage signal; as well as a switch circuit configured to place the delay locked loop circuit in an active operating mode or a calibration operating mode, wherein: When the delay locked loop circuit is in the calibration operation mode: The fixed voltage source is configured to provide the fixed voltage signal as the control voltage signal of the voltage-controlled delay line; When the delay code lock signal indicates that the first output signal is not out of phase with the last output signal by 2Π radians: the delay code setter is configured to apply the delay code setting signal to the voltage-controlled delay line so that the delay code setter sequentially applies different candidate delay codes as active delay codes to the voltage-controlled delay line; and When the delay code lock signal indicates that the first output signal is 2Π radians out of phase with the last output signal: the delay code setter is configured to assign the active candidate delay code as the selected delay code; and When the delay locked loop circuit is in the active operating mode: The charge pump is configured to provide the feedback voltage signal as the control voltage signal of the voltage-controlled delay line; and The voltage-controlled delay line is configured to use the selected delay code as the delay code.

2. The delay locked loop circuit according to claim 1, characterized in that: The delay code setter is configured to apply the delay code setting signal to the voltage-controlled delay line so that the delay code setter applies a sequence of candidate delay codes in which the values ​​of the delay codes gradually increase until the final output signal is at least 2Π radians out of phase with the first output signal.

3. The delay locked loop circuit according to claim 1 or claim 2, characterized in that: The phase signal processor comprises a D-type flip-flop, wherein the D-type flip-flop has: a data input terminal, a clock input terminal and an output terminal, wherein: The data input terminal is configured to receive one of the up pulse signal and the down pulse signal; The clock input terminal is configured to receive the other of the up pulse signal and the down pulse signal; and The output is configured to provide the delayed code lock signal.

4. The delay locked loop circuit according to claim 3, characterized in that: The D-type flip-flop further comprises an enable input, and wherein: The enable input is configured to receive an enable input signal when the delay locked loop circuit is in the calibration operation mode; and The enable input is configured to receive a disable input signal when the delay locked loop circuit is in the active operating mode.

5. A delay locked loop circuit according to any preceding claim, characterised in that The phase detector is a proportional phase detector.

6. A delay locked loop circuit according to any preceding claim, characterised in that Also includes: A reset generator configured to ensure that the delay code setter receives a first rising edge of the last output signal before a corresponding rising edge of the first output signal before the delay code setter sequentially applies the different candidate delay codes to the voltage-controlled delay line.

7. A delay locked loop circuit according to any preceding claim, characterised in that The voltage-controlled delay line comprises: A delay line bias circuit, wherein: The delay line bias circuit includes a resistor bank; the resistor bank comprising a plurality of resistors connected in series between a resistor bank connection node and ground, wherein the resistor bank has resistance values ​​that affect the magnitude of the time delay applied by the voltage controlled delay line; The delay line bias circuit includes a plurality of bypass switches, each bypass switch being associated with a resistor in the resistor bank; each bypass switch is configured to selectively include or exclude its associated resistor arranged in series between the resistor group connection node and the ground terminal so as to set the resistance value of the resistor group based on a resistance code signal; and The delay line bias circuit includes a controller that provides the resistance code signal to each of the bypass switches based on a received delay code.

8. The delay locked loop circuit according to claim 7, characterized in that: The voltage-controlled delay line includes a plurality of delay buffers connected in series to successively apply a time delay to the clock input signal; The output of the first delay buffer is the first output signal; The output of the last delay buffer is the last output signal; and said magnitude of said time delay applied by each delay buffer being based on a bias voltage signal; The delay line bias circuit additionally includes a calibration transistor; The resistance value of the resistor bank is configured to set a current through the calibration transistor; and The delay line bias circuit is configured to set the bias voltage signal based on the current through the calibration transistor.

9. A delay locked loop circuit according to any preceding claim, characterised in that: The voltage-controlled delay line includes a plurality of delay buffers connected in series to successively apply a time delay to the clock input signal; Each of the plurality of delay buffers has: Input terminal; Output terminal; middle end; as well as a duty cycle distortion reduction circuit, the duty cycle distortion reduction circuit being connected in series between the intermediate terminal and the output terminal; The duty cycle distortion reduction circuit comprises: an AC-coupled capacitor and an inverter, each of which is connected in series between the intermediate terminal and the output terminal, wherein the inverter has an inverter input terminal and an inverter output terminal; A feedback resistor is connected in series between the inverter input terminal and the inverter output terminal.

10. The delay locked loop circuit according to claim 9, characterized in that: The duty cycle distortion reduction circuit further comprises: a first enabling switch connected in series with the feedback resistor between the inverter input and the inverter output; and A second enabling switch is connected in series between the inverter output terminal and a ground terminal.

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