Clock data recovery circuit

Abstract

A clock data recovery circuit includes a phase detector, a first signal processing path, a second signal processing path, an oscillator circuit, and a phase control circuit. The phase detector samples an input data signal according to a first clock signal to generate an up control signal and a down control signal. The first signal processing path includes at least one first signal processing device to generate a phase control signal according to the up control signal and the down control signal. The second signal processing path includes at least one second signal processing device to generate a frequency control signal according to the up control signal and the down control signal. The oscillator circuit generates a plurality of second clock signals according to the frequency control signal. The phase control circuit controls a phase of the second clock signals according to the phase control signal to generate the first clock signal.

Description

TECHNICAL FIELD

[0001] The present application relates to a novel clock data recovery (CDR) circuit architecture, in particular, a clock data recovery circuit architecture with low power consumption and high performance. BACKGROUND

[0002] When data is to be transmitted from one device to another, the receiving end must know when to sample the received data signal. Usually, a phase locked loop (PLL) and a delay locked loop (DLL) are used to generate the required frequency waveform. The receiving end needs clock alignment and regeneration circuit, such as the aforementioned PLL or DLL, to regenerate the correct clock frequency from the reference clock signal and synchronize the clock with the input data. The clock data recovery circuit is a circuit for outputting a synchronous clock signal and correctly recovering data.

[0003] The conventional CDR circuit provides a clock signal through an external independent PLL circuit. However, when the number of channels is greater, the transmission distance is longer, and the number of required clock buffers is greater, resulting in a large amount of current consumption. In addition, since the input signal is usually a high-speed signal, a large area is also required for the CDR circuit layout to isolate crosstalk and noise from interfering other circuits. In addition, the CDR circuit usually samples the input signal first, and then demultiplexes and reduces the speed for subsequent internal circuits to process the sampled data at a relatively low clock rate. However, when the demultiplexing clock rate is reduced, the regenerated sampling clock signal jitter is more severe, resulting in an increase in data error rate and reducing the performance of the CDR circuit.

[0004] Therefore, a novel CDR circuit architecture is needed to make the CDR circuit have low power consumption and high performance, effectively solving the conventional problems. SUMMARY

[0005] One object of the present application is to solve the problem of high power consumption and low performance of the conventional CDR circuit.

[0006] According to one embodiment of the present invention, a clock data recovery circuit includes a phase detector, a first signal processing path, a second signal processing path, an oscillator circuit, and a phase control circuit. The phase detector receives an input data signal and a plurality of first clock signals, and samples the input data signal according to the first clock signals to generate an upper control signal and a lower control signal. The first signal processing path is coupled to the phase detector and includes at least one first signal processing device, for receiving the upper control signal and the lower control signal, and generating a phase control signal according to the upper control signal and the lower control signal. The second signal processing path is coupled to the phase detector and includes at least one second signal processing device, for receiving the upper control signal and the lower control signal, and generating a frequency control signal according to the upper control signal and the lower control signal. The oscillator circuit generates a plurality of second clock signals according to the frequency control signal. The phase control circuit receives the second clock signals and the phase control signal, and controls the phase of the second clock signals according to the phase control signal to generate a first clock signal.

[0007] According to another embodiment of the present invention, a clock data recovery circuit includes a phase detector, a first signal processing path, a second signal processing path, an oscillator circuit, and a phase control circuit. The phase detector receives an input data signal and a plurality of first clock signals, and samples the input data signal according to the first clock signals to generate an upper control signal and a lower control signal. The first signal processing path is coupled to the phase detector and includes at least one first signal processing device for receiving the upper control signal and the lower control signal, and generating a phase control signal according to the upper control signal and the lower control signal. The second signal processing path is coupled to the phase detector and includes at least one second signal processing device for receiving the upper control signal and the lower control signal, and generating a frequency control signal according to the upper control signal and the lower control signal. The oscillator circuit generates a plurality of second clock signals according to the frequency control signal. The phase control circuit receives the second clock signals and the phase control signal, and controls the phase of the second clock signals according to the phase control signal to generate a first clock signal. The data processing rate on the second signal processing path is lower than the data processing rate on the first signal processing path. Attached Figure Description

[0008] Figure 1 An example block diagram of a clock data recovery (CDR) circuit according to an embodiment of the present invention is shown.

[0009] Figure 2 This diagram shows an example circuit diagram of a phase detector according to an embodiment of the present invention.

[0010] Figure 3 This diagram shows an example waveform of the input data signal and the clock signal according to an embodiment of the present invention.

[0011] Figure 4 A circuit model schematic diagram showing part of the circuit on the proportional signal processing path according to one embodiment of the present application.

[0012] Figure 5 A circuit model schematic diagram showing part of the circuit on the integral signal processing path according to one embodiment of the present application.

[0013] Figure 6 An example block diagram showing an oscillator circuit according to one embodiment of the present application.

[0014] Figure 7 A circuit model schematic diagram showing a phase control circuit according to one embodiment of the present application.

[0015] Figure 8 A phase control schematic diagram according to one embodiment of the present application. DETAILED DESCRIPTION

[0016] Figure 1 An example block diagram showing a clock data recovery (CDR) circuit according to one embodiment of the present application. The clock data recovery circuit 100 is configured to receive an input data signal Din, and sample the input data signal Din according to at least one clock signal CLK to generate an output data signal Dout. In addition to recovering the data content, the clock data recovery circuit 100 can also continuously adjust the frequency and phase of the clock signal CLK according to the input data signal Din to synchronize the clock signal CLK with the input data.

[0017] It is noted that since the clock data recovery circuit architecture proposed by the present application is mainly used to solve the problems of high power consumption and clock signal jitter in the conventional art, the operation of data recovery of the clock data recovery circuit will be generally omitted in the following embodiments, and the operation of clock recovery will be focused on.

[0018] The clock data recovery circuit 100 can include a phase detector 101, an oscillator circuit 102, a phase control circuit 103, and two separate signal processing paths coupled to the phase detector 101. The phase detector 101 receives an input data signal Din and a plurality of first clock signals, and is configured to sample the input data signal Din according to the first clock signals to generate at least one up control signal UP and at least one down control signal DN.

[0019] Figure 2An exemplary circuit diagram of a phase detector according to one embodiment of the present application is shown. In this example, the phase detector 201 is a full-rate bang-bang phase detector (BBPD). The phase detector 201 can include a plurality of logic circuits, such as the flip-flops and XOR gates shown in the figure, but is not limited thereto. The phase detector 201 can receive an input data signal Din and a plurality of first clock signals, which in this example include a clock signal CLK and an inverted clock signal CLKB (e.g., a clock signal provided to the clock input of the lower left flip-flop), and can sample the input data signal Din according to the clock signal CLK and the inverted clock signal CLKB to generate an up control signal UP and a down control signal DN. Figure 2 The phase detector 201 can sample the input data signal Din according to the clock signal CLK and the inverted clock signal CLKB to generate an up control signal UP and a down control signal DN.

[0020] Figure 3 An exemplary waveform diagram of an input data signal and clock signals according to one embodiment of the present application is shown to illustrate the operation of the phase detector 201. The phase detector 201 samples the input data signal Din using the rising edge of the clock signal CLKB (which is equivalent to the falling edge of the clock signal CLK) and the edge (or transition) of the input data signal Din using the rising edge of the clock signal CLK, which is equivalent to a double oversampling architecture. The sequentially obtained samples are shown as S1 and S2, and the results of the XOR operation of the sequentially obtained samples are shown as UP and DN. Figure 2 The up control signal UP and the down control signal DN can be generated by the XOR operation of the sequentially obtained samples, and the values of the generated up control signal UP and down control signal DN can be used to indicate whether the phase of the clock signal is lagging or leading. For example, if the rising edge of the clock signal CLK is shifted to the left, the sample S1 = 1, which is the content of the previous data, and the sample S2 = 0, and the result of the XOR operation of the sequentially obtained samples will make the value of the down control signal DN equal to 1 (DN = 1), which indicates that the phase of the clock signal CLK is currently leading. If the rising edge of the clock signal CLK is shifted to the right, the sample S3 = 1, and the sample S2 = 0, and the result of the XOR operation of the sequentially obtained samples will make the value of the up control signal UP equal to 1 (UP = 1), which indicates that the phase of the clock signal CLK is currently lagging.

[0021] It is noted that, Figure 2 and Figure 3 An exemplary circuit and operation of a full-rate bang-bang phase detector are shown. Those skilled in the art will appreciate that the phase detector is not limited to the exemplary full-rate bang-bang phase detector shown, but can include other types of phase detectors, such as a phase frequency detector (PFD) or a charge pump phase detector (CPD). Figure 2The phase detector 101 can be implemented in various manners. For example, in other embodiments of the present application, the phase detector can also be implemented as a half-rate binary phase detector, a quarter-rate binary phase detector, etc. When the phase detector is implemented as a half-rate, quarter-rate, etc., the number of clock signals used for the sampling operation, the phase difference, and the number of the up control signal UP and the down control signal DN generated are all adjusted accordingly. In addition, the present application is not limited to be implemented by a binary phase detector. In other embodiments of the present application, the phase detector can also be implemented by other types of phase detectors.

[0022] Referring again to Figure 1 In an embodiment of the present application, the clock data recovery circuit 100 separates two signal processing paths, including a signal processing path 110 (e.g., a first signal processing path or a proportional signal processing path) and a signal processing path 120 (e.g., a second signal processing path or an integral signal processing path), after the phase detector 101, where the two signal processing paths can process the received signal at different data processing rates.

[0023] According to an embodiment of the present application, the signal processing path 110 can include at least one first signal processing device for receiving the up control signal UP and the down control signal DN and generating a phase control signal according to the up control signal UP and the down control signal DN. The signal processing path 120 can include at least one second signal processing device for receiving the up control signal UP and the down control signal DN and generating a frequency control signal according to the up control signal UP and the down control signal DN.

[0024] According to an embodiment of the present application, the input data signal Din, the up control signal UP and the down control signal DN are sequential signals, where the values of the up control signal UP and the down control signal DN are sequentially generated according to the sampling results of the input data signal Din. The up control signal UP and the down control signal DN are converted into a first number of parallel signals in the signal processing path 110, and the up control signal UP and the down control signal DN are converted into a second number of parallel signals in the signal processing path 120, where the second number can be set to be greater than the first number, so that the data processing rate of the signal processing path 120 can be lower than the data processing rate of the signal processing path 110. Therefore, according to an embodiment of the present application, the operating frequency of the at least one second signal processing device can be lower than the operating frequency of the at least one first signal processing device.

[0025] According to one embodiment of the present application, the clock data recovery circuit 100 can further include a demultiplexer (DEMUX) 104-1, a decision circuit 105, a weight circuit 106-1, and an accumulator 107 configured in the signal processing path 110. The demultiplexer 104-1 is configured to receive the up control signal UP and the down control signal DN from the phase detector 101, and demultiplex the up control signal UP and the down control signal DN, respectively, to generate a first number of demultiplexed up control signals and a first number of demultiplexed down control signals. For example, the demultiplexer 104-1 can be a demultiplexer with a degree N to generate N parallel demultiplexed up control signals UP and N parallel demultiplexed down control signals DN, respectively, thereby reducing the bit rate (bit per second, abbreviated as bps) of the input data and the up control signal and the down control signal on the signal processing path 110. For example, assuming that the original data rate (bit rate) of the input data signal Din is 20 Gbps, the bit rate can be reduced to (20 G / N) Gbps after processing by the demultiplexer 104-1. It is noted that although the bit rate on the signal processing path 110 is reduced, the total data rate is still equal to the original data rate of the input data signal Din because the demultiplexer 104-1 converts the serial signals to N parallel signals. In addition, it is noted that the demultiplexer 104-1 is not a necessary device in the embodiments of the present application. Therefore, in some embodiments of the present application, the signal processing path 110 can also not include the demultiplexer.

[0026] The N parallel demultiplexed up control signals UP and the N parallel demultiplexed down control signals DN (or, in embodiments not including the demultiplexer, the up control signal UP and the down control signal DN, which will not be specially marked below for brevity) generated by the demultiplexer 104-1 can be provided to the decision circuit 105 (or voting circuit). The decision circuit 105 generates a decision signal according to the values of the N parallel demultiplexed up control signals UP and the N parallel demultiplexed down control signals DN to determine which of the phase-lagging and phase-leading phase detection results is the majority, or whether the number of the two is the same.

[0027] Figure 4A circuit model schematic diagram showing part of the circuit on the proportional signal processing path according to one embodiment of the present application is shown. The proportional signal processing path can include a decision circuit 405, a weight circuit 406, and an accumulator 407. In this example, assume that the order of the demultiplexer on the proportional signal processing path is N=4, then the decision circuit 405 will receive 4 parallel demultiplexed up control signals UP and 4 parallel demultiplexed down control signals DN (hereinafter referred to as demultiplexed control signals UP and DN), for example, 4-bit demultiplexed control signals UP and DN (denoted as 4b UP / DN in the figure). The decision circuit 405 can sum the values of the demultiplexed control signals UP and DN, respectively, to obtain the sum results Sum UP and Sum DN, and compare the values of the two sums, where Sum UP is the sum of the values carried by the 4 parallel demultiplexed up control signals UP, and Sum DN is the sum of the values carried by the 4 parallel demultiplexed down control signals DN. If Sum UP > Sum DN, it means that the phase-lagging phase detection results are in the majority, and the decision circuit 405 can set the value of the decision signal VOT to +1. If Sum UP < Sum DN, it means that the phase-leading phase detection results are in the majority, and the decision circuit 405 can set the value of the decision signal VOT to -1. If Sum UP = Sum DN, the decision circuit 405 can set the value of the decision signal VOT to 0. In one embodiment of the present application, the decision signal VOT can be a signed number and represented by 2 bits, where the effective data amount is 1 bit.

[0028] The weight circuit 406 can multiply the value of the decision signal VOT by a weight value KP. The accumulator 407 can receive the decision signal VOT (or the weighted decision signal VOT) from the weight circuit 406 and accumulate the value of the decision signal VOT to generate an accumulated signal ACCU as the phase control signal provided to the phase control circuit.

[0029] Referring again to Figure 1The clock data recovery circuit 100 can further include a demultiplexer (DEMUX) 104-2, a calculation circuit 109, a weight circuit 106-2, and a filter circuit 108 configured on the signal processing path 120. The demultiplexer 104-2 is configured to receive the up control signal UP and the down control signal DN from the phase detector 101, and demultiplex the up control signal UP and the down control signal DN, respectively, to generate a second number of demultiplexed up control signals and a second number of demultiplexed down control signals. For example, the demultiplexer 104-2 can be a demultiplexer of order M, configured to generate M parallel demultiplexed up control signals UP and M parallel demultiplexed down control signals DN, respectively, thereby reducing the bit rate (bps) of the input data and the up and down control signals on the signal processing path 120. According to an embodiment of the present application, the order M of the demultiplexer 104-2 can be set to be greater than the order N of the demultiplexer 104-1. In this way, the bit rate of the data and signals transmitted on the signal processing path 120 can be much lower than the bit rate transmitted on the signal processing path 110.

[0030] For example, assuming that the original data rate (bit rate) of the input data signal Din is 20 Gbps, the bit rate can be reduced to (20G / M) Gbps after processing by the demultiplexer 104-2. Note that although the bit rate on the signal processing path 120 is reduced, the total data rate is still equal to the original data rate of the input data signal Din because the demultiplexer 104-2 converts the serial signals to M parallel signals.

[0031] The M parallel demultiplexed up control signals UP and the M parallel demultiplexed down control signals DN generated by the demultiplexer 104-2 can be provided to the calculation circuit 109, which calculates the difference between the M parallel demultiplexed up control signals UP and the M parallel demultiplexed down control signals DN to generate a difference signal.

[0032] Figure 5A circuit model schematic diagram showing part of the circuit on the integral signal processing path according to one embodiment of the present application is shown. The integral signal processing path can include a calculation circuit 509, a weight circuit 506, and a filter circuit 508. In this example, assuming the order of the demultiplexer on the integral signal processing path is M = 32, the calculation circuit 509 will receive 32 (labeled as 32b) parallel demultiplexed up control signals UP and 32 (labeled as 32b) parallel demultiplexed down control signals DN (hereinafter referred to as demultiplexed control signals UP and DN). The calculation circuit 509 can sum the values of the demultiplexed control signals UP and DN, respectively, to obtain the sum results Sum UP and Sum DN, and calculate the difference between the two sum results, where in this example of the integral signal processing path, the sum result Sum UP is the sum of the values carried by the 32 parallel demultiplexed up control signals UP, and the sum result Sum DN is the sum of the values carried by the 32 parallel demultiplexed down control signals DN.

[0033] The calculation circuit 509 can subtract the sum result Sum DN from the sum result Sum UP to generate a difference signal Diff, which in one embodiment of the present application can be a signed number and can be represented by multiple bits.

[0034] The weight circuit 506 can multiply the value of the difference signal Diff by a weight value KI. The filter circuit 508 can receive the difference signal Diff (or the weighted difference signal Diff) from the weight circuit 506 and filter the value of the difference signal Diff to generate a filtered signal as the frequency control signal F Ctrl provided to the oscillator circuit. According to one embodiment of the present application, assuming the value of the difference signal Diff can be represented by multiple bits (e.g., 20 bits), the filter circuit 508 can perform the filtering operation by outputting part of the bits (e.g., 10 bits) of the difference signal Diff. For example, the filter circuit 508 selects 10 bits from the highest significant bit (MSB) of the bus used to carry the difference signal Diff as the frequency control signal F Ctrl. In this way, the filtering effect can be achieved to remove the noise in the difference signal Diff so that the frequency of the clock signal will not change due to small variations in the difference signal Diff.

[0035] Figure 6An exemplary block diagram of an oscillator circuit according to an embodiment of the present application is shown. The oscillator circuit 602 can include a digital-to-analog converter 621 and a voltage-controlled oscillator 622. The digital-to-analog converter 621 is configured to convert a received digital frequency control signal F_ctrl into an analog voltage signal. The voltage-controlled oscillator 622 receives the analog voltage signal and generates a plurality of clock signals according to the analog voltage signal, wherein the plurality of clock signals have the same frequency and a predetermined phase difference. Note that since the plurality of clock signals have the same frequency, for simplicity of the drawing and the specification, the plurality of clock signals are represented by a clock signal DCK hereinafter. Figure 6 The number and the phase of the clock signal DCK generated by the oscillator circuit 102 / 602 are related to the design of the phase detector according to an embodiment of the present application. For example, when the phase detector is implemented as a full-rate phase detector, the oscillator circuit 102 / 602 can generate two clock signals having the same frequency and opposite phase. When the phase detector is implemented as a half-rate phase detector, the oscillator circuit 102 / 602 can generate four clock signals having the same frequency and a phase difference of 90 degrees, and so on.

[0036] Referring again to Figure 1 , the phase control circuit 103 can receive the plurality of clock signals DCK from the oscillator circuit 102 and the phase control signal from the accumulator 107, and control the phase of the clock signal DCK according to the phase control signal to generate the plurality of clock signals required by the phase detector, e.g., the clock signals CLK and CLKB (for simplicity of the drawing, the clock signals CLK and CLKB are represented by a clock signal CLK hereinafter). Figure 1 According to an embodiment of the present application, the phase control circuit 103 can be a phase interpolator or a digital-to-phase converter (DPC).

[0037] Figure 7 A circuit model schematic diagram of a phase control circuit according to an embodiment of the present application is shown. The phase control circuit 703 can include a modulo circuit 731 and a phase adjustment circuit 732. The modulo circuit 731 is configured to receive the phase control signal to generate a modulo result. For example, the modulo circuit 731 can divide the phase control signal (the accumulator signal ACCU) by a value PI (e.g., PI = 16) to generate the modulo result, wherein the phase resolution of the clock signal generated by the phase control circuit 703 is controlled by the value PI. The phase adjustment circuit 732 can receive the plurality of clock signals DCK from the oscillator circuit 102 / 602 and the modulo result from the modulo circuit 731, and adjust the phase of the clock signal DCK according to the modulo result to generate the clock signal required by the phase detector, e.g., the clock signals CLK and CLKB (for simplicity of the drawing, the clock signals CLK and CLKB are represented by a clock signal CLK hereinafter). Figure 7The clock signal DCK is provided to the phase detector in a negative feedback manner. Note that the phase of the clock signal DCK generated by the oscillator circuit 102 / 602 is adjusted based on the same adjustment amount.

[0038] Figure 7 A phasor diagram with PI = 16 is also shown above the phase adjustment circuit 732 to illustrate the operation of the phase adjustment circuit. In one embodiment of the present application, the phase adjustment circuit 732 can select a corresponding clock signal from the PI phase- different clock signals as the clock signal provided to the phase detector based on the modulo result.

[0039] Figure 8 A phase control diagram according to one embodiment of the present application is shown. In this example, PI = 16. The phase adjustment circuit 732 can adjust the phase of the clock signal DCK based on the modulo result, which is equivalent to selecting a corresponding clock signal from the 16 phase-different clock signals (e.g., clock signals DCK, PI, P2, P3, P4, P5... P15 shown in the figure) as the clock signal provided to the phase detector, where the clock period of the clock signal DCK is assumed to be TDCK, the phase difference of the clock signals is TDCK / 16, and the phase resolution is 360 / 16 degrees. Referring to the figure, Figure 7 the operation of the phase adjustment circuit, Figure 8 selecting a clock signal with an increased phase difference is equivalent to Figure 7 clockwise phase adjustment, selecting a clock signal with a decreased phase difference is equivalent to Figure 7 counterclockwise phase adjustment.

[0040] In embodiments of the present application, since the clock data recovery circuit includes an oscillator circuit inside, there is no need to provide a clock signal through an external independent PLL circuit as in conventional CDR circuits, which effectively reduces current consumption and the circuit area occupied by the oscillator circuit. In addition, since the integration signal processing path can generate a corresponding frequency control signal based on the sampling result of the input data signal, the clock data recovery circuit proposed in the present application can have the ability to track a spread spectrum clock (abbreviated as SSC), which can ensure that the product can pass the jitter tolerance test (abbreviated as JTT) and obtain a certification mark compared to conventional technologies. In addition, since the clock data recovery circuit proposed in the present application generates a proportional Figure 1 signal processing path 110) and an integral Figure 1The signal processing path 120 shown is separated into signal processing paths, and demultiplexers of different orders are used to make the bit rate on the integral signal processing path much lower than the bit rate on the proportional signal processing path. In this way, the circuitry used to perform relatively complex signal processing in the integral signal processing path (e.g., Figure 1 The computational circuits, weighting circuits, and filter circuits in the circuit can be designed in the digital domain. For example, the Register Transfer Level (RTL) description language and Auto Place and Route (APR) tools can be used to design the circuits, which significantly reduces the difficulty of circuit design, makes clock data recovery circuits easier to implement, and effectively solves the problem of clock signal jitter in traditional technologies, thereby effectively improving the performance of clock data recovery circuits. In addition, since the signal processing device on the integral signal processing path can operate at low frequencies, this can further reduce circuit power consumption and shrink circuit area.

[0041] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.

[0042] Explanation of reference numerals in the attached figures:

[0043] 100: Clock data recovery circuit

[0044] 101, 201: Phase detectors

[0045] 102,602: Oscillator Circuit

[0046] 103,703: Phase control circuit

[0047] 104-1, 104-2: Demultiplexer

[0048] 105,405: Decision circuit

[0049] 106-1, 106-2, 406, 506: Weighting circuits

[0050] 107,407: Accumulator

[0051] 108,508: Filter circuit

[0052] 109,509: Calculation Circuits

[0053] 110,120: Signal processing path

[0054] 621: Digital-to-Analog Converter

[0055] 622: Voltage-controlled oscillator

[0056] 731: modulo circuit

[0057] 732: phase adjustment circuit

[0058] ACCU: accumulated signal

[0059] CLK, CLKB, DCK, P1, P2, P3, P4, P5: clock signal

[0060] Diff: difference signal

[0061] Din: input data signal

[0062] DN: down control signal

[0063] Dout: output data signal

[0064] F_ctrl: frequency control signal

[0065] KI, KP: weight value

[0066] S1, S2, S3: sampling result

[0067] UP: up control signal

[0068] VOT: decision signal

Claims

1. A clock data recovery circuit, comprising: a phase detector receiving an input data signal and a plurality of first clock signals to sample the input data signal according to the plurality of first clock signals to generate an up control signal and a down control signal; a first signal processing path coupled to the phase detector and comprising at least one first signal processing device to receive the up control signal and the down control signal and to generate a phase control signal according to the up control signal and the down control signal; a second signal processing path coupled to the phase detector and comprising at least one second signal processing device to receive the up control signal and the down control signal and to generate a frequency control signal according to the up control signal and the down control signal; an oscillator circuit to generate a plurality of second clock signals according to the frequency control signal; and a phase control circuit to receive the plurality of second clock signals and the phase control signal and to control a phase of the plurality of second clock signals according to the phase control signal to generate the plurality of first clock signals.

2. The clock data recovery circuit of claim 1, wherein an operating frequency of the at least one second signal processing device is lower than an operating frequency of the at least one first signal processing device.

3. The clock data recovery circuit of claim 1, wherein the input data signal, the up control signal and the down control signal are serial signals, the up control signal and the down control signal are converted to a first number of parallel signals in the first signal processing path, the up control signal and the down control signal are converted to a second number of parallel signals in the second signal processing path, and the second number is greater than the first number.

4. The clock data recovery circuit of claim 3, further comprising: a first demultiplexer disposed in the first signal processing path to receive the up control signal and the down control signal and to demultiplex the up control signal and the down control signal, respectively, to generate the first number of demultiplexed up control signals and the first number of demultiplexed down control signals.

5. The clock data recovery circuit of claim 4, further comprising: a decision circuit disposed in the first signal processing path to receive the first number of demultiplexed up control signals and the first number of demultiplexed down control signals and to generate a decision signal according to values of the first number of demultiplexed up control signals and the first number of demultiplexed down control signals; and an accumulator disposed in the first signal processing path to receive the decision signal and to accumulate values of the decision signal to generate an accumulated signal as the phase control signal.

6. The clock data recovery circuit of claim 3, further comprising: a second demultiplexer disposed in the second signal processing path to receive the up control signal and the down control signal and to demultiplex the up control signal and the down control signal, respectively, to generate the second number of demultiplexed up control signals and the second number of demultiplexed down control signals. ​ ​ 7. The clock data recovery circuit of claim 6, further comprising: a calculation circuit configured on the second signal processing path to receive the second number of de-multiplexed upper control signals and the second number of de-multiplexed lower control signals, and to calculate a difference between the second number of de-multiplexed upper control signals and the second number of de-multiplexed lower control signals to generate a difference signal; and a filter circuit configured on the second signal processing path to receive and filter the difference signal to generate the frequency control signal.

8. The clock data recovery circuit of claim 1, wherein the phase control circuit further comprises: a modulo circuit to receive the phase control signal to generate a modulo result; and a phase adjustment circuit to receive the plurality of second clock signals and the modulo result, and to adjust phases of the plurality of second clock signals according to the modulo result to generate the plurality of first clock signals.

9. A clock data recovery circuit, comprising: a phase detector to receive an input data signal and a plurality of first clock signals to sample the input data signal according to the plurality of first clock signals to generate upper control signals and lower control signals; a first signal processing path coupled to the phase detector and comprising at least one first signal processing device to receive the upper control signals and the lower control signals, and to generate a phase control signal according to the upper control signals and the lower control signals; a second signal processing path coupled to the phase detector and comprising at least one second signal processing device to receive the upper control signals and the lower control signals, and to generate a frequency control signal according to the upper control signals and the lower control signals; an oscillator circuit to generate a plurality of second clock signals according to the frequency control signal; and a phase control circuit to receive the plurality of second clock signals and the phase control signal, and to control phases of the plurality of second clock signals according to the phase control signal to generate the plurality of first clock signals, wherein a data processing rate on the second signal processing path is lower than a data processing rate on the first signal processing path.

10. The clock data recovery circuit of claim 9, wherein an operating frequency of the at least one second signal processing device is lower than an operating frequency of the at least one first signal processing device. ​ ​ ​

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