A method for achieving a wide locking range and low jitter by optimizing the phase-locked loop structure

Abstract

This invention relates to the field of phase-locked loop (PLL) technology, specifically to a method for achieving low jitter over a wide locking range by optimizing the PLL structure. The method includes: outputting a first error signal through a phase detector, obtaining the characteristics of the first error signal, and constructing a first error signal function; obtaining a first adaptive loop bandwidth; constructing a multi-band voltage-controlled oscillator (VCO) matching mechanism, including VCOs in multiple frequency bands; during PLL locking, selecting a frequency band based on the input signal frequency and the center frequency band of the VCO to obtain a first matching frequency band; and calculating the root mean square (RMS) of the first error signal based on further analysis of the first error signal characteristics, and combining the initial feedback gain and the initial error signal RMS to obtain a first feedback gain adjustment value. This invention achieves low jitter over a wide locking range through adaptive loop bandwidth adjustment, a multi-band VCO matching mechanism, and adaptive feedback gain adjustment.

Description

Technical Field

[0001] This invention relates to the field of phase-locked loop (PLL) technology, specifically to a method for achieving a wide locking range and low jitter by optimizing the PLL structure. Background Technology

[0002] A phase-locked loop (PLL) is a negative feedback control system that uses a voltage generated by phase synchronization to tune a voltage-controlled oscillator (VCO) to generate a target frequency. It uses an externally input reference signal to control the frequency and phase of the oscillation signal inside the loop, so as to achieve automatic tracking of the output signal frequency to the input signal frequency.

[0003] In traditional phase-locked loop (PLL) designs, the loop bandwidth and feedback gain are often fixed, and it is impossible to balance a wide locking range and low jitter, which can easily lead to limited PLL performance.

[0004] To address this, a method is proposed to achieve a wide locking range and low jitter by optimizing the phase-locked loop structure. Summary of the Invention

[0005] The purpose of this invention is to provide a method for achieving low jitter over a wide locking range by optimizing the phase-locked loop (PLL) structure. Specifically, this invention relates to the field of PLL technology, and more specifically to a method for achieving low jitter over a wide locking range by optimizing the PLL structure. The method includes: outputting a first error signal through a phase detector, obtaining the characteristics of the first error signal, and constructing a first error signal function; obtaining a first adaptive loop bandwidth; constructing a multi-band voltage-controlled oscillator (VCO) matching mechanism, including VCOs of multiple frequency bands; during the PLL locking process, selecting a frequency band based on the input signal frequency and the center frequency band of the VCO to obtain a first matching frequency band; and calculating the root mean square (RMS) of the first error signal based on further analysis of the first error signal characteristics, and combining the initial feedback gain and the initial RMS of the error signal to obtain a first feedback gain adjustment value. This invention achieves low jitter over a wide locking range through adaptive loop bandwidth adjustment, a multi-band VCO matching mechanism, and adaptive feedback gain adjustment.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A method for achieving low jitter over a wide locking range by optimizing the phase-locked loop structure includes:

[0008] S10. Based on the input signal of the phase-locked loop and the output signal of the voltage-controlled oscillator, the phase detector based on the phase-locked loop outputs a first error signal, and analyzes the first error signal to obtain the first error signal characteristics. Based on the first error signal characteristics, a first error signal function is constructed, and a first adaptive loop bandwidth is obtained based on the first error signal function, the maximum loop bandwidth, and the minimum loop bandwidth.

[0009] S20. Construct a multi-band voltage-controlled oscillator matching mechanism, wherein the multi-band voltage-controlled oscillator matching mechanism includes voltage-controlled oscillators of multiple frequency bands. During the phase-locked loop locking process, the voltage-controlled oscillator is selected according to the input signal frequency of the phase-locked loop and the center frequency band of the multiple frequency bands of the voltage-controlled oscillator to obtain the first matching frequency band.

[0010] S30. Analyze the characteristics of the first error signal to obtain the root mean square of the first error signal; obtain the first feedback gain adjustment value based on the root mean square of the first error signal, the initial feedback gain, and the root mean square of the initial error signal.

[0011] Preferably, the first error signal features include error amplitude and error change rate.

[0012] The bandwidth of the first adaptive loop is:

[0013] BW adaptive (t)=BW min +(BW max -BW min )*f(e(t));

[0014] Among them, BW adaptive (t) represents the bandwidth of the first adaptive loop; BW min BW represents the minimum loop bandwidth. max denoted as the maximum loop bandwidth; f(e(t)) represents the first error signal function.

[0015] Preferably, the first error signal function is:

[0016]

[0017] Where f(e(t)) represents the first error signal function; α represents the phase error amplitude influence factor; |e(t)| represents the phase error amplitude; β represents the phase error rate of change influence factor; This represents the rate of change of phase error.

[0018] Preferably, the voltage-controlled oscillator with multiple frequency bands includes multiple center frequencies, and the suitable frequency band of the voltage-controlled oscillator is determined according to the multiple center frequencies and the input signal frequency.

[0019] Preferably, the voltage-controlled oscillator for the multiple frequency bands is:

[0020]

[0021] Wherein, MultiFVCO represents the voltage-controlled oscillator for the multiple frequency bands; f n This indicates the nth frequency band including the voltage-controlled oscillator; f represents the frequency; fn_mi f represents the minimum frequency of the nth frequency band; n_ma This represents the maximum frequency of the nth frequency band.

[0022] Preferably, the plurality of center frequencies are:

[0023]

[0024] Among them, f n_center Represents the plurality of center frequencies; f n_mi f represents the minimum frequency of the nth frequency band including the voltage-controlled oscillator; n_ma This represents the maximum frequency of the nth frequency band, including the voltage-controlled oscillator.

[0025] Preferably, the first matching frequency band is:

[0026] f selected =f q ;

[0027] q = argmin(f q_center -f input );

[0028] Among them, f selected Indicates the first matching frequency band; f q This represents the q-th frequency band of the voltage-controlled oscillator; argmin() represents a mathematical function used to find the independent variable whose value is minimized; f q_center f represents the center frequency of the q-th frequency band of the voltage-controlled oscillator; input This indicates the frequency of the input signal.

[0029] Preferably, the root mean square of the first error signal is:

[0030]

[0031] Among them, RMS e The root mean square of the first error signal is represented by ; T represents the time window; and e(t) represents the first error signal.

[0032] Preferably, the first feedback gain adjustment value is:

[0033] K feedback (t)=K0*(1+ξ*(RMS e -RMS0));

[0034] Among them, K feedback (t) represents the first feedback gain adjustment value; K0 represents the initial feedback gain; ξ represents the gain adjustment coefficient, used to control the adjustment range of the feedback gain; RMS eRMS0 represents the root mean square of the first error signal; RMS0 represents the root mean square of the initial error signal.

[0035] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0036] 1. This invention constructs a first error signal function by analyzing the characteristics of the first error signal (error amplitude and error change rate), and dynamically calculates a first adaptive loop bandwidth based on this function, the maximum loop bandwidth, and the minimum loop bandwidth. This adaptive design allows the phase-locked loop to use a larger bandwidth during rapid locking, while automatically reducing the bandwidth in a stable state to reduce jitter and avoid introducing excessive phase noise due to excessive bandwidth. This effectively balances the requirements of a wide locking range and low jitter in the design of the phase-locked loop, further improving its performance.

[0037] 2. This invention introduces a multi-band voltage-controlled oscillator matching mechanism, which can use the most suitable frequency band during the stable phase, reduce noise caused by the voltage-controlled oscillator, and reduce phase jitter. The multi-band voltage-controlled oscillator matching mechanism ensures that the optimal operating frequency band can be selected during the locking phase through intelligent matching, thereby significantly reducing system jitter while ensuring a wide locking range. This effectively balances the requirements of a wide locking range and low jitter in the design of the phase-locked loop, further improving the performance of the phase-locked loop.

[0038] 3. This invention analyzes the root mean square of the first error signal, combines the initial feedback gain and the root mean square of the initial error signal, and calculates the adjustment value of the first feedback gain. By dynamically adjusting the feedback gain, the response speed and stability of the system can be effectively controlled, further reducing jitter and achieving a more precise balance between a wide locking range and low jitter. Thus, in the design of the phase-locked loop, the requirements of a wide locking range and low jitter can be effectively balanced, further improving the performance of the phase-locked loop. Attached Figure Description

[0039] Figure 1 This is a schematic flowchart of a method for achieving low jitter over a wide locking range by optimizing the phase-locked loop structure, provided by an embodiment of the present invention.

[0040] Figure 2 A schematic diagram of the process for obtaining the first adaptive loop bandwidth provided in an embodiment of the present invention;

[0041] Figure 3 This is a schematic diagram illustrating the process of obtaining the first feedback gain adjustment value according to an embodiment of the present invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] Example 1

[0044] To improve the performance of phase-locked loop A, a method was applied to achieve low jitter over a wide locking range by optimizing the phase-locked loop structure.

[0045] refer to Figure 1 The above is a schematic flowchart of a method for achieving low jitter over a wide locking range by optimizing the phase-locked loop structure, provided by an embodiment of the present invention, including:

[0046] S10. Based on the input signal of the phase-locked loop and the output signal of the voltage-controlled oscillator, the phase detector based on the phase-locked loop outputs a first error signal, and analyzes the first error signal to obtain the first error signal characteristics. Based on the first error signal characteristics, a first error signal function is constructed, and a first adaptive loop bandwidth is obtained based on the first error signal function, the maximum loop bandwidth, and the minimum loop bandwidth.

[0047] Furthermore, the first error signal features include the error amplitude and the error change rate.

[0048] In this embodiment, the input signal is a 1.5GHz input signal, and the characteristic data of the first error signal of the A phase-locked loop part are shown in Table 1;

[0049] Table 1A: Characteristic Data of the First Error Signal in the Phase-Locked Loop

[0050]

[0051] The bandwidth of the first adaptive loop is:

[0052] BW adaptive (t)=BW min +(BW max -BW min )*f(e(t));

[0053] Among them, BW adaptive (t) represents the bandwidth of the first adaptive loop; BW min BW represents the minimum loop bandwidth. max denoted as the maximum loop bandwidth; f(e(t)) represents the first error signal function.

[0054] Furthermore, the first error signal function is:

[0055]

[0056] Where f(e(t)) represents the first error signal function; α represents the phase error amplitude influence factor; |e(t)| represents the phase error amplitude; β represents the phase error rate of change influence factor; This represents the rate of change of phase error.

[0057] This embodiment analyzes the characteristics of the first error signal (error amplitude and error change rate) to construct a first error signal function, and dynamically calculates the first adaptive loop bandwidth based on this function, the maximum loop bandwidth, and the minimum loop bandwidth. This adaptive design allows the phase-locked loop to use a larger bandwidth during rapid locking, while automatically reducing the bandwidth in a stable state to reduce jitter and avoid introducing excessive phase noise due to excessive bandwidth. This effectively balances the requirements of a wide locking range and low jitter in the design of the phase-locked loop, further improving its performance.

[0058] Reference Figure 2 A schematic diagram of the process for obtaining the first adaptive loop bandwidth provided in an embodiment of the present invention;

[0059] S20. Construct a multi-band voltage-controlled oscillator matching mechanism, wherein the multi-band voltage-controlled oscillator matching mechanism includes voltage-controlled oscillators of multiple frequency bands. During the phase-locked loop locking process, the voltage-controlled oscillator is selected according to the input signal frequency of the phase-locked loop and the center frequency band of the multiple frequency bands of the voltage-controlled oscillator to obtain the first matching frequency band.

[0060] Furthermore, the voltage-controlled oscillator for the multiple frequency bands is:

[0061]

[0062] Wherein, MultiFVCO represents the voltage-controlled oscillator for the multiple frequency bands; f n This indicates the nth frequency band including the voltage-controlled oscillator; f represents the frequency; f i_center f represents the minimum frequency of the nth frequency band; n_ma This represents the maximum frequency of the nth frequency band.

[0063] Furthermore, the plurality of center frequencies are:

[0064]

[0065] Among them, f n_center Represents the plurality of center frequencies; f n_mi f represents the minimum frequency of the nth frequency band including the voltage-controlled oscillator; n_maThis represents the maximum frequency of the nth frequency band, including the voltage-controlled oscillator.

[0066] Furthermore, the first matching frequency band is:

[0067] f selected =f q ;

[0068] q = argmin(f q_center -f input );

[0069] Among them, f selected Indicates the first matching frequency band; f q This represents the q-th frequency band of the voltage-controlled oscillator; argmin() represents a mathematical function used to find the independent variable whose value is minimized; f q_center f represents the center frequency of the q-th frequency band of the voltage-controlled oscillator; input This indicates the frequency of the input signal.

[0070] This embodiment introduces a multi-band voltage-controlled oscillator (VCO) matching mechanism, which can use the most suitable frequency band during the stabilization phase, reducing noise caused by the VCO and lowering phase jitter. The multi-band VCO matching mechanism ensures that the optimal operating frequency band can be selected during the locking phase through intelligent matching, thereby significantly reducing system jitter while ensuring a wide locking range. This effectively balances the requirements of a wide locking range and low jitter in the design of the phase-locked loop (PLL), further improving the performance of the PLL.

[0071] This embodiment, through the combination of a first adaptive loop bandwidth design and a multi-band voltage-controlled oscillator matching mechanism, enables rapid locking and low jitter at different operating stages of the phase-locked loop. The adaptive loop bandwidth adjustment provides flexible bandwidth management, while the multi-band voltage-controlled oscillator matching mechanism ensures that the most suitable frequency band can be used both during the initial locking phase and after stabilization, thus achieving a balance between a wide locking range and low jitter.

[0072] S30. Analyze the characteristics of the first error signal to obtain the root mean square of the first error signal; obtain the first feedback gain adjustment value based on the root mean square of the first error signal, the initial feedback gain, and the root mean square of the initial error signal.

[0073] Furthermore, the root mean square of the first error signal is:

[0074]

[0075] Among them, RMS e The root mean square of the first error signal is represented by ; T represents the time window; and e(t) represents the first error signal.

[0076] Furthermore, the first feedback gain adjustment value is:

[0077] K feedback (t)=K0*(1+ξ*(RMS e -RMS0));

[0078] Among them, K feedback (t) represents the first feedback gain adjustment value; K0 represents the initial feedback gain; ξ represents the gain adjustment coefficient, used to control the adjustment range of the feedback gain; RMS e RMS0 represents the root mean square of the first error signal; RMS0 represents the root mean square of the initial error signal.

[0079] Reference Figure 3 This is a schematic diagram illustrating the process of obtaining the first feedback gain adjustment value according to an embodiment of the present invention.

[0080] This embodiment analyzes the root mean square of the first error signal, combines the initial feedback gain and the root mean square of the initial error signal, and calculates the adjustment value of the first feedback gain. By dynamically adjusting the feedback gain, the response speed and stability of the system can be effectively controlled, further reducing jitter and achieving a more precise balance between a wide locking range and low jitter. This effectively balances the requirements of a wide locking range and low jitter in the design of the phase-locked loop, further improving the performance of the phase-locked loop.

[0081] This embodiment, based on adaptive loop bandwidth adjustment and multi-band voltage-controlled oscillator matching mechanism, achieves a more precise balance between a wide lock-in range and low jitter through adaptive adjustment of the feedback gain. Specifically, during the initial lock-in phase, the system accelerates lock-in by increasing the adaptive loop bandwidth and selecting a high-frequency voltage-controlled oscillator, while the adjustment of the feedback gain ensures that the rate of bandwidth increase does not introduce excessive noise. During the stabilization phase, the loop bandwidth is gradually reduced and switched to a lower frequency band, while the feedback gain adjustment further ensures that the system remains stable with minimal jitter, preventing performance instability caused by bandwidth reduction that is too rapid or too slow.

[0082] To verify the effectiveness of the method proposed in this embodiment for achieving low jitter over a wide locking range by optimizing the phase-locked loop structure, a comparative experiment was conducted. Multiple input signals were selected for comparison, and methods one, two, three, and four were chosen for comparison. Method one is the method proposed in this embodiment for achieving low jitter over a wide locking range by optimizing the phase-locked loop structure; method two is based on method one but without considering adaptive adjustment of the loop bandwidth; method three is based on method one but without considering the multi-band selection mechanism; and method four is based on method one but without considering adaptive adjustment of the feedback gain. The average output jitter and the comprehensive locking range values ​​are compared, and the specific results are shown in Table 2.

[0083] Table 2 Comparison of Output Jitter and Lock Range of Different Methods

[0084]

[0085] As shown in Table 2, the method proposed in this embodiment for achieving a wide locking range and low jitter by optimizing the phase-locked loop structure has certain advantages in both output jitter and locking range. Therefore, this method is effective compared with other methods.

[0086] This embodiment outputs a first error signal through a phase detector, obtains the characteristics of the first error signal, and constructs a first error signal function; it obtains a first adaptive loop bandwidth; it constructs a multi-band voltage-controlled oscillator (VCO) matching mechanism, including VCOs of multiple frequency bands; during the phase-locked loop (PLL) locking process, it selects a frequency band based on the input signal frequency and the center frequency band of the VCO to obtain a first matching frequency band; based on further analysis of the characteristics of the first error signal, it calculates the root mean square (RMS) of the first error signal, and combines the initial feedback gain and the RMS of the initial error signal to obtain a first feedback gain adjustment value. This invention achieves a wide locking range and low jitter effect through adaptive loop bandwidth adjustment, a multi-band VCO matching mechanism, and adaptive feedback gain adjustment.

[0087] Example 2

[0088] To improve the performance of the B phase-locked loop, a method was applied to achieve a wide locking range and low jitter by optimizing the phase-locked loop structure.

[0089] refer to Figure 1 The above is a schematic flowchart of a method for achieving low jitter over a wide locking range by optimizing the phase-locked loop structure, provided by an embodiment of the present invention, including:

[0090] S10. Based on the input signal of the phase-locked loop and the output signal of the voltage-controlled oscillator, the phase detector based on the phase-locked loop outputs a first error signal, and analyzes the first error signal to obtain the first error signal characteristics. Based on the first error signal characteristics, a first error signal function is constructed, and a first adaptive loop bandwidth is obtained based on the first error signal function, the maximum loop bandwidth, and the minimum loop bandwidth.

[0091] Furthermore, the first error signal features include the error amplitude and the error change rate.

[0092] Table 3B: Characteristic Data of the First Error Signal in the Phase-Locked Loop

[0093]

[0094] In this embodiment, the input signal is a 1.4GHz input signal, and the first error signal characteristic data of the input signal of the B phase-locked loop part are shown in Table 3;

[0095] The bandwidth of the first adaptive loop is:

[0096] BW adaptive (t)=BW min +(BW max -BW min )*f(e(t));

[0097] Among them, BW adaptive (t) represents the bandwidth of the first adaptive loop; BW min BW represents the minimum loop bandwidth. max denoted as the maximum loop bandwidth; f(e(t)) represents the first error signal function.

[0098] Furthermore, the first error signal function is:

[0099]

[0100] Where f(e(t)) represents the first error signal function; α represents the phase error amplitude influence factor; |e(t)| represents the phase error amplitude; β represents the phase error rate of change influence factor; This represents the rate of change of phase error.

[0101] Reference Figure 2 A schematic diagram of the process for obtaining the first adaptive loop bandwidth provided in an embodiment of the present invention;

[0102] This embodiment analyzes the characteristics of the first error signal (error amplitude and error change rate) to construct a first error signal function, and dynamically calculates the first adaptive loop bandwidth based on this function, the maximum loop bandwidth, and the minimum loop bandwidth. This adaptive design allows the phase-locked loop to use a larger bandwidth during rapid locking, while automatically reducing the bandwidth in a stable state to reduce jitter and avoid introducing excessive phase noise due to excessive bandwidth. This effectively balances the requirements of a wide locking range and low jitter in the design of the phase-locked loop, further improving its performance.

[0103] S20. Construct a multi-band voltage-controlled oscillator matching mechanism, wherein the multi-band voltage-controlled oscillator matching mechanism includes voltage-controlled oscillators of multiple frequency bands. During the phase-locked loop locking process, the voltage-controlled oscillator is selected according to the input signal frequency of the phase-locked loop and the center frequency band of the multiple frequency bands of the voltage-controlled oscillator to obtain the first matching frequency band.

[0104] Furthermore, the voltage-controlled oscillator for the multiple frequency bands is:

[0105]

[0106] Wherein, MultiFVCO represents the voltage-controlled oscillator for the multiple frequency bands; f n This indicates the nth frequency band including the voltage-controlled oscillator; f represents the frequency; f n_mi f represents the minimum frequency of the nth frequency band; n_ma This represents the maximum frequency of the nth frequency band.

[0107] Furthermore, the plurality of center frequencies are:

[0108]

[0109] Among them, f n_center Represents the plurality of center frequencies; f n_mi f represents the minimum frequency of the nth frequency band including the voltage-controlled oscillator; n_ma This represents the maximum frequency of the nth frequency band, including the voltage-controlled oscillator.

[0110] Furthermore, the first matching frequency band is:

[0111] f selected =f q ;

[0112] q = argmin(f q_center -f input );

[0113] Among them, f selected Indicates the first matching frequency band; f q This represents the q-th frequency band of the voltage-controlled oscillator; argmin() represents a mathematical function used to find the independent variable whose value is minimized; f q_center f represents the center frequency of the q-th frequency band of the voltage-controlled oscillator; input This indicates the frequency of the input signal.

[0114] This embodiment introduces a multi-band voltage-controlled oscillator (VCO) matching mechanism, which can use the most suitable frequency band during the stabilization phase, reducing noise caused by the VCO and lowering phase jitter. The multi-band VCO matching mechanism ensures that the optimal operating frequency band can be selected during the locking phase through intelligent matching, thereby significantly reducing system jitter while ensuring a wide locking range. This effectively balances the requirements of a wide locking range and low jitter in the design of the phase-locked loop (PLL), further improving the performance of the PLL.

[0115] This embodiment, through the combination of a first adaptive loop bandwidth design and a multi-band voltage-controlled oscillator matching mechanism, enables rapid locking and low jitter at different operating stages of the phase-locked loop. The adaptive loop bandwidth adjustment provides flexible bandwidth management, while the multi-band voltage-controlled oscillator matching mechanism ensures that the most suitable frequency band can be used both during the initial locking phase and after stabilization, thus achieving a balance between a wide locking range and low jitter.

[0116] S30. Analyze the characteristics of the first error signal to obtain the root mean square of the first error signal; obtain the first feedback gain adjustment value based on the root mean square of the first error signal, the initial feedback gain, and the root mean square of the initial error signal.

[0117] Furthermore, the root mean square of the first error signal is:

[0118]

[0119] Among them, RMS e The root mean square of the first error signal is represented by ; T represents the time window; and e(t) represents the first error signal.

[0120] Furthermore, the first feedback gain adjustment value is:

[0121] K feedback (t)=K0*(1+ξ*(RMS e -RMS0));

[0122] Among them, K feedback (t) represents the first feedback gain adjustment value; K0 represents the initial feedback gain; ξ represents the gain adjustment coefficient, used to control the adjustment range of the feedback gain; RMS e RMS0 represents the root mean square of the first error signal; RMS0 represents the root mean square of the initial error signal.

[0123] Reference Figure 3 This is a schematic diagram illustrating the process of obtaining the first feedback gain adjustment value according to an embodiment of the present invention.

[0124] This embodiment analyzes the root mean square of the first error signal, combines the initial feedback gain and the root mean square of the initial error signal, and calculates the adjustment value of the first feedback gain. By dynamically adjusting the feedback gain, the response speed and stability of the system can be effectively controlled, further reducing jitter and achieving a more precise balance between a wide locking range and low jitter. This effectively balances the requirements of a wide locking range and low jitter in the design of the phase-locked loop, further improving the performance of the phase-locked loop.

[0125] This embodiment, based on adaptive loop bandwidth adjustment and multi-band voltage-controlled oscillator matching mechanism, achieves a more precise balance between a wide lock-in range and low jitter through adaptive adjustment of the feedback gain. Specifically, during the initial lock-in phase, the system accelerates lock-in by increasing the adaptive loop bandwidth and selecting a high-frequency voltage-controlled oscillator, while the adjustment of the feedback gain ensures that the rate of bandwidth increase does not introduce excessive noise. During the stabilization phase, the loop bandwidth is gradually reduced and switched to a lower frequency band, while the feedback gain adjustment further ensures that the system remains stable with minimal jitter, preventing performance instability caused by bandwidth reduction that is too rapid or too slow.

[0126] To verify the effectiveness of the proposed method for achieving low jitter over a wide locking range by optimizing the phase-locked loop structure, a comparative experiment was conducted. Multiple input signals were selected for comparison, with Method 1, Method 2, Method 3, and Method 4 chosen for comparison. Method 1 is the proposed method for achieving low jitter over a wide locking range by optimizing the phase-locked loop structure; Method 2 is based on Method 1 without considering adaptive adjustment of the loop bandwidth; Method 3 is based on Method 1 without considering the multi-band selection mechanism; and Method 4 is based on Method 1 without considering adaptive adjustment of the feedback gain. The average output jitter and the comprehensive locking range values ​​are compared, and the specific results are shown in Table 4.

[0127] Table 4 Comparison of Output Jitter and Lock Range of Different Methods

[0128] method Output jitter (picosecond) Lock-on range (GHz) Method 1 30 1.0-2.0 Method 2 60 1.2-1.8 Method 3 50 1.3-1.7 Method 4 40 1.2-1.7

[0129] As shown in Table 4, the method proposed in this embodiment for achieving a wide locking range and low jitter by optimizing the phase-locked loop structure has certain advantages in both output jitter and locking range. Therefore, this method is effective compared with other methods.

[0130] This embodiment outputs a first error signal through a phase detector, obtains the characteristics of the first error signal, and constructs a first error signal function; it obtains a first adaptive loop bandwidth; it constructs a multi-band voltage-controlled oscillator (VCO) matching mechanism, including VCOs of multiple frequency bands; during the phase-locked loop (PLL) locking process, it selects a frequency band based on the input signal frequency and the center frequency band of the VCO to obtain a first matching frequency band; based on further analysis of the characteristics of the first error signal, it calculates the root mean square (RMS) of the first error signal, and combines the initial feedback gain and the RMS of the initial error signal to obtain a first feedback gain adjustment value. This invention achieves a wide locking range and low jitter effect through adaptive loop bandwidth adjustment, a multi-band VCO matching mechanism, and adaptive feedback gain adjustment.

[0131] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for achieving wide locking range and low jitter by optimizing a phase-locked loop structure, characterized in that, include: S10. Based on the input signal of the phase-locked loop (PLL) and the output signal of the voltage-controlled oscillator (VCO), the phase detector of the PLL outputs a first error signal, and analyzes the first error signal to obtain its characteristics. A first error signal function is then constructed based on these characteristics, and a first adaptive loop bandwidth is obtained based on the first error signal function, the maximum loop bandwidth, and the minimum loop bandwidth. The first adaptive loop bandwidth is: ; in, This represents the bandwidth of the first adaptive loop; Indicates the minimum loop bandwidth; Indicates the maximum loop bandwidth; The first error signal function is: ; in, Represents the first error signal function; This indicates the influence factor of phase error amplitude; Indicates the phase error magnitude; This represents the factor influencing the rate of change of phase error; This represents the rate of change of phase error; S20. Construct a multi-band voltage-controlled oscillator matching mechanism, wherein the multi-band voltage-controlled oscillator matching mechanism includes voltage-controlled oscillators of multiple frequency bands. During the phase-locked loop locking process, the voltage-controlled oscillator is selected according to the input signal frequency of the phase-locked loop and the center frequency band of the multiple frequency bands of the voltage-controlled oscillator to obtain the first matching frequency band. S30. Analyze the characteristics of the first error signal to obtain the root mean square (RMS) of the first error signal; obtain the first feedback gain adjustment value based on the RMS of the first error signal, the initial feedback gain, and the RMS of the initial error signal; the first feedback gain adjustment value is: ; in, This represents the first feedback gain adjustment value; This represents the initial feedback gain; This represents the gain adjustment coefficient, used to control the adjustment range of the feedback gain; This represents the root mean square of the first error signal; The root mean square of the initial error signal is represented.

2. The method for achieving low jitter over a wide locking range by optimizing the phase-locked loop structure according to claim 1, characterized in that: The first error signal features include error amplitude and error rate of change.

3. The method for achieving low jitter over a wide locking range by optimizing the phase-locked loop structure according to claim 1, characterized in that: The voltage-controlled oscillator with multiple frequency bands includes multiple center frequencies, and the suitable frequency band of the voltage-controlled oscillator is determined according to the multiple center frequencies and the input signal frequency.

4. The method for achieving a wide locking range and low jitter by optimizing the phase-locked loop structure according to claim 3, characterized in that: The voltage-controlled oscillators for the multiple frequency bands are: ; in, This refers to voltage-controlled oscillators (VCOs) operating in the aforementioned frequency bands. This indicates the first voltage-controlled oscillator. One frequency band; Indicates frequency; Indicates the first The minimum frequency of each frequency band; Indicates the first The maximum frequency of each frequency band.

5. The method for achieving a wide locking range and low jitter by optimizing the phase-locked loop structure according to claim 3, characterized in that: The plurality of center frequencies are: ; in, Indicates the plurality of center frequencies; This indicates the first voltage-controlled oscillator. The minimum frequency of each frequency band; This indicates the first voltage-controlled oscillator. The maximum frequency of each frequency band.

6. The method for achieving low jitter over a wide locking range by optimizing the phase-locked loop structure according to claim 5, characterized in that: The first matching frequency band is: ; ; in, This indicates the first matching frequency band; The first voltage-controlled oscillator One frequency band; It represents a mathematical function used to find the independent variable whose function value is minimized; The first voltage-controlled oscillator The center frequency of each frequency band; This indicates the frequency of the input signal.

7. The method for achieving low jitter over a wide locking range by optimizing the phase-locked loop structure according to claim 1, characterized in that: The root mean square of the first error signal is: ; in, This represents the root mean square of the first error signal; Indicates a time window; This represents the first error signal.

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