Phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination

Abstract

The invention discloses a phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination. The phase-locked loop system comprises a sampling phase discriminator which comprises a first sampling path, a second sampling path and a non-overlapping sampling clock generation circuit used for generating a first sampling clock signal and a second sampling clock signal; alternately sampling and updating the phase error voltage signal through the first sampling path and the second sampling path; the transconductance amplifier is used for receiving the phase error voltage signal and a reference voltage and inputting an output current signal into the filter so as to output an integral voltage signal; the filter is also used for receiving the phase error voltage signal and outputting a proportional voltage signal; the voltage-controlled oscillator is used for receiving the integral voltage signal and the proportional voltage signal and outputting a feedback clock signal. According to the phase-locked loop system provided by the invention, the rising edge and the falling edge of the clock signal are fully utilized to update the control voltage at double reference frequency.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of phase-locked loop, and particularly relates to a phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination. BACKGROUND

[0002] Phase-locked loop (PLL) is an important component in contemporary electronic systems, and is widely used in wired and wireless communications. The PLL provides a stable clock source for the operation of these systems. At present, most of the voltage-controlled oscillators in the market adopt LC oscillators, which have good phase noise performance. However, LC oscillators also have problems such as large area and electromagnetic interference. In contrast, ring oscillators have the characteristics of high integration, natural generation of multiple phase clocks, and small electromagnetic interference. However, the main disadvantage of ring oscillators is poor phase noise characteristics. Therefore, it is very important to expand the loop bandwidth of the phase-locked loop to suppress the noise of the ring voltage-controlled oscillator.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the application, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] In order to solve the above problems existing in the prior art, the application provides a phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination. The technical problem to be solved by the application is solved by the following technical scheme: The application provides a phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination, which comprises a sampling phase discriminator, a transconductance amplifier, a filter and a voltage-controlled oscillator. The sampling phase discriminator comprises a first sampling path, a second sampling path and a non-overlapping sampling clock generation circuit. The first sampling path is used for sampling and outputting a first phase error voltage signal corresponding to the first sampling path under the control of a reference clock signal and a feedback clock signal. The second sampling path is used for sampling and outputting a second phase error voltage signal corresponding to the second sampling path under the control of an inverted reference clock signal and an inverted feedback clock signal. The non-overlapping sampling clock generation circuit is used for generating first and second sampling clock signals that do not overlap with each other to control the sampling of the first and second sampling paths. The first and second phase error voltage signals are used to alternately update the phase error voltage signal. The transconductance amplifier is used for receiving the phase error voltage signal and a reference voltage, converting the voltage difference between the phase error voltage signal and the reference voltage into a current signal, and inputting the current signal into the filter to output an integral voltage signal. The filter is also used for receiving the phase error voltage signal and filtering out the reference frequency ripple of the phase error voltage signal to output a proportional voltage signal. The voltage-controlled oscillator is used for adjusting the output frequency under the control of the integral voltage signal and the proportional voltage signal and outputting a feedback clock signal.

[0005] In an embodiment of the present application, the first sampling path comprises a first main sampling circuit and a first slave sampling circuit. The first main sampling circuit comprises a first capacitor, a fourth MOS transistor and a plurality of first switch control modules connected in parallel, each first switch control module comprising a first MOS transistor, a second MOS transistor, a third MOS transistor and a first resistor. The source of the first MOS transistor is connected with a power supply, the drain of the first MOS transistor is connected with the source of the second MOS transistor, the gate of the first MOS transistor is connected with the output end of a first enable signal, the gate of the second MOS transistor is connected with the output end of a reference clock signal, the drain of the second MOS transistor is connected with the source of the third MOS transistor, the gate of the third MOS transistor is connected with the output end of a feedback clock signal, the drain of the third MOS transistor is connected with the first end of the first resistor, the second end of each first resistor is connected with a first node, one end of the first capacitor is connected with the first node, and the other end of the first capacitor is grounded, the drain of the fourth MOS transistor is connected with the drain of the third MOS transistor of each first switch control module, the gate of the fourth MOS transistor is connected with the output end of the reference clock signal, and the source of the fourth MOS transistor is grounded, and the voltage signal of the first node is a first sampling voltage signal. The first slave sampling circuit comprises a first gate voltage self-boosting switch and a third capacitor, the first end of the first gate voltage self-boosting switch is connected with the first node, the second end of the first gate voltage self-boosting switch is connected with a third node, one end of the third capacitor is connected with the third node, and the other end of the third capacitor is grounded, and the first slave sampling circuit is used for enabling the first gate voltage self-boosting switch to sample the first sampling voltage signal under the control of a first sampling clock signal, and updating the voltage of the third node to be a phase error voltage signal corresponding to the first sampling path.

[0006] In an embodiment of the present application, the second sampling path comprises a second main sampling circuit and a second slave sampling circuit. The second main sampling circuit comprises a second capacitor, an eighth MOS transistor and a plurality of second switch control modules connected in parallel, each second switch control module comprising a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and a second resistor. The source of the fifth MOS is connected with a power supply, the drain of the fifth MOS is connected with the source of the sixth MOS, and the gate of the fifth MOS is connected with the output end of the second enable signal; the gate of the sixth MOS is connected with the output end of the inverted reference clock signal, and the drain of the sixth MOS is connected with the source of the seventh MOS; the gate of the seventh MOS is connected with the output end of the inverted feedback clock signal, and the drain of the seventh MOS is connected with the first end of the second resistor; the second end of each second resistor is connected with the second node, one end of the second capacitor is connected with the second node, and the other end of the second capacitor is grounded; the drain of the eighth MOS is connected with the drain of the seventh MOS of each second switch control module, the gate of the eighth MOS is connected with the output end of the inverted reference clock signal, and the source of the eighth MOS is grounded; the voltage signal of the second node is a second sampling voltage signal; The second slave sampling circuit comprises a second gate voltage bootstrap switch and a third capacitor; the first end of the second gate voltage bootstrap switch is connected with the second node, and the second end of the second gate voltage bootstrap switch is connected with the third node; the second slave sampling circuit is used for enabling the second gate voltage bootstrap switch to sample the second sampling voltage signal under the control of the second sampling clock signal, and updating the voltage of the third node as a phase error voltage signal corresponding to the second sampling path.

[0007] In an embodiment of the present application, the capacitance value of the first capacitor is 1-2 pF, and the capacitance value of the second capacitor is 1-2 pF.

[0008] In an embodiment of the present application, the ratio of the capacitance value of the first capacitor to the capacitance value of the third capacitor is (3-4):1, and the ratio of the capacitance value of the second capacitor to the capacitance value of the third capacitor is (3-4):1.

[0009] In an embodiment of the present application, the first MOS, the second MOS, the third MOS, the fifth MOS, the sixth MOS and the seventh MOS are all P-type MOS. The fourth MOS and the eighth MOS are both N-type MOS.

[0010] In an embodiment of the present application, the filter comprises a fourth capacitor and a fifth capacitor; One end of the fourth capacitor is connected with the fourth node, and the other end of the fourth capacitor is grounded; the fourth node is connected with the third node and the voltage-controlled oscillator, and is used for inputting a proportional voltage signal to the voltage-controlled oscillator; One end of the fifth capacitor is connected with the fifth node, and the other end of the fifth capacitor is grounded; the fifth node is connected with the output end of the trans-impedance amplifier and the input end of the voltage-controlled oscillator, for inputting the integral voltage signal to the voltage-controlled oscillator; the input end of the trans-impedance amplifier is connected with the output end of the reference voltage and the third node.

[0011] In one embodiment of the present application, the filter further comprises a third resistor, one end of the third resistor is connected with the third node, and the other end of the third resistor is connected with the fourth node.

[0012] In one embodiment of the present application, the stored charge amount of the fifth capacitor is 500-700 coulombs.

[0013] Compared with the prior art, the present application has the following beneficial effects: 1. The phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination provided by the present application generates phase error voltage signals through the first sampling path and the second sampling path alternately sampling, can fully utilize the rising edge and the falling edge of the reference clock signal, generates a control voltage with an update frequency of twice the reference clock signal, and further expands the loop bandwidth of the phase-locked loop and improves the noise suppression capability of the voltage-controlled oscillator.

[0014] 2. The scheme provided by the present application adopts a double-path mode of proportional path and integral path, outputs a proportional voltage signal to the voltage-controlled oscillator through the path to broaden the loop bandwidth, and outputs an integral voltage signal to the voltage-controlled oscillator through the integral path to introduce a pole in the phase-locked loop system to enhance the stability.

[0015] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a circuit schematic diagram of a type II phase-locked loop in the related art; Figure 2 is a circuit schematic diagram of a type I phase-locked loop in the related art; Figure 3 is Figure 2 is a waveform diagram corresponding to the type I phase-locked loop circuit in the present application; Figure 4 is a circuit schematic diagram of a phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination provided by an embodiment of the present application; Figure 5 is Figure 4 is a waveform diagram corresponding to the phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination in the present application.

[0017] MARKED FOR EXPLANATION: Class II PLL: 01 - frequency and phase detector; 02 - charge pump; 03 - loop filter; 04 - voltage controlled oscillator; 05 - feedback divider; Rs - series resistor; C01 - first capacitor; C02 - second capacitor; Class I PLL: 001 - phase detector; 002 - master-slave sampling filter; 003 - voltage controlled oscillator; 004 - feedback divider; 005 - non-overlapping sampling clock generation circuit; CK01 - first sampling clock signal; CK02 - second sampling clock signal; V01 - first voltage signal; V02 - second voltage signal; V03 - third voltage signal; C001 - first capacitor; C002 - second capacitor; S1 - first switch; S2 - second switch; 1 - sampling phase detector; 11 - first gate voltage bootstrap switch; 12 - second gate voltage bootstrap switch; 13 - non-overlapping sampling clock generation circuit; 2 - transconductance amplifier; 3 - filter; 4 - voltage controlled oscillator; 5 - self-timed frequency divider; REF - reference clock signal; FB - feedback clock signal; REFB - inverted reference clock signal; FBB - inverted feedback clock signal; M1 - first MOS transistor; M2 - second MOS transistor; M3 - third MOS transistor; M4 - fourth MOS transistor; M5 - fifth MOS transistor; M6 - sixth MOS transistor; M7 - seventh MOS transistor; M8 - eighth MOS transistor; C1 - first capacitor; C2 - second capacitor; C3 - third capacitor; C4 - fourth capacitor; C5 - fifth capacitor; CK1 - first sampling clock signal; CK2 - second sampling clock signal; N1 - first node; N2 - second node; N3 - third node; N4 - fourth node; N5 - fifth node; R1 - first resistor; R2 - second resistor; R3 - third resistor; EN1 - first enable signal; EN2 - second enable signal; Vref - reference voltage; VI - integral voltage signal; VP - proportional voltage signal; V1 - first sampling voltage signal; V2 - second sampling voltage signal; V3 - phase error voltage signal; V31 - first phase error voltage signal; V32 - second phase error voltage signal. DETAILED DESCRIPTION

[0018] In order to further clarify the technical means and effects taken by the present application to achieve the predetermined purposes, a kind of phase-locked loop system based on high-speed low-jitter double-edge sampling phase detection according to the present application is described in detail below in combination with the specific embodiments and the drawings.

[0019] The foregoing and other technical contents, features and effects of the present application can be clearly presented in the specific embodiment description below in combination with the drawings. Through the description of the specific embodiments, the technical means and effects taken by the present application to achieve the predetermined purposes can be more deeply and specifically understood, however, the attached drawings are only provided for reference and explanation, and are not used to limit the technical solutions of the present application.

[0020] Furthermore, the terms "first", "second", etc. are used herein for descriptive purposes only and are not to be construed as indicating or implying relative importance or an ordered sequence. Accordingly, features identified by "first", "second", etc. can implicitly or explicitly comprise one or more of the features.

[0021] The terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process or method that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process or method.

[0022] In the related art, as shown in Figure 1 The figure shows a schematic diagram of a charge pump type phase-locked loop of the second category; the phase-locked loop comprises a frequency discriminator 01, a charge pump 02, a loop filter 03, a voltage-controlled oscillator 04 and a feedback frequency divider 05. The loop filter 03 comprises a series resistance Rs, a first capacitor C01 and a second capacitor C02, the frequency discriminator 01 is used to detect the phase difference and generate a pulse signal to control the charging and discharging switches of the charge pump 02, the charge pump 02 is controlled by the pulse signal generated by the frequency discriminator 01 to charge the loop filter 03 and further generate the control voltage of the voltage-controlled oscillator 04. When the phase-locked loop is locked, there is no phase error, but due to the limitation of the loop stability, the loop bandwidth of the phase-locked loop of the second category cannot exceed one-tenth of the reference frequency, and the noise suppression ability of the voltage-controlled oscillator 04 is limited. As shown in Figure 2The figure shows a schematic diagram of a class of phase-locked loop; the phase-locked loop includes a phase detector 001, a master-slave sampling filter 002, a voltage-controlled oscillator 003, a feedback frequency divider 004, and a non-overlapping sampling clock generation circuit 005. The non-overlapping sampling clock generation circuit 005 is used to generate a first sampling clock signal CK01 and a second sampling clock signal CK02. The master-slave sampling filter 002 includes a master sampler and a slave sampler. The master sampler includes a first switch S1 and a first capacitor C001, which quickly captures the instantaneous value of the input first voltage signal V01 at the rising edge of the first sampling clock signal CK01 and stores it on the first capacitor C001, so that the voltage at one end of the first capacitor C001 is the second voltage signal V02; the slave sampler includes a second switch S2 and a second capacitor C002, which receives the second voltage signal V02 output by the master sampler and holds the value at the falling edge (or after delay) of the first sampling clock signal CK01, and outputs a third voltage signal V03 to the voltage-controlled oscillator 003. However, when the switch of the master sampler is turned off, due to channel charge injection and clock feedthrough, an error voltage will be introduced on the hold capacitor, resulting in a steady-state error in the voltage signal. The sampling class phase-locked loop solves the problem of the traditional charge pump phase-locked loop, and can still maintain stability with a larger loop bandwidth, but Figure 3 As can be seen, there is still a large phase difference when locked.

[0023] To solve the above problems, the embodiment of the present application provides a phase-locked loop system based on high-speed low-jitter double-edge sampling phase detection, as shown in Figure 4As shown, the phase-locked loop comprises a sampling phase detector 1, a trans-impedance amplifier 2, a filter 3 and a voltage-controlled oscillator 4. The sampling phase detector 1 comprises a first sampling path, a second sampling path and a non-overlapping sampling clock generation circuit 13. The first sampling path is used to sample and output a first phase error voltage signal V31 corresponding to the first sampling path under the control of a reference clock signal REF and a feedback clock signal FB. The second sampling path is used to sample and output a second phase error voltage signal V32 corresponding to the second sampling path under the control of an inverted reference clock signal REFB and an inverted feedback clock signal FBB. The non-overlapping sampling clock generation circuit 13 is used to generate a first sampling clock signal CK1 and a second sampling clock signal CK2 that do not overlap with each other to control the first sampling path and the second sampling path to sample. The first phase error voltage signal V31 and the second phase error voltage signal V32 are used to alternately update a phase error voltage signal V3. The trans-impedance amplifier 2 is used to receive the phase error voltage signal V3 and a reference voltage, convert a voltage difference between the phase error voltage signal V3 and the reference voltage Vref into a current signal and input the current signal into the filter 3 to obtain an integral voltage signal VI. The filter 3 is used to receive the phase error voltage signal V3 and filter out a reference frequency ripple of the phase error voltage signal V3 to output a proportional voltage signal Vp. The reference frequency ripple is a component of periodic fluctuation on the phase error voltage signal. The voltage-controlled oscillator 4 is used to adjust an output frequency under the control of receiving the integral voltage signal VI and the proportional voltage signal Vp and output the feedback clock signal FB.

[0024] That is, in the sampling phase detector 1, the first sampling path responds to rising edges and falling edges of the reference clock signal REF and the feedback clock signal FB, the second sampling path responds to rising edges and falling edges of the inverted reference clock signal REFB and the inverted feedback clock signal FBB, and the two paths can alternately sample and update the phase error voltage signal V3 respectively. In this way, the rising edges and the falling edges of the reference clock signal REF can be fully utilized to generate a control voltage with an update frequency twice that of the reference clock signal REF, thereby expanding the loop bandwidth of the phase-locked loop and improving the noise suppression capability of the voltage-controlled oscillator.

[0025] In addition, the scheme provided by the present application adopts a double-path mode of a proportional path and an integral path, outputs the proportional voltage signal Vp to the voltage-controlled oscillator 4 through the path to expand the loop bandwidth, and outputs the integral voltage signal VI to the voltage-controlled oscillator 4 through the integral path to introduce a pole in the phase-locked loop system to enhance stability.

[0026] For example, the voltage-controlled oscillator 4 outputs a feedback clock signal FB and an inverted feedback clock signal FBB through the self-timed frequency divider 5, which are input into the two middle sampling paths of the sampling phase detector 1 and also input into the non-overlapping sampling clock generation circuit 13 (not shown in the figure). Figure 4 Similarly, the reference clock signal REF and the inverted reference clock signal REFB are input into the two middle sampling paths of the sampling phase detector 1 and also input into the non-overlapping sampling clock generation circuit 13 (not shown in the figure). Figure 4

[0027] In an embodiment of the present application, the first sampling path comprises a first main sampling circuit and a first slave sampling circuit.

[0028] The first main sampling circuit comprises a first capacitor C1, a fourth MOS transistor M4, and a plurality of first switch control modules connected in parallel, each of which comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, and a first resistor R1. The source of the first MOS transistor M1 is connected to a power supply, the drain of the first MOS transistor M1 is connected to the source of the second MOS transistor M2, and the gate of the first MOS transistor M1 is connected to the output terminal of a first enable signal EN1; the gate of the second MOS transistor M2 is connected to the output terminal of a reference clock signal REF, the drain of the second MOS transistor M2 is connected to the source of the third MOS transistor M3; the gate of the third MOS transistor M3 is connected to the output terminal of a feedback clock signal FB, and the drain of the third MOS transistor M3 is connected to the first terminal of the first resistor R1; the second terminal of each first resistor R1 is connected to a first node N1, one end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is grounded; the drain of the fourth MOS transistor M4 is connected to the drain of the third MOS transistor M3 of each first switch control module, the gate of the fourth MOS transistor M4 is connected to the output terminal of the reference clock signal REF, and the source of the fourth MOS transistor M4 is grounded; and the voltage of the first node N1 is a first sampling voltage signal V1.

[0029] In this embodiment, the first resistor R1 and the first capacitor C1 in each first switch control module form a first RC circuit, which allows the output first voltage to be slowly charged to the first capacitor C1 through the first node N1 to control the slope, and at the same time, prevents the clock signal (the reference clock signal REF and the feedback clock signal FB) from being directly fed through to the first capacitor C1 to prevent the waveform of the rising edge or the falling edge from having a "spike". In this way, the combination of the first RC circuit (slope generator circuit) and the phase detector forms a sampling phase detector 1 with simple structure, small area occupation, and convenience for phase-locked loop integration.

[0030] ​The first slave sampling circuit comprises a first gate voltage bootstrap switch 11 and a third capacitor C3; a first end of the first gate voltage bootstrap switch 11 is connected with the first node N1, a second end of the first gate voltage bootstrap switch 11 is connected with the third node N3, one end of the third capacitor C3 is connected with the third node N3, and the other end of the third capacitor C3 is grounded. The first slave sampling circuit is used for enabling the first sampling clock signal CK1 to control the first gate voltage bootstrap switch 11 to sample the first sampling voltage signal V1, and updating the voltage of the third node N3 as the first phase error voltage signal V31 corresponding to the first sampling path. In this way, the sampling phase detector 1 is combined with the gate voltage bootstrap switch, and the sampling precision and linearity are improved.

[0031] Exemplarily, the first MOS tube M1, the second MOS tube M2 and the third MOS tube M3 are P-type MOS tubes, and the fourth MOS tube M4 is an N-type MOS tube.

[0032] Exemplarily, the capacitance value of the first capacitor C1 is 1-2 pF.

[0033] In an embodiment of the present application, the second sampling path comprises a second main sampling circuit and a second slave sampling circuit. The second main sampling circuit comprises a second capacitor C2, an eighth MOS tube M8 and a plurality of second switch control modules connected in parallel, each second switch control module comprising a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7 and a second resistor R2.

[0034] The source of the fifth MOS tube M5 is connected with a power supply, the drain of the fifth MOS tube M5 is connected with the source of the sixth MOS tube M6, and the gate of the fifth MOS tube M5 is connected with the output end of the second enable signal EN2; the gate of the sixth MOS tube M6 is connected with the output end of the inverted reference clock signal REFB, the drain of the sixth MOS tube M6 is connected with the source of the seventh MOS tube M7; the gate of the seventh MOS tube M7 is connected with the output end of the inverted feedback clock signal FBB, and the drain of the seventh MOS tube M7 is connected with the first end of the second resistor R2; the second end of each second resistor R2 is connected with the second node N2, one end of the second capacitor C2 is connected with the second node N2, and the other end of the second capacitor C2 is grounded; the drain of the eighth MOS tube M8 is connected with the drain of the seventh MOS tube M7 of each second switch control module, the gate of the eighth MOS tube M8 is connected with the output end of the inverted reference clock signal REFB, and the source of the eighth MOS tube M8 is grounded; the voltage of the second node N2 is the second sampling voltage signal V2.

[0035] In this embodiment, the second resistance R2 and the second capacitor C2 in each second switch control module form a second RC circuit, which enables the output second sampling voltage signal V2 to be slowly charged to the second capacitor C2 through the second node N2, controls the slope, and prevents the clock signal (inverted reference clock signal REFB and inverted feedback clock signal FBB) from being directly fed to the second capacitor C2.

[0036] The second slave sampling circuit includes a second gate voltage bootstrap switch 12 and a third capacitor C3. The first end of the second gate voltage bootstrap switch 12 is connected with the second node N2, and the second end of the second gate voltage bootstrap switch 12 is connected with the third node N3. The second slave sampling circuit is used to enable the second sampling clock signal CK2 to control the second gate voltage bootstrap switch 12 to sample the second sampling voltage signal V2, and update the voltage of the third node N3 to be the second phase error voltage signal V32 corresponding to the second sampling path. In the first slave sampling circuit and the second slave sampling circuit, the third capacitor C3 is a shared capacitor of the two circuits. When the first slave sampling circuit samples, the first gate voltage bootstrap switch 11 and the third capacitor C3 work; when the second slave sampling circuit samples, the second gate voltage bootstrap switch 12 and the third capacitor C3 work.

[0037] In an example, the fifth MOS transistor M5, the sixth MOS transistor M6 and the seventh MOS transistor M7 are P-type MOS transistors, and the eighth MOS transistor M8 is an N-type MOS transistor.

[0038] In an example, the capacitance value of the second capacitor C2 is 1-2 pF. It can be understood that the first capacitor C1 and the second capacitor C2 can be equal or not equal.

[0039] In an example, the ratio of the capacitance value of the first capacitor C1 to the capacitance value of the third capacitor C3 is (3-4):1. Similarly, the ratio of the capacitance value of the second capacitor C2 to the capacitance value of the third capacitor C3 is (3-4):1. That is, the third capacitor C3 can be selected according to the first capacitor C1 or the second capacitor C2.

[0040] Referring to Figure 4 and Figure 5 , the working process of the phase-locked loop based on double-edge sampling phase discrimination provided by the application is that: when the enable signal EN is at a low level, the sampling phase discriminator 1 is in a working state. In the initial stage, when the feedback clock signal FB is at a low level and the reference clock signal REF is at a high level, the second MOS transistor M2 is disconnected, the first MOS transistor M1, the third MOS transistor M3 and the fourth MOS transistor M4 are turned on, at this time, the first capacitor C1 only has a discharge path to the ground, and the first sampling voltage signal V1 is at a low level.

[0041] When the reference clock signal REF changes from high level to low level, the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 are turned on, and the fourth MOS transistor M4 is turned off. At this time, the first capacitor C1 only has a discharge path to the ground, and the first sampling voltage signal V1 is discharged to a low potential. Then, the feedback clock signal FB changes from high level to low level, and the first sampling path of the sampling phase detector 1 waits for the next working period. Meanwhile, when the inverted reference clock signal REFB changes from high level to low level, the fifth MOS transistor M5, the sixth MOS transistor M6, and the seventh MOS transistor M7 are turned on, and the eighth MOS transistor M8 is turned off. At this time, only the second capacitor C2 has a charging path to the power supply, and the second sampling voltage signal V2 continuously rises. Until the inverted feedback clock signal FBB changes from low level to high level, the fifth MOS transistor M5, the sixth MOS transistor M6 are turned on, and the seventh MOS transistor M7 and the eighth MOS transistor M8 are turned off. The second capacitor C2 keeps the same potential, and the inverted feedback clock signal FBB signal passes through the non-overlapping sampling clock generation circuit 13 to generate the second sampling clock signal CK2. The second sampling clock signal CK2 controls the gate voltage boost switch to resample the second sampling voltage signal V2 to the third capacitor C3, and updates the phase error voltage signal V3. When the inverted reference clock signal REFB changes from low level to high level, the fifth MOS transistor M5 and the eighth MOS transistor M8 are turned on, and the sixth MOS transistor M6 and the seventh MOS transistor M7 are turned off. At this time, the second capacitor C2 only has a discharge path to the ground, and the second sampling voltage signal V2 is discharged to a low potential. Then, the inverted feedback clock signal FBB changes from high level to low level, and the second sampling path of the sampling phase detector 1 waits for the next working period. Therefore, the first sampling path and the second sampling path alternately update the phase error voltage signal V3 in one period of the reference clock signal REF, so that the update speed of the control signal of the voltage-controlled oscillator 4 is twice the frequency of the reference clock signal REF, and the loop bandwidth is expanded.

[0042] When the reference clock signal REF changes from low level to high level, the first MOS transistor M1, the fourth MOS transistor M4 are turned on, and the second MOS transistor M2 and the third MOS transistor M3 are turned off. At this time, the first capacitor C1 only has a discharge path to the ground, and the first sampling voltage signal V1 is discharged to a low potential. Then, the feedback clock signal FB changes from high level to low level, and the first sampling path of the sampling phase detector 1 waits for the next working period. Meanwhile, when the inverted reference clock signal REFB changes from high level to low level, the fifth MOS transistor M5, the sixth MOS transistor M6, and the seventh MOS transistor M7 are turned on, and the eighth MOS transistor M8 is turned off. At this time, only the second capacitor C2 has a charging path to the power supply, and the second sampling voltage signal V2 continuously rises. Until the inverted feedback clock signal FBB changes from low level to high level, the fifth MOS transistor M5, the sixth MOS transistor M6 are turned on, and the seventh MOS transistor M7 and the eighth MOS transistor M8 are turned off. The second capacitor C2 keeps the same potential, and the inverted feedback clock signal FBB signal passes through the non-overlapping sampling clock generation circuit 13 to generate the second sampling clock signal CK2. The second sampling clock signal CK2 controls the gate voltage boost switch to resample the second sampling voltage signal V2 to the third capacitor C3, and updates the phase error voltage signal V3. When the inverted reference clock signal REFB changes from low level to high level, the fifth MOS transistor M5 and the eighth MOS transistor M8 are turned on, and the sixth MOS transistor M6 and the seventh MOS transistor M7 are turned off. At this time, the second capacitor C2 only has a discharge path to the ground, and the second sampling voltage signal V2 is discharged to a low potential. Then, the inverted feedback clock signal FBB changes from high level to low level, and the second sampling path of the sampling phase detector 1 waits for the next working period. Therefore, the first sampling path and the second sampling path alternately update the phase error voltage signal V3 in one period of the reference clock signal REF, so that the update speed of the control signal of the voltage-controlled oscillator 4 is twice the frequency of the reference clock signal REF, and the loop bandwidth is expanded.

[0043] In one embodiment of the present application, the filter 3 comprises a fourth capacitor C4 and a fifth capacitor C5. One end of the fourth capacitor C4 is connected to the fourth node N4, and the other end of the fourth capacitor C4 is grounded. The fourth node N4 is connected to the third node N3 and the voltage-controlled oscillator 4, for inputting the proportional voltage signal Vp to the voltage-controlled oscillator 4. One end of the fifth capacitor C5 is connected to the fifth node N5, and the other end of the fifth capacitor C5 is grounded. The fifth node N5 is connected to the output of the trans-impedance amplifier 2 and the input of the voltage-controlled oscillator 4, for inputting the integral voltage signal VI to the voltage-controlled oscillator 4. The input of the trans-impedance amplifier 2 is connected to the output of the reference voltage Vref and the third node N3. In one example, the filter 3 further comprises a third resistor R3, one end of the third resistor R3 is connected to the third node N3, and the other end of the third resistor R3 is connected to the fourth node N4.

[0044] In this embodiment, the third resistor R3 and the fourth capacitor C4 constitute a proportional path, and the phase error voltage signal V3 output by the sampling phase detector 1 is taken as the control voltage (proportional voltage signal VP) of the proportional path. The output of the reference voltage Vref and the output of the phase error voltage signal V3 are connected to the input of the trans-impedance amplifier 2, and in combination with the fifth capacitor C5, form an integral path, and output the control voltage (integral voltage signal VI) of the integral path. In the integral path, the trans-impedance amplifier 2 converts the voltage difference between the reference voltage Vref and the phase error voltage signal V3 into a current signal, which is transmitted to the fifth capacitor C5 to form the integral voltage signal VI, which is input to the voltage-controlled oscillator 4 as one control voltage signal of the voltage-controlled oscillator 4. The integral path plays a role of clamping the direct current level of the phase error voltage signal V3 on one hand, so that the gain of the proportional path voltage-controlled oscillator 4 is in a region with good linearity, and on the other hand, also introduces a pole in the loop of the phase-locked loop, so that the loop is more stable.

[0045] For example, the stored charge amount of the fifth capacitor C5 is 500-700 coulombs.

[0046] The above is a further detailed description of the present application in combination with specific preferred embodiments, and the specific implementation of the present application should not be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the protection scope of the present application.

Claims

1. A phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination, characterized in that, The sampling phase detector (1), the trans-impedance amplifier (2), the filter (3) and the voltage-controlled oscillator (4) are included. The sampling phase detector (1) includes a first sampling path, a second sampling path and a non-overlapping sampling clock generation circuit (13); the first sampling path is used for sampling and outputting a first phase error voltage signal (V31) corresponding to the first sampling path under the control of a reference clock signal (REF) and a feedback clock signal (FB); the second sampling path is used for sampling and outputting a second phase error voltage signal (V32) corresponding to the second sampling path under the control of an inverted reference clock signal (REFB) and an inverted feedback clock signal (FBB); the non-overlapping sampling clock generation circuit (13) is used for generating a first sampling clock signal (CK1) and a second sampling clock signal (CK2) that do not overlap with each other to control the first sampling path and the second sampling path to sample; the first phase error voltage signal (V31) and the second phase error voltage signal (V32) are used for alternately updating a phase error voltage signal (V3); The trans-impedance amplifier (2) is used for receiving the phase error voltage signal (V3) and a reference voltage (Vref), converting a voltage difference between the phase error voltage signal (V3) and the reference voltage (Vref) into a current signal and inputting the current signal into the filter (3) to output an integral voltage signal (VI); The filter (3) is also used for receiving the phase error voltage signal (V3) and filtering out a reference frequency ripple of the phase error voltage signal (V3) to output a proportional voltage signal (Vp); The voltage-controlled oscillator (4) is used for adjusting an output frequency under the control of the integral voltage signal (VI) and the proportional voltage signal (Vp) and outputting the feedback clock signal.

2. The phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination of claim 1, wherein, The first sampling path includes a first main sampling circuit and a first slave sampling circuit. The first main sampling circuit includes a first capacitor (C1), a fourth MOS tube (M4) and a plurality of first switch control modules connected in parallel, each first switch control module including a first MOS tube (M1), a second MOS tube (M2), a third MOS tube (M3) and a first resistor (R1); The source of the first MOS transistor (M1) is connected with a power supply, the drain of the first MOS transistor (M1) is connected with the source of a second MOS transistor (M2), the gate of the first MOS transistor (M1) is connected with the output terminal of a first enable signal (EN1); the gate of the second MOS transistor (M2) is connected with the output terminal of a reference clock signal (REF), the drain of the second MOS transistor (M2) is connected with the source of a third MOS transistor (M3); the gate of the third MOS transistor (M3) is connected with the output terminal of a feedback clock signal (FB), the drain of the third MOS transistor (M3) is connected with the first terminal of a first resistor (R1); the second terminal of each first resistor (R1) is connected with a first node (N1), one end of a first capacitor (C1) is connected with the first node (N1), and the other end of the first capacitor (C1) is grounded; the drain of a fourth MOS transistor (M4) is connected with the drain of the third MOS transistor (M3) of each first switch control module, the gate of the fourth MOS transistor (M4) is connected with the output terminal of the reference clock signal (REF), and the source of the fourth MOS transistor (M4) is grounded; the voltage signal of the first node (N1) is a first sampling voltage signal (V1); The first slave sampling circuit comprises a first gate voltage bootstrap switch (11) and a third capacitor (C3); the first end of the first gate voltage bootstrap switch (11) is connected with the first node (N1), the second end of the first gate voltage bootstrap switch (11) is connected with a third node (N3), one end of the third capacitor (C3) is connected with the third node (N3), and the other end of the third capacitor (C3) is grounded; the first slave sampling circuit is used for enabling the first gate voltage bootstrap switch (11) to sample the first sampling voltage signal (V1) under the control of a first sampling clock signal (CK1), and updating the voltage of the third node (N3) as a phase error voltage signal (V3) corresponding to a first sampling path.

3. The phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination of claim 2, wherein, The second sampling path comprises a second main sampling circuit and a second slave sampling circuit; The second main sampling circuit comprises a second capacitor (C2), an eighth MOS transistor (M8) and a plurality of parallel-connected second switch control modules, each second switch control module comprises a fifth MOS transistor (M5), a sixth MOS transistor (M6), a seventh MOS transistor (M7) and a second resistor (R2); A source of the fifth MOS transistor (M5) is connected with a power supply, a drain of the fifth MOS transistor (M5) is connected with a source of a sixth MOS transistor (M6), a gate of the fifth MOS transistor (M5) is connected with an output terminal of a second enable signal (EN2); a gate of the sixth MOS transistor (M6) is connected with an output terminal of an inverted reference clock signal (REFB), a drain of the sixth MOS transistor (M6) is connected with a source of a seventh MOS transistor (M7); a gate of the seventh MOS transistor (M7) is connected with an output terminal of an inverted feedback clock signal (FBB), a drain of the seventh MOS transistor (M7) is connected with a first terminal of the second resistor (R2); a second terminal of each of the second resistors (R2) is connected with a second node (N2), one end of the second capacitor (C2) is connected with the second node (N2), and the other end of the second capacitor (C2) is grounded; a drain of the eighth MOS transistor (M8) is connected with a drain of the seventh MOS transistor (M7) of each second switch control module, a gate of the eighth MOS transistor (M8) is connected with an output terminal of the inverted reference clock signal (REFB), and a source of the eighth MOS transistor (M8) is grounded; a voltage signal of the second node (N2) is a second sampling voltage signal (V2); The second slave sampling circuit comprises a second gate voltage bootstrap switch (12) and the third capacitor (C3); a first end of the second gate voltage bootstrap switch (12) is connected with the second node (N2), and a second end of the second gate voltage bootstrap switch (12) is connected with a third node (N3); the second slave sampling circuit is used for enabling the second gate voltage bootstrap switch (12) to sample the second sampling voltage signal (V2) under the control of a second sampling clock signal (CK2), and updating a voltage of the third node (N3) as a phase error voltage signal (V3) corresponding to a second sampling path.

4. The phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination of claim 3, wherein, The first capacitor (C1) has a capacitance value of 1-2 pF, and the second capacitor (C2) has a capacitance value of 1-2 pF.

5. The phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination of claim 3, wherein, The ratio of the capacitance value of the first capacitor (C1) to the capacitance value of the third capacitor (C3) is (3-4):1, and the ratio of the capacitance value of the second capacitor (C2) to the capacitance value of the third capacitor (C3) is (3-4):

1.

6. The phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination of claim 3, wherein, The first MOS transistor (M1), the second MOS transistor (M2), the third MOS transistor (M3), the fifth MOS transistor (M5), the sixth MOS transistor (M6) and the seventh MOS transistor (M7) are all P-type MOS transistors. The fourth MOS transistor (M4) and the eighth MOS transistor (M8) are both N-type MOS transistors.

7. The phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination of claim 3, wherein, The filter (3) comprises a fourth capacitor (C4) and a fifth capacitor (C5); One end of the fourth capacitor (C4) is connected with a fourth node (N4), and the other end of the fourth capacitor (C4) is grounded; the fourth node (N4) is connected with the third node (N3) and the voltage-controlled oscillator, and is used for inputting a proportional voltage signal (Vp) to the voltage-controlled oscillator; One end of the fifth capacitor (C5) is connected with the fifth node (N5), and the other end of the fifth capacitor (C5) is grounded; the fifth node (N5) is connected with the output end of the trans-impedance amplifier (2) and the input end of the voltage-controlled oscillator, for inputting the integral voltage signal (VI) to the voltage-controlled oscillator; the input end of the trans-impedance amplifier (2) is connected with the output end of the reference voltage (Vref) and the third node (N3).

8. The phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination of claim 7, wherein, The filter (3) further comprises a third resistor (R3), one end of the third resistor (R3) is connected with the third node (N3), and the other end of the third resistor (R3) is connected with the fourth node (N4).

9. The phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination of claim 8, wherein, The stored charge amount of the fifth capacitor (C5) is 500-700 coulombs.

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