Techniques for providing efficient access to a pooled accelerator device

Abstract

A technique for providing efficient access to a pooled accelerator device includes an accelerator sled. The accelerator sled includes an accelerator device and a controller connected to the accelerator device. The controller provides accelerator abstraction data to the compute sled. The accelerator abstraction data represents the accelerator device as one or more logical devices, each of which has one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region. The controller further receives a request from the compute sled to perform an operation on an identified memory region of the accelerator device using a corresponding access mode. Furthermore, the controller converts the request from a first format to a second format, the first format being different from the second format and usable by the accelerator device to perform the operation. Furthermore, the controller performs the operation on the identified memory region of the accelerator device using the corresponding access mode in response to the request. Other embodiments are also described and claimed.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Indian Provisional Patent Application No. 201741030632, filed on August 30, 2017, and U.S. Provisional Patent Application No. 62 / 584,401, filed on November 10, 2017. Background Art

[0003] Accelerator devices (such as field-programmable gate arrays (FPGAs) or other devices capable of accelerating the execution of functions) are typically attached directly to a central processing unit (CPU) using high-speed interconnects (e.g., PCI Express, RLink, etc.). However, in some data centers, accelerator devices may be decoupled from hosts (e.g., computing devices executing applications that may periodically request acceleration of functions), allowing applications executing on a large number of hosts to access the accelerator devices on demand. There are many application frameworks and applications with customized stacks for accessing accelerator devices. In addition, the use of accelerator devices by applications can vary from using a single accelerator device to using multiple accelerator devices simultaneously. The wide range of application programming models, frameworks, and protocols for accessing accelerator devices often results in a significant amount of available capacity (e.g., logic gates, processing cycles, etc.) of each accelerator device being dedicated to managing communications with the hosts (e.g., parsing requests submitted in various protocols), when this capacity might otherwise be allocated to accelerating functions on behalf of the hosts in the data center. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The concepts described herein are illustrated in the accompanying drawings by way of example and not limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. Where appropriate, reference numerals have been repeated between the figures to indicate corresponding or similar elements.

[0005] Figure 1 is a simplified block diagram of at least one embodiment of a data center executing workloads with disaggregated resources;

[0006] Figure 2 yes Figure 1 A simplified block diagram of at least one embodiment of a pod for a data center;

[0007] Figure 3 can be included in Figure 2 A perspective view of at least one embodiment of a bracket in a compartment;

[0008] Figure 4 yes Figure 3 A side plane elevation view of the bracket;

[0009] Figure 5 It is the one with the sled installed. Figure 3 Perspective view of the bracket;

[0010] Figure 6 yes Figure 5 A simplified block diagram of at least one embodiment of a top side of a sled;

[0011] Figure 7 yes Figure 6 A simplified block diagram of at least one embodiment of a bottom side of a sled;

[0012] Figure 8 Available in Figure 1 A simplified block diagram of at least one embodiment of a computing sled in a data center;

[0013] Figure 9 yes Figure 8 A top perspective view of at least one embodiment of a computing sled;

[0014] Figure 10 Available in Figure 1 A simplified block diagram of at least one embodiment of an accelerator sled in a data center;

[0015] Figure 11 yes Figure 10 A top perspective view of at least one embodiment of an accelerator skid;

[0016] Figure 12 Available in Figure 1 A simplified block diagram of at least one embodiment of a storage device sled in a data center;

[0017] Figure 13 yes Figure 12 a top perspective view of at least one embodiment of a storage device skid;

[0018] Figure 14 Available in Figure 1 A simplified block diagram of at least one embodiment of a storage sled in a data center; and

[0019] Figure 15 It is available in Figure 1 A simplified block diagram of a system established within a data center for executing workloads using managed nodes consisting of disaggregated resources.

[0020] Figure 16 is a simplified block diagram of at least one embodiment of a system for providing efficient pooling of accelerator devices;

[0021] Figure 17 yes Figure 16 A simplified block diagram of at least one embodiment of an accelerator skid of a system;

[0022] Figure 18 Can be Figure 16 and 17 A simplified block diagram of at least one embodiment of an environment established by an accelerator sled; and

[0023] Figure 19-22 Can be Figure 16 and Figure 17 A simplified flow chart of at least one embodiment of a method performed by an accelerator sled for providing efficient pooling of accelerator devices. DETAILED DESCRIPTION

[0024] While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown as examples in the drawings and will be described in detail herein. However, it should be understood that there is no intention to limit the concepts of the present disclosure to the specific forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.

[0025] References in the specification to "one embodiment," "an embodiment," "illustrative embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with one embodiment, it is considered within the knowledge of one skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described. Furthermore, it should be understood that items included in a list of the form "at least one of A, B, and C" can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items included in a list of the form "at least one of A, B, or C" can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

[0026] The disclosed embodiments may, in some cases, be implemented using hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a volatile or non-volatile machine-readable (e.g., computer-readable) storage medium, which instructions may be read and executed by one or more processors. A machine-readable storage medium may be implemented as any storage device, mechanism, or other physical structure (e.g., a volatile or non-volatile memory, a media disk, or other media device) for storing or transmitting information in a machine-readable form.

[0027] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be appreciated that such specific arrangement and / or order may not be required. Rather, in some embodiments, such features may be arranged in a manner and / or order different from that shown in the illustrative figures. Furthermore, the inclusion of structural or method features in a particular figure is not intended to imply that such features are required in all embodiments, and in some embodiments, such features may not be included or may be combined with other features.

[0028] Now refer to Figure 1 A data center 100, in which disaggregated resources can collaborate to execute one or more workloads (e.g., applications on behalf of customers), includes a plurality of pods 110, 120, 130, 140, each of which includes one or more rows of racks. As described in more detail herein, each rack houses a plurality of sleds, each of which can be implemented as a computing device (such as a server) primarily equipped with a specific type of resource (e.g., memory devices, data storage devices, accelerator devices, general-purpose processors). In an illustrative embodiment, the sleds in each pod 110, 120, 130, 140 are connected to a plurality of pod switches (e.g., switches that route data communications to and from the sleds within the pod). The pod switches, in turn, are connected to a spine switch 150, which switches communications among the pods (e.g., pods 110, 120, 130, 140) in the data center 100. In some embodiments, the sleds can be connected to the fabric using Intel Omni-Path Technology. As described in more detail herein, resources within a sled in a data center 100 can be assigned to a group (referred to herein as a "managed node") containing resources from one or more other sleds to be utilized together in the execution of a workload. Workloads can be executed as if the resources belonging to the managed nodes were located on the same sled. Resources in a managed node can even be attributed to sleds belonging to different racks and even to different pods 110, 120, 130, 140. Certain resources of a single sled can be assigned to one managed node, while other resources of the same sled are assigned to a different managed node (e.g., one processor assigned to one managed node and another processor of the same sled assigned to a different managed node). By disaggregating resources into sleds primarily consisting of a single type of resource (e.g., a compute sled primarily consisting of compute resources, a memory sled primarily consisting of memory resources), and selectively allocating and de-allocating the disaggregated resources to form nodes assigned to perform workload management, data center 100 provides more efficient resource utilization compared to a typical data center consisting of hyper-converged servers containing compute, memory, storage, and possibly additional resources. Consequently, data center 100 can provide better performance (e.g., throughput, operations per second, latency, etc.) than a typical data center with the same number of resources.

[0029] Now refer to Figure 2 In the illustrated embodiment, pod 110 includes a collection of rows 200, 210, 220, and 230 of racks 240. As described in greater detail herein, each rack 240 can accommodate multiple sleds (e.g., 16 sleds) and provide power and data connectivity to the accommodated sleds. In the illustrated embodiment, the racks in each row 200, 210, 220, and 230 are connected to a plurality of pod switches 250 and 260. Pod switches 250 include a set of ports 252 to which the sleds of the racks of pod 110 connect, and another set of ports 254 that connect pod 110 to the spine switch 150 to provide connectivity to other pods in data center 100. Similarly, pod switches 260 include a set of ports 262 to which the sleds of the racks of pod 110 connect, and another set of ports 264 that connect pod 110 to the spine switch 150. Thus, the use of these pairs of switches 250 and 260 provides a significant amount of redundancy for pod 110. For example, if either of the switches 250, 260 fails, the sled in the bay 110 can still maintain data communications with the rest of the data center 100 (e.g., sleds in other bays) via the other switch 250, 260. Additionally, in the illustrative embodiment, the switches 150, 250, 260 can be implemented as dual-mode optical switches capable of routing both Internet Protocol (IP) communications carrying Internet Protocol (IP) packets and communications according to a second, high-performance link layer protocol (e.g., Intel's Omni-Path Architecture, InfinityBand) via the optical signaling medium of optical fiber.

[0030] It should be appreciated that each of the other bays 120, 130, 140 (as well as any additional bays of the data center 100) may be similarly structured to be Figure 2 As shown in and about Figure 2 The pods 110 are similar to those depicted and have components similar to those of pod 110 (e.g., each pod may have a row of brackets that accommodate multiple skids as described above). Furthermore, while two pod switches 250, 260 are shown, it should be understood that in other embodiments, each pod 110, 120, 130, 140 may be connected to a different number of pod switches (e.g., to provide even more failover capabilities).

[0031] Now refer to Figure 3-5 Each illustrative rack 240 of the data center 100 includes two elongated legs 302, 304 arranged vertically. For example, the elongated legs 302, 304 may extend upward from the floor of the data center 100 when deployed. As described below, the rack 240 also includes one or more pairs 310 of horizontally extending arms 312 (in the example shown) configured to support the data center 100 skid. Figure 3). One extended arm 312 of the pair of extended arms 312 extends outwardly from the extended support post 302 , and the other extended arm 312 extends outwardly from the extended support post 304 .

[0032] In the illustrative embodiment, each sled in the data center 100 is shown as a chassisless sled. That is, each sled has a chassisless circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage devices, etc.) are mounted, as discussed in more detail below. Accordingly, the bracket 240 is configured to receive a chassisless sled. For example, each pair 310 of extended arms 312 defines a sled slot 320 of the bracket 240 that is configured to receive a corresponding chassisless sled. To do so, each illustrative extended arm 312 includes a circuit board rail 330 configured to receive the sled's chassisless circuit board substrate. Each circuit board rail 330 is secured to or otherwise mounted to the top side 332 of the corresponding extended arm 312. For example, in the illustrative embodiment, each circuit board rail 330 is mounted at the distal end of the corresponding extended arm 312 relative to the corresponding extended support column 302, 304. For clarity of the figures, not every circuit board rail 330 may be referenced in every figure.

[0033] Each circuit board rail 330 includes inner walls that define a circuit board slot 380 configured to receive a chassis-less circuit board substrate of the sled 400 when the sled 400 is received in the corresponding sled slot 320 of the bracket 240. To do so, Figure 4 As shown in FIG, a user (or robot) aligns the chassis-less circuit board substrate of the illustrative chassis-less sled 400 with the sled slot 320. The user or robot can then slide the chassis-less circuit board substrate forward into the sled slot 320 such that each side edge 414 of the chassis-less circuit board substrate is received in a corresponding circuit board slot 380 of the circuit board guides 330 of the pair 310 of extended arms 312 defining the corresponding sled slot 320, as shown in FIG. Figure 4 . By having a robotically accessible and robotically manipulable sled that includes disaggregated resources, each type of resource can be upgraded independently of each other and at its own optimal refresh rate. Additionally, the sled is configured to blindly mate with the power and data communication cables in each rack 240, enhancing their ability to be quickly removed, upgraded, reinstalled, and / or replaced. Thus, in some embodiments, the data center 100 can operate (e.g., perform workloads, undergo maintenance and / or upgrades, etc.) without human involvement on the data center floor. In other embodiments, a human can facilitate one or more maintenance or upgrade operations in the data center 100.

[0034] It should be appreciated that each circuit board guide 330 is double-sided. That is, each circuit board guide 330 includes inner walls that define a circuit board slot 380 on each side of the circuit board guide 330. In this manner, each circuit board guide 330 can support a chassis-less circuit board substrate on each side. Thus, a single additional extended leg can be added to the bracket 240 to convert the bracket 240 into a dual bracket solution, which can accommodate a plurality of skid slots 320. Figure 3 The illustrative rack 240 includes seven pairs 310 of extended arms 312, which define seven corresponding sled slots 320, each configured to receive and support a corresponding sled 400, as discussed above. Of course, in other embodiments, the rack 240 may include additional or fewer pairs 310 of extended arms 312 (i.e., additional or fewer sled slots 320). It should be appreciated that because the sled 400 is chassisless, the sled 400 may have an overall height that differs from a typical server. Therefore, in some embodiments, the height of each sled slot 320 may be shorter than the height of a typical server (e.g., shorter than a single row unit "1U"). That is, the vertical distance between each pair 310 of extended arms 312 may be less than a standard rack unit "1U." Furthermore, due to the relative reduction in the height of the sled slots 320, the overall height of the rack 240 may, in some embodiments, be shorter than the height of a conventional rack housing. For example, in some embodiments, each of the extended legs 302, 304 may have a length of six feet or less. Furthermore, in other embodiments, the rack 240 may have different dimensions. Furthermore, it should be appreciated that the rack 240 does not include any walls, enclosures, or the like. Furthermore, the rack 240 is an enclosure-free rack that is open to the local environment. Of course, in some cases, such as those where the rack 240 forms an end-of-row rack in the data center 100, an end plate may be attached to one of the extended legs 302, 304.

[0035] In some embodiments, various interconnects can be routed upward or downward through the extended legs 302, 304. To facilitate such routing, each extended leg 302, 304 includes interior walls defining an interior cavity in which the interconnects can be positioned. The interconnects routed through the extended legs 302, 304 can be implemented as any type of interconnect, including, but not limited to, data or communication interconnects that provide a communication connection to each sled slot 320, power interconnects that provide power to each sled slot 320, and / or other types of interconnects.

[0036] In the illustrative embodiment, the rack 240 includes a support platform on which corresponding optical data connectors (not shown) are mounted. Each optical data connector is associated with a corresponding sled slot 320 and is configured to mate with the optical data connector of the corresponding sled 400 when the sled 400 is received in the corresponding sled slot 320. In some embodiments, optical connections between components in the data center 100 (e.g., sleds, racks, and switches) are made using blind-mate optical connections. For example, a door on each cable can prevent dust from contaminating the optical fibers inside the cable. During connection to the blind-mate optical connector mechanism, the door is pushed open as the cable end enters the connector mechanism. Subsequently, the optical fibers inside the cable enter the gel within the connector mechanism, and the optical fibers of one cable come into contact with the optical fibers of the other cable within the gel within the connector mechanism.

[0037] The illustrative rack 240 also includes a fan array 370 coupled to the cross arms of the rack 240. The fan array 370 includes one or more rows of cooling fans 372 aligned in a horizontal line between the extended legs 302, 304. In the illustrative embodiment, the fan array 370 includes one row of cooling fans 372 for each sled slot 320 of the rack 240. As discussed above, in the illustrative embodiment, each sled 400 does not include any onboard cooling system, and therefore, the fan array 370 provides cooling for each sled 400 received in the rack 240. In the illustrative embodiment, each rack 240 also includes a power supply associated with each sled slot 320. Each power supply is secured to one of the pair 310 of extended arms 312 that define the corresponding sled slot 320. For example, the rack 240 may include a power supply coupled to or secured to each extended arm 312 extending from the extended legs 302. Each power supply includes a power connector configured to mate with a power connector of the sled 400 when the sled 400 is received in the corresponding sled slot 320. In the illustrative embodiment, the sled 400 does not include any onboard power supply, and therefore, the power supply provided in the bracket 240 provides power to the corresponding sled 400 when the corresponding sled 400 is mounted to the bracket 240.

[0038] Now refer to Figure 6 In the illustrative embodiment, the sled 400 is configured to be installed in a corresponding rack 240 of the data center 100 as discussed above. In some embodiments, each sled 400 may be optimized or otherwise configured to perform a specific task, such as a computing task, an acceleration task, a data storage task, etc. For example, the sled 400 may be implemented as follows with respect to Figure 8-9 The computing skid 800 discussed below Figure 10-11 The accelerator skid 1000 discussed below Figure 12-13The storage device sled 1200 discussed, or a sled optimized or otherwise configured to perform other specialized tasks, such as the storage sled 1400 (described below with respect to FIG. Figure 14 is discussed).

[0039] As discussed above, the illustrative sled 400 includes a chassisless circuit board substrate 602 that supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that the circuit board substrate 602 is "chassisless" in that the sled 400 does not include a housing or enclosure. Rather, the chassisless circuit board substrate 602 is open to the local environment. The chassisless circuit board substrate 602 can be formed from any material capable of supporting the various electrical components mounted thereon. For example, in the illustrative embodiment, the chassisless circuit board substrate 602 is formed from an FR-4 glass-reinforced epoxy laminate. Of course, in other embodiments, other materials can be used to form the chassisless circuit board substrate 602.

[0040] As discussed in greater detail below, chassisless circuit board substrate 602 includes multiple features that improve the thermal cooling characteristics of various electrical components mounted on chassisless circuit board substrate 602. As discussed, chassisless circuit board substrate 602 does not include a housing or enclosure, which improves air flow over the electrical components of sled 400 by reducing structures that could inhibit air flow. For example, because chassisless circuit board substrate 602 is not positioned in a separate housing or enclosure, there is no backplane (e.g., a chassis' backplane) to chassisless circuit board substrate 602, which could inhibit air flow over the electrical components. Furthermore, chassisless circuit board substrate 602 has a geometry configured to reduce the length of the air flow path across the electrical components mounted to chassisless circuit board substrate 602. For example, the illustrative chassisless circuit board substrate 602 has a width 604 that is greater than a depth 606 of chassisless circuit board substrate 602. In one particular embodiment, for example, the chassisless circuit board substrate 602 has a width of approximately 21 inches and a depth of approximately 9 inches, as compared to a typical server having a width of approximately 17 inches and a depth of approximately 39 inches. Thus, the air flow path 608 extending from the front edge 610 to the rear edge 612 of the chassisless circuit board substrate 602 has a shorter distance relative to a typical server, which can improve the thermal cooling characteristics of the sled 400. Furthermore, although Figure 6Although not shown, the various physical resources mounted to the chassisless circuit board substrate 602 are mounted in corresponding positions so that no two substantially heat-generating electrical components shade each other (as discussed in more detail below). That is, no two electrical components that generate appreciable heat during operation (i.e., sufficiently greater than a nominal amount of heat to negatively impact the cooling of another electrical component) are mounted to the chassisless circuit board substrate 602 linearly in a row with each other along the direction of the airflow path 608 (i.e., in a direction extending from the leading edge 610 to the trailing edge 612 of the chassisless circuit board substrate 602).

[0041] As discussed above, the illustrative sled 400 includes one or more physical resources 620 mounted to the top side 650 of the chassisless circuit board substrate 602. Figure 6 Two physical resources 620 are shown in FIG. 1 , but it should be appreciated that in other embodiments, the sled 400 may include one, two, or more physical resources 620. The physical resources 620 may be implemented as any type of processor, controller, or other computing circuit capable of performing various tasks, such as computing functions and / or controlling the functionality of the sled 400, for example, depending on the type or intended functionality of the sled 400. For example, as discussed in more detail below, the physical resources 620 may be implemented as a high-performance processor in an embodiment where the sled 400 is implemented as a compute sled, as an accelerator coprocessor or circuit in an embodiment where the sled 400 is implemented as an accelerator sled, as a storage device controller in an embodiment where the sled 400 is implemented as a storage device sled, or as a collection of memory devices in an embodiment where the sled 400 is implemented as a memory sled.

[0042] The sled 400 also includes one or more additional physical resources 630 mounted to the top side 650 of the chassisless circuit board substrate 602. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC), as discussed in more detail below. Of course, depending on the type and functionality of the sled 400, in other embodiments, the physical resources 630 may include additional or other electrical components, circuits, and / or devices.

[0043] Physical resource 620 is communicatively coupled to physical resource 630 via input / output (I / O) subsystem 622. I / O subsystem 622 may be implemented as circuitry and / or components for facilitating input / output operations with physical resource 620, physical resource 630, and / or other components of sled 400. For example, I / O subsystem 622 may be implemented as or otherwise include a memory controller hub, an input / output control hub, an integrated sensor hub, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, optical guides, printed circuit board traces, etc.), and / or other components and subsystems for facilitating input / output operations. In the illustrative embodiment, I / O subsystem 622 is shown as or otherwise includes a double data rate 4 (DDR4) data bus or a DDR5 data bus.

[0044] In some embodiments, the sled 400 may also include a resource-to-resource interconnect 624. The resource-to-resource interconnect 624 may be implemented as any type of communication interconnect capable of facilitating resource-to-resource communication. In an illustrative embodiment, the resource-to-resource interconnect 624 is implemented as a high-speed point-to-point interconnect (e.g., faster than the I / O subsystem 622). For example, the resource-to-resource interconnect 624 may be implemented as a Quick Path Interconnect (QPI), an Ultra Path Interconnect (UPI), or other high-speed point-to-point interconnect dedicated for resource-to-resource communication.

[0045] The sled 400 also includes a power connector 640 configured to mate with a corresponding power connector of the bracket 240 when the sled 400 is installed in the corresponding bracket 240. The sled 400 receives power from the bracket 240's power supply via the power connector 640 to power the various electrical components of the sled 400. That is, the sled 400 does not include any local power source (i.e., onboard power supply) for providing power to the electrical components of the sled 400. The elimination of a local or onboard power source facilitates a reduction in the overall footprint of the chassisless circuit board substrate 602, which, as discussed above, can increase thermal cooling characteristics of the various electrical components mounted on the chassisless circuit board substrate 602. In some embodiments, power is provided to the processor 820 via vias directly beneath the processor 820 (e.g., through the bottom side 750 of the chassisless circuit board substrate 602), providing an increased thermal budget, additional current and / or voltage, and better voltage control over typical circuit boards.

[0046] In some embodiments, the sled 400 may also include mounting features 642 configured to mate with a mounting arm or other structure of a robot to facilitate the robot's placement of the sled 400 in the bracket 240. The mounting features 642 may be implemented as any type of physical structure that allows the robot to grasp the sled 400 without damaging the chassisless circuit board substrate 602 or the electrical components mounted thereon. For example, in some embodiments, the mounting features 642 may be implemented as non-conductive pads that attach to the chassisless circuit board substrate 602. In other embodiments, the mounting features may be implemented as brackets, clips, or other similar structures that attach to the chassisless circuit board substrate 602. The specific number, shape, size, and / or composition of the mounting features 642 may depend on the design of the robot configured to manage the sled 400.

[0047] Now refer to Figure 7 In addition to the physical resources 630 mounted on the top side 650 of the chassisless circuit board substrate 602, the slider 400 also includes one or more memory devices 720 mounted to the bottom side 750 of the chassisless circuit board substrate 602. That is, the chassisless circuit board substrate 602 is implemented as a double-sided circuit board. The physical resources 620 are communicatively coupled to the memory devices 720 via the I / O subsystem 622. For example, the physical resources 620 and the memory devices 720 can be communicatively coupled by one or more through-vias extending through the chassisless circuit board substrate 602. In some embodiments, each physical resource 620 can be communicatively coupled to a different set of one or more memory devices 720. Alternatively, in other embodiments, each physical resource 620 can be communicatively coupled to each memory device 720.

[0048] The memory device 720 can be implemented as any type of memory device capable of storing data for the physical resource 620 during operation of the sled 400, such as any type of volatile memory (e.g., dynamic random access memory (DRAM)) or non-volatile memory. Volatile memory can be a storage medium that requires power to maintain the state of the data stored by the medium. Non-limiting examples of volatile memory can include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One specific type of DRAM that can be used in the memory module is synchronous dynamic random access memory (SDRAM). In a specific embodiment, the DRAM of the memory component may conform to standards promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards, and the communication interface of a memory device that implements such standards may be referred to as a DDR-based interface.

[0049] In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technology. The memory device may also include next generation non-volatile devices, such as Intel 3D XPoint TMMemory or other byte-addressable, write-in-place non-volatile memory device. In one embodiment, the memory device may be or may include a memory device using chalcogenide glass, multi-threshold NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, magnetoresistive random access memory (MRAM) memory combined with memristor technology, resistive memory including metal oxide-based, oxygen vacancy-based, and conductive bridge random access memory (CB-RAM), or spin transfer torque (STT)-MRAM, a device based on electron spin magnetic junction memory, a device based on magnetic tunneling junction (MTJ), a device based on DW (domain wall) and SOT (spin-orbit transfer), a thyristor-based memory device, or any combination of the above, or other memory. The memory device may refer to the die itself and / or to a packaged memory product. In some embodiments, a memory device may include a transistor-less stackable cross-point architecture in which memory cells are located at the intersections of word lines and bit lines and are individually addressable, and in which bit storage is based on changes in bulk resistance.

[0050] Now refer to Figure 8 In some embodiments, the sled 400 may be implemented as a compute sled 800. The compute sled 800 is optimized or otherwise configured to perform computational tasks. Of course, as discussed above, the compute sled 800 may rely on other sleds (such as an acceleration sled and / or a storage device sled) to perform such computational tasks. The compute sled 800 includes various physical resources (e.g., electrical components) similar to those of the sled 400, which are Figure 8 The same reference number has been used in the above. Figure 6 and Figure 7 The descriptions provided for such components are applicable to corresponding components of the computing sled 800 and are not repeated herein for clarity of the description of the computing sled 800 .

[0051] In the illustrative computing sled 800, the physical resources 620 are implemented as processors 820. Although Figure 8Only two processors 820 are shown in FIG. 1 , but it should be appreciated that in other embodiments, the computing sled 800 may include additional processors 820. Illustratively, the processors 820 are implemented as high-performance processors 820 and may be configured to operate at a relatively high power rating. Although processors 820 operating at a greater power rating than typical processors (which operate at approximately 155-230 W) generate additional heat, the enhanced thermal cooling characteristics of the chassisless circuit board substrate 602 discussed above facilitate higher power operation. For example, in the illustrative embodiment, the processors 820 are configured to operate at a power rating of at least 250 W. In some embodiments, the processors 820 may be configured to operate at a power rating of at least 350 W.

[0052] In some embodiments, the compute sled 800 may also include a processor-to-processor interconnect 842. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the processor-to-processor interconnect 842 may be implemented as any type of communication interconnect capable of facilitating communication over the processor-to-processor interconnect 842. In an illustrative embodiment, the processor-to-processor interconnect 842 is implemented as a high-speed point-to-point interconnect (e.g., faster than the I / O subsystem 622). For example, the processor-to-processor interconnect 842 may be implemented as a Quick Path Interconnect (QPI), an Ultra Path Interconnect (UPI), or other high-speed point-to-point interconnect dedicated for processor-to-processor communication.

[0053] The computing sled 800 also includes communications circuitry 830. The illustrative communications circuitry 830 includes a network interface controller (NIC) 832, which may also be referred to as a host fabric interface (HFI). NIC 832 may be implemented as or otherwise include any type of integrated circuit, discrete circuit, controller chip, chipset, add-in board, daughter card, network interface card, or other device that can be used by the computing sled 800 to connect to another computing device (e.g., another sled 400). In some embodiments, NIC 832 may be implemented as part of a system-on-chip (SoC) that includes one or more processors, or included on a multi-chip package that also includes one or more processors. In some embodiments, NIC 832 may include a local processor (not shown) and / or local memory (not shown), both of which are local to NIC 832. In such embodiments, the local processor of NIC 832 may be capable of performing one or more of the functions of processor 820. Additionally or alternatively, in such embodiments, the local memory of the NIC 832 may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and / or other levels.

[0054] The communication circuit 830 is communicatively coupled to an optical data connector 834. The optical data connector 834 is configured to mate with a corresponding optical data connector of the rack 240 when the computing sled 800 is installed in the rack 240. Illustratively, the optical data connector 834 includes a plurality of optical fibers that lead from a mating surface of the optical data connector 834 to an optical transceiver 836. The optical transceiver 836 is configured to convert incoming optical signals from the rack-side optical data connector into electrical signals, and convert electrical signals into outgoing optical signals to the rack-side optical data connector. Although shown as forming part of the optical data connector 834 in the illustrative embodiment, in other embodiments, the optical transceiver 836 may form part of the communication circuit 830.

[0055] In some embodiments, the compute sled 800 may also include an expansion connector 840. In such embodiments, the expansion connector 840 is configured to mate with a corresponding connector of an expansion chassisless circuit board substrate to provide additional physical resources to the compute sled 800. The additional physical resources may, for example, be used by the processor 820 during operation of the compute sled 800. The expansion chassisless circuit board substrate may be substantially similar to the chassisless circuit board substrate 602 discussed above and may include various electrical components mounted thereon. The specific electrical components mounted to the expansion chassisless circuit board substrate may depend on the intended functionality of the expansion chassisless circuit board substrate. For example, the expansion chassisless circuit board substrate may provide additional computing resources, memory resources, and / or storage resources. Thus, the additional physical resources of the expansion chassisless circuit board substrate may include, but are not limited to, processors, memory devices, storage devices, and / or accelerator circuits, including, for example, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), security coprocessors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and / or circuits.

[0056] Now refer to Figure 9 , shows an illustrative embodiment of a computing sled 800. As shown, a processor 820, communication circuitry 830, and optical data connectors 834 are mounted to the top side 650 of the chassisless circuit board substrate 602. The physical resources of the computing sled 800 can be mounted to the chassisless circuit board substrate 602 using any suitable attachment or mounting technique. For example, the various physical resources can be mounted in corresponding sockets (e.g., a processor socket), brackets, or trays. In some cases, some of the electrical components can be mounted directly to the chassisless circuit board substrate 602 via soldering or similar techniques.

[0057] As discussed above, the respective processors 820 and communications circuitry 830 are mounted to the top side 650 of the chassisless circuit board substrate 602 so that no two heat-generating electrical components are shielded from each other. In the illustrative embodiment, the processors 820 and communications circuitry 830 are mounted in corresponding locations on the top side 650 of the chassisless circuit board substrate 602 so that no two of those physical resources are linearly aligned with other physical resources along the direction of the air flow path 608. It should be appreciated that although the optical data connectors 834 are aligned with the communications circuitry 830, the optical data connectors 834 do not generate heat or generate nominal heat during operation.

[0058] The memory devices 720 of the computing sled 800 are mounted to the bottom side 750 of the chassisless circuit board substrate 602 discussed above with respect to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the processors 820 located on the top side 650 via the I / O subsystem 622. Because the chassisless circuit board substrate 602 is implemented as a double-sided circuit board, the memory devices 720 and the processors 820 can be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassisless circuit board substrate 602. Of course, in some embodiments, each processor 820 can be communicatively coupled to a different set of one or more memory devices 720. Alternatively, in other embodiments, each processor 820 can be communicatively coupled to each memory device 720. In some embodiments, the memory devices 720 can be mounted to one or more memory mezzanines on the bottom side of the chassisless circuit board substrate 602 and can be interconnected with the corresponding processors 820 via a ball grid array.

[0059] Each processor 820 includes a heat sink 850 attached thereto. Because the memory devices 720 are mounted to the bottom side 750 of the chassisless circuit board substrate 602 (and the vertical spacing of the sled 400 in the corresponding bracket 240), the top side 650 of the chassisless circuit board substrate 602 includes additional "free" area or space that facilitates the use of heat sinks 850 that are larger in size than traditional heat sinks used in typical servers. Furthermore, due to the improved thermal cooling characteristics of the chassisless circuit board substrate 602, none of the processor heat sinks 850 include cooling fans attached thereto. In other words, each heat sink 850 is implemented as a fanless heat sink.

[0060] Now refer to Figure 10In some embodiments, the sled 400 may be implemented as an accelerator sled 1000. The accelerator sled 1000 is optimized or otherwise configured to perform specialized computational tasks, such as machine learning, encryption, hashing, or other computationally intensive tasks. In some embodiments, for example, the compute sled 800 may offload tasks to the accelerator sled 1000 during operation. The accelerator sled 1000 includes various components similar to the sled 400 and / or the compute sled 800, which are Figure 10 The same reference number has been used in the above. Figure 6 、 7 The descriptions of such components provided in and 8 are applicable to corresponding components of the accelerator sled 1000 and are not repeated herein for clarity of description of the accelerator sled 1000.

[0061] In the illustrative accelerator sled 1000, the physical resources 620 are implemented as accelerator circuits 1020. Although Figure 10 Only two accelerator circuits 1020 are shown, but it should be appreciated that in other embodiments, the accelerator sled 1000 may include additional accelerator circuits 1020. For example, Figure 11 As shown in , in some embodiments, the accelerator sled 1000 may include four accelerator circuits 1020. The accelerator circuits 1020 may be implemented as any type of processor, coprocessor, computational circuit, or other device capable of performing computational or processing operations. For example, the accelerator circuits 1020 may be implemented as, for example, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a security coprocessor, a graphics processing unit (GPU), a machine learning circuit, or other specialized processors, controllers, devices, and / or circuits.

[0062] In some embodiments, the accelerator sled 1000 may also include an accelerator-to-accelerator interconnect 1042. Similar to the resource-to-resource interconnect 624 of the sled 600 discussed above, the accelerator-to-accelerator interconnect 1042 may be implemented as any type of communication interconnect capable of facilitating accelerator-to-accelerator communication. In an illustrative embodiment, the accelerator-to-accelerator interconnect 1042 is implemented as a high-speed point-to-point interconnect (e.g., faster than the I / O subsystem 622). For example, the accelerator-to-accelerator interconnect 1042 may be implemented as a Quick Path Interconnect (QPI), an Ultra Path Interconnect (UPI), or other high-speed point-to-point interconnect dedicated for processor-to-processor communication. In some embodiments, the accelerator circuit 1020 may be daisy-chained with a primary accelerator circuit 1020 connected to the NIC 832 and memory 720 via the I / O subsystem 622, and a secondary accelerator circuit 1020 connected to the NIC 832 and memory 720 via the primary accelerator circuit 1020.

[0063] Now refer to Figure 11 , shows an illustrative embodiment of an accelerator sled 1000. As discussed above, the accelerator circuit 1020, the communication circuit 830, and the optical data connector 834 are mounted to the top side 650 of the chassisless circuit board substrate 602. Furthermore, each accelerator circuit 1020 and the communication circuit 830 are mounted to the top side 650 of the chassisless circuit board substrate 602 so that no two heat-generating electrical components are shadowed by each other, as discussed above. The memory device 720 of the accelerator sled 1000 is mounted to the bottom side 750 of the chassisless circuit board substrate 602, as discussed above with respect to the sled 600. Although mounted to the bottom side 750, the memory device 720 is communicatively coupled to the accelerator circuit 1020 located on the top side 650 via the I / O subsystem 622 (e.g., via vias). Additionally, each accelerator circuit 1020 may include a heat sink 1070 that is larger than conventional heat sinks used in servers. As discussed above with reference to heat sink 870 , heat sink 1070 may be larger than conventional heat sinks because the “free” area provided by memory devices 750 is located on the bottom side 750 of chassisless circuit board substrate 602 rather than the top side 650 .

[0064] Now refer to Figure 12 In some embodiments, the sled 400 may be implemented as the storage sled 1200. The storage sled 1200 is optimized or otherwise configured to store data in a data storage 1250 local to the storage sled 1200. For example, during operation, the compute sled 800 or the accelerator sled 1000 may store data and retrieve data from the data storage 1250 of the storage sled 1200. The storage sled 1200 includes various components similar to those of the sled 400 and / or the compute sled 800. Figure 12 The same reference number has been used in the above. Figure 6 、 7 The descriptions of such components provided in and 8 apply to corresponding components of the storage device sled 1200 and are not repeated herein for clarity of the description of the storage device sled 1200.

[0065] In the illustrative storage sled 1200, the physical resource 620 is implemented as a storage controller 1220. Although Figure 12Only two storage controllers 1220 are shown in FIG. 1 , but it should be appreciated that in other embodiments, the storage sled 1200 may include additional storage controllers 1220. The storage controllers 1220 may be implemented as any type of processor, controller, or control circuit capable of controlling the storage and retrieval of data into the data storage device 1250 based on requests received via the communication circuitry 830. In an illustrative embodiment, the storage controllers 1220 are implemented as relatively low-power processors or controllers. For example, in some embodiments, the storage controllers 1220 may be configured to operate at a nominal power of approximately 75 watts.

[0066] In some embodiments, the storage device sled 1200 may also include a controller-to-controller interconnect 1242. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1242 may be implemented as any type of communication interconnect capable of facilitating controller-to-controller communication. In an illustrative embodiment, the controller-to-controller interconnect 1242 is implemented as a high-speed point-to-point interconnect (e.g., faster than the I / O subsystem 622). For example, the controller-to-controller interconnect 1242 may be implemented as a Quick Path Interconnect (QPI), an Ultra Path Interconnect (UPI), or other high-speed point-to-point interconnect dedicated for processor-to-processor communication.

[0067] Now refer to Figure 13 , shows an illustrative embodiment of a storage device sled 1200. In the illustrative embodiment, the data storage device 1250 is implemented as or otherwise includes a storage device cage 1252 configured to accommodate one or more solid-state drives (SSDs) 1254. To do so, the storage device cage 1252 includes a number of mounting slots 1256, each configured to receive a corresponding solid-state drive 1254. Each mounting slot 1256 includes a plurality of drive guides 1258 that cooperate to define an access opening 1260 for the corresponding mounting slot 1256. The storage device cage 1252 is secured to the chassisless circuit board substrate 602 such that the access opening faces away from the chassisless circuit board substrate 602 (i.e., toward the front of the chassisless circuit board substrate 602). Thus, when the storage device sled 1200 is installed in the corresponding bracket 204, the solid-state drives 1254 are accessible. For example, a solid-state drive 1254 may be swapped out of a bracket 240 (eg, via a robot) while the storage device sled 1200 remains installed in the corresponding bracket 240 .

[0068] The storage cage 1252 illustratively includes 16 mounting slots 1256 and is capable of mounting and storing 16 solid-state drives 1254. Of course, in other embodiments, the storage cage 1252 can be configured to store additional or fewer solid-state drives 1254. Furthermore, in the illustrative embodiment, the solid-state drives are mounted vertically within the storage cage 1252, but in other embodiments, they may be mounted in different orientations within the storage cage 1252. Each solid-state drive 1254 can be implemented as any type of data storage device capable of storing long-term data. To do so, the solid-state drives 1254 can include the volatile and non-volatile memory devices discussed above.

[0069] like Figure 13 , the storage device controller 1220, communication circuitry 830, and optical data connectors 834 are illustratively mounted to the top side 650 of the chassisless circuit board substrate 602. Again, as discussed above, the electrical components of the storage device sled 1200 may be mounted to the chassisless circuit board substrate 602 using any suitable attachment or mounting technique, including, for example, sockets (e.g., a processor socket), brackets, brackets, solder connections, and / or other mounting or securing techniques.

[0070] As discussed above, the respective storage controllers 1220 and communications circuitry 830 are mounted to the top side 650 of the chassisless circuit board substrate 602 such that no two heat-generating electrical components shadow each other. For example, the storage controllers 1220 and communications circuitry 830 are mounted in corresponding locations on the top side 650 of the chassisless circuit board substrate 602 such that no two of those electrical components are in a linear row with the others along the direction of the air flow path 608.

[0071] The memory devices 720 of the storage sled 1200 are mounted to the bottom side 750 of the chassisless circuit board substrate 602, as discussed above with respect to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the storage controller 1220 located on the top side 650 via the I / O subsystem 622. Furthermore, because the chassisless circuit board substrate 602 is implemented as a double-sided circuit board, the memory devices 720 and the storage controllers 1220 can be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassisless circuit board substrate 602. Each storage controller 1220 includes a heat sink 1270 affixed thereto. As discussed above, due to the improved thermal cooling characteristics of the chassisless circuit board substrate 602 of the storage sled 1200, none of the heat sinks 1270 include a cooling fan attached thereto. That is, each heat sink 1270 is implemented as a fanless heat sink.

[0072] Now refer to Figure 14In some embodiments, the sled 400 may be implemented as a memory sled 1400. The memory device sled 1400 is optimized or otherwise configured to provide other sleds 400 (e.g., the compute sled 800, the accelerator sled 1000, etc.) with access to a pool of memory local to the memory sled 1200 (e.g., in two or more sets 1430, 1432 of the memory devices 720). For example, during operation, the compute sled 800 and the accelerator sled 1000 may remotely write to and / or read from one or more of the memory sets 1430, 1432 of the memory sled 1200 using a logical address space that maps to physical addresses in the memory sets 1430, 1432. The memory sled 1400 includes various components similar to those of the sled 400 and / or the compute sled 800, which are described in detail in the accompanying drawings. Figure 14 The same reference number has been used in the above. Figure 6 、 7 The descriptions of such components provided in and 8 apply to corresponding components of the memory sled 1400 and are not repeated herein for clarity of the description of the memory sled 1400.

[0073] In the illustrative memory sled 1400, the physical resource 620 is implemented as a memory controller 1420. Although Figure 14 Only two memory controllers 1420 are shown in FIG. 1 , but it should be appreciated that in other embodiments, the memory sled 1400 may include additional memory controllers 1420. The memory controllers 1420 may be implemented as any type of processor, controller, or control circuitry capable of controlling the reading and writing of data in the memory sets 1430, 1432 based on requests received via the communication circuitry 830. In the illustrative embodiment, each memory device controller 1220 connects to a corresponding memory set 1430, 1432 to write to and read from the memory devices 720 within the corresponding memory set 1430, 1432, and enforces any permissions (e.g., read, write, etc.) associated with the sled 1400 that has sent a request to the memory sled 1400 to perform a memory access operation (e.g., read or write).

[0074] In some embodiments, memory sled 1400 may also include a controller-to-controller interconnect 1442. Similar to the resource-to-resource interconnect 624 of sled 400 discussed above, controller-to-controller interconnect 1442 may be implemented as any type of communication interconnect capable of facilitating controller-to-controller communication. In an illustrative embodiment, controller-to-controller interconnect 1442 is implemented as a high-speed point-to-point interconnect (e.g., faster than I / O subsystem 622). For example, controller-to-controller interconnect 1442 may be implemented as a Quick Path Interconnect (QPI), an Ultra Path Interconnect (UPI), or other high-speed point-to-point interconnect dedicated for processor-to-processor communication. Thus, in some embodiments, a memory controller 1420 may access memory within a memory set 1432 associated with another memory controller 1420 via controller-to-controller interconnect 1442. In some embodiments, a scalable memory controller is comprised of multiple smaller memory controllers (referred to herein as "chiplets") on a memory sled (e.g., memory sled 1400). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller can scale to a significant number of memory controllers and I / O ports (e.g., up to 16 memory channels). In some embodiments, memory controller 1420 can implement memory interleaving (e.g., one memory address is mapped to memory set 1430, the next memory address is mapped to memory set 1432, and a third address is mapped to memory set 1430, etc.). Interleaving can be managed within memory controller 1420 or across network links from a CPU socket (e.g., of compute sled 800) to memory sets 1430, 1432, and can improve the latency associated with performing memory access operations compared to accessing contiguous memory addresses from the same memory device.

[0075] Additionally, in some embodiments, the memory sled 1400 can be connected to one or more other sleds 400 (e.g., in the same rack 240 or an adjacent rack 240) via waveguide using a waveguide connector 1480. In the illustrated embodiment, the waveguide is a 64 mm waveguide that provides 16 Rx (receive) lanes and 16 Rt (transmit) lanes. In the illustrated embodiment, each lane is either 16 GHz or 32 GHz. In other embodiments, the frequency can be different. Using a waveguide can provide high-throughput access to a memory pool (e.g., memory banks 1430 and 1432) to another sled (e.g., a sled 400 in the same rack 240 as the memory sled 1400 or an adjacent rack 240) without adding load to the optical data connector 834.

[0076] Now refer to Figure 15A system for executing one or more workloads (e.g., applications) can be implemented in accordance with data center 100. In an illustrative embodiment, system 1510 includes an orchestrator server 1520, which can be implemented as a managed node. The managed node includes a computing device (e.g., compute sled 800) executing management software (e.g., a cloud operating environment such as OpenStack). The managed node is communicatively coupled to a plurality of sleds 400, including a plurality of compute sleds 1530 (e.g., each similar to compute sled 800), memory sleds 1540 (e.g., each similar to memory sled 1400), accelerator sleds 1550 (e.g., each similar to memory sled 1000), and storage sleds 1560 (e.g., each similar to storage sled 1200). One or more of sleds 1520, 1540, 1550, 1560, such as those grouped by orchestrator server 1520 into managed nodes 1570, can collectively execute workloads (e.g., applications 1232 executed in virtual machines or containers). Managed nodes 1570 can be implemented as an assembly of physical resources 620, such as processors 820, memory resources 720, accelerator circuits 1020, or data storage devices 1250, from the same or different sleds 400. Furthermore, managed nodes can be created, defined, or "spun up" by orchestrator server 1520 when a workload is assigned to the managed node or at any other time, and can exist regardless of whether any workload is currently assigned to the managed node. In an illustrative embodiment, orchestrator server 1520 can selectively allocate and / or de-allocate physical resources 620 from sleds 400 and / or add and / or remove one or more sleds 400 from managed nodes 1570 as a function of quality of service (QoS) targets (e.g., performance targets associated with throughput, latency, instructions per second, etc.) associated with a service level agreement for a workload (e.g., application 1532). In doing so, orchestrator server 1520 may receive telemetry data indicating performance conditions (e.g., throughput, latency, instructions per second, etc.) in each sled 400 of managed nodes 1570 and compare the telemetry data with the quality of service targets to determine whether the quality of service targets are being met. If so, orchestrator server 1520 may additionally determine whether one or more physical resources can be de-allocated from managed node 1570 while still meeting the QoS targets, thereby freeing those physical resources for use by another managed node (e.g., to execute a different workload). Alternatively, if the QoS targets are not currently being met, orchestrator server 1520 may determine to dynamically allocate additional physical resources to assist in the execution of the workload (e.g., application 1532) while the workload is currently executing.

[0077] Furthermore, in some embodiments, orchestrator server 1520 can identify trends in resource utilization of workloads (e.g., applications 1532), such as by identifying execution phases of the workloads (e.g., applications 1532) (e.g., time periods during which different operations are executed, each with different resource utilization characteristics), and preemptively identify available resources in data center 100 and allocate them to managed nodes 1570 (e.g., within a predetermined time period starting with the associated phase). In some embodiments, orchestrator server 1520 can model performance based on various latency and distribution schemes to place workloads across compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in data center 100. For example, orchestrator server 1520 can utilize a model that considers resource performance on sled 400 (e.g., FPGA performance, memory access latency, etc.) and the performance of the path through the network to the resources (e.g., FPGA) (e.g., congestion, latency, bandwidth). Thus, orchestrator server 1520 can determine which resource(s) should be used for which workloads based on the total latency associated with each potential resource available in data center 100 (e.g., the latency associated with the performance of the resource itself, but also the latency associated with the path through the network between the compute sled executing the workload and sled 400 on which the resources are located).

[0078] In some embodiments, orchestrator server 1520 can use telemetry data reported from sled 400 (e.g., temperature, fan speed, etc.) to generate a thermal profile of data center 100 and allocate resources to managed nodes as a function of the thermal profile and predicted thermal profile associated with different workloads to maintain target temperatures and thermal distribution within data center 100. Additionally or alternatively, in some embodiments, orchestrator server 1520 can organize the received telemetry data into a hierarchical model that indicates relationships between managed nodes (e.g., spatial relationships, such as the physical location of the resources of managed nodes within data center 100, and / or functional relationships, such as grouping managed nodes by customers served by the managed nodes, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads with each other, etc.). Based on the differences in physical location and resources among the managed nodes, a given workload can establish different resource utilization across the resources of different managed nodes (e.g., causing different internal temperatures, using different percentages of processor or memory capacity). Orchestrator server 1520 can determine the difference based on the telemetry data stored in the hierarchical model and factor the difference into predicting the future resource utilization of the workload (if the workload is reassigned from one managed node to another managed node) to accurately balance resource utilization in data center 100.

[0079] To reduce the computational load on orchestrator server 1520 and the data transfer load on the network, in some embodiments, orchestrator server 1520 may send self-test information to sleds 400, enabling each sled 400 to determine locally (e.g., on sled 400) whether the telemetry data generated by sled 400 meets one or more conditions (e.g., available capacity meeting a predefined threshold, temperature meeting a predefined threshold, etc.). Each sled 400 may then report a simplified result (e.g., yes or no) back to orchestrator server 1520, which may use the result to determine resource allocation to managed nodes.

[0080] Now refer to Figure 16 , refer to the above reference Figure 1 The depicted data center 100 implements a system 1610 for allocating resources across the data center. In the illustrative embodiment, system 1610 includes an orchestrator server 1620 communicatively coupled to multiple sleds, including a compute sled 1630 and an accelerator sled 1640. One or more of sleds 1630 and 1640 can be grouped, such as by orchestrator server 1620, into managed nodes to collectively execute workloads (e.g., applications 1638). Managed nodes can be implemented as an assembly of resources, such as compute resources, memory resources, storage resources, or other resources, from the same or different sleds or racks. Furthermore, managed nodes can be created, defined, or "spun" by orchestrator server 1620 when a workload is assigned to the managed node or at any other time, and can exist regardless of whether any workload is currently assigned to the managed node. System 1610 can be located in a data center and provide storage and compute services (e.g., cloud services) to client devices 1614 that communicate with system 1610 via a network 1612. Orchestrator server 1620 may support a cloud operating environment such as OpenStack, and managed nodes established by orchestrator server 1620 may execute one or more applications or processes (ie, workloads), such as in virtual machines or containers, on behalf of users of client devices (not shown).

[0081] In the illustrative embodiment, the compute sled 1630 executes an application 1638 (e.g., a workload). The accelerator sled 1640 includes a plurality of accelerator devices 1644, 1646 coupled to a controller 1642. The controller 1642, in the illustrative embodiment, abstracts the details of the accelerator devices 1644, 1646 and presents the accelerator devices 1644, 1646 as one or more logical devices available to the compute sled 1630 on a request basis. In addition, the controller 1642 is operable to convert between a message format (e.g., a protocol) used between the compute sled 1630 and the accelerator sled 1640 over the network 1612 and a message format used internally for communications between the controller 1642 and the accelerator devices 1644, 1646, such as messages formatted for a local bus (e.g., Peripheral Component Interconnect Express (PCIe)).

[0082] Now refer to Figure 17 The accelerator sled 1640 may be implemented as any type of computing device capable of performing the functions described herein, including: providing accelerator abstraction data to the compute sled; receiving a request from the compute sled to perform an operation on an identified memory region of the accelerator device; converting the request from one format to a different format, and performing the operation on the identified memory region of the accelerator device using a corresponding access mode in response to the request. Figure 17 , the illustrative accelerator sled 1640 includes a compute engine 1702, an input / output (I / O) subsystem 1710, a communication circuit 1712, and one or more accelerator devices 1716. Of course, in other embodiments, the accelerator sled 1640 may include other or additional components, such as components typically found in a computer (e.g., a display, peripheral devices, etc.). Furthermore, in some embodiments, one or more of the illustrative components may be incorporated into another component or otherwise form part of another component.

[0083] The computing engine 1702 can be implemented as any type of device or collection of devices capable of performing the various computing functions described below. In some embodiments, the computing engine 1702 can be implemented as a single device, such as an integrated circuit, an embedded system, a field programmable gate array (FPGA), a system on a chip (SOC), or other integrated system or device. In an illustrative embodiment, the computing engine 1702 includes or is implemented as a controller 1642 and a memory 1706. The controller 1642 can be implemented as any type of processor capable of performing the functions described herein. For example, the controller 1642 can be implemented as a microcontroller, a single-core or multi-core processor, or other processor or processing / control circuitry. In some embodiments, the controller 1642 can be implemented as, include, or be coupled to an FPGA, an application-specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware that facilitates the performance of the functions described herein. In an illustrative embodiment, the controller 1642 includes an abstraction logic unit 1708, which can be implemented as any device or circuit (e.g., a coprocessor, an ASIC, etc.) that can represent the accelerator device 1716 to other computing devices (e.g., the compute sled 1630) as one or more logical devices (e.g., devices accessible using a network communication protocol (e.g., TCP / IP) rather than a local bus protocol (e.g., PCIe)) and can enable access to regions of the accelerator device (e.g., memory regions) via a proxy mode (e.g., acting as an intermediary between the compute sled 1630 and target accelerator devices 1720, 1722) and / or a direct access mode (e.g., remote direct memory access).

[0084] Memory 1706 can be implemented as any type of volatile (e.g., dynamic random access memory (DRAM) or the like) or non-volatile memory or data storage device capable of performing the functions described herein. Volatile memory can be a storage medium that requires power to maintain the state of the data stored by the medium. Non-limiting examples of volatile memory can include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One specific type of DRAM that can be used in the memory module is synchronous dynamic random access memory (SDRAM). In a specific embodiment, the DRAM of the memory component may conform to standards promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards, and the communication interface of a memory device that implements such standards may be referred to as a DDR-based interface.

[0085] In one embodiment, the memory device is a block-addressable memory device, such as a memory device based on NAND or NOR technology. The memory device may also include future generation non-volatile devices, such as three-dimensional cross-point memory devices (e.g., Intel 3D XPoint™ memory) or other byte-addressable write-in-place non-volatile memory devices. In one embodiment, the memory device may be or may include a memory device using chalcogenide glass, multi-threshold NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, magnetoresistive random access memory (MRAM) memory combined with memristor technology, resistive memory including metal oxide-based, oxygen vacancy-based, and conductive bridge random access memory (CB-RAM), or spin transfer torque (STT)-MRAM, a device based on electron spin magnetic junction memory, a device based on magnetic tunneling junction (MTJ), a device based on DW (domain wall) and SOT (spin-orbit transfer), a thyristor-based memory device, or any combination of the above, or other memory. The memory device may refer to the die itself and / or the packaged memory product.

[0086] In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™ memory) may include a transistor-free, stackable crosspoint architecture in which memory cells are located at the intersection of word lines and bit lines and are individually addressable, and in which bit storage is based on changes in bulk resistance. In some embodiments, all or a portion of memory 1706 may be integrated into controller 1642. In operation, memory 1706 may store various software and data used during operation, such as accelerator abstraction data, access policy data, applications, programs, and libraries.

[0087] The compute engine 1702 is communicatively coupled to the other components of the accelerator sled 1640 via an I / O subsystem 1710. The I / O subsystem 1710 may be implemented as circuitry and / or components for facilitating input / output operations with the compute engine 1702 (e.g., with the controller 1642 and / or the memory 1706) and the other components of the accelerator sled 1640. For example, the I / O subsystem 1710 may be implemented as or otherwise include a memory controller hub, an input / output control hub, an integrated sensor hub, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, optical guides, printed circuit board traces, etc.), and / or other components and subsystems for facilitating input / output operations. In some embodiments, the I / O subsystem 1710 may form part of a system on a chip (SoC) and be incorporated into the compute engine 1702 along with one or more of the following: the controller 1642, the memory 1706, and the other components of the accelerator sled 1640.

[0088] Communication circuitry 1712 may be implemented as any communication circuitry, device, or collection thereof that enables communication between accelerator sled 1640 and another computing device (e.g., compute sled 1630, orchestrator server 1620) over network 1612. Communication circuitry 1712 may be configured to implement such communication using any one or more communication technologies (e.g., wired or wireless communication) and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, etc.).

[0089] Communications circuitry 1712 may include a network interface controller (NIC) 1714 (e.g., as an add-in device), which may also be referred to as a host fabric interface (HFI). NIC 1714 may be implemented as one or more add-in boards, daughter cards, network interface cards, controller chips, chipsets, or other devices that can be used by accelerator sled 1640 to connect to another computing device (e.g., compute sled 1630, orchestrator server 1620, etc.). In some embodiments, NIC 1714 may be implemented as part of a system-on-chip (SoC) that includes one or more processors, or included on a multi-chip package that also includes one or more processors. In some embodiments, NIC 1714 may include a local processor (not shown) and / or local memory (not shown), both of which are local to NCI 1714. In such embodiments, the local processor of NIC 1714 may be capable of performing one or more of the functions of compute engine 1702 described herein. Additionally or alternatively, in such embodiments, the local memory of the NIC 1714 may be integrated into one or more components of the accelerator sled 1640 at the board level, socket level, chip level, and / or other levels.

[0090] Similar to Figure 16 Accelerator devices 1644 and 1646 are shown in FIG. Accelerator device 1716 includes multiple FPGAs 1720 and 1722. In the illustrated embodiment, each FPGA 1720 and 1722 includes multiple slots 1730, 1732, 1740, and 1742, each of which can be implemented as part of logic or circuitry (e.g., logic gates) present on the corresponding FPGA 1720 and 1722 and can be programmed using a bitstream to provide a core capable of accelerating a specific function. Additionally, each FPGA 1720 and 1722 includes memory 1734 and 1744, similar to memory 1706 described above. In the illustrated embodiment, each memory 1734 and 1744 also includes one or more registers associated with management commands (such as those for resetting or reprogramming the FPGA 1720 and 1722) and one or more registers associated with user commands (such as commands to execute an accelerated function according to a set of parameters).

[0091] The accelerator sled 1640 may also include one or more data storage devices 1718, which may be implemented as any type of device configured for short-term or long-term storage of data, such as, for example, memory devices and circuits, memory cards, hard drives, solid-state drives, or other data storage devices. Each data storage device 1718 may include a system partition that stores data and firmware code for the data storage device 1718. Each data storage device 1718 may also include one or more operating system partitions that store data files and are executable by the operating system.

[0092] Orchestrator server 1620, compute sled 1630, and client device 1614 may have similar Figure 17 1640, with the exception that, in some embodiments, orchestrator server 1620, compute sled 1630, and / or client device 1614 may not include accelerator device 1716. The description of those components of accelerator sled 1640 is equally applicable to the description of the components of those devices and is not repeated herein for the sake of brevity. In addition, it should be appreciated that any of accelerator sled 1640, compute sled 1630, orchestrator server 1620, or client device 1614 may include other components, subcomponents, and devices typically found in computing devices that are not discussed above with reference to accelerator 1640 and are not discussed herein for the sake of brevity.

[0093] As described above, orchestrator server 1620, sleds 1630, 1640, and client device 1614 are illustratively in communication via network 1612, which can be implemented as any type of wired or wireless communication network, including a global network (e.g., the Internet), a local area network (LAN) or wide area network (WAN), a cellular network (e.g., Global System for Mobile Communications (GSM), 3G, Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX)), etc.), a digital subscriber line (DSL) network, a cable network (e.g., a coaxial network, a fiber optic network, etc.), or any combination thereof.

[0094] Now refer to Figure 18During operation, the accelerator sled 1640 can establish an environment 1800. The illustrative environment 1800 includes a network communicator 1820 and an access manager 1830. Each component of the environment 1800 can be implemented as hardware, firmware, software, or a combination thereof. Thus, in some embodiments, one or more of the components of the environment 1800 can be implemented as a collection of electrical devices or circuits (e.g., network communicator circuit 1820, access manager circuit 1830, etc.). It should be appreciated that in such embodiments, one or more of the network communicator circuit 1820 or access manager circuit 1830 can form part of one or more of the following: the compute engine 1702, the accelerator device 1716, the I / O subsystem 1710, the communication circuit 1712, and / or other components of the accelerator sled 1640. In the illustrative embodiment, environment 1800 includes accelerator abstraction data 1802, which can be implemented as any data indicating one or more logical devices, memory regions, and access modes associated with each memory region (e.g., direct access mode or proxy mode) that represent accelerator device 1716 as accessible to a remote computing device (e.g., compute sled 1630). Furthermore, environment 1800 includes access policy data 1804, which can be implemented as any data indicating management commands that can be requested and whether each command is allowed or not allowed. Thus, access policy data 1804 can be provided by an administrator of system 1610, hard-coded, or provided from another source (e.g., a source different from a typical customer of system 1610).

[0095] In the illustrative environment 1800, network communicator 1820 (which, as discussed above, can be implemented as hardware, firmware, software, virtualized hardware, emulation architecture, and / or combinations thereof) is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from accelerator sled 1640, respectively. To do so, network communicator 1820 is configured to receive and process data packets from a system or computing device (e.g., compute sled 1630, orchestrator server 1620, etc.), and to prepare and send data packets to the computing device or system (e.g., compute sled 1630, orchestrator server 1620, etc.). Accordingly, in some embodiments, at least some of the functionality of network communicator 1820 can be performed by communication circuitry 1712, and in the illustrative embodiment, by NIC 1714.

[0096] The access manager 1830 (which can be implemented as hardware, firmware, software, virtualized hardware, emulation architecture, and / or a combination thereof) is configured to identify the accelerator device 1716 present on the accelerator sled 1630, generate accelerator abstract data 1802 to represent the accelerator device 1716 as one or more logical devices to any remote computing device (e.g., the computing sled 1630), and enable access to memory regions of the accelerator device 1716 through proxy mode or direct access mode. To do so, in the illustrative embodiment, the access manager 1830 includes an accelerator device identifier 1832, a proxy access manager 1834, and a direct access manager 1836.

[0097] In the illustrative embodiment, the accelerator device identifier 1832 is configured to identify the accelerator devices 1716, including their attributes (e.g., accelerator device type, number of FPGA slots, memory regions), and available capacity, and generate accelerator abstract data 1802 that represents the accelerator devices 1716 as one or more logical devices for use by a remote computing device (e.g., the compute sled 1630). In the illustrative embodiment, the accelerator device identifier 1832 provides in the accelerator abstract data 1802 an indication of the access pattern associated with each identified region of each accelerator device. For example, the accelerator device identifier 1832 may enable only proxy mode for memory regions (e.g., the management command register region), which may present a security risk to the system 1610, potentially compromise the accelerator sled 1640, or disrupt operations of the accelerator sled 1640 being executed on behalf of other customers (e.g., on behalf of applications executing on the compute sled 1630 or another sled (not shown)), and may enable direct access to other memory regions (e.g., the user command register region, memory regions reserved for bitstreams, input parameters, output data, etc.). In the illustrative embodiment, the proxy access manager 1834 is configured to receive requests from remote computing devices (e.g., the compute sled 1630), determine whether the operation (e.g., command) associated with the request is allowed or not allowed (e.g., as a function of the access policy data 1804), and pass a request to the corresponding accelerator device 1716 to allow it. Conversely, the direct access manager 1836 is configured to provide direct access (e.g., direct read or write access) to the memory regions of the corresponding accelerator device 1716.

[0098] It should be appreciated that each of the accelerator device identifier 1832, the proxy access manager 1834, and the direct access manager 1836 can be individually implemented as hardware, firmware, software, virtualized hardware, emulation architecture, and / or a combination thereof. For example, the accelerator device identifier 1832 can be implemented as a hardware component, while the proxy access manager 1834 and the direct access manager 1836 are implemented as virtualized hardware components, or as some other combination of hardware, firmware, software, virtualized hardware, emulation architecture, and / or a combination thereof.

[0099] Now refer to Figure 19 In operation, the accelerator sled 1640 may perform a method 1900 for providing efficient pooling of accelerator devices. The method 1900 begins at block 1902, where the accelerator sled 1640 identifies the accelerator devices 1716 present on the accelerator sled 1640 (e.g., during bus enumeration, such as during a boot sequence, or otherwise by querying devices connected to one or more local buses (such as a PCIe bus) of the accelerator sled 1640). In the illustrative embodiment, the accelerator sled 1640 identifies the attributes of the accelerator devices 1716, as indicated in block 1904. In doing so, the accelerator sled 1640 may identify the type of accelerator device 1716 present on the accelerator sled 1640 (e.g., FPGA, ASIC, graphics processor, etc.), as indicated in block 1906. For example, the controller 1642 may query each detected accelerator device 1716 for a code indicating the type, or may read a register containing data indicating the type of the accelerator device. As indicated in block 1908, the accelerator sled 1640 may identify the FPGAs (e.g., FPGAs 1720, 1722) present on the accelerator sled 1640. In doing so, and as indicated in block 1910, the accelerator sled 1640 may also identify any slots (e.g., slots 1730, 1732, 1740, 1742) in the FPGAs 1720, 1722, such as by querying each FPGA 1720, 1722 for the slot number. Additionally, as indicated in block 1912, the accelerator sled 1640 may identify any other type of accelerator device (e.g., an ASIC, a graphics processor, etc.) present on the accelerator sled 1640.

[0100] In block 1914, the accelerator sled 1640, in the illustrative embodiment, identifies regions of memory 1734, 1744 that are available for access by a remote computing device (e.g., compute sled 1630). In doing so, the accelerator sled 1640 identifies random access memory regions (as indicated in block 1916), user command register regions (as indicated in block 1918), and management command register regions (as indicated in block 1920), such as by querying each accelerator device 1716 for an address range associated with the region. As described in greater detail herein, the accelerator sled 1640 may associate each type of memory region with a corresponding access mode (e.g., proxy or direct) to be used by the remote computing device (e.g., compute sled 1630). In block 1922, the accelerator sled 1640 may further identify the available capacity of each accelerator device 1716 (e.g., the number of slots not yet allocated to execute functions on behalf of the remote computing device, the percentage of total processing capacity still available, etc.).

[0101] Subsequently, in block 1924, the accelerator sled 1640 determines whether to provide acceleration to a computing device (e.g., the compute sled 1630). For example, the accelerator sled 1640 may receive a request from the compute sled 1630 for data indicating available acceleration capacity on the accelerator sled 1640 in preparation for requesting acceleration of a specific function. In response to a determination that the accelerator sled 1640 has not been requested to provide acceleration to the computing device, the method 1900 loops back to block 1902 to continue monitoring the available capacity and properties of the accelerator device 1716 on the accelerator sled 1640. Otherwise, the method 1900 proceeds to Figure 20 Block 1926 is performed, where the accelerator sled 1640 provides accelerator abstraction data 1802 that represents the identified accelerator device 1716 as one or more logical devices to a compute device (e.g., the compute sled 1630). As described herein, the number of logical devices can be different than the number of accelerator devices 1716 physically present on the accelerator sled 1640 (e.g., the mapping is not necessarily one-to-one).

[0102] Now refer to Figure 20When providing the accelerator abstraction data 1802, the accelerator sled 1640 may represent the plurality of accelerator devices 1716 as a single logical device, as indicated in block 1928. Additionally or alternatively, the accelerator sled 1640 may represent a single accelerator device 1716 as multiple logical devices, as indicated in block 1930. In doing so, the accelerator sled 1640 may represent each slot (e.g., slots 1730, 1732) of the FPGA as a separate logical device, as indicated in block 1932. The accelerator sled 1640 may represent the accelerator device as a plurality of logical devices determined as a function of the available capacity of the accelerator device 1716 (e.g., the available capacity determined in block 1922), as indicated in block 1934. For example, accelerator sled 1640 may represent two accelerator devices with only 50% available capacity as a single logical device, and / or may represent an accelerator device with twice the capacity (or twice the reference amount of capacity) of the other accelerator devices on accelerator sled 1640 as two logical devices. In block 1936, accelerator sled 1640, in the illustrative embodiment, indicates memory regions of accelerator device 1716 that are accessible to a remote computing device (e.g., compute sled 1630). In doing so, accelerator sled 1640 indicates the random access memory (e.g., volatile memory) available for access (in block 1938), the user command register region available for access (in block 1940), and the management command register region available for access (in block 1942). In the illustrative embodiment, accelerator sled 1640 also indicates the available access modes for each memory region, as indicated in block 1944. In doing so, the accelerator sled 1640 indicates memory areas available for direct access mode (e.g., random access memory for temporarily storing bitstreams, parameters associated with function execution on the accelerator device, outputs from one or more function executions, etc.), as indicated in box 1946. Additionally, the accelerator sled 1640, in the illustrative embodiment, indicates memory areas available for access via proxy mode (e.g., where the controller 1642 acts as an intermediary to evaluate commands and selectively reject or issue commands to the corresponding accelerator device), as indicated in box 1948. Subsequently, in box 1950, the accelerator sled 1640 determines whether a request has been received (e.g., from the compute sled 1630) (e.g., to perform an operation with one or more of the logic devices represented therein). If not, the method 1900 continues to wait for such a request. Otherwise, the method 1900 proceeds to Figure 21 Block 1952 where the accelerator sled 1640 determines the parameters of the request.

[0103] Now refer to Figure 21Upon determining the parameters of the request, the accelerator sled 1640 determines whether the request is a direct access request or a proxy access request, as indicated in block 1954. The accelerator sled 1640 may make this determination by comparing one or more commands (e.g., operation names) in the request to a predefined set of commands available for each type of access mode (e.g., read or write may correspond to direct access, while reprogram or reset may correspond to proxy access). The type of access requested may be identified based on an indication of the requested access type (e.g., 0 for direct access or 1 for proxy access) or based on other factors. In any case, the accelerator sled 1640, in the illustrative embodiment, also determines the memory region to be accessed (e.g., by indicating a parameter that previously provided to the compute sled 1630 in the accelerator abstraction data 1802 to indicate a memory address or other identifier of the memory region), as indicated in block 1956. In the illustrative embodiment, the accelerator sled 1640 also converts the received request from a format used for communication over the network 1612 (e.g., TCP / IP) to a format usable with the accelerator devices 1716 on the accelerator sled (e.g., a PCIe format or other format associated with a local bus), as indicated at block 1958. Thus, by reformatting communications between the network 1612 and the accelerator devices 1716 on the accelerator sled 1640, the accelerator sled 1640 can free up significant processing capacity on each accelerator device 1716 that would otherwise be dedicated to managing different communication protocols.

[0104] In block 1960, the accelerator sled 1640 compares the requested parameters with the allowed access mode associated with the memory region to be accessed (e.g., the access mode indicated in block 1944). Thereafter, in block 1962, the accelerator sled 1640 determines a subsequent course of action based on whether the calculation sled 1630 requested an access mode that is allowed for the corresponding memory region. If not, the method 1900 proceeds to block 1964, where the accelerator sled 1640 returns an error message indicating an incorrect access mode for the memory region, and then loops back to Figure 201716. As indicated in block 1972, the accelerator sled 1640 may reprogram the one or more accelerator devices 1716. As indicated in block 1974, in some instances, such as where the requested operation is not allowed (e.g., based on the access policy data 1804), the accelerator sled 1640 may prevent the operation from being performed. Subsequently, the method 1900 loops back to Figure 20 1950, where the accelerator sled 1640 waits for another request from the compute sled 1630. Referring back to block 1966, if proxy access is not requested, the method 1900 proceeds to Figure 22 Block 1976 where the accelerator sled 1640 determines a subsequent course of action as a function of whether the remote computing device (eg, computing sled 1630) requests direct access.

[0105] Now refer to Figure 22 If the accelerator sled 1640 determines that the remote computing device (eg, computing sled 1630) has not requested direct access, then the method 1900 loops back to Figure 20The method 1900 proceeds to block 1950 , where the accelerator sled 1640 awaits another request from the remote computing device. Otherwise (e.g., if the compute sled 1630 does request direct access), the method 1900 proceeds to block 1978 , where the accelerator sled 1640 performs the requested direct access operation on the identified memory region. In doing so, the accelerator sled 1640 may enable the remote computing device (e.g., compute sled 1630) to directly write data to the identified memory region, as indicated in block 1980 . As indicated in block 1982 , the accelerator sled 1640 may enable the remote computing device (e.g., compute sled 1630) to write parameter data for use by the acceleration function (e.g., input data to be operated on). Additionally or alternatively, the accelerator sled 1640 may enable the remote computing device to write a bitstream representing the accelerated function (e.g., kernel) to be executed on the accelerator device 1716 , as indicated in block 1984 . As indicated in block 1986, the accelerator sled 1640 may enable the remote computing device to read data directly from the identified memory area. In doing so, the accelerator sled 1640 may enable the remote computing device to read output data resulting from the execution of the accelerated function (e.g., output data written to volatile memory). Additionally, the accelerator sled 1640 may convert any response (e.g., a response containing the read data) to be sent back to the remote computing device (e.g., compute sled 1630) from the format used by the corresponding accelerator device 1716 into a format that can be used for communication over a network (e.g., TCP / IP). Subsequently, the method 1900 loops back to Figure 20 Block 1950 where the accelerator sled 1640 waits for another request from a remote computing device (eg, the compute sled 1630 ).

[0106] Example

[0107] Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more of the examples described below, and any combination thereof.

[0108] Example 1 includes an accelerator sled comprising: an accelerator device; a controller connected to the accelerator device, wherein the controller is to (i) provide accelerator abstraction data to a compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region; (ii) receive a request from the compute sled to perform an operation on an identified memory region of the accelerator device using a corresponding access mode; (iii) convert the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; and (iv) perform the operation on the identified memory region of the accelerator device using the corresponding access mode in response to the request.

[0109] Example 2 includes the subject matter of Example 1, and wherein performing the operation on the identified memory region comprises performing the operation in a proxy mode.

[0110] Example 3 includes the subject matter of any of Examples 1 and 2, and wherein performing the operation in proxy mode includes: comparing the requested operation with policy data indicating whether one or more operations are allowed or not allowed; and performing the requested operation on an identified memory area of the accelerator device in response to a determination that the requested operation is allowed.

[0111] Example 4 includes the subject matter of any of Examples 1-3, and wherein performing the requested operation comprises performing the requested operation on a management command register.

[0112] Example 5 includes the subject matter of any of Examples 1-4, and wherein performing the requested operation comprises reprogramming the accelerator device or resetting the accelerator device.

[0113] Example 6 includes the subject matter of any of Examples 1-5, and wherein performing the operation on the identified memory region of the accelerator device comprises performing a direct access operation.

[0114] Example 7 includes the subject matter of any of Examples 1-6, and wherein performing the direct access operation comprises enabling the compute sled to write data to the identified memory region of the accelerator device.

[0115] Example 8 includes the subject matter of any of Examples 1-7, and wherein performing the direct access operation comprises enabling the compute sled to read data from the identified memory region of the accelerator device.

[0116] Example 9 includes the subject matter of any of Examples 1-8, and wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and wherein providing accelerator abstraction data comprises providing accelerator abstraction data representing the plurality of accelerator devices as a single logical device.

[0117] Example 10 includes the subject matter of any of Examples 1-9, and wherein providing the accelerator abstraction data comprises providing accelerator abstraction data representing the accelerator device as a plurality of logical devices.

[0118] Example 11 includes the subject matter of any of Examples 1-10, and wherein the accelerator device is a field programmable gate array having a plurality of slots, and providing the accelerator abstraction data representing the accelerator device as a plurality of logical devices comprises providing accelerator abstraction data representing each slot as a different logical device.

[0119] Example 12 includes the subject matter of any of Examples 1-11, and wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled, and the controller is further to identify the accelerator devices present on the sled and the memory region of each accelerator device accessible by the compute sled.

[0120] Example 13 includes the subject matter of any of Examples 1-12, and wherein identifying a region of each accelerator device accessible by the compute sled comprises identifying one or more of: a random access memory region, a user command register region, or a management command register region.

[0121] Example 14 includes a method comprising: providing, by an accelerator sled including an accelerator device connected to a controller, accelerator abstraction data to a compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region; receiving, by the accelerator sled and from the compute sled, a request to perform an operation on an identified memory region of the accelerator device using a corresponding access mode; converting, by the controller, the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; and performing, by the accelerator sled and in response to the request, the operation on the identified memory region of the accelerator device using the corresponding access mode.

[0122] Example 15 includes the subject matter of Example 14, and wherein performing the operation on the identified memory region comprises performing the operation in a proxy mode.

[0123] Example 16 includes the subject matter of any of Examples 14 and 15, and wherein performing the operation in proxy mode comprises: comparing the requested operation with policy data indicating whether one or more operations are allowed or not allowed; and performing the requested operation on the identified memory area of the accelerator device in response to a determination that the requested operation is allowed.

[0124] Example 17 includes the subject matter of any of Examples 14-16, and wherein performing the requested operation comprises performing the requested operation on a management command register.

[0125] Example 18 includes the subject matter of any of Examples 14-17, and wherein performing the requested operation comprises reprogramming the accelerator device or resetting the accelerator device.

[0126] Example 19 includes the subject matter of any of Examples 14-18, and wherein performing the operation on the identified memory region of the accelerator device comprises performing a direct access operation.

[0127] Example 20 includes the subject matter of any of Examples 14-19, and wherein performing the direct access operation comprises enabling the compute sled to write data to the identified memory region of the accelerator device.

[0128] Example 21 includes the subject matter of any of Examples 14-20, and wherein performing the direct access operation comprises enabling the compute sled to read data from the identified memory region of the accelerator device.

[0129] Example 22 includes the subject matter of any of Examples 14-21, and wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and wherein providing accelerator abstraction data comprises providing accelerator abstraction data representing the plurality of accelerator devices as a single logical device.

[0130] Example 23 includes the subject matter of any of Examples 14-22, and wherein providing the accelerator abstraction data comprises providing accelerator abstraction data representing the accelerator device as a plurality of logical devices.

[0131] Example 24 includes the subject matter of any of Examples 14-23, and wherein the accelerator device is a field programmable gate array having a plurality of slots, and wherein providing the accelerator abstraction data representing the accelerator device as a plurality of logical devices comprises providing accelerator abstraction data representing each slot as a different logical device.

[0132] Example 25 includes the subject matter of any of Examples 14-24, and wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled, the method further comprising identifying, by the accelerator sled, the accelerator devices present on the accelerator sled and the memory region of each accelerator device accessible by the compute sled.

[0133] Example 26 includes the subject matter of any of Examples 14-25, and wherein identifying a region of each accelerator device accessible by the compute sled comprises identifying one or more of: a random access memory region, a user command register region, or a management command register region.

[0134] Example 27 includes an accelerator skid comprising components for performing the method of any of Examples 14-26.

[0135] Example 28 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause the accelerator sled to perform the method of any of Examples 14-26.

[0136] Example 29 includes an accelerator sled comprising a compute engine that performs the method of any of Examples 14-26.

[0137] Example 30 includes an accelerator sled comprising: an accelerator device; an access manager circuit that provides accelerator abstraction data to a compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region; a network communicator circuit that receives a request from the compute sled to perform an operation on an identified memory region of the accelerator device using a corresponding access mode; wherein the access manager circuit is further to convert the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; and in response to the request, perform the operation on the identified memory region of the accelerator device using the corresponding access mode.

[0138] Example 31 includes the subject matter of Example 30, and wherein performing the operation on the identified memory region comprises performing the operation in a proxy mode.

[0139] Example 32 includes the subject matter of any of Examples 30 and 31, and wherein performing the operation in proxy mode comprises: comparing the requested operation with policy data indicating whether one or more operations are allowed or not allowed; and performing the requested operation on an identified memory area of the accelerator device in response to a determination that the requested operation is allowed.

[0140] Example 33 includes the subject matter of any of Examples 30-32, and wherein performing the requested operation comprises performing the requested operation on a management command register.

[0141] Example 34 includes the subject matter of any of Examples 30-33, and wherein performing the requested operation comprises reprogramming the accelerator device or resetting the accelerator device.

[0142] Example 35 includes the subject matter of any of Examples 30-34, and wherein performing the operation on the identified memory region of the accelerator device comprises performing a direct access operation.

[0143] Example 36 includes the subject matter of any of Examples 30-35, and wherein performing the direct access operation comprises enabling the compute sled to write data to the identified memory region of the accelerator device.

[0144] Example 37 includes the subject matter of any of Examples 30-36, and wherein performing the direct access operation comprises enabling the compute sled to read data from the identified memory region of the accelerator device.

[0145] Example 38 includes the subject matter of any of Examples 30-37, and wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and wherein providing accelerator abstract data comprises providing accelerator abstract data representing the plurality of accelerator devices as a single logical device.

[0146] Example 39 includes the subject matter of any of Examples 30-38, and wherein providing the accelerator abstraction data comprises providing accelerator abstraction data representing the accelerator device as a plurality of logical devices.

[0147] Example 40 includes the subject matter of any of Examples 30-39, and wherein the accelerator device is a field programmable gate array having a plurality of slots, and providing the accelerator abstraction data representing the accelerator device as a plurality of logical devices comprises providing accelerator abstraction data representing each slot as a different logical device.

[0148] Example 41 includes the subject matter of any of Examples 30-40, and wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled, and the access manager circuit is further to identify the accelerator devices present on the sled and the memory region of each accelerator device accessible by the compute sled.

[0149] Example 42 includes the subject matter of any of Examples 30-41, and wherein identifying a region of each accelerator device accessible by the compute sled comprises identifying one or more of: a random access memory region, a user command register region, or a management command register region.

[0150] Example 43 includes an accelerator sled comprising: an accelerator device; means for providing accelerator abstraction data to a compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region; circuitry for receiving a request from the compute sled to perform an operation on an identified memory region of the accelerator device using a corresponding access mode; means for converting the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; and means for performing the operation on the identified memory region of the accelerator device using the corresponding access mode in response to the request.

[0151] Example 44 includes the subject matter of Example 43, and wherein means for performing the operation on the identified memory region comprises means for performing the operation in a proxy mode.

[0152] Example 45 includes the subject matter of any of Examples 43 and 44, and wherein the means for performing the operation in proxy mode includes: means for comparing the requested operation with policy data indicating whether one or more operations are allowed or not allowed; and means for performing the requested operation on the identified memory area of the accelerator device in response to a determination that the requested operation is allowed.

[0153] Example 46 includes the subject matter of any of Examples 43-45, and wherein the means for performing the requested operation comprises circuitry for performing the requested operation on a management command register.

[0154] Example 47 includes the subject matter of any of Examples 43-46, and wherein the means for performing the requested operation comprises circuitry for reprogramming the accelerator device or resetting the accelerator device.

[0155] Example 48 includes the subject matter of any of Examples 43-47, and wherein the means for performing the operation on the identified memory region of the accelerator device comprises circuitry for performing a direct access operation.

[0156] Example 49 includes the subject matter of any of Examples 43-48, and wherein the means for performing the direct access operation comprises circuitry for enabling the compute sled to write data to the identified memory region of the accelerator device.

[0157] Example 50 includes the subject matter of any of Examples 43-49, and wherein the circuitry for performing the direct access operation comprises circuitry for enabling the compute sled to read data from the identified memory region of the accelerator device.

[0158] Example 51 includes the subject matter of any of Examples 43-50, and wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and wherein the means for providing accelerator abstraction data comprises circuitry for providing accelerator abstraction data representing the plurality of accelerator devices as a single logical device.

[0159] Example 52 includes the subject matter of any of Examples 43-51, and wherein the means for providing the accelerator abstraction data comprises circuitry for providing accelerator abstraction data representing the accelerator device as a plurality of logic devices.

[0160] Example 53 includes the subject matter of any of Examples 43-52, and wherein the accelerator device is a field programmable gate array having a plurality of slots, and the circuitry for providing the accelerator abstraction data representing the accelerator device as a plurality of logical devices includes circuitry for providing accelerator abstraction data representing each slot as a different logical device.

[0161] Example 54 includes the subject matter of any of Examples 43-53, and wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled, and the computing device further comprises circuitry for identifying the accelerator devices present on the sled and the memory region of each accelerator device accessible by the computing sled.

[0162] Example 55 includes the subject matter of any of Examples 43-54, and wherein the circuitry for identifying a region of each accelerator device accessible by the compute sled comprises circuitry for identifying one or more of: a random access memory region, a user command register region, and a management command register region.

[0163] The present invention also provides the following technical solutions:

[0164] 1. An accelerator skid, comprising:

[0165] accelerator device;

[0166] A controller connected to the accelerator device, wherein the controller is to (i) provide accelerator abstraction data to the compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region; (ii) receive a request from the compute sled to perform an operation on an identified memory region of the accelerator device using a corresponding access mode; (iii) convert the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; and (iv) perform the operation on the identified memory region of the accelerator device using the corresponding access mode in response to the request.

[0167] . An accelerator skid as described in technical solution 1, wherein performing the operation on the identified memory area includes performing the operation in a proxy mode.

[0168] The accelerator skid according to technical solution 2, wherein performing the operation in proxy mode comprises:

[0169] comparing the requested operation to policy data indicating whether one or more operations are allowed or not allowed; and

[0170] The requested operation is performed on the identified memory region of the accelerator device in response to a determination that the requested operation is allowed.

[0171] . An accelerator sled as described in Technical Solution 3, wherein executing the requested operation includes executing the requested operation on a management command register.

[0172] . The accelerator sled as described in Technical Solution 3, wherein executing the requested operation includes reprogramming the accelerator device or resetting the accelerator device.

[0173] . The accelerator sled as described in technical solution 1, wherein performing the operation on the identified memory area of the accelerator device includes performing a direct access operation.

[0174] . The accelerator sled as described in technical solution 6, wherein performing the direct access operation includes enabling the computing sled to write data to the identified memory area of the accelerator device.

[0175] . The accelerator sled as described in technical solution 6, wherein performing the direct access operation includes enabling the computing sled to read data from the identified memory area of the accelerator device.

[0176] The accelerator skid according to claim 1, wherein the accelerator device is one of a plurality of accelerator devices on the accelerator skid; and

[0177] Wherein providing the accelerator abstraction data comprises providing accelerator abstraction data representing the plurality of accelerator devices as a single logical device.

[0178] . The accelerator sled as described in technical solution 1, wherein providing the accelerator abstract data includes providing accelerator abstract data that represents the accelerator device as multiple logical devices.

[0179] . An accelerator sled as described in technical solution 10, wherein the accelerator device is a field programmable gate array having multiple slots, and providing the accelerator abstract data representing the accelerator device as multiple logical devices includes providing accelerator abstract data representing each slot as a different logical device.

[0180] . An accelerator sled as described in technical solution 1, wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled, and the controller further identifies the accelerator devices present on the sled and the memory area of each accelerator device accessible by the computing sled.

[0181] One or more machine-readable storage media, comprising a plurality of instructions stored thereon that, in response to being executed, cause an accelerator sled to:

[0182] providing accelerator abstraction data to a compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region;

[0183] receiving, from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode;

[0184] converting the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; and

[0185] The operation is performed on the identified memory region of the accelerator device with the corresponding access mode in response to the request.

[0186] . One or more machine-readable storage media as described in technical solution 13, wherein performing the operation on the identified memory area includes performing the operation in proxy mode.

[0187] One or more machine-readable storage media as described in technical solution 14, wherein performing the operation in proxy mode includes:

[0188] comparing the requested operation to policy data indicating whether one or more operations are allowed or not allowed; and

[0189] The requested operation is performed on the identified memory region of the accelerator device in response to a determination that the requested operation is allowed.

[0190] . One or more machine-readable storage media as described in technical solution 15, wherein executing the requested operation includes executing the requested operation on a management command register.

[0191] . One or more machine-readable storage media as described in technical solution 15, wherein executing the requested operation includes reprogramming or resetting the accelerator device.

[0192] . One or more machine-readable storage media as described in technical solution 13, wherein performing the operation on the identified memory area of the accelerator device includes performing a direct access operation.

[0193] . One or more machine-readable storage media as described in technical solution 18, wherein performing the direct access operation includes enabling the computing sled to write data to the identified memory area of the accelerator device.

[0194] . One or more machine-readable storage media as described in technical solution 18, wherein performing the direct access operation includes enabling the computing sled to read data from the identified memory area of the accelerator device.

[0195] One or more machine-readable storage media as described in technical solution 13, wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and

[0196] Wherein providing the accelerator abstraction data comprises providing accelerator abstraction data representing the plurality of accelerator devices as a single logical device.

[0197] . One or more machine-readable storage media as described in technical solution 13, wherein providing the accelerator abstraction data includes providing accelerator abstraction data that represents the accelerator device as multiple logical devices.

[0198] . One or more machine-readable storage media as described in technical solution 22, wherein the accelerator device is a field programmable gate array having multiple slots, and providing the accelerator abstract data representing the accelerator device as multiple logical devices includes providing accelerator abstract data representing each slot as a different logical device.

[0199] . One or more machine-readable storage media as described in technical solution 13, wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled, and the plurality of instructions, when executed, further cause the accelerator sled to identify the accelerator devices present on the sled and the memory area of each accelerator device accessible by the computing sled.

[0200] An accelerator skid, comprising:

[0201] accelerator device;

[0202] means for providing accelerator abstraction data to the compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region;

[0203] circuitry for receiving a request from the compute sled to perform an operation on an identified memory region of the accelerator device with a corresponding access mode;

[0204] means for converting the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation;

[0205] Means for performing the operation on the identified memory region of the accelerator device with the corresponding access mode in response to the request.

[0206] A method comprising:

[0207] providing, by an accelerator sled including an accelerator device connected to a controller, accelerator abstraction data to a compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region;

[0208] receiving, by the accelerator sled and from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode;

[0209] converting, with the controller, the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; and

[0210] The operation is performed by the accelerator sled and in response to the request on the identified memory region of the accelerator device with the corresponding access mode.

[0211] . A method as described in technical solution 26, wherein performing the operation on the identified memory area includes performing the operation in proxy mode.

[0212] The method of technical solution 27, wherein performing the operation in proxy mode includes:

[0213] comparing the requested operation to policy data indicating whether one or more operations are allowed or not allowed; and

[0214] The requested operation is performed on the identified memory region of the accelerator device in response to a determination that the requested operation is allowed.

Claims

1. An accelerator skid, comprising: accelerator device; a controller coupled to the accelerator device, wherein the controller (i) is to provide accelerator abstraction data to the compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region; (ii) receiving a request from the compute sled to perform an operation on the identified memory region of the accelerator device using a corresponding access mode; (iii) converting the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; and (iv) performing the operation on the identified memory area of the accelerator device using the corresponding access mode in response to the request, wherein performing the operation on the identified memory area includes performing the operation in a proxy mode, wherein performing the operation in the proxy mode includes: comparing the requested operation to policy data indicating whether one or more operations are allowed or not allowed; as well as The requested operation is performed on the identified memory region of the accelerator device in response to a determination that the requested operation is allowed. 2 . The accelerator sled of claim 1 , wherein performing the requested operation comprises performing the requested operation on a management command register. 3 . The accelerator sled of claim 1 , wherein performing the requested operation comprises reprogramming the accelerator device or resetting the accelerator device.

4. The accelerator sled of claim 1 , wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and Wherein providing the accelerator abstraction data comprises providing accelerator abstraction data representing the plurality of accelerator devices as a single logical device. 5 . The accelerator sled of claim 1 , wherein providing the accelerator abstraction data comprises providing accelerator abstraction data representing the accelerator device as a plurality of logical devices.

6. The accelerator sled of claim 5, wherein the accelerator device is a field programmable gate array having a plurality of slots, and providing the accelerator abstraction data representing the accelerator device as a plurality of logical devices comprises providing accelerator abstraction data representing each slot as a different logical device.

7. The accelerator sled of claim 1 , wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled, and the controller is further to identify the accelerator devices present on the sled and the memory region of each accelerator device accessible by the compute sled.

8. An accelerator skid, comprising: accelerator device; a controller coupled to the accelerator device, wherein the controller (i) is to provide accelerator abstraction data to the compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region; (ii) receiving a request from the compute sled to perform an operation on the identified memory region of the accelerator device using a corresponding access mode; (iii) converting the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; and (iv) performing the operation on the identified memory area of the accelerator device using the corresponding access mode in response to the request, wherein performing the operation on the identified memory area of the accelerator device includes performing a direct access operation, wherein performing the direct access operation includes enabling the compute sled to write data to the identified memory area of the accelerator device, wherein performing the direct access operation includes enabling the compute sled to read data from the identified memory area of the accelerator device.

9. The accelerator sled of claim 8, wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and Wherein providing the accelerator abstraction data comprises providing accelerator abstraction data representing the plurality of accelerator devices as a single logical device.

10. The accelerator sled of claim 8, wherein providing the accelerator abstraction data comprises providing accelerator abstraction data representing the accelerator device as a plurality of logical devices.

11. The accelerator sled of claim 10, wherein the accelerator device is a field programmable gate array having a plurality of slots, and providing the accelerator abstraction data representing the accelerator device as a plurality of logical devices comprises providing accelerator abstraction data representing each slot as a different logical device.

12. The accelerator sled of claim 8, wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled, and the controller is further to identify the accelerator devices present on the sled and the memory region of each accelerator device accessible by the compute sled.

13. An accelerator skid, comprising: accelerator device; means for providing accelerator abstraction data to the compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region; circuitry for receiving a request from the compute sled to perform an operation on an identified memory region of the accelerator device with a corresponding access mode; means for converting the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; means for performing the operation on the identified memory region of the accelerator device with the corresponding access mode in response to the request, wherein the means for performing the operation on the identified memory region comprises means for performing the operation in a proxy mode, wherein the means for performing the operation in the proxy mode comprises: means for comparing a requested operation to policy data indicating whether one or more operations are allowed or not allowed; as well as Means for performing the requested operation on the identified memory region of the accelerator device in response to a determination that the requested operation is allowed.

14. The accelerator sled of claim 13, wherein the means for performing the requested operation comprises circuitry for performing the requested operation on a management command register.

15. The accelerator sled of claim 13, wherein the means for performing the requested operation includes circuitry for reprogramming or resetting the accelerator device.

16. The accelerator sled of claim 13, wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and Wherein the means for providing the accelerator abstraction data comprises circuitry for providing accelerator abstraction data representing the plurality of accelerator devices as a single logical device.

17. The accelerator sled of claim 13, wherein the means for providing the accelerator abstraction data comprises circuitry for providing accelerator abstraction data representing the accelerator device as a plurality of logical devices.

18. The accelerator sled of claim 17, wherein the accelerator device is a field programmable gate array having a plurality of slots, and the circuitry for providing the accelerator abstraction data representing the accelerator device as a plurality of logical devices comprises circuitry for providing accelerator abstraction data representing each slot as a different logical device.

19. The accelerator sled of claim 13, wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled, and the accelerator sled further comprises circuitry for identifying the accelerator devices present on the sled and the memory region of each accelerator device accessible by the compute sled.

20. An accelerator skid, comprising: accelerator device; means for providing accelerator abstraction data to the compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region; circuitry for receiving a request from the compute sled to perform an operation on an identified memory region of the accelerator device with a corresponding access mode; means for converting the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; A component for performing the operation on the identified memory area of the accelerator device using the corresponding access mode in response to the request, wherein the component for performing the operation on the identified memory area of the accelerator device includes a circuit for performing a direct access operation, wherein the component for performing the direct access operation includes a circuit for enabling the compute sled to write data to the identified memory area of the accelerator device, and wherein the component for performing the direct access operation includes a circuit for enabling the compute sled to read data from the identified memory area of the accelerator device.

21. The accelerator sled of claim 20, wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and Wherein the means for providing the accelerator abstraction data comprises circuitry for providing accelerator abstraction data representing the plurality of accelerator devices as a single logical device.

22. The accelerator sled of claim 20, wherein the means for providing the accelerator abstraction data comprises circuitry for providing accelerator abstraction data representing the accelerator device as a plurality of logical devices.

23. The accelerator sled of claim 22, wherein the accelerator device is a field programmable gate array having a plurality of slots, and the circuitry for providing the accelerator abstraction data representing the accelerator device as a plurality of logical devices comprises circuitry for providing accelerator abstraction data representing each slot as a different logical device.

24. The accelerator sled of claim 20, wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled, and the compute sled further comprises circuitry for identifying the accelerator devices present on the sled and the memory region of each accelerator device accessible by the compute sled.

25. A method comprising: providing, by an accelerator sled including an accelerator device connected to a controller, accelerator abstraction data to a compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region; receiving, by the accelerator sled and from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode; converting, with the controller, the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; as well as performing, by the accelerator sled and in response to the request, the operation on the identified memory region of the accelerator device with the corresponding access mode, Wherein performing the operation on the identified memory area includes performing the operation in a proxy mode, wherein performing the operation in the proxy mode includes: comparing the requested operation to policy data indicating whether one or more operations are allowed or not allowed; as well as The requested operation is performed on the identified memory region of the accelerator device in response to a determination that the requested operation is allowed.

26. A method comprising: providing, by an accelerator sled including an accelerator device connected to a controller, accelerator abstraction data to a compute sled, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and the accelerator abstraction data defines an access mode that can be used to access each corresponding memory region; receiving, by the accelerator sled and from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode; converting, with the controller, the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; as well as performing, by the accelerator sled and in response to the request, the operation on the identified memory region of the accelerator device with the corresponding access mode, Wherein performing the operation on the identified memory area of the accelerator device includes performing a direct access operation, wherein performing the direct access operation includes enabling the compute sled to write data to the identified memory area of the accelerator device, wherein performing the direct access operation includes enabling the compute sled to read data from the identified memory area of the accelerator device.

27. A computer readable medium having stored thereon instructions which, when executed, cause a computing device to perform the method of claim 25.

28. A computer readable medium having stored thereon instructions which, when executed, cause a computing device to perform the method of claim 26.

29. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform the method according to claim 25.

30. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform the method according to claim 26.

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