Semiconductor device package and method for manufacturing semiconductor device package

Abstract

The present application relates to a semiconductor device package and a method for manufacturing a semiconductor device package. The present invention provides a substrate, which includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer and including an interconnection structure, and an interconnection element. The interconnection element extends from the first surface of the first dielectric layer to the second surface of the first dielectric layer and is surrounded by the interconnection structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor device packaging, and to a substrate including a dielectric layer, a patterned conductive layer including an interconnect structure, and an interconnect element surrounded by the interconnect structure. Background Art

[0002] Semiconductor device packages may include interconnect elements (eg, conductive vias) for electrical connection between two or more conductive layers separated or insulated by insulating / dielectric layers. However, such structures may be problematic in certain respects. Summary of the invention

[0003] In some embodiments, according to one aspect, a substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer and including an interconnect structure, and an interconnect element. The interconnect element extends from the first surface of the first dielectric layer to the second surface of the first dielectric layer and is surrounded by the interconnect structure.

[0004] In some embodiments, according to another aspect, the substrate includes a dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the dielectric layer and including an interconnect structure, and an interconnect element having a first surface and a second surface and tapering from the first surface to the second surface. The interconnect element extends from the first surface of the dielectric layer to the second surface of the dielectric layer and is surrounded by the interconnect structure.

[0005] In some embodiments, according to another aspect, the substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer and including an interconnect structure, a second patterned conductive layer adjacent to the second surface of the first dielectric layer, and an interconnection element electrically connecting the first patterned conductive layer to the second patterned conductive layer and surrounded by the interconnect structure. The interconnection element and at least a portion of the second patterned conductive layer are formed as a single structure.

[0006] In some embodiments, according to another aspect, a semiconductor device package includes a substrate and a semiconductor device. The substrate includes a dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the dielectric layer and including an interconnect structure, and an interconnect element having a first surface and a second surface and tapering from the first surface to the second surface. The interconnect element extends from the first surface of the dielectric layer to the second surface of the dielectric layer and is surrounded by the interconnect structure. The semiconductor device is disposed on the substrate and electrically connected to the interconnect structure.

[0007] In some embodiments, according to another aspect, a method for manufacturing a substrate is disclosed. The method includes: providing a carrier and a conductive layer; patterning the conductive layer to form a patterned conductive layer including a conductive pad, the conductive pad including an interconnect structure defining an opening; forming a first dielectric layer on the patterned conductive layer, the first dielectric layer having a first surface and a second surface opposite to the first surface; forming an opening in the first dielectric layer, the opening of the conductive pad and the opening of the first dielectric layer being continuous; forming an interconnect element in the opening of the first dielectric layer so that the interconnect element extends to the opening of the interconnect structure and is surrounded by the interconnect structure; and removing the carrier. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A A cross-sectional view illustrating a substrate according to some embodiments of the present disclosure.

[0009] Figure 1B Illustrated are cross-sectional views of interconnect elements according to some embodiments of the present disclosure.

[0010] Figure 1C A top view of a substrate according to some embodiments of the present disclosure is illustrated.

[0011] Figure 1D A top view of a substrate according to some embodiments of the present disclosure is illustrated.

[0012] Figure 1E Illustrated are cross-sectional views of interconnect elements according to some embodiments of the present disclosure.

[0013] Figure 1F Illustrated are cross-sectional views of interconnect elements according to some embodiments of the present disclosure.

[0014] Figure 1G Illustrated are cross-sectional views of interconnect elements according to some embodiments of the present disclosure.

[0015] Figure 1H Illustrated are cross-sectional views of interconnect elements according to some embodiments of the present disclosure.

[0016] Figure 2 A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0017] Figure 3A A cross-sectional view illustrating a substrate according to some embodiments of the present disclosure.

[0018] Figure 3B Illustrated are cross-sectional views of interconnect elements according to some embodiments of the present disclosure.

[0019] Figure 3C Illustrated are cross-sectional views of interconnect elements according to some embodiments of the present disclosure.

[0020] Figure 3D A top view of a substrate according to some embodiments of the present disclosure is illustrated.

[0021] Figure 3E A top view of a substrate according to some embodiments of the present disclosure is illustrated.

[0022] Figure 4 A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0023] Figure 5A A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0024] Figure 5B A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0025] Figure 5C A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0026] Figure 5D A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0027] Figure 5E A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0028] Fig. 6A A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0029] Figure 6B A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0030] Figure 6C A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0031] Fig.6D A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0032] Fig. 6E A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0033] Fig. 6F A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0034] Figure 6G A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0035] Figure 6H A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0036] Fig.6IA method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0037] Figure 6J A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0038] Figure 6K A method of manufacturing a substrate according to some embodiments of the present disclosure is described.

[0039] Figure 7 A cross-sectional view illustrating a comparative substrate according to some embodiments of the present disclosure.

[0040] Fig. 8A A cross-sectional view illustrating a comparative substrate according to some embodiments of the present disclosure.

[0041] Figure 8B A top view of a comparative substrate according to some embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0042] Common reference numerals are used throughout the drawings and detailed description to refer to the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description made in conjunction with the accompanying drawings.

[0043] Spatial descriptions such as "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "above," "below," etc. are specified relative to a component or group of components or a plane of a component or group of components for orienting one or more components as shown in the associated figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner, with the proviso that the advantages of the embodiments of the present disclosure will not be deviated by such arrangements.

[0044] Figure 1A is a cross-sectional view of a substrate 1 according to some embodiments of the present disclosure. The substrate 1 comprises a dielectric layer 10, a patterned conductive layer 11, a dielectric layer 12, an interconnection element 13 and a patterned conductive layer 15.

[0045] The dielectric layer 10 has a surface 10a and a surface 10b opposite to the surface 10a. The dielectric layer 10 includes a resin layer and glass fibers.

[0046] The patterned conductive layer 11 is adjacent to the surface 10a of the dielectric layer 10. The patterned conductive layer 11 includes a conductive pad 111 and a conductive trace 112 adjacent to the conductive pad 111. The conductive pad 111 includes an interconnect structure, such as a ring / ring-shaped structure. The conductive pad 111 and the conductive trace 112 of the patterned conductive layer 11 are embedded in the dielectric layer 10.

[0047] The patterned conductive layer 15 is adjacent to the surface 10b of the dielectric layer 10. The patterned conductive layer 15 includes a conductive pad 151 and a conductive trace 152 adjacent to the conductive pad 151. The conductive pad 151 and the conductive trace 152 of the patterned conductive layer 15 are disposed on the surface 10b of the dielectric layer 10. In some embodiments, the width of the conductive trace 112 of the patterned conductive layer 11 is smaller than the width of the conductive trace 152 of the patterned conductive layer 15 (for example, the ratio of the width of the conductive trace 112 to the width of the conductive trace 152 is about 0.9 or less, about 0.8 or less, or about 0.7 or less). The length of the conductive trace 112 of the patterned conductive layer 11 is smaller than the length of the conductive trace 152 of the patterned conductive layer 15 (for example, the ratio of the length of the conductive trace 112 to the length of the conductive trace 152 is about 0.9 or less, about 0.8 or less, or about 0.7 or less).

[0048] The interconnection element 13 includes a portion 131 and a portion 132. The interconnection element 13 extends at least from the surface 10a of the dielectric layer 10 to the surface 10b of the dielectric layer 10. The portion 131 of the interconnection element 13 is surrounded by the ring / ring-shaped structure of the conductive pad 111. The portion 132 of the interconnection element 13 is covered by the conductive pad 111. The interconnection element 13 electrically connects the conductive pad 111 of the patterned conductive layer 11 to the conductive pad 151 of the patterned conductive layer 15. The interconnection element 13 may be a conductive via. The interconnection element 13 may be or may include copper, aluminum, gold, another metal, a metal alloy, another suitable conductive material, or a combination thereof. The material of the interconnection element 13 may be the same as or different from the material of the patterned conductive layer 11 or 15.

[0049] Portion 131 has a cylindrical structure. Portion 132 has a cone structure. In some embodiments, portion 131 has a cylindrical structure. Portion 131 may be a solid cylindrical column, a solid square column, or a solid column having another suitable polygonal or non-polygonal shape. Portion 132 has a cone structure or a volcanic cone structure. Portion 131 is embedded in the ring / ring structure of conductive pad 111.

[0050] The dielectric layer 12 is disposed on the surface 10b of the dielectric layer 10. The dielectric layer 12 defines an opening to partially expose the conductive pad 151. The conductive trace 152 is covered by the dielectric layer 12.

[0051] Figure 1Bis a cross-sectional view of an interconnection element 13 according to some embodiments of the present disclosure, and shows Figure 1A Magnified view of the area delimited by the dashed line in FIG.

[0052] The conductive pad 111 has a surface 111a. The surface 111a of the conductive pad 111 is substantially coplanar with the surface 10a of the dielectric layer 10. The surface 131u of the portion 131 is substantially coplanar with the surface 10a of the dielectric layer 10. The conductive pad 111 has a width W4 (eg, diameter or width).

[0053] The substrate 1 also includes a patterned conductive layer 133, such as Figure 1B . The patterned conductive layer 133 includes a portion 133a, a portion 133b, and a portion 133c. The portion 131 of the interconnection element 13 includes a portion 131a and a portion 133a of the patterned conductive layer 133. The portion 132 of the interconnection element 13 includes a portion 132a and a portion 133b of the patterned conductive layer 133. The portion 133c of the patterned conductive layer 133 contacts the conductive pad 151. The patterned conductive layer 133 is a seed layer. The patterned conductive layer 133 contacts the ring / ring-shaped structure of the dielectric layer 10 and the patterned conductive layer 11. The surface 131u of the portion 131 may be the surface of the portion 133a of the patterned conductive layer 133.

[0054] The interconnection element 13 has a surface 131u and a surface 1321 opposite to the surface 131u. The surface 1321 is a surface of the portion 132 of the interconnection element 13, and the surface 1321 is substantially coplanar with the surface 10b of the dielectric layer 10. The interconnection element 13 tapers from the surface 1321 to the surface 131u (e.g., the width of the interconnection element 13 becomes smaller (e.g., gradually smaller) from the surface 1321 to the surface 131u). The width W1 of the portion 131 (e.g., the maximum width of the portion 131) is smaller than the width W2 of the portion 132 (e.g., the minimum width of the portion 132). For example, the ratio of the width W1 to the width W2 may be about 0.9 or less, about 0.8 or less, or about 0.7 or less. The width W2 of the portion 132 is smaller than the width W3 of the portion 132 of the interconnection element 13 (e.g., the maximum width of the portion 132). Portion 132 tapers from a lower surface of portion 132 to an upper surface of portion 132. Width W4 of conductive pad 111 is greater than or equal to width W2 of portion 132 of interconnection element 13. For example, a ratio of width W2 to width W4 may be about 0.9 or less, about 0.8 or less, or about 0.7 or less.

[0055] The size (e.g., length or width) of the conductive pad 111 can be flexibly specified. The width W4 of the conductive pad 111 can be less than or equal to the width W3 of the portion 132. For example, the ratio of the width W4 to the width W3 can be about 0.9 or less, about 0.8 or less, or about 0.7 or less. The width W4 of the conductive pad 111 is in the range of about 75 micrometers (μm) to about 80 μm.

[0056] According to one or more embodiments, the portion 131 of the interconnection element 13 is firmly embedded in the ring / annular structure of the conductive liner 111. Since the interconnection element 13 is substantially surrounded by the conductive liner 111 in a three-dimensional form, the stress at the interface between the interconnection element 13 and the conductive liner 111 is relieved. Cracks formed at the interface can be effectively avoided.

[0057] Figure 1C 1 is a top view of a substrate 1 according to some embodiments of the present disclosure. The ring / ring-shaped structure of the conductive pad 111 in the dielectric layer 10 surrounds a portion 131 of the interconnection element 13 (including the portion 131a and the portion 133a of the patterned conductive layer 133). The shape of the conductive pad 111 or the interconnection element 13 can be set according to design criteria. The shape of the conductive pad 111 can be circular or polygonal. The shape of the ring / ring-shaped structure of the conductive pad 111 can be circular or polygonal.

[0058] Figure 1D is a top view of a substrate according to some embodiments of the present disclosure. Figure 1D The substrate is similar to Figure 1C The substrate 1 is different in that it comprises an interconnection element 13', wherein the interconnection element comprises a portion 131' ( Figure 1D Not shown), part 131' includes two parts 131'a ( Figure 1D The two portions 131'a of the patterned conductive layer 133' of the interconnection element 13' are not shown in the figure and the two portions 133'a of the patterned conductive layer 133' of the interconnection element 13'. The two portions 131'a can be disposed inside the two portions 133'a respectively. The two portions 133'a of the portion 131' of the interconnection element 13' are surrounded by the ring / ring-shaped structure of the conductive pad 111'. Figure 1D The substrate provides a physical connection between the conductive pad 111 ′ and the interconnection element 13 ′.

[0059] Figure 1E is a cross-sectional view of an interconnection element 13 of a substrate 1E according to some embodiments of the present disclosure. Figure 1E The substrate 1E is similar to Figure 1BThe present invention is a substrate 1 of the present invention, except that the width W4' of the conductive pad 111" is substantially equal to the width W2 of the portion 132. The width W4' of the conductive pad 111" is less than the width W3 of the portion 132. For example, the ratio of the width W4' to the width W3 can be about 0.9 or less, about 0.8 or less, or about 0.7 or less. The width W4' of the conductive pad 111" is in the range of about 25 μm to about 30 μm. With this configuration, the surface density of the patterned conductive layer 11 can be increased.

[0060] Figure 1F is a cross-sectional view of an interconnection element 13 ″ of a substrate 1F according to some embodiments of the present disclosure. Figure 1F The substrate 1F is similar to Figure 1B The present invention is a substrate 1 of the present invention, except that the dielectric layer 16 is disposed on the portion 131″ of the interconnection element 13″ and is surrounded by the ring / annular structure of the conductive pad 111. The surface 10a of the dielectric layer 10 and the upper surface of the dielectric layer 16 are substantially coplanar. The surface 10a of the dielectric layer 10 is higher than the surface 131″u of the portion 131″. The dielectric layer 16 covers the interconnection element 13″. The material of the dielectric layer 16 may be the same as that of the dielectric layer 10, or may be different from the material of the dielectric layer 10.

[0061] Figure 1G is a cross-sectional view of an interconnection element 13 ′″ of a substrate 1G according to some embodiments of the present disclosure. Figure 1G The substrate 1G is similar to Figure 1B substrate 1, except that the interconnection element 13'" further includes a portion 134 surrounded by a ring / ring-like structure of the conductive pad 151', and the patterned conductive layer 133'" includes portions 133a, 133b and 133'c. Portion 134 includes portion 134a and portion 133'c of the patterned conductive layer 133'". Portion 134 has a cylindrical structure. Portion 134 can be a cylindrical column, a square column, or a column having another suitable polygonal or non-polygonal shape. Portion 134 has a width W5. The width W5 of portion 134 can be less than, substantially equal to, or greater than the width W2 of portion 132.

[0062] Figure 1H is a cross-sectional view of an interconnection element 13"" of a substrate 1H according to some embodiments of the present disclosure. Figure 1H The substrate 1H is similar in some respects to Figure 1Gsubstrate. Substrate 1H includes a patterned conductive layer 133"', which includes portions 133a, 133b and 133"c. For substrate 1H, a width W5' of portion 134' is greater than a width W2 of portion 132 and a width W5' of portion 134' is substantially equal to a width W3 of portion 132. Portion 134' includes portion 134'a and portion 133"c of patterned conductive layer 133". Portion 134' is surrounded by a ring / ring-like structure of a conductive pad 151".

[0063] Figure 2 is a cross-sectional view of a semiconductor device package 2 according to some embodiments of the present disclosure. The semiconductor device package 2 includes a substrate 1, a dielectric layer 20, a connection element 21, an encapsulation body 22, a conductive pillar 23, a solder ball 25, and a semiconductor device 27.

[0064] A dielectric layer 20 is disposed on the substrate 1. The dielectric layer 20 may include a solder resist, such as a passivation material, a resin, or a polymer.

[0065] The connecting element 21 is disposed between the substrate 1 and the conductive pillar 23. The semiconductor device 27 includes an active surface facing the surface 10a of the dielectric layer 10. The semiconductor device 27 is electrically connected to the patterned conductive layer 11 through the connecting element 21 and the conductive pillar 23. The semiconductor device 27 is electrically connected to the ring / ring structure of the conductive pad 111. The semiconductor device 27 can be a flip chip type device. The connecting element 21 contacts the conductive pad 111 of the patterned conductive layer 11 and the interconnection element 13. The connecting element 21 can include a solder material, tin (Sn) or other suitable materials. The conductive pillar 23 can include a conductive metal, such as copper (Cu), gold (Au) or other suitable materials. The encapsulation body 22 is disposed on the surface 10a of the dielectric layer 10. The encapsulation body 22 encapsulates the substrate 1 and the semiconductor device 27. The solder ball 25 is disposed in the opening of the dielectric layer 12. The solder ball 25 is electrically connected to the conductive pad 151.

[0066] Since the interconnection element 13 is embedded in the ring / annular structure of the conductive pad 111 , the shape of the interconnection element 13 can be regular and the interconnection element 13 can be specifically positioned.

[0067] Figure 3A is a cross-sectional view of a substrate 3 according to some embodiments of the present disclosure. The substrate 3 includes a dielectric layer 10, a patterned conductive layer 11, a dielectric layer 12, a dielectric layer 14, a patterned conductive layer 15, an interconnection element 17, and an external conductive pad 19.

[0068] The dielectric layer 10 has a surface 10a and a surface 10b opposite to the surface 10a. The dielectric layer 10 includes a resin layer and glass fibers.

[0069] The patterned conductive layer 11 is adjacent to the surface 10a of the dielectric layer 10. The patterned conductive layer 11 includes a conductive pad 111 and a conductive trace 112 adjacent to the conductive pad 111. The conductive pad 111 includes an interconnect structure, such as a ring / ring-shaped structure. The conductive pad 111 and the conductive trace 112 of the patterned conductive layer 11 are embedded in the dielectric layer 10.

[0070] The patterned conductive layer 15 is adjacent to the surface 10b of the dielectric layer 10. The patterned conductive layer 15 includes a conductive pad 151 and a conductive trace 152 adjacent to the conductive pad 151. The conductive pad 151 and the conductive trace 152 of the patterned conductive layer 15 are disposed on the surface 10b of the dielectric layer 10. In some embodiments, the width of the conductive trace 112 of the patterned conductive layer 11 is smaller than the width of the conductive trace 152 of the patterned conductive layer 15 (for example, the ratio of the width of the conductive trace 112 to the width of the conductive trace 152 is about 0.9 or less, about 0.8 or less, or about 0.7 or less). The length of the conductive trace 112 of the patterned conductive layer 11 is smaller than the length of the conductive trace 152 of the patterned conductive layer 15 (for example, the ratio of the length of the conductive trace 112 to the length of the conductive trace 152 is about 0.9 or less, about 0.8 or less, or about 0.7 or less).

[0071] The interconnection element 17 includes a portion 171 and a portion 172. The interconnection element 17 extends at least from the surface 10a of the dielectric layer 10 to the surface 10b of the dielectric layer 10. The portion 171 of the interconnection element 17 is surrounded by the ring / ring-shaped structure of the conductive pad 111. The portion 172 of the interconnection element 17 is covered by the conductive pad 111. The interconnection element 17 electrically connects the conductive pad 111 of the patterned conductive layer 11 to the conductive pad 151 of the patterned conductive layer 15. The interconnection element 17 may be a conductive via. The interconnection element 17 may be or may include copper, aluminum, gold, another metal, a metal alloy, another suitable conductive material, or a combination thereof. The material of the interconnection element 17 may be the same as or different from the material of the patterned conductive layer 11 or 15.

[0072] Portion 171 has a cylindrical structure. Portion 172 has a cone structure. In some embodiments, portion 171 has a cylindrical structure defining an upper recess. Portion 171 can be a solid cylindrical column, a solid square column, or a solid column having another suitable polygonal or non-polygonal shape. Portion 172 has a cone structure or a volcanic cone structure. Portion 171 is embedded in the ring / ring structure of conductive pad 111.

[0073] The dielectric layer 14 is disposed on the surface 10a of the dielectric layer 10. The dielectric layer 14 defines an opening to partially expose the portion 171. The patterned conductive layer 11 is covered by the dielectric layer 14.

[0074] The external conductive pad 19 is disposed on the dielectric layer 14. The external conductive pad 19 extends to the interconnection element 17. The external conductive pad 19 is electrically connected to the conductive pad 151 through the interconnection element 17. The external conductive pad 19 contacts the dielectric layer 14 and the portion 171. A portion of the external conductive pad 19 is surrounded by the dielectric layer 14. A portion of the external conductive pad 19 is surrounded by the portion 171. A portion of the external conductive pad 19 is surrounded by the conductive pad 111. The external conductive pad 19 has a T-shape. The external conductive pad 19 has an anchor shape. The external conductive pad 19 includes a portion protruding through the dielectric layer 20 and entering into the portion 171.

[0075] The dielectric layer 12 is disposed on the surface 10b of the dielectric layer 10. The dielectric layer 12 defines an opening to partially expose the conductive pad 151. The conductive trace 152 is covered by the dielectric layer 12.

[0076] Figure 3B is a cross-sectional view of an interconnection element 17 according to some embodiments of the present disclosure, and shows Figure 3A Magnified view of the area delimited by the dashed line in FIG.

[0077] The conductive pad 111 has a surface 111a. The surface 111a of the conductive pad 111 is substantially coplanar with the surface 10a of the dielectric layer 10. The conductive pad 111 has a width W4 (e.g., diameter or width). The portion 171 of the interconnection element 17 has a surface 171u, which includes a curved portion (or a concave portion) having a curved shape and a substantially planar portion. The planar portion of the surface 171u of the portion 171 is substantially coplanar with the surface 111a of the conductive pad 111. The curved portion of the surface 171u of the portion 171 is lower than the surface 111a of the conductive pad 111. The width of the surface 171u of the interconnection element 17 is greater than the width of the opening of the dielectric layer 14.

[0078] The patterned conductive layer 173 includes a portion 173a, a portion 173b, and a portion 173c. The portion 171 of the interconnection element 17 includes a portion 171a and a portion 173a of the patterned conductive layer 173. The portion 172 of the interconnection element 17 includes a portion 172a and a portion 173b of the patterned conductive layer 173. The portion 173c of the patterned conductive layer 173 contacts the conductive pad 151. The patterned conductive layer 173 is a seed layer. The patterned conductive layer 173 contacts the dielectric layer 10, the ring / ring structure of the patterned conductive layer 11, and the dielectric layer 14.

[0079] The interconnection element 17 has a surface 171u and a surface 1721 opposite to the surface 171u. The surface 1721 of the portion 172 and the surface 10b of the dielectric layer 10 are substantially coplanar. The interconnection element 17 tapers from the surface 1721 to the surface 171u. The width W1 of the portion 171 is less than the width W2 of the portion 172 (for example, the ratio of the width W1 to the width W2 is about 0.9 or less, about 0.8 or less, or about 0.7 or less). The width W2 of the portion 172 is less than the width W3 of the portion 172 (for example, the ratio of the width W2 to the width W3 is about 0.9 or less, about 0.8 or less, or about 0.7 or less). The width W3 may be the maximum width of the portion 172. The portion 172 tapers from the lower surface of the portion 172 to the upper surface of the portion 172. The width W4 of the conductive pad 111 is greater than or equal to the width W2 of the portion 172 of the interconnection element 17.

[0080] The size (e.g., length or width) of the conductive pad 111 can be flexibly specified. The width W4 of the conductive pad 111 can be less than or equal to the width W3 of the portion 132 (e.g., the ratio of the width W4 to the width W3 can be about 0.9 or less, about 0.8 or less, or about 0.7 or less). The width W4 of the conductive pad 111 is in the range of about 75 μm to about 80 μm.

[0081] In one or more embodiments, the portion 171 of the interconnection element 17 is firmly embedded in the ring / annular structure of the conductive liner 111. Since the interconnection element 17 is substantially surrounded by the conductive liner 111 in a three-dimensional form, the stress at the interface between the interconnection element 17 and the conductive liner 111 can be relieved. Cracks formed at the interface can be effectively avoided.

[0082] The outer conductive pad 19 includes a portion 191, a portion 192, and a portion 193. The portion 191 is disposed on the dielectric layer 14 and covers the dielectric layer. The portion 192 is embedded in the dielectric layer 14. The portion 193 (also referred to as a protruding portion) is embedded in the ring / annular structure of the conductive pad 111. The portion 193 is surrounded by the portion 171. The portion 193 contacts the dielectric layer 14 and the portion 171a of the portion 171.

[0083] Figure 3C is a cross-sectional view of an interconnection element 17 ′ of a substrate 3C according to some embodiments of the present disclosure. Figure 3C The substrate 3C is similar to Figure 3B The outer conductive pad 19' of the substrate 3C includes a portion 193' (also referred to as a protruding portion) that contacts the dielectric layer 14, the portion 171'a, and a portion 173a of the portion 171' of the interconnection element 17'. The portion 193' of the outer conductive pad 19' may protrude to the interconnection element 17' of the substrate 3C and may contact the portion 172a of the interconnection element 17'. Figure 3C The size of the portion 193' may be greater than Figure 3B The size of the section 193.

[0084] Figure 3D 1 is a top view of a substrate 3 according to some embodiments of the present disclosure. The ring / ring-shaped structure of the conductive pad 111 surrounds a portion 171 of the interconnection element 17 (including the portion 171a and the portion 173a of the patterned conductive layer 173). The shape of the conductive pad 111 or the interconnection element 17 can be set according to design criteria. The shape of the conductive pad 111 can be circular or polygonal. The shape of the ring / ring-shaped structure of the conductive pad 111 can be circular or polygonal.

[0085] Figure 3E is a top view of a substrate 3E according to some embodiments of the present disclosure. Figure 3E The substrate 3E is similar to Figure 3D Substrate 3. In substrate 3E, the conductive pad 111"' includes four slopes (for example, at the corner portion) and the portion 171" includes four slopes (for example, at the corner portion). The shape of the conductive pad 111"' or the ring / ring-like structure of the conductive pad 111"' is an octagon and the shape of the portion 171" (including the portion 171"a and the portion 173'a of the patterned conductive layer 173') is an octagon.

[0086] Figure 4 is a cross-sectional view of a semiconductor device package 4 according to some embodiments of the present disclosure. The semiconductor device package 4 includes a substrate 3, a connecting element 21, an encapsulation body 22, a conductive pillar 23, a solder ball 25, and a semiconductor device 27.

[0087] The connecting element 21 is disposed between the substrate 3 and the conductive pillar 23. The semiconductor device 27 includes an active surface facing the surface 10a of the dielectric layer 10. The semiconductor device 27 is electrically connected to the patterned conductive layer 11 through the connecting element 21, the conductive pillar 23 and the external conductive pad 19. The semiconductor device 27 is electrically connected to the ring / ring structure of the conductive pad 111. The semiconductor device 27 can be a flip chip type device. The connecting element 21 contacts the external conductive pad 19. The connecting element 21 can include a solder material, tin or other suitable materials. The conductive pillar 23 can include Cu, Au or other suitable materials. The encapsulation body 22 is disposed on the surface 10a of the dielectric layer 10. The encapsulation body 22 encapsulates the substrate 3 and the semiconductor device 27. The solder ball 25 is disposed in the opening of the dielectric layer 12. The solder ball 25 is electrically connected to the conductive pad 151.

[0088] Since the interconnection element 17 is embedded in the ring / annular structure of the conductive pad 111 , the shape of the interconnection element 17 can be regular and the interconnection element 17 can be specifically positioned.

[0089] FIG. 5A to FIG. 5E Describe the manufacturing of some embodiments according to the present disclosure Figure 1A 1. In some embodiments, FIG. 5A to FIG. 5E The method can be applied to make Figure 3A In the following description, the formation of a single interconnection element 13 and other components may be described, but in one or more embodiments, the formation of multiple interconnection elements 13 and / or other components may be implemented using the methods described herein.

[0090] refer to Figure 5A , a method for manufacturing a substrate 1 includes providing a carrier 50 and a conductive layer disposed on the carrier 50. The conductive layer is patterned to form a patterned conductive layer 11. A conductive pad 111 and a conductive trace 112 of the patterned conductive layer 11 are defined during the patterning operation. A ring / ring-shaped structure of the conductive pad 111 is defined during the patterning operation. The ring / ring-shaped structure of the conductive pad 111 defines an opening. The size of the pad and the trace can be defined according to design criteria.

[0091] refer to Figure 5B , the dielectric layer 10 is laminated on the carrier 50. Other components, such as a redistribution layer and / or a filler, may be included in the dielectric layer 10.

[0092] refer to Figure 5C The opening 52 is formed in the dielectric layer 10 by a laser drilling operation, a mechanical drilling operation or other suitable operation. The opening of the conductive pad 111 of the patterned conductive layer 11 and the opening 52 of the dielectric layer 10 are continuous.

[0093] Conductive layer 133"" is formed on dielectric layer 10. Conductive layer 133"" is formed in the opening of conductive liner 111 and opening 52 of dielectric layer 10. Conductive layer 133"" is a seed layer. Conductive layer 133"" can be formed by sputtering or chemical vapor deposition (CVD) operation. The thickness of conductive layer 133"" ranges from about 0.2μm to about 0.8μm.

[0094] The patterned conductive layer 11 includes a conductive pad 111 and a conductive trace 112 adjacent to the conductive pad 111. The conductive pad 111 includes a ring / annular structure. During the laser drilling operation, the conductive pad 111 can block the laser so that the shape of the opening 52 is regular and consistent.

[0095] In some embodiments, when the laser drilling operation is completed, there is a residual portion of the dielectric layer 10 disposed in the opening 52. The residual portion may correspond to Figure 1F The remaining portion is disposed in a portion of the opening of the ring / annular structure of the conductive pad 111.

[0096] refer to Figure 5D, a conductive layer is formed in the opening of the conductive pad 111 and the opening 52 of the dielectric layer 10, and is adjacent to the surface 10b of the dielectric layer 10 by an electroplating operation. Subsequently, the conductive layer and the seed layer 133"" are patterned to form an interconnection element 13, a patterned conductive layer 133, and a patterned conductive layer 15 including a conductive pad 151 and a conductive trace 152. The interconnection element 13 extends to the opening of the ring / ring structure of the conductive pad 111 and is surrounded by the ring / ring structure of the conductive pad 111. The interconnection element 13 in the opening 52 may have a regular and consistent shape.

[0097] The interconnection element 13 and at least a portion of the patterned conductive layer 15 (e.g., the conductive pad 151) are integrally formed. The interconnection element 13 and the portion of the patterned conductive layer 15 are formed as a unitary piece or as a single structure. The lattice of the interconnection element 13 and the lattice of the portion of the patterned conductive layer 15 are the same or similar to each other. There is no non-continuous interface between the interconnection element 13 and the portion of the patterned conductive layer 15.

[0098] The materials of the patterned conductive layer 133 and the patterned conductive layer 11 may be different or the same. The materials of the patterned conductive layer 133 and the interconnection element 13 may be different or the same.

[0099] refer to Figure 5E , a dielectric layer 12 is formed on a surface 10b of the dielectric layer 10. The dielectric layer 12 may be a solder resist layer. The dielectric layer 12 defines an opening to expose at least a portion of the patterned conductive layer 15 (e.g., a portion disposed on the interconnection element 13). The dielectric layer 20 is disposed on the surface 10a of the dielectric layer 10. The dielectric layer 20 defines an opening to expose the patterned conductive layer 11. The material of the dielectric layer 20 may be the same as or different from the material of the dielectric layer 12. The carrier 50 is removed.

[0100] FIG. 6A to FIG. 6K Describe the manufacturing of some embodiments according to the present disclosure Figure 3A 3. Method of Substrate 3.

[0101] refer to Fig. 6A , the method for manufacturing the substrate 3 includes providing a carrier 50 and a conductive layer 61 disposed on the carrier 50. The conductive layer 61 is patterned to form a patterned conductive layer 11' on the conductive layer 61. The conductive pads 111 and the conductive traces 112 of the patterned conductive layer 11' are defined during the patterning operation. The ring / ring-shaped structure of the conductive pads is defined during the patterning operation. The ring / ring-shaped structure of the conductive pads defines an opening. The size of the conductive pads 111 and the conductive traces 112 can be set according to design criteria. The conductive layer 61 can be used as a stop layer for subsequent laser drilling operations.

[0102] refer to Figure 6BThe dielectric layer 10 is laminated on the carrier 50 and the patterned conductive layer 11 ′. Other components, such as a redistribution layer and / or a filler, may be included in the dielectric layer 10 .

[0103] refer to Figure 6C The opening 52 is formed in the dielectric layer 10 by a laser drilling operation, a mechanical drilling operation or other suitable operation. The opening of the patterned conductive layer 11' and the opening 52 of the dielectric layer 10 are continuous.

[0104] Conductive layer 173' is formed on dielectric layer 10. Conductive layer 173' is a seed layer. During the laser drilling operation, conductive pad 111 can block the laser so that the shape of opening 52 is regular and consistent. The laser drilling operation can be stopped at stop layer 61. The thickness of the stop layer can be in the range of about 2μm to about 3μm.

[0105] refer to Fig.6D , a conductive layer is formed in the opening and on the surface 10b of the dielectric layer 10 by an electroplating operation. Subsequently, the conductive layer and the seed layer 173' are patterned to form the interconnection element 17, the patterned conductive layer 173, and the patterned conductive layer 15 including the conductive pad 151 and the conductive trace 152. The interconnection element 17 extends to the opening of the ring / ring structure of the conductive pad 111 and is surrounded by the ring / ring structure of the conductive pad 111. The interconnection element 17 in the opening 52 may have a regular and consistent shape.

[0106] The interconnection element 17 and at least a portion of the patterned conductive layer 15 (e.g., the conductive pad 151) are integrally formed. The interconnection element 17 and the portion of the patterned conductive layer 15 are formed as a unitary piece or as a single structure. The lattice of the interconnection element 17 and the lattice of the portion of the patterned conductive layer 15 are the same or similar to each other. There is no non-continuous interface between the interconnection element 17 and the portion of the patterned conductive layer 15.

[0107] refer to Fig. 6E , remove the carrier 50 and remove the stop layer 61 and a portion of the patterned conductive layer 11' to form the patterned conductive layer 11. Remove a portion of the patterned conductive layer 173. The patterned conductive layer 11 includes a conductive pad 111 and a conductive trace 112 adjacent to the conductive pad 111. The conductive pad 111 includes a ring / ring-like structure.

[0108] refer to Fig. 6F, dielectric layer 12 is formed on surface 10b of dielectric layer 10. Dielectric layer 12 may be a solder resist layer. Dielectric layer 12 defines an opening to expose at least a portion of patterned conductive layer 15 (e.g., conductive pad 151). Dielectric layer 14 is formed on surface 10a of dielectric layer 10 and on patterned conductive layer 11. Dielectric layer 14 defines an opening to expose interconnection element 17. Dielectric layer 14 may be a solder resist layer. The material of dielectric layer 14 may be different from the material of dielectric layer 12. Interconnection element 17 includes portion 172 and portion 171".

[0109] refer to Figure 6G An over-etching / micro-etching operation is performed to form an opening 54' defined by the dielectric layer 14 and the interconnection element 17. A portion 171" of the interconnection element 17 is over-etched to form a portion 171 having a surface including a curved portion.

[0110] refer to Figure 6H , a conductive layer 195 is formed on the dielectric layer 12 and the dielectric layer 14. The conductive layer 195 is a seed layer. A first portion of the conductive layer 195 is disposed on the dielectric layer 12, and a second portion of the conductive layer 195 is disposed on the dielectric layer 14.

[0111] refer to Fig.6I , the dielectric layer 51 is disposed on the first portion of the conductive layer 195 disposed on the dielectric layer 12. The dielectric layer 51 may be a dry film or a photoresist layer.

[0112] refer to Figure 6J The conductive layer 19' is formed on the second portion of the conductive layer 195 disposed on the dielectric layer 14 by an electroplating operation. The conductive layer 19' includes the second portion of the conductive layer 195.

[0113] refer to Figure 6K , the conductive layer 19' is patterned to form an external conductive pad 19. The external conductive pad 19 has an anchor shape.

[0114] Figure 7 A cross-sectional view of a comparative substrate 5 is illustrated. The substrate 5 includes a dielectric layer 10, a patterned conductive layer 61, an interconnection element 63, and a conductive layer 65.

[0115] The dielectric layer 10 has a surface 10a and a surface 10b opposite to the surface 10a. The patterned conductive layer 61 includes a conductive pad 611 and a conductive trace 612 adjacent to the conductive pad 611. The patterned conductive layer 65 includes a conductive pad 651 and a conductive trace 652 adjacent to the conductive pad 651. The interconnection element 63 is disposed between the patterned conductive layer 61 and the patterned conductive layer 65.

[0116] The conductive pad 611 of the patterned conductive layer 61 is large so that it can be aligned with the interconnection element 63 during the manufacture of the substrate 5. However, such a conductive pad 611 can reduce the available space on the surface 10a of the dielectric layer 10. In addition, since the interconnection element 63 contacts the conductive pad 611 two-dimensionally, cracks can be easily formed at the position / interface 67 between the conductive pad 611 and the interconnection element 63.

[0117] Fig. 8A is a cross-sectional view of a comparative substrate 6. The substrate 6 comprises a dielectric layer 10, a patterned conductive layer 61', an interconnection element 63' and a conductive layer 65.

[0118] The dielectric layer 10 has a surface 10a and a surface 10b opposite to the surface 10a. The patterned conductive layer 61' includes a conductive pad 611' and a conductive trace 612' adjacent to the conductive pad 611'. The patterned conductive layer 65 includes a conductive pad 651 and a conductive trace 652 adjacent to the conductive pad 651. The interconnection element 63' is disposed between the surface 10a and the surface 10b of the dielectric layer 10.

[0119] The interconnection element 63' is exposed from the surface 10a of the dielectric layer 10, and the interconnection element 63' at the surface 10a ( Figure 8B 63') is larger than the lateral width / dimension of the conductive pad 611' at the surface 10a. In this comparative example, the conductive pad 611' is surrounded by the interconnection element 63'. However, since the interconnection element 63' at the surface 10a of the dielectric layer 10 is exposed, the available space on the surface 10a of the dielectric layer 10 (e.g., the space for routing the trace 612') may be smaller.

[0120] Figure 8B is a top view of a comparative substrate 6 according to some embodiments of the present disclosure. Because higher stress may be concentrated at the location 61c, the location 61c where the conductive pad 611' protrudes from the dielectric layer 10 into the interconnection element 63' may have cracked.

[0121] Furthermore, the interconnection element 63' may be irregularly shaped by the laser drilling operation. The irregular shape of the interconnection element 63' may cause the substrate 6 to be electrically disconnected from the semiconductor device disposed on the substrate 6.

[0122] As used herein and not otherwise defined, the terms "substantially," "substantially," "approximately," and "about" are used to describe and take into account minor variations. When used in conjunction with an event or circumstance, the terms may encompass situations where the event or circumstance clearly occurs as well as situations where the event or circumstance closely approximates to occurring. For example, when used in conjunction with a numerical value, the terms may encompass a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces within a few microns positioned along the same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm positioned along the same plane.

[0123] As used herein, the singular terms "a", "an", and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the former component is directly on (e.g., physically in contact with) the latter component, as well as the case where one or more intermediate components are located between the former component and the latter component.

[0124] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations are not restrictive. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the artistic reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically described. This specification and drawings should be considered illustrative rather than restrictive. Modifications may be made to make specific situations, materials, material compositions, methods or processes suitable for the goals, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limiting.

Claims

1. A substrate comprising: a first dielectric layer having a first surface and a second surface opposite the first surface; a first patterned conductive layer adjacent to the first surface of the first dielectric layer and comprising an interconnect structure embedded in the first dielectric layer and a conductive trace adjacent to the interconnect structure; as well as an interconnection element extending from the first surface of the first dielectric layer to the second surface of the first dielectric layer and surrounded by the interconnection structure, wherein the first surface of the first dielectric layer, a top surface of the interconnect structure, and a top surface of the interconnect element are substantially coplanar, wherein the first patterned conductive layer is embedded in the first dielectric layer, and the first surface of the first dielectric layer is substantially coplanar with a surface of the first patterned conductive layer, The interconnection element comprises a first portion and a second portion, wherein the first portion of the interconnection element comprises a cylindrical structure and the second portion of the interconnection element comprises a conical structure, and wherein a width of the first portion of the interconnection element is smaller than a width of the second portion of the interconnection element. 2 . The substrate of claim 1 , wherein the interconnection element comprises a second patterned conductive layer in contact with the first dielectric layer and the interconnection structure of the first patterned conductive layer.

3. The substrate of claim 1, wherein the first surface of the first dielectric layer is substantially coplanar with a surface of the first portion of the interconnect element, and a width of the interconnect structure is substantially equal to a width of a top surface of the second portion of the interconnect element.

4. The substrate of claim 1, wherein a thickness of the first portion of the interconnect element, a thickness of the interconnect structure, and a thickness of the conductive trace are substantially the same. 5 . The substrate of claim 1 , wherein the interconnect structure completely covers a top surface of the second portion of the interconnect element. 6 . The substrate of claim 1 , wherein a surface of the interconnect element adjacent to the first surface of the first dielectric layer is exposed to air.

7. A substrate comprising: a first dielectric layer having a first surface and a second surface opposite the first surface; a first patterned conductive layer adjacent to the first surface of the first dielectric layer and comprising an interconnect structure embedded in the first dielectric layer and a conductive trace adjacent to the interconnect structure; an interconnect element extending from the first surface of the first dielectric layer to the second surface of the first dielectric layer and surrounded by the interconnect structure; as well as a second patterned conductive layer adjacent to the second surface of the first dielectric layer, wherein the interconnect element electrically connects the first patterned conductive layer to the second patterned conductive layer, wherein the first surface of the first dielectric layer, a top surface of the interconnect structure, and a top surface of the interconnect element are substantially coplanar, The interconnection element comprises a first portion and a second portion, and the second portion of the interconnection element has an upper surface and a lower surface, and the second portion of the interconnection element tapers from the lower surface to the upper surface.

8. The substrate of claim 7, wherein the second surface of the first dielectric layer is substantially coplanar with the lower surface of the second portion of the interconnect element.

9. The substrate of claim 7, further comprising a third dielectric layer defining an opening, wherein the interconnect element is exposed by the opening of the third dielectric layer. 10 . The substrate of claim 9 , wherein a surface of the interconnection element exposed by the third dielectric layer includes a portion having a curved shape. 11 . The substrate of claim 10 , wherein a width of the surface of the interconnection element is greater than a width of the opening of the third dielectric layer. 12 . The substrate of claim 9 , further comprising a conductive pad disposed on the third dielectric layer and extending to the interconnection element, the conductive pad having an anchor shape.

13. The substrate of claim 9, wherein the second patterned conductive layer is a seed layer.

14. A substrate comprising: a dielectric layer having a first surface and a second surface opposite to the first surface; a first patterned conductive layer adjacent to the first surface of the dielectric layer and comprising interconnect structures and conductive traces embedded in the dielectric layer; as well as an interconnecting element having a first surface and a second surface and tapering from the first surface to the second surface, wherein the interconnect element extends from the first surface of the dielectric layer to the second surface of the dielectric layer and is surrounded by the interconnect structure, and wherein a top surface of the interconnect element and a top surface of the interconnect structure constitute a bonding surface, The interconnection element comprises a first portion and a second portion, wherein the first portion of the interconnection element comprises a cylindrical structure and the second portion of the interconnection element comprises a conical structure, and a width of the interconnection structure is less than or equal to a maximum width of the second portion of the interconnection element.

15. The substrate of claim 14, wherein the interconnection element further comprises a second patterned conductive layer in contact with the dielectric layer and the interconnection structure of the first patterned conductive layer, and wherein the interconnection element comprises a seed layer, a top surface of the seed layer being substantially coplanar with a surface of the first patterned conductive layer. 16 . The substrate of claim 15 , wherein a first portion of a side surface of the seed layer contacts the interconnect structure. 17 . The substrate according to claim 16 , wherein the first portion of the side surface of the seed layer is substantially perpendicular to the top surface of the seed layer, and the second portion of the side surface of the seed layer is an inclined surface.

18. The substrate of claim 14, wherein a surface of the interconnect structure adjacent to the first surface of the dielectric layer is exposed to air.

19. A substrate comprising: a dielectric layer having a first surface and a second surface opposite to the first surface; a first patterned conductive layer adjacent to the first surface of the dielectric layer and comprising an interconnect structure; a second patterned conductive layer adjacent to the second surface of the dielectric layer; as well as an interconnection element electrically connecting the first patterned conductive layer to the second patterned conductive layer and surrounded by the interconnection structure, wherein the interconnection element and at least a portion of the second patterned conductive layer are formed as a single body structure, The interconnection element comprises a first part and a second part, wherein the first part of the interconnection element comprises a cylindrical structure and the second part of the interconnection element comprises a conical structure, and the interconnection element is embedded in the interconnection structure in a three-dimensional form, so that the interconnection structure surrounds and contacts the first part of the interconnection element and contacts the second part of the interconnection element.

20. The substrate of claim 19, further comprising: a second dielectric layer disposed on the first patterned conductive layer and defining an opening, wherein the interconnect element is exposed by the opening of the second dielectric layer; as well as A conductive pad is disposed on the second dielectric layer and extends to the interconnection element, a portion of the conductive pad being laterally surrounded by the interconnection structure.

21. A semiconductor device package, comprising: A substrate comprising: a first dielectric layer having a first surface and a second surface opposite the first surface; a first patterned conductive layer adjacent to the first surface of the first dielectric layer and comprising interconnect structures and conductive traces embedded in the first dielectric layer; a second patterned conductive layer adjacent to the second surface of the first dielectric layer; Interconnecting elements; a second dielectric layer disposed on the first patterned conductive layer and defining an opening, wherein the interconnection element is exposed in the opening of the second dielectric layer; and an external conductive liner disposed on the second dielectric layer and extending into the interconnection element, a portion of the external conductive liner being laterally surrounded by the interconnection structure, wherein the top surface of the outer conductive pad constitutes a bonding surface, wherein the interconnection element extends from the first surface of the first dielectric layer to the second surface of the first dielectric layer to electrically connect the first patterned conductive layer and the second patterned conductive layer, and the interconnection element is surrounded by the interconnection structure, and A semiconductor device is disposed on the substrate and electrically connected to the interconnect structure.

22. The semiconductor device package of claim 21, wherein the first patterned conductive layer further comprises a conductive pad including the interconnect structure. 23 . The semiconductor device package of claim 22 , wherein the first patterned conductive layer further comprises a first conductive trace adjacent to the conductive pad. 24 . The semiconductor device package of claim 23 , further comprising a second patterned conductive layer, wherein the interconnection element and at least a portion of the second patterned conductive layer are formed as a single body structure. 25 . The semiconductor device package of claim 24 , wherein the second patterned conductive layer further comprises a second conductive trace, and wherein a width of the first conductive trace of the first patterned conductive layer is smaller than a width of the second conductive trace of the second patterned conductive layer.

26. The semiconductor device package according to claim 23 further comprises a connecting element, and wherein the semiconductor device includes an active surface facing the first surface of the first dielectric layer and electrically connected to the conductive pad of the first patterned conductive layer through the connecting element, and the connecting element contacts the conductive pad of the first patterned conductive layer with the interconnection element.

27. The semiconductor device package of claim 22, wherein a width of the top surface of the outer conductive pad is substantially equal to a width of the interconnect structure.

28. The semiconductor device package of claim 22, wherein the interconnection element comprises a first portion and a second portion, and wherein a width of the conductive pad is greater than or equal to a width of the second portion of the interconnection element.

29. The semiconductor device package of claim 21, further comprising: a second dielectric layer defining an opening, wherein the interconnection element is exposed by the opening of the second dielectric layer, and a surface of the interconnection element exposed by the second dielectric layer includes a portion having a curved shape, and A conductive pad is disposed on the second dielectric layer and extends to the interconnection element, the conductive pad having an anchor shape.

30. The semiconductor device package of claim 21, wherein the interconnect element further comprises a second patterned conductive layer contacting the interconnect structure of the first dielectric layer and the first patterned conductive layer.

31. The semiconductor device package of claim 21, wherein the interconnection element has a first surface and a second surface and tapers from the first surface to the second surface.

32. A method for manufacturing a substrate, comprising: providing a carrier and a conductive layer; patterning the conductive layer to form a patterned conductive layer including a conductive pad including an interconnect structure defining an opening; forming a first dielectric layer on the patterned conductive layer, the first dielectric layer having a first surface and a second surface opposite to the first surface; forming an opening in the first dielectric layer, the opening of the conductive pad and the opening of the first dielectric layer being continuous; forming an interconnection element in the opening of the first dielectric layer so that the interconnection element extends to the opening of the interconnection structure and is surrounded by the interconnection structure, wherein the interconnection element comprises a first portion and a second portion, wherein the first portion of the interconnection element comprises a vertically extending structure and the second portion of the interconnection element comprises a tapered structure, the interconnection element being three-dimensionally embedded in the interconnection structure so that the interconnection structure surrounds and contacts a sidewall of the first portion of the interconnection element and contacts a top surface of the second portion of the interconnection element; as well as The carrier is removed.

33. The method of claim 32, further comprising: forming a second dielectric layer on the patterned conductive layer, and An opening is formed in the second dielectric layer to expose the interconnect element.

34. The method of claim 33, further comprising: over-etching the interconnection element to form an over-etched surface of the interconnection element including a portion having a curved shape; as well as An external connection pad is formed on the second dielectric layer, the external connection pad having an anchor shape.

35. The method of claim 32, wherein the opening of the first dielectric layer is formed by a laser drilling operation, and wherein the interconnect element fills at least a portion of the opening of the first dielectric layer and the opening of the interconnect structure.

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