Display device

Abstract

Provided is a display device. The display device includes: a substrate including a display area; a first thin film transistor disposed in the display area of the substrate and having a first semiconductor layer including a silicon semiconductor and a first gate electrode insulated from the first semiconductor layer by a first gate insulating layer; a second thin film transistor disposed in the display area of the substrate and having a second semiconductor layer including an oxide semiconductor and a second gate electrode insulated from the second semiconductor layer; and a storage capacitor at least partially stacked with the first thin film transistor and having a lower electrode and an upper electrode, wherein the second semiconductor layer and one of the lower electrode and the upper electrode are disposed on the same layer.

Description

[0001] Korean Patent Application No. 10-2018-0029280, filed with the Korean Intellectual Property Office on March 13, 2018 and entitled "Display Device", is incorporated herein by reference in its entirety. Technical Field

[0002] One or more embodiments herein relate to a display device, and more particularly, to a display device driven by a thin film transistor including a silicon semiconductor and a thin film transistor including an oxide semiconductor. Background Art

[0003] Generally, a display device includes a display device and a driving circuit for controlling electrical signals of the display device. The driving circuit includes a plurality of thin film transistors (TFTs), storage capacitors, and a plurality of wirings.

[0004] Recently, in order to precisely control the light emission intensity of a display device, the number of TFTs of each display device has increased. Therefore, the display device requires, for example, high integration density, low power consumption, low process cost, short process time, etc. Summary of the Invention

[0005] An embodiment relates to a display device including: a substrate including a display area; a first thin film transistor disposed in the display area of the substrate, the first thin film transistor having a first semiconductor layer including a silicon semiconductor and a first gate electrode insulated from the first semiconductor layer by a first gate insulating layer; a second thin film transistor disposed in the display area of the substrate, the second thin film transistor having a second semiconductor layer including an oxide semiconductor and a second gate electrode insulated from the second semiconductor layer; and a storage capacitor at least partially stacked with the first thin film transistor, the storage capacitor having a lower electrode and an upper electrode. The second semiconductor layer and one of the lower electrode and the upper electrode may be disposed on the same layer.

[0006] The display device may further include a second gate insulating layer disposed in a horizontal direction between the first gate electrode and the second semiconductor layer. The lower electrode of the storage capacitor and the first gate electrode of the first thin film transistor may be formed as an integral body, and the upper electrode of the storage capacitor may be disposed on the second gate insulating layer.

[0007] The second semiconductor layer of the second thin film transistor may include a second channel region, a second source region, and a second drain region. The second source region and the second drain region may be respectively disposed at two opposite sides of the second channel region. The upper electrode of the storage capacitor and at least one of the second source region and the second drain region may include the same material.

[0008] The display device may further include a display device driven by a first thin film transistor and a second thin film transistor. The first thin film transistor may include a driving thin film transistor to supply a driving current to the display device.

[0009] The display device may further include a first wiring located in the display area. The first wiring and the upper electrode of the storage capacitor may be arranged on the same layer and may include the same material.

[0010] The display device may further include a second wiring located in the display area. The second wiring and the first gate electrode may be arranged on the same layer and may include the same material.

[0011] The display device may further include: a second gate insulating layer arranged between the first gate electrode and the second semiconductor layer in a horizontal direction; and a third gate insulating layer arranged between the second semiconductor layer and the second gate electrode. The lower electrode of the storage capacitor and the second semiconductor layer may be arranged on the same layer. The dielectric layer of the storage capacitor and the third gate insulating layer may be formed of the same material. The upper electrode of the storage capacitor and the second gate electrode of the second thin film transistor may be arranged on the same layer.

[0012] According to one or more embodiments, the display device may include: a substrate including a first region, a second region, and a bending region located between the first region and the second region, and the bending region is bent about a bending axis; a first thin film transistor, a second thin film transistor, and a storage capacitor arranged in the first region of the substrate; a connection wiring extending from the first region through the bending region to the second region; and an inner wiring and an outer wiring respectively connected to the connection wiring and separated from each other by the bending region. The first thin film transistor may have a first semiconductor layer including a silicon semiconductor and a first gate electrode insulated from the first semiconductor layer by a first gate insulating layer. The second thin film transistor may have a second semiconductor layer including an oxide semiconductor layer and a second gate electrode insulated from the second semiconductor layer by a third gate electrode. The second semiconductor layer and one of the lower electrode and the upper electrode of the storage capacitor may be arranged on the same layer.

[0013] The display device may further include a display device driven by a first thin film transistor and a second thin film transistor. The first thin film transistor may include a driving thin film transistor to supply a driving current to the display device.

[0014] The storage capacitor may at least partially overlap with the first thin film transistor in a vertical direction.

[0015] The display device may further include a second gate insulating layer disposed between the first gate electrode of the first thin film transistor and the second semiconductor layer in a horizontal direction. The lower electrode of the storage capacitor and the first gate electrode of the first thin film transistor may be formed integrally. The upper electrode of the storage capacitor may be disposed on the second gate insulating layer.

[0016] Portions of the inner wiring and the outer wiring may be disposed on the same layer. The inner wiring, the outer wiring, and the first gate electrode may include the same material.

[0017] Portions of the inner wiring and the outer wiring may be disposed on the same layer. The inner wiring, the outer wiring, and the second gate electrode may include the same material.

[0018] The display device may further include a third gate insulating layer disposed between the second semiconductor layer and the second gate electrode. The third gate insulating layer may be disposed under the inner wiring. The width of the third gate insulating layer disposed under the inner wiring may be substantially the same as the width of the inner wiring.

[0019] The display device may further include: an interlayer insulating layer disposed on the substrate and covering the second gate electrode; a first electrode disposed on the interlayer insulating layer and connected to the first semiconductor layer; and a planarization layer covering the first electrode.

[0020] The display device may further include a connection electrode disposed on the planarization layer and connected to the first electrode through a contact hole defined in the planarization layer. The connection wiring and the connection electrode may include the same material.

[0021] The display device may further include an inorganic insulating layer including an opening or a groove corresponding to the bending region. The opening or the groove of the inorganic insulating layer may be filled with an organic material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Features will become apparent to those skilled in the art by describing exemplary embodiments in detail with reference to the accompanying drawings, in which:

[0023] Figure 1 A top plan view of a display device according to an embodiment is shown;

[0024] Figure 2 A cross-sectional view of a part of a display device according to an embodiment is shown;

[0025] Figures 3 to 11 Cross-sectional views respectively showing manufacturing steps of the display device;

[0026] Figure 12 A cross-sectional view of a part of a display device according to another embodiment is shown;

[0027] Figure 13A cross-sectional view of a part of a display device according to another embodiment is shown;

[0028] Figure 14 A cross-sectional view of a part of a display device according to another embodiment is shown;

[0029] Figure 15 A perspective view of a part of a display device according to another embodiment is shown;

[0030] Figure 16 A cross-sectional view of a part of a display device according to another embodiment is shown;

[0031] Figure 17 A cross-sectional view of a part of a display device according to another embodiment is shown;

[0032] Figure 18 An equivalent circuit diagram of a pixel included in a display device according to an embodiment is shown; and

[0033] Figure 19 A layout diagram showing the positions of a plurality of thin film transistors and storage capacitors in a pixel included in a display device according to an embodiment is shown. DETAILED DESCRIPTION

[0034] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the exemplary embodiments to those skilled in the art.

[0035] In the drawings, the dimensions of layers and regions may be exaggerated for clarity. It will also be understood that when a layer or element is referred to as being "on" another layer or substrate, the layer or element may be directly on the other layer or substrate, or an intermediate layer may also be present. Additionally, it will be understood that when a layer is referred to as being "under" another layer, the layer may be directly underneath, or one or more intermediate layers may also be present. Further, it will be understood that when a layer is referred to as being "between" two layers, the layer may be the only layer between the two layers, or one or more intermediate layers may also be present. Like reference numerals always denote like elements.

[0036] Since the present disclosure allows for various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. The advantages and features of the present disclosure and the methods for achieving the advantages and features will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein.

[0037] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, where like reference numerals always refer to like elements, and repeated description will be omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When a phrase such as "at least one of (...)" appears after a list of elements, it modifies the entire list of elements, not individual elements in the list.

[0038] Although the terms "first", "second" may be used herein to describe various elements, these elements should not be limited by these terms, and these terms are only used to distinguish one element from another.

[0039] Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are also intended to include the plural forms.

[0040] It will also be understood that the terms "comprises" and / or its variations used herein specify the presence of the stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0041] For ease of explanation, the dimensions of the elements may be exaggerated. In other words, since the dimensions and thicknesses of the elements in the drawings are arbitrarily shown for ease of explanation, the present disclosure is not limited thereto.

[0042] When a particular embodiment can be implemented differently, the specific process order can be performed in an order different from that described. For example, two consecutively described processes can be performed substantially at the same time, or two consecutively described processes can be performed in an order opposite to that described.

[0043] It will be understood that when a layer, region or element is referred to as being "connected" to another layer, region or element, the layer, region or element can be directly or indirectly connected to the other layer, region or element. That is, intermediate layers, regions, elements can exist. For example, when a layer, region or element is electrically connected to another layer, region or element, the layer, region or element can be directly and electrically connected to the other layer, region or element, or intermediate layers, regions, elements can exist.

[0044] Figure 1 A top plan view of a display device according to an embodiment is shown.

[0045] In the display area DA of the substrate 110, pixels PX each including various display devices (e.g., organic light-emitting devices (OLEDs)) may be arranged. In the peripheral area PA of the substrate 110, various wirings for supplying electrical signals to the display area DA may be arranged. In other embodiments, the present disclosure may be applied to various display devices such as liquid crystal displays (LCDs), electrophoretic image displays, electroluminescent displays, and the like.

[0046] Figure 2 A cross-sectional view showing a part of the display device of the display device 10 according to an embodiment is shown.

[0047] Referring to Figure 2 , the display device 10 according to an embodiment may include a first thin-film transistor T1 including a silicon semiconductor, a second thin-film transistor T2 including an oxide semiconductor, and a storage capacitor Cst at least partially overlapping with the first thin-film transistor T1 and including an upper electrode C2 and a lower electrode C1. In addition, the second semiconductor layer AO2 of the second thin-film transistor T2 and one of the upper electrode C2 and the lower electrode C1 of the storage capacitor Cst may be arranged on the same layer. For example, as shown in Figure 2 , the second semiconductor layer AO2 of the second thin-film transistor T2 and the upper electrode C2 of the storage capacitor Cst may be arranged on the same layer. For example, the second semiconductor layer AO2 of the second thin-film transistor T2 and the lower electrode C1 of the storage capacitor Cst may have the same level from the substrate 110. For example, the second semiconductor layer AO2 of the second thin-film transistor T2 may be at a level higher than the level of the first semiconductor layer AS1 of the first thin-film transistor T1 from the substrate 110.

[0048] The first thin-film transistor T1 may include a first semiconductor layer AS1 including a silicon semiconductor and a first gate electrode G1 insulated from the first semiconductor layer AS1. The first thin-film transistor T1 may include a first source electrode SE1 and a first drain electrode DE1 connected to the first semiconductor layer AS1. The first thin-film transistor T1 may be used as, for example, a driving thin-film transistor in a driving circuit.

[0049] The second thin-film transistor T2 may include a second semiconductor layer AO2 including an oxide semiconductor and a second gate electrode G2 insulated from the second semiconductor layer AO2. The second thin-film transistor T2 may include a second source electrode SE2 and a second drain electrode DE2 connected to the second semiconductor layer AO2. The second thin-film transistor T2 may be used as a switching thin-film transistor. In other embodiments, the second thin-film transistor T2 may be any type of thin-film transistor other than the driving thin-film transistor in the driving circuit. For example, the first semiconductor layer AS1 of the first thin-film transistor T1 may be closer to the substrate 110 than the second semiconductor layer AO2 of the second thin-film transistor T2.

[0050] According to an embodiment, the first semiconductor layer AS1 of the first thin film transistor T1 (e.g., used as a driving thin film transistor) may include polysilicon with high reliability, and the second semiconductor layer AO2 of the second thin film transistor T2 (e.g., used as a switching thin film transistor) may include an oxide semiconductor layer with low leakage current.

[0051] For example, when the driving thin film transistor of a display device (e.g., directly affecting the brightness of the display device) includes a semiconductor layer containing, for example, polysilicon with high reliability, due to the high reliability of the driving thin film transistor, the display device can have high resolution or high definition.

[0052] For example, when a thin film transistor has a semiconductor layer including an oxide semiconductor (which has high carrier mobility and low leakage current), the thin film transistor may not have a large voltage drop during a long driving time. In other words, when a thin film transistor including an oxide semiconductor can be driven at a low frequency, the thin film transistor can have a low voltage drop, such that there is no significant color change in the image due to the low voltage drop of the thin film transistor operating at a low frequency. Therefore, the power consumption of a driving circuit including a thin film transistor having a semiconductor layer containing an oxide semiconductor can be lower than that of a driving circuit including a thin film transistor having a semiconductor layer containing polysilicon.

[0053] In an embodiment, when at least one of the other thin film transistors of a display device (except its driving thin film transistor) includes a semiconductor layer (i.e., an active layer) containing an oxide semiconductor, the power consumption of the display device can be reduced. For example, as the number of thin film transistors having a semiconductor layer containing an oxide semiconductor increases, the power consumption of the display device can be reduced.

[0054] According to an embodiment, the display device 10 may include a storage capacitor Cst stacked with the first thin film transistor T1, such that the display device 10 can have a high integration density. In addition, by arranging the second semiconductor layer AO2 on the same layer as one of the upper electrode C2 and the lower electrode C1 of the storage capacitor Cst, the process time and process cost of the display device 10 can be reduced.

[0055] Hereinafter, with reference to Figure 2 , the components included in the display device 10 will be described according to the stacking order of the components on the substrate 110.

[0056] The substrate 110 may include, for example, a glass material, a ceramic material, a metal material, or a flexible or bendable material. For example, when the substrate 110 is flexible or bendable, the substrate 110 may include a polymer, such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). For example, the substrate 110 may have a single-layer or multi-layer structure formed of the above materials. When the substrate 110 has a multi-layer structure, the substrate 110 may include, for example, an inorganic material layer. In some embodiments, the substrate 110 may have a multi-layer structure in which an organic material layer, an inorganic material layer, and an organic material layer are sequentially stacked.

[0057] The buffer layer 111 may enhance the smoothness of the upper surface of the substrate 110 and may be formed of an oxide film (e.g., silicon oxide (SiO x )) and / or a nitride film (e.g., silicon nitride (SiN x ))

[0058] A barrier layer (not shown) may also be included between the substrate 110 and the buffer layer 111. The barrier layer may prevent impurities from the substrate 110, etc. from penetrating into the first semiconductor layer AS1 of the first thin film transistor T1 or may minimize the penetration of impurities from the substrate 110, etc. into the first semiconductor layer AS1 of the first thin film transistor T1. The barrier layer may include an inorganic material (e.g., an oxide or a nitride), an organic material, or a composite of an organic material and an inorganic material, and may have a single-layer structure or a multi-layer structure including, for example, an inorganic material and an organic material.

[0059] The first semiconductor layer AS1 including a silicon semiconductor of the first thin film transistor T1 may be disposed on the buffer layer 111 and may include a first source region S1 and a first drain region D1 separated from each other and a first channel region A1 disposed between the first source region S1 and the first drain region D1.

[0060] The first semiconductor layer AS1 of the first thin film transistor T1 may include, for example, polysilicon. The first source region S1 and the first drain region D1 may be doped with impurities and may have conductivity. The first source region S1 and the first drain region D1 of the first semiconductor layer AS1 may be connected to the first source electrode SE1 and the first drain electrode DE1 through a first contact hole CNT1 and a second contact hole CNT2, respectively. In an embodiment, the positions of the first source region S1 and the first drain region D1 of the first thin film transistor T1 may be exchanged with each other.

[0061] The first gate electrode G1 of the first thin film transistor T1 may be disposed above the first semiconductor layer AS1. The first gate insulating layer 112 may be disposed between the first semiconductor layer AS1 and the first gate electrode G1 of the first thin film transistor T1.

[0062] The first gate insulating layer 112 may include an inorganic material containing, for example, an oxide or a nitride. For example, the first gate insulating layer 112 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), or zinc oxide (ZnO 2 ). The first gate electrode G1 of the first thin film transistor T1 that overlaps with the first channel region A1 may include, for example, molybdenum (Mo), copper (Cu), and titanium (Ti), and may have a single-layer structure or a multi-layer structure.

[0063] The storage capacitor Cst may overlap with the first gate electrode G1 of the first thin film transistor T1. The storage capacitor Cst may include a lower electrode C1 and an upper electrode C2. The second gate insulating layer 113 may be disposed between the lower electrode C1 and the upper electrode C2 of the storage capacitor Cst. The first gate electrode G1 may not only be used as the first gate electrode G1 of the first thin film transistor T1, but also as the lower electrode C1 of the storage capacitor Cst. For example, the first gate electrode G1 of the first thin film transistor T1 and the lower electrode C1 of the storage capacitor Cst may be formed integrally. The upper electrode C2 of the storage capacitor Cst may be disposed on the second gate insulating layer 113 to at least partially overlap with the lower electrode C1 of the storage capacitor Cst. The upper electrode C2 of the storage capacitor Cst may be electrically connected to a driving voltage line for supplying a driving voltage. For example, the upper electrode C2 of the storage capacitor Cst may be formed as a part of a grid wiring that crosses the driving voltage line, and may supply the driving voltage. For example, the second gate insulating layer 113 may be disposed in a horizontal direction parallel to the top surface of the substrate 110 between the first gate electrode G1 of the first thin film transistor T1 and the second semiconductor layer AO2 of the second thin film transistor T2.

[0064] The second gate insulating layer 113 may include an inorganic material layer containing, for example, an oxide or a nitride. For example, the second gate insulating layer 113 may include, for example, SiO 2 , SiN x , SiON, Al 2 O 3 , TiO2 , Ta 2 O 5 , HfO 2 or ZnO 2 etc.

[0065] The second semiconductor layer AO2 of the second thin film transistor T2 (e.g., including an oxide semiconductor layer and not overlapping with the upper electrode C2 of the storage capacitor Cst in the vertical direction) may be disposed on the second gate insulating layer 113. The second semiconductor layer AO2 may include a second source region S2 and a second drain region D2 (e.g., which may have conductivity and may be separated from each other) and a second channel region A2 disposed between the second source region S2 and the second drain region D2. The second source region S2 and the second drain region D2 may be connected to the second source electrode SE2 and the second drain electrode DE2 through a third contact hole CNT3 and a fourth contact hole CNT4, respectively. In an embodiment, the positions of the second source region S2 and the second drain region D2 of the second thin film transistor T2 may be exchanged with each other.

[0066] The second semiconductor layer AO2 of the second thin film transistor T2 may include a ZnO-based material, such as ZnO, indium (In)-ZnO, gallium (Ga)-In-ZnO, etc. In some embodiments, the second semiconductor layer AO2 may be an In-Ga-ZnO (IGZO) semiconductor containing metals (e.g., In and Ga are added to ZnO).

[0067] The second source region S2 and the second drain region D2 of the second thin film transistor T2 may be formed by a conductive process (e.g., by adjusting the carrier concentration of the oxide semiconductor). For example, the second source region S2 and the second drain region D2 of the second thin film transistor T2 may be formed by increasing the carrier concentration of the oxide semiconductor using plasma processing employing, for example, a hydrogen-based gas, a fluorine-based gas, or a combination thereof.

[0068] The upper electrode C2 of the storage capacitor Cst and the second semiconductor layer AO2 may be formed of the same material and may be formed on the same layer. For example, the upper electrode C2 of the storage capacitor Cst and at least one of the second source region S2 and the second drain region D2 of the second thin film transistor T2 may include the same material. In other words, the upper electrode C2 of the storage capacitor Cst may be formed by a conductive process (e.g., by adjusting the carrier concentration of the oxide semiconductor). For example, the upper electrode C2 of the storage capacitor Cst may be formed by increasing the carrier concentration of the oxide semiconductor using plasma processing employing, for example, a hydrogen-based gas, a fluorine-based gas, or a combination thereof.

[0069] The first wiring W1 may include the same material as the upper electrode C2 of the storage capacitor Cst and the second semiconductor layer AO2 of the second thin film transistor T2. The first wiring W1 may be disposed on the second gate insulating layer 113. The first wiring W1 may supply a signal, such as an initialization voltage, to the first thin film transistor T1 via the second thin film transistor T2 or another thin film transistor (not shown). For example, the first wiring W1 and the second semiconductor layer AO2 of the second thin film transistor T2 may be at the same level from the substrate 110.

[0070] The first wiring W1 and the second semiconductor layer AO2 of the second thin film transistor T2 may be formed of the same material and may be formed on the same layer, for example, on the second gate insulating layer 113. For example, the first wiring W1 and at least one of the second source region S2 and the second drain region D2 may be formed of the same material. In other words, the first wiring W1 may be formed by a conductive process (e.g., by adjusting the carrier concentration of an oxide semiconductor). For example, the first wiring W1 may be formed by increasing the carrier concentration of an oxide semiconductor by using a plasma process employing, for example, a hydrogen-based gas, a fluorine-based gas, or a combination thereof.

[0071] The second gate electrode G2 of the second thin film transistor T2 may be disposed above the second semiconductor layer AO2, and the third gate insulating layer 115 may be disposed between the second semiconductor layer AO2 and the second gate electrode G2. The second gate electrode G2 of the second thin film transistor T2 may overlap with the second channel region A2 and may be insulated from the second semiconductor layer AO2 by the third gate insulating layer 115.

[0072] Since the third gate insulating layer 115 and the second gate electrode G2 may be formed by a process using the same mask, the side surface of the third gate insulating layer 115 may be disposed in the same plane as the side surface of the second gate electrode G2. In other words, the side surface of the third gate insulating layer 115 may be aligned with the side surface of the second gate electrode G2 in the vertical direction. For example, in the horizontal direction, the width of the third gate insulating layer 115 may be substantially the same as the width of the second gate electrode G2.

[0073] The third gate insulating layer 115 may include an inorganic material containing, for example, an oxide or a nitride. For example, the third gate insulating layer 115 may include, for example, SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、Ta 2 O 5 、HfO 2 or ZnO 2and so on. The second gate electrode G2 may be disposed on the third gate insulating layer 115 and may include, for example, Mo, Cu, Ti, etc. In some embodiments, the second gate electrode G2 may have a single-layer structure or a multi-layer structure. The second gate electrode G2 may be connected to a scan line for supplying a scan signal to the second thin film transistor T2.

[0074] The interlayer insulating layer 116 may be disposed on the second gate electrode G2, and the first source electrode SE1 and / or the first drain electrode DE1 are connected to the first semiconductor layer AS1, and the second source electrode SE2 and / or the second drain electrode DE2 are connected to the second semiconductor layer AO2. A data line for supplying a data signal and a drive voltage line for supplying a drive voltage may be disposed on the interlayer insulating layer 116. The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, or the second drain electrode DE2 may be directly or via another thin film transistor connected to the data line or the drive voltage line.

[0075] The interlayer insulating layer 116 may include an inorganic material containing, for example, an oxide or a nitride. For example, the interlayer insulating layer 116 may include, for example, SiO 2 , SiN x , SiON, Al 2 O 3 , TiO 2 , Ta 2 O 5 , HfO 2 or ZnO 2 and so on.

[0076] The first source electrode SE1 and / or the first drain electrode DE1 and the second source electrode SE2 and / or the second drain electrode DE2 may include a material having high conductivity, for example, a metal or a conductive oxide. For example, the first source electrode SE1 and / or the first drain electrode DE1 and the second source electrode SE2 and / or the second drain electrode DE2 may each have a single-layer structure or a multi-layer structure including, for example, Al, Cu, Ti, etc. In some embodiments, the first source electrode SE1 and / or the first drain electrode DE1 and the second source electrode SE2 and / or the second drain electrode DE2 may each have a three-layer structure including, for example, Ti or Al. For example, each three-layer structure may be formed by continuously stacking Ti, Al, and Ti.

[0077] The planarization layer 118 may be disposed on the first source electrode SE1 and / or the first drain electrode DE1, the second source electrode SE2 and / or the second drain electrode DE2. The planarization layer 118 may include an organic material, such as acrylic, BCB, PI, or HMDSO. In an embodiment, the planarization layer 118 may include an inorganic material. The planarization layer 118 may serve as a protective layer covering the first thin film transistor T1 and the second thin film transistor T2, and may have a smooth upper surface. In some embodiments, the planarization layer 118 may have a single-layer structure or a multi-layer structure.

[0078] The organic light emitting device OLED may include a pixel electrode 310, a counter electrode 330, and an intermediate layer 320 including an emission layer and located between the pixel electrode 310 and the counter electrode 330. For example, the pixel electrode 310 of the organic light emitting device OLED may be disposed on the planarization layer 118.

[0079] The pixel electrode 310 may be connected to the first drain electrode DE1 through a contact hole defined in the planarization layer 118, and may be connected to the first drain region D1 of the first thin film transistor T1 via the first drain electrode DE1. The pixel electrode 310 may be directly connected to the first thin film transistor T1, or may be indirectly connected to the first thin film transistor T1 via another thin film transistor (not shown) for controlling the light emission of the organic light emitting device OLED.

[0080] The pixel electrode 310 may be a reflective electrode including a reflective layer. The reflective layer may include at least one of, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), and chromium (Cr). In some embodiments, the pixel electrode 310 may include a transparent electrode or a semi-transparent electrode located on the reflective layer. The transparent electrode or the semi-transparent electrode may include at least one of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 )), indium gallium oxide (IGO), and aluminum zinc oxide (AZO).

[0081] In an embodiment, the pixel electrode 310 may have a three-layer structure including, for example, ITO or Ag. For example, the three-layer structure may be formed by continuously stacking ITO, Ag, and ITO.

[0082] The pixel defining layer 120 may be disposed on the planarization layer 118. The pixel defining layer 120 may define pixels by forming openings corresponding to each sub-pixel (e.g., an opening that at least exposes the central region of the pixel electrode 310). The pixel defining layer 120 may prevent arcing etc. at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310. The pixel defining layer 120 may include an organic material, e.g., PI or HMDSO etc.

[0083] The intermediate layer 320 of the organic light-emitting device OLED may include, for example, a low molecular weight material or a high molecular weight material. When the intermediate layer 320 includes a low molecular weight material, the intermediate layer 320 may have a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) etc., and may have a single-layer structure or a multi-layer structure. The low molecular weight material may include various organic materials, e.g., copper phthalocyanine (CuPc), N,N'-bis(naphthalen-1-yl)-N,N'-diphenylbenzidine (NPB), tris(8-hydroxyquinolinato)aluminum (Alq 3 ) etc. The various organic materials may be formed by a vacuum deposition method.

[0084] When the intermediate layer 320 includes a high molecular weight material, the intermediate layer 320 may have a structure including, for example, an HTL and an EML. For example, the HTL may include, for example, poly(3,4-ethylenedioxythiophene) (PEDOT), and the EML may include polymer materials such as poly(phenylene vinylene) (PPV) and polyfluorene. The intermediate layer 320 may be formed by, for example, a screen printing method, an inkjet printing method, a laser-induced thermal imaging (LITI) method, etc.

[0085] In some embodiments, the intermediate layer 320 may have many different structures. For example, the intermediate layer 320 may include an integrated layer corresponding to a plurality of pixel electrodes. For example, the intermediate layer 320 may have a patterned layer corresponding to each of the plurality of pixel electrodes.

[0086] The counter electrode 330 of the organic light-emitting device OLED may be formed as an integrated type with respect to a plurality of organic light-emitting devices to correspond to the plurality of pixel electrodes 310. The counter electrode 330 may be a transparent electrode or a semi-transparent electrode. For example, the counter electrode 330 may include at least one of, for example, Al, Mg, Li, Ca, Cu, LiF / Ca, LiF / Al, MgAg, and CaAg, and may be formed as a thin film having a thickness of, for example, about several nm to about several tens of nm.

[0087] Since the organic light-emitting device OLED is liable to be damaged due to moisture or oxygen penetrating from the outside, a thin film encapsulation layer (not shown) may encapsulate the organic light-emitting device OLED for protection. The thin film encapsulation layer (not shown) may cover the display area DA and may extend to the outer periphery of the display area DA. The thin film encapsulation layer may include an inorganic encapsulation layer including at least one inorganic material and an organic layer including at least one organic material. In some embodiments, the thin film encapsulation layer may have a stacked structure of a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0088] For example, spacers for protecting the mask from being cut may be formed on the pixel defining layer 120, and various functional layers such as a polarizing layer, a black matrix, a color filter, and / or a touch screen including touch electrodes for reducing reflection of external light may be provided on the thin film encapsulation layer.

[0089] Figures 3 to 11 are respectively shown Figure 2 cross-sectional views of the manufacturing steps of the display device 10. The steps shown in Figures 3 to 11 may be performed on the substrate 110 disposed on a carrier substrate (not shown), and the carrier substrate may be removed after performing the steps shown in Figure 11 .

[0090] Referring to Figure 3 , a buffer layer 111 and a polysilicon layer AS1' are formed on the substrate 110. The buffer layer 111 may include an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer structure or a multi-layer structure.

[0091] The polysilicon layer AS1' may be formed by forming amorphous silicon on the entire surface of the substrate 110, annealing the amorphous silicon to form polysilicon, and patterning the polysilicon using a first mask (not shown). In an embodiment, the polysilicon layer AS1' may be formed by directly forming polysilicon on the entire surface of the substrate 110 and patterning the polysilicon.

[0092] Referring to Figure 4 , a first gate insulating layer 112 may be formed on the buffer layer 111 to cover the polysilicon layer AS1', and then a first gate electrode G1 may be formed on the first gate insulating layer 112.

[0093] The first gate electrode G1 may be formed by coating a conductive material on the first gate insulating layer 112 and patterning the conductive material using a second mask (not shown). For example, the conductive material may include, for example, Mo, Cu, and / or Ti

[0094] After the first gate electrode G1 is formed, the first source region S1 and the first drain region D1 can be formed by doping impurities so that the first source region S1 and the first drain region D1 can have conductivity. For example, the first source region S1 and the first drain region D1 can be formed by using the first gate electrode G1 as a blocking member and doping the polysilicon layer AS1' with impurities. In other words, in this step, the polysilicon layer AS1' can become the first semiconductor layer AS1 including the first source region S1, the first drain region D1, and the first channel region A1 where impurities are not doped.

[0095] Referring to Figure 5 , after the second gate insulating layer 113 is formed on the first gate insulating layer 112 to cover the first gate electrode G1, a pre-second semiconductor layer AO2', a pre-top electrode C2', and a pre-first wiring W1' including an oxide semiconductor can be formed on the second gate insulating layer 113.

[0096] According to an embodiment, the pre-second semiconductor layer AO2', the pre-top electrode C2', and the pre-first wiring W1' can be formed by applying (or depositing) an oxide semiconductor on the second gate insulating layer 113 and patterning the oxide semiconductor using a third mask (not shown).

[0097] The oxide semiconductor layer can include, for example, a ZnO-based material, such as ZnO, In-ZnO, Ga-In-ZnO, etc. In some embodiments, the oxide semiconductor can be an In-Ga-ZnO (IGZO) semiconductor including metals such as In and Ga in ZnO.

[0098] Referring to Figure 6 , a third gate insulating layer 115 and a second gate electrode G2 can be formed on the pre-second semiconductor layer AO2'. The third gate insulating layer 115 and the second gate electrode G2 can be formed by continuously applying (or depositing) an insulating material and a conductive material on the second gate insulating layer 113 and simultaneously patterning the insulating material and the conductive material using a fourth mask (not shown). Since the third gate insulating layer 115 and the second gate electrode G2 are formed simultaneously using the same mask, the third gate insulating layer 115 and the second gate electrode G2 can have substantially the same width.

[0099] Referring to Figure 7 , the second source region S2, the second drain region D2, the top electrode C2, and the first wiring W1 are formed by a conductive process (for example, by increasing the carrier concentration of a part of the pre-second semiconductor layer AO2', the pre-top electrode C2', and the pre-first wiring W1'). For example, since the second gate electrode G2 can be used as a blocking member, the second channel region A2 of the second semiconductor layer AO2 can be not be conductive and can maintain the characteristics of a semiconductor.

[0100] In some embodiments, plasma processing may be used to perform a conductive process. The plasma processing may be performed by using, for example, a hydrogen-based gas, a fluorine-based gas, or a combination thereof.

[0101] In the conductive process, hydrogen gas may penetrate in the thickness direction of the oxide semiconductor and increase the concentration of carriers, such that the surface resistance of the oxide semiconductor may be reduced. For example, plasma processing using hydrogen gas may reduce the oxide metal in the oxide semiconductor by removing the oxygen of the oxide metal, such that the surface resistance of the oxide semiconductor may be reduced.

[0102] In some embodiments, when plasma processing is performed by using a fluorine-based gas, the fluorine component on the surface of the oxide semiconductor increases and the oxygen component decreases. Accordingly, additional carriers may be formed on the surface of the oxide semiconductor. Accordingly, the carrier concentration of the oxide semiconductor increases and the surface resistance of the oxide semiconductor decreases. For example, the fluorine-based gas may be, for example, CF 4 、C 4 F 8 、NF 3 、SF 6 or a combination thereof.

[0103] In another embodiment, plasma processing may be performed by using nitrogen gas. During the plasma processing by using nitrogen gas, an annealing process may be performed simultaneously. For example, the annealing process may be performed at a temperature of about 300 °C to about 400 °C for about 1 hour to about 2 hours.

[0104] By the plasma processing, the carrier concentration of the oxide semiconductor may be adjusted from a range of about 1.0E+14 cm -3 to about 1.0E+18 cm -3 to a value equal to or greater than 1.0E+19 cm -3 .

[0105] Next, the first contact hole CNT1 and / or the second contact hole CNT2 may expose the first source region S1 and / or the first drain region D1 of the first semiconductor layer AS1, and may be formed to cover the second semiconductor layer AO2, the upper electrode C2, and the first wiring W1 by forming an interlayer insulating layer 116, and then a part of the interlayer insulating layer 116, the second gate insulating layer 113, and the first gate insulating layer 112 may be simultaneously removed (or penetrated) by using a fifth mask (not shown).

[0106] After the first contact hole CNT1 and / or the second contact hole CNT2 are formed, an annealing process may be performed. The annealing process may be a process for increasing the carrier mobility of the first semiconductor layer AS1 by heating the first semiconductor layer AS1.

[0107] During the annealing process, an oxide layer can be formed on the surface of the first source region S1 exposed through the first contact hole CNT1 and / or on the surface of the first drain region D1 exposed through the second contact hole CNT2. To remove the oxide layer, a washing process can be performed after the annealing process. For example, buffered oxide etchant (BOE) can be used as the detergent for the washing process.

[0108] Although BOE can etch oxide semiconductors, when forming the first contact hole CNT1 and / or the second contact hole CNT2, the second semiconductor layer AO2 including the oxide semiconductor can be protected from BOE by the interlayer insulating layer 116.

[0109] Referring to Figure 8 , by using a sixth mask (not shown) process to etch the interlayer insulating layer 116, the third contact hole CNT3 and / or the fourth contact hole CNT4 can expose the second source region S2 and / or the second drain region D2 of the second semiconductor layer AO2, respectively.

[0110] Referring to Figure 9 , a first source electrode SE1, a first drain electrode DE1, a second source electrode SE2, and a second drain electrode DE2 can be formed on the interlayer insulating layer 116. After forming a conductive material on the interlayer insulating layer 116, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 can be formed simultaneously by patterning the conductive material using a seventh mask (not shown). In other words, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 can be arranged on the same layer and can include the same material. For example, each of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 can have a three-layer structure including, for example, Ti or Al. For example, the three-layer structure can be formed by continuously stacking Ti, Al, and Ti.

[0111] The first source electrode SE1 can fill the first contact hole CNT1 and contact the first source region S1 of the first semiconductor layer AS1 through the first contact hole CNT1. The first drain electrode DE1 can fill the second contact hole CNT2 and can contact the first drain region D1 of the first semiconductor layer AS1 through the second contact hole CNT2.

[0112] The second source electrode SE2 can fill the third contact hole CNT3 and can contact the second source region S2 of the second semiconductor layer AO2 through the third contact hole CNT3. The second drain electrode DE2 can fill the fourth contact hole CNT4 and can contact the second drain region D2 of the second semiconductor layer AO2 through the fourth contact hole CNT4.

[0113] Reference Figure 10 As shown in Figure 10 , a planarization layer 118 may be formed on the interlayer insulating layer 116 to cover the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2. The planarization layer 118 may include a via VIA that exposes the first drain electrode DE1. The planarization layer 118 may be formed by forming an organic material to cover the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 and patterning the via VIA using an eighth mask (not shown). For example, the organic material may include, for example, acrylic, benzocyclobutene (BCB), PI, or HMDSO, etc.

[0114] Reference Figure 11 As shown in Figure 11 , after forming the pixel electrode 310 on the planarization layer 118 using a ninth mask (not shown), a pixel defining layer 120 may be formed on the planarization layer 118 and the pixel electrode 310 using a tenth mask (not shown). For example, the pixel defining layer 120 may have an opening that exposes a part of the pixel electrode 310.

[0115] The pixel electrode 310 may fill the via VIA and may be in contact with the first drain electrode DE1 through the via VIA. In some embodiments, the connection region where the first drain electrode DE1 and the pixel electrode 310 are connected to each other may not be on the first thin film transistor T1. For example, the first thin film transistor T1 and the pixel electrode 310 may be connected to each other via another thin film transistor, and the connection region of the pixel electrode 310 may be disposed on the other thin film transistor.

[0116] Next, an organic light emitting device OLED may be formed by forming an intermediate layer 320 including an organic emission layer on the pixel electrode 310 and forming a counter electrode 330 on the intermediate layer 320.

[0117] Figure 12 A cross-sectional view of a part of the display device 20 according to another embodiment is shown.

[0118] Reference Figure 12 As shown in Figure 12 , the display device 20 may include a first thin film transistor T1 including a silicon semiconductor, a second thin film transistor T2 including an oxide semiconductor, and a storage capacitor Cst that at least partially overlaps with the first thin film transistor T1. The upper electrode C2 of the storage capacitor Cst and the second semiconductor layer AO2 of the second thin film transistor T2 may include the same material and may be formed on the same layer.

[0119] The storage capacitor Cst may include a lower electrode C1, an upper electrode C2, and a second gate insulating layer 113 disposed between the lower electrode C1 and the upper electrode C2. The lower electrode C1 of the storage capacitor Cst and the first gate electrode G1 of the first thin film transistor T1 may be formed as one body. For example, the first gate electrode G1 may not only serve as the first gate electrode G1 of the first thin film transistor T1 but also as the lower electrode C1 of the storage capacitor Cst.

[0120] In an embodiment, the display device 20 may include a second wiring W2. The second wiring W2 and the first gate electrode G1 of the first thin film transistor T1 may be formed on the same layer and may be formed of the same material. For example, the second wiring W2 may be disposed on the first gate insulating layer 112 and may include, for example, Mo, Cu, and / or Ti. The second wiring W2 may supply a signal, for example, an initialization voltage, to the first thin film transistor T1 via the second thin film transistor T2 or another thin film transistor (not shown).

[0121] Figure 13 A cross-sectional view of a part of a display device 30 according to another embodiment is shown.

[0122] Referring to Figure 13 , the display device 30 may include a first thin film transistor T1 including a silicon semiconductor, a second thin film transistor T2 including an oxide semiconductor, and a storage capacitor Cst at least partially overlapping the first thin film transistor T1. In Figure 13 , the lower electrode C1″ of the storage capacitor Cst and the second semiconductor layer AO2 of the second thin film transistor T2 may be formed of the same material and may be formed on the same layer.

[0123] The storage capacitor Cst may include a lower electrode C1″ and an upper electrode C2″ and a dielectric layer 115' disposed between the lower electrode C1″ and the upper electrode C2″. The lower electrode C1″ and the second semiconductor layer AO2 of the second thin film transistor T2 may be formed simultaneously. For example, the lower electrode C1″ may include an oxide semiconductor material and may be made conductive by increasing the carrier concentration via plasma processing or the like. For example, the lower electrode C1″ may include a ZnO-based material including, for example, ZnO, In-ZnO, Ga-In-ZnO, and may be formed by increasing the carrier concentration of the oxide semiconductor layer by using plasma processing with, for example, a hydrogen-based gas, a fluorine-based gas, or a combination thereof.

[0124] The upper electrode C2″ and the second gate electrode G2 of the second thin film transistor T2 can be formed of the same material and can be formed on the same layer. The dielectric layer 115″ and the third gate insulating layer 115 can be formed of the same material and can have different levels from the substrate 110. Since the upper electrode C2″ and the dielectric layer 115' can be formed in the same mask process, the widths of the upper electrode C2″ and the dielectric layer 115″ can be substantially the same as each other.

[0125] In an embodiment, since the lower electrode C1″ of the storage capacitor Cst and the second semiconductor layer AO2 of the second thin film transistor T2 can be formed in the same process, the process time and process cost of the display device 30 can be reduced.

[0126] Figure 14 A cross-sectional view showing a part of a display device 40 according to another embodiment is shown.

[0127] Referring to Figure 14 , the display device 40 may include a first thin film transistor T1 including a silicon semiconductor, a second thin film transistor T2 including an oxide semiconductor, and a storage capacitor Cst at least partially overlapping with the first thin film transistor T1. The upper electrode C2 of the storage capacitor Cst and the second semiconductor layer AO2 of the second thin film transistor T2 may include the same material and may be formed on the same layer.

[0128] The storage capacitor Cst may include a lower electrode C1 and an upper electrode C2 and a second gate insulating layer 113 located between the lower electrode C1 and the upper electrode C2. The lower electrode C1 and the first gate electrode G1 may be formed integrally. For example, the first gate electrode G1 may not only serve as the gate electrode G1 of the first thin film transistor T1 but also as the lower electrode C1 of the storage capacitor Cst.

[0129] In an embodiment, the display device 40 may include a connection electrode CM and / or a third wiring W3 located on the planarization layer 118, and may include an upper planarization layer 119 covering the connection electrode CM and / or the third wiring W3.

[0130] The third wiring W3 may serve as a driving voltage line for supplying a driving voltage or a data line for supplying a data signal. The connection electrode CM may be connected to the first drain electrode DE1 through a contact hole defined in the planarization layer 118. The third wiring W3 and the connection electrode CM may include a conductive material, such as a metal. For example, each of the third wiring W3 and the connection electrode CM may include, for example, Al, Cu, and Ti, and may have a single-layer structure or a multi-layer structure. By including the third wiring W3, a data signal or a driving voltage can be supplied through various paths, and interference between wirings can be minimized.

[0131] The upper planarization layer 119 may cover the third wiring W3 and the connection electrode CM. The upper planarization layer 119 may include an organic material, for example, acrylic, BCB, PI, or HMDSO. The upper surface of the upper planarization layer 119 may be smoothed. The upper planarization layer 119 may have a single-layer structure or a multi-layer structure. The organic light-emitting device OLED may include a pixel electrode 310, a counter electrode 330, and an intermediate layer 320 including an emission layer and located between the pixel electrode 310 and the counter electrode 330. The organic light-emitting device OLED may be disposed on the upper planarization layer 119. The pixel electrode 310 may be in contact with the connection electrode CM through a via hole in the upper planarization layer 119.

[0132] According to an embodiment, an eleventh mask process for patterning the connection electrode CM and the third wiring W3 and a twelfth mask process for patterning the upper planarization layer 119 including a via hole may be performed.

[0133] Figure 15 A perspective view of a part of a display device according to an embodiment is shown. In the display device according to an embodiment, a part of a substrate 110 included in the display device may be bent, and a part of the display device may be bent like the substrate 110. However, for ease of explanation, Figure 16 and Figure 17 a display device in an unbent state (i.e., in a flat state) is shown.

[0134] As Figure 15 shown, the substrate 110 included in the display device according to an embodiment may have a bending region BA extending in a first direction (i.e., the y direction). With respect to a second direction (i.e., the x direction) intersecting the first direction, the bending region BA may be located between a first region 1A and a second region 2A. For example, as Figure 15 shown, the substrate 110 may be bent about a bending axis BAX extending in the first direction (i.e., the y direction). For example, as Figure 15 shown, the substrate 110 may be bent about the bending axis BAX with a regular radius of curvature at the center of the curvature. In another embodiment, the substrate 110 may be bent about the bending axis BAX with an irregular radius of curvature at the center of the curvature.

[0135] Figure 16 A display device 50 including a bending region BA according to an embodiment is shown. For example, as Figure 16 shown, the display area DA of the display device 50 may have the same structure as the Figure 14 display device 40 in. In other embodiments, the display area DA may have the same structure as the display areas DA of the above-described display devices 10, 20, and 30.

[0136] The first region 1A may include a display region DA and a part of a non-display region NDA outside the display region DA. The second region 2A may include another part of the non-display region NDA.

[0137] The bending region BA may be disposed between the first region 1A and the second region 2A. The organic material layer 160 may be disposed in the bending region BA. The inorganic insulating layer 125 including, for example, a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, and an interlayer insulating layer 116 that may each include an inorganic material may not be disposed in the bending region BA. For example, as Figure 16 shown, the inorganic insulating layer 125 may have an opening OP corresponding to the bending region BA. In other words, the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 116 may have openings corresponding to the bending region BA. The opening OP of the inorganic insulating layer 125 corresponding to the bending region BA may overlap with the bending region BA. For example, the width of the opening OP of the inorganic insulating layer 125 may be wider than the width of the bending region BA.

[0138] For example, as Figure 16 shown, the inner side of the opening 111a of the buffer layer 111 may be the same as the inner side of the opening 112a of the first gate insulating layer 112. In other embodiments, the width of the opening 112a of the first gate insulating layer 112 may be larger than the width of the opening 111a of the buffer layer 111.

[0139] For example, when forming the first contact hole CNT1 and the second contact hole CNT2, the opening 112a of the first gate insulating layer 112, the opening 113a of the second gate insulating layer 113, and the opening 116a of the interlayer insulating layer 116 may be formed simultaneously. After simultaneously forming the opening 112a of the first gate insulating layer 112, the opening 113a of the second gate insulating layer 113, and the opening 116a of the interlayer insulating layer 116, a first source electrode SE1 and a first drain electrode DE1 may be respectively formed in the first contact hole CNT1 and the second contact hole CNT2. After forming the first source electrode SE1 and the first drain electrode DE1, the opening OP of the inorganic insulating layer 125 may be formed in an additional masking process for forming the opening 111a of the buffer layer 111. Therefore, in an embodiment, a thirteenth masking process may be performed.

[0140] In some embodiments, in order to correspond to the bent region BA, a groove instead of an opening OP may be formed in the inorganic insulating layer 125. For example, the groove corresponding to the bent region BA may penetrate the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 116, and may not penetrate the buffer layer 111. In another embodiment, the groove corresponding to the bent region BA may not penetrate at least one of the first gate insulating layer 112, the second gate insulating layer 113, the interlayer insulating layer 116, and the buffer layer 111, so that the substrate 110 may not be exposed.

[0141] The display device 50 may include an organic material layer 160 filling the opening OP or the groove of the inorganic insulating layer 125. For example, the organic material layer 160 may overlap with the bent region BA. The organic material layer 160 may extend to a part of the non-bent region outside the bent region BA. For example, the width of the organic material layer 160 may be larger than the width of the bent region BA. In addition, the lower surface of the organic material layer 160 (e.g., the surface facing the substrate 110) may be narrower than the upper surface of the organic material layer 160. In other words, the sidewall of the opening OP may form an obtuse angle θ with the upper surface of the substrate 110. The organic material layer 160 may have an irregular thickness. For example, the organic material layer 160 may have a maximum thickness in its middle part and a minimum thickness at its edge. In an embodiment, the organic material layer 160 may have a uniform thickness.

[0142] The organic material layer 160 may include at least one of, for example, acrylic, methacrylic acid, polyester, polyethylene, polypropylene, PET, PEN, PC, PI, polyethylene sulfonate, polyoxymethylene, polyarylate, and HMDSO. The organic material layer 160 and the planarization layer 118 of the display region DA may be formed of the same material at the same time. In an embodiment, the organic material layer 160 and the planarization layer 118 of the display region DA may be formed of different materials at different times. The organic material layer 160 may be variously modified. For example, the organic material layer 160 and the upper planarization layer 119 or the pixel defining layer 120 may be formed of the same material at the same time.

[0143] The display device 50 may include a connection wiring 215. The connection wiring 215 may extend from the first region 1A via the bent region BA to the second region 2A, and may be disposed on the organic material layer 160. For example, the connection wiring 215 may be disposed on the inorganic insulating layer 125 including the interlayer insulating layer 116 in a region where the organic material layer 160 is not disposed. The connection wiring 215 may be used as a wiring for supplying an electrical signal to the display region DA. The connection wiring 215 and the connection electrode CM may be formed at the same time and may be formed of the same material.

[0144] As described above, although Figure 16The figure shows a display device in an unbent state (i.e., in a flat state), but as Figure 15 shown, the display device according to an embodiment may be in a state where the substrate 110 etc. are bent in the bending region BA. In other words, when manufacturing the display device, the substrate 110 may have a substantially flat state as Figure 16 shown, and then the substrate 110 etc. may be bent in the bending region BA so that the display device may have a form substantially the same as the form Figure 15 shown. Although tensile stress may be applied to the connection wiring 215 when the substrate 110 etc. are bent in the bending region BA, due to the flexibility of the organic material layer 160, defects of the connection wiring 215 on the organic material layer 160 in the bent state can be prevented, or the defects of the connection wiring 215 on the organic material layer 160 in the bent state can be minimized.

[0145] When the inorganic insulating layer 125 does not include an opening OP or a groove in the bending region BA and has a continuous form from the first region 1A to the second region 2A (i.e., when the connection wiring 215 is disposed on the inorganic insulating layer 125), large tensile stress will be applied to the connection wiring 215 through the bending operation of the substrate 100 etc. For example, since the inorganic insulating layer 125 has a higher rigidity than the organic material layer 160, in the bending region BA, the possibility of the inorganic insulating layer 125 cracking is high. When cracks occur in the inorganic insulating layer 125, the cracks in the inorganic insulating layer 125 will damage the connection wiring 215 on the inorganic insulating layer 125, and thus the possibility of defects (e.g., disconnection) of the connection wiring 215 will increase.

[0146] However, as described above, when the inorganic insulating layer 125 can include an opening OP in the bending region BA and the connection wiring 215 can be disposed on the organic material layer 160 filling the opening OP, since the inorganic insulating layer 125 with a high crack possibility may not be in the bending region BA, the possibility of the inorganic insulating layer 125 cracking will be significantly reduced. In addition, due to the low rigidity of the organic material layer 160, the possibility of cracks in the organic material layer 160 including organic materials is not high. Therefore, cracks etc. formed in the connection wiring 215 on the organic material layer 160 can be prevented, or cracks etc. formed in the connection wiring 215 on the organic material layer 160 can be minimized.

[0147] The display device 50 according to an embodiment may further include an inner wiring 213i and an outer wiring 213o connected to the connection wiring 215. The inner wiring 213i and the outer wiring 213o are disposed in the first region 1A or the second region 2A on a layer other than the layer of the connection wiring 215, and may be electrically connected to the connection wiring 215. For example, the inner wiring 213i and the outer wiring 213o may be formed on the first gate insulating layer 112.

[0148] Referring to Figure 16 , the inner wiring 213i can be disposed in the first region 1A, and the outer wiring 213o can be disposed in the second region 2A. The inner wiring 213i and the outer wiring 213o can be formed of the same material. The inner wiring 213i, the outer wiring 213o, and the first gate electrode G1 can be formed on the same layer. For example, the inner wiring 213i, the outer wiring 213o, and the first gate electrode G1 can be formed on the first gate insulating layer 112.

[0149] The connection wiring 215 can be connected to the inner wiring 213i and the outer wiring 213o through a fifth contact hole CNT5 and a sixth contact hole CNT6 that penetrate the interlayer insulating layer 116 and the second gate insulating layer 113.

[0150] The inner wiring 213i in the first region 1A can be electrically connected to the first thin film transistor T1, the second thin film transistor T2, etc. in the display region DA. For example, the connection wiring 215 can be electrically connected to the first thin film transistor T1, the second thin film transistor T2, and / or the first wiring W1, etc. in the display region DA through the inner wiring 213i. The inner wiring 213i can be connected to a conductive layer formed on different layers in the display region DA through a contact hole. For example, a conductive layer formed on the interlayer insulating layer 116 or a conductive layer formed on the second gate insulating layer 113.

[0151] By using the connection wiring 215, the outer wiring 213o in the second region 2A can be electrically connected to the first thin film transistor T1, the second thin film transistor T2, and / or the first wiring W1 in the display region DA. The outer wiring 213o can be connected to a conductive layer formed on different layers in the second region 2A through a contact hole. For example, a conductive layer provided on the interlayer insulating layer 116 or a conductive layer provided on the second gate insulating layer 113.

[0152] As described above, the inner wiring 213i and the outer wiring 213o can be electrically connected to the elements in the display region DA while being disposed outside the display region DA. For example, the inner wiring 213i and the outer wiring 213o can extend toward the display region DA while being disposed outside the display region DA, and can be at least partially disposed in the display region DA.

[0153] Although the connection wiring 215 may cross the bending region BA, since the connection wiring 215 may have a material with a high elongation rate, cracks or disconnections of the connection wiring 215 in the bending region BA can be prevented, or cracks or disconnections of the connection wiring 215 in the bending region BA can be minimized. When the inner wiring 213i and the outer wiring 213o are used to supply electrical signals in the first region 1A and the second region 2A, since the inner wiring 213i and the outer wiring 213o may have materials with an elongation rate lower than that of the connection wiring 215 and electrical / physical characteristics different from those of the connection wiring 215, the efficiency of the display device in supplying electrical signals can be improved or the error rate in the manufacturing process can be reduced.

[0154] For example, the inner wiring 213i and the outer wiring 213o may include, for example, Mo, and the connection wiring 215 may include, for example, Al. The connection wiring 215, the inner wiring 213i, and the outer wiring 213o may each have a multilayer structure. Meanwhile, the end of the outer wiring 213o in the second region 2A may be exposed outward and may be electrically connected to various electronic devices or a printed circuit board.

[0155] Various modifications or deformations can be made to the inorganic insulating layer 125 disposed between the connection wiring 215 and the inner wiring 213i and between the connection wiring 215 and the outer wiring 213o. For example, only the interlayer insulating layer 116 may be located between the connection wiring 215 and the inner wiring 213i and between the connection wiring 215 and the outer wiring 213o. In another embodiment, only the interlayer insulating layer 116 may be located between the connection wiring 215 and the inner wiring 213i, and the interlayer insulating layer 116 and the second gate insulating layer 113 may be located between the connection wiring 215 and the outer wiring 213o.

[0156] Figure 17 A cross-sectional view of a part of a display device 60 according to another embodiment is shown.

[0157] Referring to Figure 17 , the display device 60 may include a bending region BA located between the first region 1A and the second region 2A. The first region 1A may include a first thin film transistor T1 including a silicon semiconductor, a second thin film transistor T2 including an oxide semiconductor, and a storage capacitor Cst stacked with the first thin film transistor T1. For example, the second semiconductor layer AO2 of the second thin film transistor T2 and one electrode of the storage capacitor Cst may be disposed on the same layer, for example, on the second gate insulating layer 113.

[0158] The inorganic insulating layer 125 may include an opening OP or a groove corresponding to the bending region BA. The organic material layer 160 may fill the opening OP or the groove. The connection wiring 215 may be disposed on the organic material layer 160. The connection wiring 215 may extend from the first region 1A to the second region 2A.

[0159] The connection wiring 215 may be connected to the inner wiring 213i and the outer wiring 213o through contact holes CNT5' and CNT6' penetrating the interlayer insulating layer 116.

[0160] The inner wiring 213i may be disposed in the first region 1A. The outer wiring 213o may be disposed in the second region 2A. The inner wiring 213i, the outer wiring 213o, and the second gate electrode G2 may be formed of the same material and may be on the same layer. For example, the inner wiring 213i, the outer wiring 213o, and the second gate electrode G2 may be disposed on the third gate insulating layer 115. For example, since the inner wiring 213i and the third gate insulating layer 115 may be formed using the same mask process, the width of the inner wiring 213i may be substantially the same as the width of the third gate insulating layer 115 disposed below the inner wiring 213i, and the width of the outer wiring 213o may be substantially the same as the width of the third gate insulating layer 115 disposed below the outer wiring 213o.

[0161] The inner wiring 213i in the first region 1A may be electrically connected to the first thin film transistor T1, the second thin film transistor T2, etc. in the display region DA. The connection wiring 215 may be electrically connected to the first thin film transistor T1, the second thin film transistor T2, and / or the first wiring W1, etc. in the display region DA through the inner wiring 213i. Through the contact hole, the inner wiring 213i may be connected to a conductive layer formed on different layers in the display region DA, for example, a conductive layer formed on the interlayer insulating layer 116 or a conductive layer formed on the second gate insulating layer 113.

[0162] Through the use of the connection wiring 215, the outer wiring 213o in the second region 2A may be electrically connected to the first thin film transistor T1, the second thin film transistor T2, and / or the first wiring W1 in the display region DA. Through the contact hole, the outer wiring 213o may be connected to a conductive layer formed on different layers in the second region 2A, for example, a conductive layer placed on the interlayer insulating layer 116 or a conductive layer placed on the second gate insulating layer 113.

[0163] As described above, the inner wiring 213i and the outer wiring 213o may be electrically connected to the elements in the display region DA while being placed outside the display region DA. For example, the inner wiring 213i and the outer wiring 213o may extend toward the display region DA while being placed outside the display region DA, and may be at least partially placed in the display region DA.

[0164] As Figure 17 shown, the inner wiring 213i, the outer wiring 213o, and the second gate electrode G2 may be formed of the same material and may be on the same layer. In another embodiment, the inner wiring 213i and the first gate electrode G1 may be formed of the same material and may be on the same layer. The outer wiring 213o and the second gate electrode G2 may be formed of the same material and may be on the same layer. In other embodiments, the first gate electrode G1 and portions of the inner wiring 213i and the outer wiring 213o may be formed of the same material and may be on the same layer. The second gate electrode G2 and other portions of the inner wiring 213i and the outer wiring 213o may be formed of the same material and may be on the same layer.

[0165] Figure 18 An equivalent circuit diagram of a pixel PX included in a display device according to an embodiment is shown.

[0166] Referring Figure 18 , the pixel PX may include signal lines 131, 133, 151, 153, 155, and 161, a plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7 connected to the signal lines 131, 133, 151, 153, 155, and 161, a storage capacitor Cst, an initialization voltage line 141, a driving voltage line 165, and an organic light emitting device OLED.

[0167] As Figure 18 shown, each pixel PX may include signal lines 131, 133, 151, 153, 155, and 161, an initialization voltage line 141, and a driving voltage line 165. In another embodiment, at least one of the signal lines 131, 133, 151, 153, 155, and 161, the initialization voltage line 141, and / or the driving voltage line 165 may be shared by adjacent pixels.

[0168] Each pixel PX may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, and a second initialization thin film transistor T7.

[0169] Figure 18It is shown that the compensation thin-film transistor T3, the first initialization thin-film transistor T4, and the second initialization thin-film transistor T7 can be n-channel MOSFETs (NMOS), while the other thin-film transistors T1, T2, T5, and T6 can be p-channel MOSFETs (PMOS). In some embodiments, among the multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7, only one thin-film transistor can be NMOS and the other thin-film transistors can be PMOS. In another embodiment, all of the multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7 can be NMOS.

[0170] The first scan line 131 can supply the first scan signal S m . The second scan line 153 can supply the second scan signal S to the compensation gate electrode G3 of the compensation thin-film transistor T3 n' . The pre-scan line 151 can supply the pre-scan signal S to the first initialization thin-film transistor T4 n-1 . The emission control line 133 can supply the emission control signal E to the operation control thin-film transistor T5 and the emission control thin-film transistor T6 n . The post-scan line 155 can supply the post-scan signal S to the second initialization thin-film transistor T7 n+1 . The data line 161 that intersects the first scan line 131 can supply the data signal D to the operation control drain electrode D5 of the operation control thin-film transistor T5 through the switch thin-film transistor T2 m .

[0171] The drive voltage line 165 can supply the drive voltage ELVDD to the drive thin-film transistor T1. The initialization voltage line 141 can supply the initialization voltage Vint for initializing the pixel electrode to the drive thin-film transistor T1.

[0172] The drive gate electrode G1 of the drive thin-film transistor T1 can be connected to the lower electrode C1 of the storage capacitor Cst. The drive source electrode S1 of the drive thin-film transistor T1 can be connected to the drive voltage line 165 via the operation control thin-film transistor T5. The drive drain electrode D1 of the drive thin-film transistor T1 can be electrically connected to the pixel electrode of the organic light-emitting device OLED via the emission control thin-film transistor T6. The drive thin-film transistor T1 can receive the data signal D according to the switching operation of the switch thin-film transistor T2 m , and can provide the drive current I to the organic light-emitting device OLED OLED .

[0173] The switching gate electrode G2 of the switching thin film transistor T2 can be connected to the first scan line 131. The switching source electrode S2 of the switching thin film transistor T2 can be connected to the data line 161. The switching drain electrode D2 of the switching thin film transistor T2, which is connected to the driving source electrode S1 of the driving thin film transistor T1, can be connected to the driving voltage line 165 via the operation control thin film transistor T5. The switching thin film transistor T2 can be turned on in response to the first scan signal S received from the first scan line 131, and can perform a switching operation to transfer the data signal D received from the data line 161 to the driving source electrode S1 of the driving thin film transistor T1. m and can perform a switching operation to transfer the data signal D received from the data line 161 m to the driving source electrode S1 of the driving thin film transistor T1.

[0174] The compensation gate electrode G3 of the compensation thin film transistor T3 can be connected to the second scan line 153. The compensation drain electrode D3 of the compensation thin film transistor T3, which is connected to the driving drain electrode D1 of the driving thin film transistor T1, can be connected to the pixel electrode of the organic light emitting device OLED via the emission control thin film transistor T6. The compensation source electrode S3 of the compensation thin film transistor T3 can be connected to the lower electrode C1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 can be turned on in response to the second scan signal S received through the second scan line 153, and can electrically connect the driving gate electrode G1 and the driving drain electrode D1 of the driving thin film transistor T1, thereby performing diode connection on the driving thin film transistor T1. n' and can electrically connect the driving gate electrode G1 and the driving drain electrode D1 of the driving thin film transistor T1, thereby performing diode connection on the driving thin film transistor T1.

[0175] The first initialization gate electrode G4 of the first initialization thin film transistor T4 can be connected to the pre-scan line 151. The first initialization source electrode S4 of the first initialization thin film transistor T4 can be connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the initialization voltage line 141. The first initialization drain electrode D4 of the first initialization thin film transistor T4 can be connected to the lower electrode C1 of the storage capacitor Cst, the compensation source electrode S3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 can be turned on in response to the pre-scan signal S received from the pre-scan line 151, and can initialize the voltage of the driving gate electrode G1 of the driving thin film transistor T1 by supplying the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1. n-1 and can initialize the voltage of the driving gate electrode G1 of the driving thin film transistor T1 by supplying the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1.

[0176] The operation control gate electrode G5 of the operation control thin film transistor T5 can be connected to the emission control line 133, the operation control source electrode S5 of the operation control thin film transistor T5 can be connected to the drive voltage line 165, and the operation control drain electrode D5 of the operation control thin film transistor T5 can be connected to the drive source electrode S1 of the drive thin film transistor T1 and the switch drain electrode D2 of the switch thin film transistor T2.

[0177] The emission control gate electrode G6 of the emission control thin film transistor T6 can be connected to the emission control line 133, the emission control source electrode S6 of the emission control thin film transistor T6 can be connected to the drive drain electrode D1 of the drive thin film transistor T1 and the compensation drain electrode D3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 can be electrically connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting device OLED.

[0178] The operation control thin film transistor T5 and the emission control thin film transistor T6 can be simultaneously turned on in response to the emission control signal E received from the emission control line 133 n and can transmit the drive voltage ELVDD to the organic light emitting device OLED, so that the drive current I OLED can flow through the organic light emitting device OLED.

[0179] The second initialization gate electrode G7 of the second initialization thin film transistor T7 can be connected to the post-scan line 155, the second initialization drain electrode D7 of the second initialization thin film transistor T7 can be connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting device OLED, and the second initialization source electrode S7 of the second initialization thin film transistor T7 can be connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line 141. The second initialization thin film transistor T7 can be turned on in response to the post-scan signal S received from the post-scan line 155 n+1 and can initialize the pixel electrode of the organic light emitting device OLED.

[0180] As Figure 18 shown, the second initialization thin film transistor T7 can be connected to the post-scan line 155. In another embodiment, the second initialization thin film transistor T7 can be connected to the emission control line 133 and can be driven in response to the emission control signal E n while. At the same time, Figure 18 the positions of the source electrodes S1 to S7 and the drain electrodes D1 to D7 can be changed according to whether the transistor is a p-type transistor or an n-type transistor.

[0181] Figure 19A layout diagram showing the positions of a plurality of thin film transistors and storage capacitors in a pixel included in a display device according to an embodiment.

[0182] Referring to Figure 19 , a pixel in a display device according to an embodiment may include a first scan line 131, a second scan line 153, a front scan line 151, a rear scan line 155, an emission control line 133, and an initialization voltage line 141 extending in a first direction, and a data line 161 and a driving voltage line 165 extending in a second direction to intersect with the first scan line 131, the second scan line 153, the front scan line 151, the rear scan line 155, the emission control line 133, and the initialization voltage line 141. In an embodiment, the data line 161 may be two wirings provided in one pixel and separated from each other. In another embodiment, the data line 161 may be a single wiring included in each pixel.

[0183] The pixel may include a driving thin film transistor T1, a switching thin film transistor T2, a compensating thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, a second initialization thin film transistor T7, and a storage capacitor Cst.

[0184] In an embodiment, the driving thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, and the emission control thin film transistor T6 may be thin film transistors respectively including silicon semiconductors.

[0185] The compensating thin film transistor T3, the first initialization thin film transistor T4, and the second initialization thin film transistor T7 may be thin film transistors respectively including oxide semiconductors.

[0186] The semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, and the emission control thin film transistor T6 may be placed on the same layer and may include the same material. For example, the semiconductor layer may be formed of, for example, polysilicon.

[0187] The semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, and the emission control thin film transistor T6 may be arranged on a buffer layer 111 (as Figure 2 shown), and the buffer layer 111 is arranged on a substrate 110.

[0188] The semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, and the emission control thin film transistor T6 may be connected to each other and may be bent or curved in various forms.

[0189] In each of the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, and the emission control thin film transistor T6, a channel region, a source region, and a drain region may be included. The source region and the drain region may be located at two opposite sides of the channel region. For example, the source region and the drain region may be doped with impurities, such as n-type impurities or p-type impurities. The source region and the drain region are connected to a source electrode and a drain electrode, respectively. Hereinafter, the terms "source electrode" and "drain electrode" are respectively referred to as the terms "source region" and "drain region".

[0190] The driving thin film transistor T1 may include a driving semiconductor layer and a driving gate electrode. Since the driving semiconductor layer may have a bent form, the driving channel region may be formed longer than each of the other channel regions of the other thin film transistors. For example, since the driving semiconductor layer may have a form of being bent / kinked multiple times, such as omega "Ω" or the letter "S", the driving channel region of the driving thin film transistor T1 may have a large length in a narrow region. Since the driving channel region may have a large length, the driving range of the gate voltage applied to the driving gate electrode may be increased. Therefore, the gray scale of the light emitted from the organic light emitting device OLED can be controlled more finely, and the display quality can be improved. The driving gate electrode formed in an island shape may be stacked with the driving channel region, where the first gate insulating layer 112 (for example, in Figure 2 is) located between the driving gate electrode and the driving channel region.

[0191] The storage capacitor Cst may be arranged to be stacked with the driving thin film transistor T1. The storage capacitor Cst may include a lower electrode C1 and an upper electrode C2. The driving gate electrode may be used not only as the gate electrode of the driving thin film transistor T1 but also as the lower electrode C1 of the storage capacitor Cst. In other words, the driving gate electrode and the lower electrode C1 may be integrated with each other. The upper electrode C2 of the storage capacitor Cst may be arranged to be stacked with the lower electrode C1 of the storage capacitor Cst, and the second gate insulating layer 113 (for example, in Figure 2 is) located between the upper electrode C2 and the lower electrode C1 of the storage capacitor Cst.

[0192] The switching thin film transistor T2 may include a switching semiconductor layer and a switching gate electrode. One side of the switching semiconductor layer may be connected to the data line 161 through a contact hole, and the other side of the switching semiconductor layer may be connected to the driving semiconductor layer. The switching gate electrode may be arranged as a part of the first scan line 131.

[0193] The operation control thin film transistor T5 may include an operation control semiconductor layer and an operation control gate electrode. One side of the operation control semiconductor layer may be connected to the driving voltage line 165 through a contact hole, and the other side of the operation control semiconductor layer may be connected to the driving semiconductor layer. The operation control gate electrode may be arranged as a part of the emission control line 133.

[0194] The emission control thin film transistor T6 may include an emission control semiconductor layer and an emission control gate electrode. One side of the emission control semiconductor layer may be connected to the driving semiconductor layer, and the other side of the emission control semiconductor layer may be connected to the connection electrode CM through a contact hole. The connection electrode CM may be connected to the pixel electrode 310 of the organic light emitting device OLED (e.g., in Figure 2 ). The emission control gate electrode may be set as a part of the emission control line 133.

[0195] The semiconductor layers of the compensation thin film transistor T3, the first initialization thin film transistor T4, and the second initialization thin film transistor T7 may be disposed on the same layer and may include the same material. For example, the semiconductor layer may include an oxide semiconductor.

[0196] Each semiconductor layer may include a channel region, a source region, and a drain region. The source region and the drain region may be respectively disposed at two opposite sides of the channel region. For example, the source region and the drain region may be regions where the carrier concentration is increased due to plasma processing. The source region and the drain region may be respectively connected to a source electrode and a drain electrode. Hereinafter, the terms "source electrode" and "drain electrode" are respectively referred to as the terms "source region" and "drain region".

[0197] The compensation thin film transistor T3 may include a compensation semiconductor layer containing an oxide semiconductor and a compensation gate electrode. One side of the compensation semiconductor layer may be bridged to the driving gate electrode through the node connection line 166. The compensation semiconductor layer may be connected to the first initialization semiconductor layer. The other side of the compensation semiconductor layer may be connected to the driving semiconductor layer and the emission control semiconductor layer. The compensation gate electrode may be set as a part of the second scan line 153.

[0198] The first initialization thin film transistor T4 may include a first initialization semiconductor layer containing an oxide semiconductor and a first initialization gate electrode. One side of the first initialization semiconductor layer may be connected to the initialization voltage line 141, and the other side of the first initialization semiconductor layer may be bridged to the driving gate electrode through the node connection line 166. The first initialization gate electrode may be set as a part of the pre-scan line 151.

[0199] The second initialization thin film transistor T7 may include a second initialization semiconductor layer and a second initialization gate electrode. One side of the second initialization semiconductor layer may be connected to the initialization voltage line 141, and the other side of the second initialization semiconductor layer may be connected to the emission control semiconductor layer through a contact hole. The second initialization gate electrode may be set as a part of the post-scanning line 155.

[0200] A third gate insulating layer 115 corresponding to each channel region (e.g., in Figure 2 may be disposed between the compensation semiconductor layer and the compensation gate electrode, between the first initialization semiconductor layer and the first initialization gate electrode, and between the second initialization semiconductor layer and the second initialization gate electrode.

[0201] An interlayer insulating layer 116 (e.g., in Figure 2 may be disposed on the thin film transistors T3, T4, and T7 each including an oxide semiconductor, and the data line 161 and the driving voltage line 165 may be disposed on an upper region of the interlayer insulating layer 116 (e.g., in Figure 2 ).

[0202] In an embodiment, the initialization voltage line 141 and the oxide semiconductor layer may be disposed on the same layer and may be formed of the same material. In another embodiment, the initialization voltage line 141 and the driving gate electrode may be disposed on the same layer. In some embodiments, the initialization voltage line 141 and the upper electrode C2 of the storage capacitor Cst may be disposed on the same layer and may be formed of the same material.

[0203] In an embodiment, the first scanning line 131 and the emission control line 133 may be formed of the same material and may be formed on the same layer. The driving gate electrode and the data line 161, the driving voltage line 165, the node connection line 166, and the connection electrode CM may be formed of the same material and may be formed on the same layer as each other.

[0204] The display devices 10, 20, 30, 40, 50, and 60 according to embodiments may respectively include a first thin film transistor T1 including a silicon semiconductor and a second thin film transistor T2 including an oxide semiconductor. Accordingly, the power consumption of the display devices 10, 20, 30, 40, 50, and 60 may be reduced, and high quality may be achieved.

[0205] In addition, the display devices 10, 20, 30, 40, 50, and 60 according to the embodiments may each include a storage capacitor Cst that at least partially overlaps with the first thin film transistor T1. Since the second semiconductor layer AO2 of the second thin film transistor T2 and one electrode of the storage capacitor Cst can be disposed on the same layer, the process time and process cost of the display devices 10, 20, 30, 40, 50, and 60 can be reduced, and the display devices 10, 20, 30, 40, 50, and 60 can have a high integration density.

[0206] Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims. Accordingly, the scope of the present disclosure is not limited by the specific embodiments of the present disclosure, but is defined by the appended claims.

[0207] Example embodiments have been disclosed herein, and although specific terms have been employed, they have been used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some instances, as will be apparent to those of ordinary skill in the art upon submission of the present application, unless otherwise expressly stated, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display device, the display device comprises: a substrate including a display area; a first thin film transistor disposed in the display area of the substrate, the first thin film transistor having a first semiconductor layer including a silicon semiconductor and a first gate electrode insulated from the first semiconductor layer by a first gate insulating layer; a second thin film transistor disposed in the display area of the substrate, the second thin film transistor having a second semiconductor layer including an oxide semiconductor and a second gate electrode insulated from the second semiconductor layer; and a storage capacitor at least partially stacked with the first thin film transistor, the storage capacitor having a lower electrode and an upper electrode, wherein: the second semiconductor layer and one of the lower electrode and the upper electrode are disposed on the same layer, and the first semiconductor layer and the second semiconductor layer are disposed on different layers.

2. The display device according to claim 1, the display device further comprises: a second gate insulating layer disposed between the first gate electrode and the second semiconductor layer, wherein: the lower electrode of the storage capacitor and the first gate electrode of the first thin film transistor are formed as a single body, and the upper electrode of the storage capacitor is disposed on the second gate insulating layer.

3. The display device according to claim 1, wherein: the second semiconductor layer of the second thin film transistor includes a second channel region, a second source region, and a second drain region, the second source region and the second drain region are respectively disposed on two opposite sides of the second channel region, and the upper electrode of the storage capacitor and at least one of the second source region and the second drain region include the same material.

4. The display device according to claim 1, the display device further comprises: a display device driven by the first thin film transistor and the second thin film transistor, wherein, the first thin film transistor includes a driving thin film transistor to supply a driving current to the display device.

5. The display device according to claim 1, the display device further comprises: a first wiring located in the display area, wherein, the first wiring and the upper electrode of the storage capacitor are disposed on the same layer and include the same material.

6. The display device according to claim 1, the display device further comprises: a second wiring located in the display area, wherein, the second wiring and the first gate electrode are disposed on the same layer and include the same material.

7. The display device according to claim 1, the display device further comprises: a second gate insulating layer disposed between the first gate electrode and the second semiconductor layer; and a third gate insulating layer disposed between the second semiconductor layer and the second gate electrode, wherein: the lower electrode of the storage capacitor and the second semiconductor layer are disposed on the same layer; the dielectric layer of the storage capacitor and the third gate insulating layer are formed of the same material; and the upper electrode of the storage capacitor and the second gate electrode of the second thin film transistor are disposed on the same layer.

8. The display device according to claim 1, wherein the display device further comprises: an interlayer insulating layer disposed on the second gate electrode; a first electrode disposed on the interlayer insulating layer and connected to the first semiconductor layer through a contact hole defined in the interlayer insulating layer; a planarization layer disposed on the first electrode; a connection electrode disposed on the planarization layer and connected to the first electrode through a contact hole defined in the planarization layer; and an upper planarization layer disposed on the connection electrode.

9. The display device according to claim 8, wherein the display device further comprises: an organic light-emitting device disposed on the upper planarization layer, the organic light-emitting device including a pixel electrode, an intermediate layer including an organic emission layer, and a counter electrode.

10. A display device, the display device comprises: a substrate including a first region, a second region, and a bending region located between the first region and the second region, the bending region being bent about a bending axis; a first thin film transistor, a second thin film transistor, and a storage capacitor disposed in the first region of the substrate; a connection wiring extending from the first region through the bending region to the second region; and an inner wiring and an outer wiring respectively connected to the connection wiring, the inner wiring and the outer wiring being separated from each other by the bending region, wherein: the first thin film transistor has a first semiconductor layer including a silicon semiconductor and a first gate electrode insulated from the first semiconductor layer by a first gate insulating layer, the second thin film transistor has a second semiconductor layer including an oxide semiconductor layer and a second gate electrode insulated from the second semiconductor layer by a third gate insulating layer, the second semiconductor layer is disposed on the same layer as one of a lower electrode and an upper electrode of the storage capacitor, and the first semiconductor layer and the second semiconductor layer are provided on different layers.

11. The display device according to claim 10, wherein the display device further comprises: a display device driven by the first thin film transistor and the second thin film transistor, wherein the first thin film transistor is a driving thin film transistor for supplying a driving current to the display device.

12. The display device according to claim 10, wherein the storage capacitor is at least partially overlapped with the first thin film transistor.

13. The display device according to claim 10, wherein the display device further comprises: a second gate insulating layer disposed between the first gate electrode of the first thin film transistor and the second semiconductor layer, wherein: the lower electrode of the storage capacitor is formed integrally with the first gate electrode of the first thin film transistor, and the upper electrode of the storage capacitor is disposed on the second gate insulating layer.

14. The display device according to claim 10, wherein: parts of the inner wiring and the outer wiring are disposed on the same layer, and wherein the inner wiring, the outer wiring, and the first gate electrode include the same material.

15. The display device according to claim 10, wherein, Part of the inner wiring and the outer wiring are arranged on the same layer, and wherein, the inner wiring, the outer wiring, and the second gate electrode are made of the same material.

16. The display device according to claim 15, the display device further comprises: A third gate insulating layer located between the second semiconductor layer and the second gate electrode, wherein: The third gate insulating layer is arranged under the inner wiring, and The width of the third gate insulating layer arranged under the inner wiring is the same as the width of the inner wiring.

17. The display device according to claim 10, the display device further comprises: An interlayer insulating layer arranged on the substrate and covering the second gate electrode; A first electrode arranged on the interlayer insulating layer and connected to the first semiconductor layer; and A planarization layer covering the first electrode.

18. The display device according to claim 17, the display device further comprises: An organic material layer arranged between the substrate and the connection wiring in the bending region, wherein, The organic material layer and the planarization layer are made of the same material.

19. The display device according to claim 18, the display device further comprises: A connection electrode arranged on the planarization layer and connected to the first electrode via a contact hole defined in the planarization layer, wherein, The connection wiring and the connection electrode are made of the same material.

20. The display device according to claim 18, the display device further comprises: An inorganic insulating layer including an opening or a groove corresponding to the bending region, wherein, The organic material layer fills the opening or the groove of the inorganic insulating layer.

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