Semiconductor device and method of forming the same

Abstract

The present invention discloses a semiconductor device and a method for forming the same. One of the semiconductor devices includes a first conductive layer, an organic layer, a silicon layer, a magnetic layer, and a second conductive layer. The organic layer is disposed on the first conductive layer and exposes a portion of the first conductive layer. The silicon layer is disposed on the organic layer and contacts the organic layer. The magnetic layer is disposed on the first conductive layer. The second conductive layer is disposed on the organic layer and the magnetic layer to electrically connect the first conductive layer.

Description

Technical Field

[0001] An embodiment of the present invention relates to a semiconductor device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically made by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements on the semiconductor substrate.

[0003] In general, an inductor is a passive electrical component that can store energy in a magnetic field formed by an electric current passing therethrough. Inductors can be used in a wide variety of applications. However, there are many challenges associated with semiconductor devices that include inductors. Summary of the invention

[0004] According to an embodiment of the present invention, a semiconductor device includes a first conductive layer, an organic layer, a silicon layer, a magnetic layer, and a second conductive layer. The organic layer is disposed on the first conductive layer and exposes a portion of the first conductive layer. The silicon layer is disposed on the organic layer and contacts the organic layer. The magnetic layer is disposed on the first conductive layer. The second conductive layer is disposed on the organic layer and the magnetic layer to electrically connect the first conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the key dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] Figure 1 is a flow chart illustrating a method of forming a semiconductor device according to some embodiments of the present invention.

[0007] FIG. 2A to FIG. 2E is a schematic cross-sectional view of a method of forming a semiconductor device according to some embodiments.

[0008] Figure 3 is a schematic cross-sectional view of a semiconductor device according to some embodiments.

[0009] Figure 4 is a schematic cross-sectional view of a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and structures are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a second feature on or on a first feature may include an embodiment in which the second feature is formed to be in direct contact with the first feature, and may also include an embodiment in which an additional feature may be formed between the second feature and the first feature so that the second feature may not be in direct contact with the first feature. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than itself representing the relationship between the various embodiments and / or configurations discussed.

[0011] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "on", "over", "overlying", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature(s) shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0012] The present invention may also include other features and processes. For example, a test structure may be included to assist in verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may, for example, include a test pad formed in a redistribution layer or on a substrate and allowing testing of a three-dimensional package or a three-dimensional integrated circuit, the use of a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used together with a test method including intermediate verification of known good dies to improve yield and reduce costs.

[0013] Figure 1 is a flow chart illustrating a method of forming a semiconductor device according to some embodiments of the present invention. FIG. 2A to FIG. 2E is a schematic cross-sectional view of a method of forming a semiconductor device according to some embodiments.

[0014] Reference Figure 1 and Figure 2AIn step S10, a silicon layer 118 is formed on the first conductive layer 116. In some embodiments, a substrate 100 is provided. The substrate 100 is a semiconductor substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon germanium substrate, or a substrate formed of other suitable semiconductor materials. Depending on the design requirements, the substrate 100 may be a P-type substrate or an N-type substrate, and may have a doped region therein.

[0015] Circuit 102 is formed on substrate 100. In some embodiments, circuit 102 includes a gate stack formed of a dielectric layer and an electrode layer. The dielectric layer may include an interfacial layer (IL), and a high-k layer having a dielectric constant greater than about 4, greater than about 8, or even greater than about 10. The dielectric layer is deposited by a suitable technique such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, etc. The electrode layer may include a single layer or multiple layers (e.g., a metal layer, a liner layer, a wetting layer, an adhesion layer, combinations thereof, etc.), and may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, etc.

[0016] An inter-layer dielectric (ILD) layer 104 is formed on the substrate 100. In some embodiments, the inter-layer dielectric layer 104 covers the circuit 102. In some embodiments, the inter-layer dielectric layer 104 includes a low dielectric constant dielectric material having a dielectric constant of less than about 4, less than about 3.5, or even less than about 3. The low dielectric constant material includes phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), silicon oxycarbide (SiO x C y ), spin-on-glass (SOG), spin-on-polymer (SOP), or a combination thereof. The interlayer dielectric layer 104 may be formed by a suitable method such as spin coating, chemical vapor deposition, or plasma-enhanced chemical vapor deposition (PECVD). The interlayer dielectric layer 104 may have a single-layer or multi-layer structure.

[0017] Contacts 106 are formed through the interlayer dielectric layer 104 to provide electrical contacts for connecting the circuit 102. In some embodiments, openings are formed in the interlayer dielectric layer 104 by photolithography and etching processes. A diffusion barrier layer and / or an adhesion layer (not shown) may be lined and the openings may be filled with a conductive material. In some embodiments, the diffusion barrier layer comprises TaN, Ta, TiN, Ti, CoW, combinations thereof, etc., and the conductive material comprises copper, tungsten, aluminum, silver, combinations thereof, etc.

[0018] An interconnect structure 108 is formed over the substrate 100. In some embodiments, the interconnect structure 108 is formed on the interlayer dielectric layer 104. In some embodiments, the interconnect structure 108 includes one or more inter-metal dielectric (IMD) layers 110 and associated metallization features 112 (e.g., metal layers and vias) embedded in the IMD layers 110. Typically, the one or more IMD layers 110 and associated metallization features 112 are used to interconnect the circuits 102 to each other and to provide external electrical connections. The IMD layer 110 includes a low dielectric constant dielectric material having a dielectric constant of less than about 4, less than about 3.5, or even less than about 3. Low dielectric constant materials include phosphosilicate glass, borophosphosilicate glass, fluorinated silicate glass, silicon oxycarbide, spin-on glass, spin-on polymers, combinations thereof, and the like. In some embodiments, the IMD layer 110 is formed by a suitable method such as spin coating, chemical vapor deposition, or plasma enhanced chemical vapor deposition.

[0019] In some embodiments, one or more insulating etch stop layers (not shown) may be positioned between adjacent dielectric layers (e.g., interlayer dielectric layer 104 and intermetallic dielectric layer 110). The insulating etch stop layer is formed of a dielectric material having a different etch selectivity than the adjacent layers. In some embodiments, the insulating etch stop layer may be formed of SiN, SiCN, SiCO, combinations thereof, and the like, and may be formed by a suitable method such as chemical vapor deposition or plasma enhanced chemical vapor deposition.

[0020] A passivation layer 114 is formed on the substrate 100. In some embodiments, the passivation layer 114 is formed on the intermetallic dielectric layer 110. In some embodiments, the passivation layer 114 may be formed of a dielectric material such as SiN, plasma-enhanced oxide (PEOX), plasma-enhanced SiN (PE-SiN), plasma-enhanced undoped silicate glass (PE-USG), high-density plasma (HDP) chemical vapor deposition (CVD) oxide, or a combination thereof. The passivation layer 114 is formed to protect the underlying layers from various environmental pollutants.

[0021] A first conductive layer 116 is formed over the passivation layer 114. In some embodiments, the first conductive layer 116 includes aluminum, copper, or a copper alloy. In some embodiments, the first conductive layer 116 may be formed by an electroplating process. In alternative embodiments, the first conductive layer 116 may include a copper layer coated with electroless nickel electro-lesspalladium immersion gold (ENEPIG), wherein the electroless nickel palladium immersion gold includes a nickel layer, a palladium layer on the nickel layer, and a gold layer on the palladium layer. The gold layer may be formed using immersion plating. In yet other alternative embodiments, other conductive materials may be used to form the first conductive layer 116. Those skilled in the art will appreciate that the number and size of the first conductive layer 116 are merely examples, and the number and size of the first conductive layer 116 are not limited by the embodiments of the present invention.

[0022] In some embodiments, a silicon layer 118 is formed on the exposed surface of the first conductive layer 116. In some embodiments, the silicon layer 118 is formed on the sidewalls 116a and the top surface 116b of the first conductive layer 116 and physically contacts the sidewalls 116a and the top surface 116b. In some embodiments, the silicon layer 118 has a silicon concentration of not less than 40%. In some embodiments, the silicon concentration of the silicon layer 118 is in a range from 40% to 100%. In some embodiments, the silicon layer 118 is an amorphous silicon layer. In some embodiments, for example, the silicon layer 118 is a nitrogen-free layer. In some embodiments, for example, the silicon layer 118 is an oxygen-free layer. The silicon layer 118 can be formed by a suitable method such as chemical vapor deposition or plasma enhanced chemical vapor deposition. The precursor gas of the deposition process includes a silicon-containing gas, which can be a silane gas, such as silane, methyl silane (1MS), dimethyl silane (2MS), trimethyl silane (3MS), and combinations thereof. In addition, a carrier gas that does not react with the precursor gas may be added, wherein the carrier gas may include an inert gas such as helium, argon, etc. The precursor gas may or may not include other gases that react with the silicon-containing gas. In some embodiments, for example, the precursor gas for forming the silicon layer 118 includes silane, and the carrier gas includes argon. For example, the silicon layer 118 may be a substantially conformal layer, wherein the thickness of the silicon layer 118 on the sidewall 116a of the first conductive layer 116 and the thickness of the silicon layer 118 on the top surface 116b are close to each other. In some embodiments, the thickness of the silicon layer 118 may be greater than 500 angstroms. In some embodiments, the thickness of the silicon layer 118 may be less than about 1 μm. The silicon layer 118 may have a single-layer or multi-layer structure.

[0023] In some embodiments, a dielectric layer 120 is formed on the silicon layer 118. In some embodiments, the dielectric layer 120 physically contacts the silicon layer 118. In some embodiments, the dielectric layer 120 comprises, for example, SiN, SiC, SiCN, SiCO, SiON, SiO x The dielectric layer 120 may be an inorganic material such as nitride-oxide-nitride (NON), oxide-nitride-oxide (ONO), or a combination thereof, and may be formed by a suitable method such as chemical vapor deposition or plasma enhanced chemical vapor deposition. The dielectric layer 120 may have a single-layer or multi-layer structure. For example, the thickness of the dielectric layer 120 may be in the range from about 2000 angstroms to 2.5 μm.

[0024] In some embodiments, a material layer (not shown) of the silicon layer 118 and a material layer (not shown) of the dielectric layer 120 are sequentially blanket-formed on the first conductive layer 116 and the passivation layer 114, and the material layer of the silicon layer 118 and the material layer of the dielectric layer 120 are patterned using the same mask to form the dielectric layer 120 and the silicon layer 118. Figure 2A As shown in FIG. 1 , for example, a bottom portion 118 a of the silicon layer 118 is located below a bottom portion 120 a of the dielectric layer 120 .

[0025] Reference Figure 1 and Figure 2A In step S20, an organic layer 122 is formed on the silicon layer 118, wherein the silicon layer 118 is disposed between the organic layer 122 and the first conductive layer 116. In some embodiments, the organic layer 122 is formed on the substrate 100 to cover the first conductive layer 116 and fill the opening between the first conductive layers 116. In some embodiments, the organic layer 122 is disposed on the dielectric layer 120 on the sidewall 116a and the top surface 116b of the first conductive layer 116, and physically contacts the dielectric layer 120. In some embodiments, the organic layer 122 may be formed of a polymer containing carbon and oxygen (e.g., epoxy resin, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), etc.). For example, the thickness of the organic layer 122 is greater than 30 μm. The organic layer 122 may have a single-layer or multi-layer structure. The organic layer 122 may be formed by a suitable method such as spin coating, lamination, deposition, etc. In some embodiments, the adhesion of the organic layer 122 to the first conductive layer 116 is improved due to the silicon layer 118 formed therebetween. Therefore, delamination of the organic layer 122 from the first conductive layer 116 is prevented, and the reliability of the semiconductor device is improved.

[0026] Reference Figure 2B , an opening OP1 is formed in the silicon layer 118, the dielectric layer 120, and the organic layer 122 to expose a portion of the first conductive layer 116. In some embodiments, the opening OP1 is formed by photolithography and etching processes. The etching process may be a wet etching process or a dry etching process.

[0027] Reference Figure 1 and Figure 2BIn step S30, a silicon layer 124 and an inorganic layer 126 are sequentially formed on the organic layer 122, wherein the silicon layer 124 is disposed between the organic layer 122 and the inorganic layer 126. In some embodiments, for example, the silicon layer 124 is blanket-formed on the organic layer 122, and the inorganic layer 126 is blanket-formed on the silicon layer. In some embodiments, before forming the silicon layer 124, plasma treatment may be performed on the exposed surface of the organic layer 122. For example, the plasma treatment is an argon plasma treatment. In some embodiments, for example, by performing the plasma treatment, the carbon-rich surface of the organic layer 122 may be changed into an oxygen-rich surface. In some embodiments, the silicon layer 124 is formed on the modified surface of the organic layer 122. In some embodiments, for example, Si-O bonds may be formed between silicon atoms at the surface of the silicon layer 124 and oxygen atoms at the modified surface of the organic layer 122. In addition, Si-Si bonds and / or Si-H bonds may be formed between the silicon layer 124 and the organic layer 122. In some embodiments, the silicon layer 124 may be deposited by using silane as a precursor gas and using argon as a carrier gas. In the case of using argon as a carrier gas, the plasma treatment may be omitted because the argon acts as a plasma treatment. The material and formation method of the silicon layer 124 may be similar to the material and formation method of the silicon layer 118, and the details have been repeatedly described herein. In some embodiments, the material of the silicon layer 118 may be the same or different from the material of the silicon layer 124. The silicon concentration of the silicon layer 118 may be the same or different from the silicon concentration of the silicon layer 124.

[0028] An inorganic layer 126 is formed on the silicon layer 124. In some embodiments, the inorganic layer 126 comprises SiN, SiC, SiCN, SiCO, SiON, SiO x , nitride-oxide-nitride (NON), oxide-nitride-oxide (ONO), or a combination thereof, and can be formed by a suitable method such as chemical vapor deposition or plasma enhanced chemical vapor deposition. The inorganic layer 126 can have a single-layer or multi-layer structure. For example, the thickness of the inorganic layer 126 is in the range from about 2000 angstroms to 2.5 μm. In some embodiments, for example, covalent bonds such as Si-N bonds and / or Si-O bonds can be formed between the silicon layer 124 and the inorganic layer 126 containing nitride and / or oxide.

[0029] In some embodiments, when the silicon layer 124 is formed on the organic layer 122, covalent bonds such as Si-O bonds, Si-Si bonds, and / or Si-H bonds are formed between the silicon layer 124 and the organic layer 122. For example, when the inorganic layer 126 containing nitride and / or oxide is deposited on the silicon layer 124, covalent bonds such as Si-N bonds and / or Si-O bonds may be formed between the silicon layer 124 and the inorganic layer 126. In some embodiments, by inserting the silicon layer 124 between the organic layer 122 and the inorganic layer 126 and in physical contact with the organic layer 122 and the inorganic layer 126, covalent bonds other than hydrogen bonds are formed between the silicon layer 124 and the organic layer 122 and between the silicon layer 124 and the inorganic layer 126. Therefore, the inorganic layer 126 adheres to the organic layer 122 through the interposed silicon layer 124, and the adhesion between the inorganic layer 126 and the organic layer 122 is improved. In some embodiments, when viewed on a microscopic scale, the interface between the silicon layer 124 and the organic layer 122 or between the silicon layer 124 and the inorganic layer 126 is smooth, and burrs indicating delamination at the interface are significantly reduced. In addition, the silicon layer 124 is disposed between the first conductive layer 116 and the inorganic layer 126, and thus the inorganic layer 126 does not contact the first conductive layer 116. Therefore, delamination of the inorganic layer 126 from the first conductive layer 116 is prevented.

[0030] Reference Figure 2C , an opening OP2 is formed in the silicon layer 124 and the inorganic layer 126 to expose the first conductive layer 116. In some embodiments, the opening OP2 is formed by patterning the silicon layer 124 and the inorganic layer 126 using the same mask. That is, the opening OP2 is formed by photolithography and etching processes. In some embodiments, the opening OP2 is disposed in the opening OP1.

[0031] Reference Figure 1 and Figure 2CIn step S40, a magnetic layer 128 is formed on the first conductive layer 116. In some embodiments, the magnetic layer 128 is formed on the inorganic layer 126 on the first conductive layer 116. In some embodiments, the magnetic layer 128 includes a magnetic metal material containing cobalt (Co), zirconium (Zr), tantalum (Ta), niobium (Nb), rhenium (Re), neodymium (Nd), praseodymium (Pr), dysprosium (Dy), or a combination thereof. In some embodiments, the magnetic layer 128 includes an amorphous cobalt (Co) alloy, which includes cobalt (Co) and zirconium (Zr). Zirconium (Zr) helps to make cobalt (Co) amorphous. In some embodiments, the magnetic layer 128 includes a cobalt-zirconium (CoZr) alloy having one or more additional elements, such as tantalum (Ta) and niobium (Nb). In some other embodiments, the magnetic layer 128 comprises a cobalt-zirconium (CoZr) alloy having one or more additional elements, such as rare earth elements, which contribute to improving the ferromagnetic resonance of the cobalt-zirconium (CoZr) alloy. The rare earth elements include rhenium (Re), neodymium (Nd), praseodymium (Pr), or dysprosium (Dy). In some embodiments, the magnetic layer 128 comprises CoZrTa, CoZr, CoZrRe, NiFe, or a combination thereof. The magnetic layer 128 can be formed by a suitable method, such as physical vapor deposition, chemical vapor deposition, or the like.

[0032] Reference Figure 1 and Figure 2D In step S50, an organic layer 130 is formed on the magnetic layer 128. In some embodiments, the organic layer 130 is formed on the inorganic layer 126 to cover the magnetic layer 128. The material and formation method of the organic layer 130 may be similar to the material and formation method of the organic layer 122, and the details have been repeatedly described herein. In some embodiments, the material of the organic layer 122 and the material of the organic layer 130 may be the same or different. An opening OP3 is formed in the organic layer 130 to expose the first conductive layer 116, and the opening OP3 is disposed in the opening OP2. The opening OP3 is formed by photolithography and etching processes.

[0033] Reference Figure 1 and Figure 2DIn step S60, a silicon layer 132 and an inorganic layer 134 are sequentially formed on the organic layer 130, wherein the silicon layer 132 is disposed between the organic layer 130 and the inorganic layer 134. In some embodiments, the silicon layer 132 is formed on the organic layer 130, and the inorganic layer 134 is formed on the silicon layer 132. The silicon layer 132 and the inorganic layer 134 include an opening OP4 to expose a portion of the first conductive layer 116. The opening OP4 is formed by photolithography and etching processes, and the opening OP4 is disposed in the opening OP3. The materials and formation methods of the silicon layer 132 and the inorganic layer 134 may be similar to the materials and formation methods of the silicon layer 124 and the inorganic layer 126, and the details have been repeatedly described herein. In some embodiments, the material of the silicon layer 132 may be the same as or different from the materials of the silicon layers 118 and 124. In some embodiments, the material of the inorganic layer 134 may be the same as or different from the material of the inorganic layer 126. In some embodiments, when the silicon layer 132 is formed on the organic layer 130, covalent bonds such as Si-O bonds, Si-Si bonds, and / or Si-H bonds may be formed between the organic layer 130 and the silicon layer 132. In addition, for example, when the inorganic layer 134 containing nitride and / or oxide is deposited on the silicon layer 132, covalent bonds such as Si-N bonds and / or Si-O bonds may be formed between the silicon layer 132 and the inorganic layer 134. In some embodiments, by inserting the silicon layer 132 between the organic layer 130 and the inorganic layer 134 and in physical contact with the organic layer 130 and the inorganic layer 134, covalent bonds other than hydrogen bonds are formed between the silicon layer 132 and the organic layer 130 and between the silicon layer 132 and the inorganic layer 134. Therefore, the inorganic layer 134 adheres to the organic layer 130 through the interposed silicon layer 132, and the adhesion between the inorganic layer 134 and the organic layer 130 is improved. In addition, the silicon layer 132 is disposed between the first conductive layer 116 and the inorganic layer 134, and thus the inorganic layer 134 does not contact the first conductive layer 116. Therefore, delamination of the inorganic layer 134 from the first conductive layer 116 is prevented.

[0034] Reference Figure 1 and Figure 2EIn step S70, a second conductive layer 136 is formed on the organic layer 130 to electrically connect the first conductive layer 116. In some embodiments, the second conductive layer 136 is formed on the inorganic layer 134. In some embodiments, a conductive material is filled into the opening OP4 to form a through hole 138 in the opening OP4 and to form the second conductive layer 136 on the through hole 138. In some embodiments, the second conductive layer 136 is electrically connected to the first conductive layer 116 through the through hole 138. The through hole 138 and the second conductive layer 136 include aluminum, copper, or a copper alloy. In some embodiments, the second conductive layer 136 may be formed by an electroplating process. In alternative embodiments, the through hole 138 and the second conductive layer 136 may include a copper layer coated with electroless nickel palladium immersion gold (ENEPIG), the electroless nickel palladium immersion gold including a nickel layer, a palladium layer on the nickel layer, and a gold layer on the palladium layer. The gold layer may be formed using immersion plating. In yet other alternative embodiments, other conductive materials may be used to form the through hole 138 and the second conductive layer 136. Those skilled in the art will appreciate that the number and size of the through holes 138 are merely examples, and the number and size of the through holes 138 are not limited by the embodiments of the present invention. Similarly, although the second conductive layer 136 is electrically connected to the two first conductive layers 116, the present invention is not limited thereto. In some alternative embodiments, the second conductive layer 136 may be electrically connected to one or more than two first conductive layers 116.

[0035] In some embodiments, the first conductive layer 116, the second conductive layer 136, and the through hole 138 therebetween form a post-passivation interconnect (PPI) structure 140 on the magnetic layer 128. The magnetic layer 128 is insulated from the post-passivation interconnect structure 140 by the organic layer 130, the silicon layer 132, and the inorganic layer 134. In some embodiments, for example, the post-passivation interconnect structure 140 is spiral-shaped, and the magnetic layer 128 is disposed in the central region of the spiral. In some embodiments, for example, the second conductive layer 136 may be formed as a connection pad at the end of the spiral structure. In some embodiments, for example, the post-passivation interconnect structure 140 forms a magnetic inductor structure with the magnetic layer 128.

[0036] In some embodiments, a dielectric layer 142 is formed on the inorganic layer 134 to encapsulate the second conductive layer 136. In some embodiments, the dielectric layer 142 may be formed of a polymer such as epoxy resin, polyimide, benzocyclobutane (BCB), polybenzoxazole (PBO), etc. The dielectric layer 142 may be formed by a suitable method such as spin coating, lamination, deposition, etc.

[0037] Reference Figure 1 and Figure 2EIn step S80, an under bump metallization (UBM) layer 144 and a bump 146 are formed to electrically connect the second conductive layer 136. In some embodiments, the under bump metallization layer 144 is formed in and on the dielectric layer 142 to electrically connect to the second conductive layer 136. In some embodiments, the under bump metallization layer 144 includes copper, nickel, titanium, a combination thereof, etc., and is formed by an electroplating process. Then, a bump 146 is formed on the under bump metallization layer 144 and electrically connected to the under bump metallization layer 144. In some embodiments, the bump 146 includes a conductive material with a low resistivity (e.g., Sn, Pb, Ag, Cu, Ni, Bi, or an alloy thereof), and can be formed by a suitable process such as evaporation, plating, drop ball, or screen printing. Therefore, a semiconductor structure including a magnetic inductor structure and a bump 146 is completed. In some embodiments, the magnetic inductor structure and the packaging structure are formed in the same area, but the present invention is not limited thereto. In some alternative embodiments, the substrate 100 may have a first region and a second region adjacent to the first region, the first region being a region in which a magnetic inductor structure is formed, and the second region being a packaging region configured to integrate the semiconductor device into an application specific integrated circuit (ASIC).

[0038] In some embodiments, Figure 2A As shown in FIG. 1 , the silicon layer 118 and the dielectric layer 120 are formed by the same patterning process, but the present invention is not limited thereto. In some alternative embodiments, such as Figure 3 As shown in , the silicon layer 118 and the dielectric layer 120 can be formed by different patterning processes. That is, a material layer (not shown in the figure) of the silicon layer 118 is blanket-formed on the first conductive layer 116 and the passivation layer 114 and is patterned by using a first mask to form the silicon layer 118. Next, a material layer (not shown in the figure) of the dielectric layer 120 is blanket-formed on the silicon layer 118 and the passivation layer 114 and is patterned by using a second mask different from the first mask to form the dielectric layer 120. Therefore, as shown in FIG. Figure 3 As shown in , the entire silicon layer 118 is located within the dielectric layer 120, and the dielectric layer 120 covers the entire exposed surface of the silicon layer 118. Therefore, for example, the silicon layer 118 is not exposed. In addition, in some alternative embodiments, such as Figure 4 As shown in , the dielectric layer 120 can be omitted, that is, the organic layer 122 is formed on the silicon layer 118 and physically contacts the silicon layer 118, and the adhesion between the organic layer 122 and the first conductive layer 116 is also improved.

[0039] In some embodiments, the semiconductor device includes a first conductive layer 116, a magnetic layer 128, a second conductive layer 136, organic layers 122, 130, inorganic layers 126, 134, and silicon layers 124, 132 located between the organic layers 122, 130 and the inorganic layers 126, 134. In some embodiments, the organic layer 122 may be disposed between the first conductive layer 116 and the magnetic layer 128. In some embodiments, the organic layer 130 may be disposed between the second conductive layer 136 and the magnetic layer 128. Since the inorganic layers 126, 134 are adhered to the organic layers 122, 130 through the silicon layers 124, 132, the adhesion of the inorganic layers 126, 134 to the organic layers 122, 130 is improved. Therefore, delamination of the inorganic layers 126, 134 from the organic layers 122, 130 is prevented, and the reliability of the semiconductor device is improved. In addition, in some embodiments, a silicon layer 118 is formed between the first conductive layer 116 and the organic layer 122, and thus the adhesion of the organic layer 122 to the first conductive layer 116 is improved. Therefore, delamination of the organic layer 122 from the first conductive layer 116 is prevented, and the reliability of the semiconductor device is improved. In some embodiments, for example, silicon layers 124, 132 are formed between the organic layers 122, 130 and the inorganic layers 126, 134, respectively. In some alternative embodiments, one of the silicon layers may be omitted, that is, the silicon layer may be inserted between the organic layer and the inorganic layer as required.

[0040] Conventionally, in semiconductor devices including magnetic inductor structures, high topography structures and thus high film stress may cause severe delamination and poor adhesion between an organic layer and an inorganic layer or between an organic layer and a conductive layer. In some embodiments, by inserting a silicon layer between an organic layer and an inorganic layer, covalent bonds rather than hydrogen bonds may be formed between the silicon layer and the organic layer and between the silicon layer and the inorganic layer. Thus, adhesion between the organic layer and the inorganic layer is improved. In addition, the silicon layer between the organic layer and the conductive layer may improve adhesion between the organic layer and the conductive layer. Thus, delamination of the organic layer from the inorganic layer or the conductive layer is reduced, and reliability of the semiconductor device is improved.

[0041] According to some embodiments of the present invention, a semiconductor device includes a first conductive layer, an organic layer, a silicon layer, a magnetic layer, and a second conductive layer. The organic layer is disposed on the first conductive layer and exposes a portion of the first conductive layer. The silicon layer is disposed on the organic layer and contacts the organic layer. The magnetic layer is disposed on the first conductive layer. The second conductive layer is disposed on the organic layer and the magnetic layer to electrically connect the first conductive layer.

[0042] According to some embodiments of the present invention, the silicon layer is an amorphous silicon layer.

[0043] According to some embodiments of the present invention, the semiconductor device further includes an inorganic layer, wherein the silicon layer is disposed between the organic layer and the inorganic layer, and the inorganic layer does not contact the first conductive layer.

[0044] According to some embodiments of the present invention, the silicon layer contacts the inorganic layer.

[0045] According to some embodiments of the present invention, the organic layer is disposed between the first conductive layer and the magnetic layer.

[0046] According to some embodiments of the present invention, the organic layer is disposed between the second conductive layer and the magnetic layer.

[0047] According to some embodiments of the present invention, the semiconductor device further includes a bump disposed on the second conductive layer and electrically connected to the second conductive layer.

[0048] According to an alternative embodiment of the present invention, a semiconductor device includes a first conductive layer, an organic layer, a silicon layer, and a magnetic layer. The organic layer is arranged beside the first conductive layer. The silicon layer is arranged between the organic layer and the first conductive layer. The magnetic layer is arranged on the first conductive layer.

[0049] According to some embodiments of the present invention, the silicon layer is an amorphous silicon layer.

[0050] According to some embodiments of the present invention, the silicon layer contacts the first conductive layer and the organic layer.

[0051] According to some embodiments of the present invention, the semiconductor device further includes a dielectric layer disposed between the organic layer and the silicon layer, and the dielectric layer does not contact the first conductive layer.

[0052] According to some embodiments of the present invention, the dielectric layer is an inorganic layer.

[0053] According to some embodiments of the present invention, the silicon layer is disposed on sidewalls and a top surface of the first conductive layer and contacts the sidewalls and the top surface.

[0054] According to some embodiments of the present invention, the semiconductor device further includes a bump electrically connected to the first conductive layer.

[0055] According to some alternative embodiments of the present invention, a method for forming a semiconductor device includes at least the following steps: forming an organic layer on a first conductive layer, wherein a portion of the first conductive layer is exposed; forming a silicon layer on the organic layer, wherein the silicon layer contacts the organic layer; forming a magnetic layer on the first conductive layer; forming a second conductive layer on the organic layer and the magnetic layer to electrically connect the first conductive layer.

[0056] According to some embodiments of the present invention, the silicon layer is formed by plasma enhanced chemical vapor deposition (PECVD).

[0057] According to some embodiments of the present invention, the method further comprises performing a plasma treatment on the organic layer before forming the silicon layer.

[0058] According to some embodiments of the present invention, the method further comprises forming an inorganic layer on the silicon layer, wherein the silicon layer is disposed between the organic layer and the inorganic layer.

[0059] According to some embodiments of the present invention, the organic layer is formed between the first conductive layer and the magnetic layer.

[0060] According to some embodiments of the present invention, the organic layer is formed between the second conductive layer and the magnetic layer.

[0061] The above content summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures to implement the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications to this article without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A first conductive layer including a first surface; an organic layer disposed on the first surface of the first conductive layer; a silicon layer disposed on and contacting the organic layer, and extending onto and contacting the first surface of the first conductive layer; A magnetic layer, disposed on the first conductive layer; as well as The second conductive layer is disposed on the organic layer and the magnetic layer to electrically connect the first conductive layer, wherein the magnetic layer is located between the first conductive layer and the second conductive layer. The semiconductor device according to claim 1 , wherein the silicon layer is an amorphous silicon layer. 3 . The semiconductor device according to claim 1 , further comprising a non-conductive inorganic layer, wherein the silicon layer is provided between the organic layer and the non-conductive inorganic layer, and the non-conductive inorganic layer does not contact the first conductive layer. 4 . The semiconductor device according to claim 1 , wherein the organic layer is provided between the first conductive layer and the magnetic layer. 5 . The semiconductor device according to claim 1 , wherein the organic layer is provided between the second conductive layer and the magnetic layer. 6 . The semiconductor device according to claim 1 , further comprising a bump disposed on the second conductive layer and electrically connected to the second conductive layer. 7 . The semiconductor device according to claim 1 , wherein the organic layer includes a second surface and a sidewall surface between the first surface and the second surface of the first conductive layer, and the silicon layer is located on the second surface, the sidewall surface, and the first surface. 8 . The semiconductor device according to claim 1 , further comprising another silicon layer, wherein the another silicon layer is located between a sidewall of the first conductive layer and the organic layer.

9. A semiconductor device, characterized in that: include: a first conductive layer; An organic layer and a non-conductive inorganic layer are disposed on the first conductive layer; a silicon layer disposed between the organic layer and the non-conductive inorganic layer and in contact with the organic layer and the non-conductive inorganic layer, wherein the organic layer is located between the silicon layer and the first conductive layer; as well as A magnetic layer and a second conductive layer, wherein the magnetic layer is located between the first conductive layer and the second conductive layer. 10 . The semiconductor device according to claim 9 , wherein the silicon layer is an amorphous silicon layer. 11 . The semiconductor device according to claim 9 , further comprising a dielectric layer disposed between the organic layer and the first conductive layer, and the dielectric layer does not contact the first conductive layer. 12 . The semiconductor device according to claim 9 , wherein the silicon layer is further disposed on and contacts sidewalls and a top surface of the first conductive layer. 13 . The semiconductor device according to claim 9 , further comprising a bump electrically connected to the first conductive layer. 14 . The semiconductor device according to claim 9 , wherein a silicon concentration in the silicon layer ranges from 40% to 100%.

15. A method for forming a semiconductor device, characterized in that: include: forming an organic layer over the first conductive layer, wherein the first surface of the first conductive layer is exposed; forming a silicon layer on the organic layer, wherein the silicon layer contacts the organic layer and the silicon layer extends onto the first surface of the first conductive layer and contacts the first surface of the first conductive layer; forming a magnetic layer on the first conductive layer; as well as A second conductive layer is formed on the organic layer and the magnetic layer to electrically connect the first conductive layer, wherein the magnetic layer is located between the first conductive layer and the second conductive layer.

16. The method of claim 15, wherein the silicon layer is formed by plasma enhanced chemical vapor deposition. 17 . The method of claim 15 , further comprising performing a plasma treatment on the organic layer before forming the silicon layer. 18 . The method of claim 15 , further comprising forming a non-conductive inorganic layer on the silicon layer, wherein the silicon layer is disposed between the organic layer and the non-conductive inorganic layer.

19. The method of claim 15, wherein the organic layer is formed between the first conductive layer and the magnetic layer.

20. The method of claim 15, wherein the organic layer is formed between the second conductive layer and the magnetic layer.

21. A semiconductor device, characterized in that: include: a first conductive layer; A first organic layer, a first non-conductive inorganic layer, and a first silicon layer located between the first organic layer and the first non-conductive inorganic layer, disposed on the first conductive layer; A second organic layer, a second non-conductive inorganic layer, and a second silicon layer located between the second organic layer and the second non-conductive inorganic layer are disposed on the first conductive layer, wherein the first silicon layer and the second silicon layer directly contact the first conductive layer; and A magnetic layer and a second conductive layer, wherein the magnetic layer is located between the first conductive layer and the second conductive layer. 22 . The semiconductor device according to claim 21 , wherein the second organic layer directly contacts the first non-conductive inorganic layer. 23 . The semiconductor device of claim 21 , wherein bottommost surfaces of the first silicon layer, the second organic layer, and the second silicon layer are substantially coplanar. 24 . The semiconductor device of claim 21 , wherein the first organic layer comprises a top surface and a sidewall surface, and the first silicon layer is continuously located on the top surface and the sidewall surface. 25 . The semiconductor device according to claim 21 , wherein a sidewall of the first silicon layer is substantially flush with a sidewall of the first non-conductive inorganic layer. 26 . The semiconductor device according to claim 21 , wherein a sidewall of the second silicon layer is substantially flush with a sidewall of the second non-conductive inorganic layer.

Images