Methods and systems for budget-friendly and simplified training of deep neural networks

Abstract

Disclosed are a method and system for budgeted and simplified training of deep neural networks (DNNs). In one example, a trainer is used to train the DNN using multiple training sub-images derived from downsampled training images. A tester is used to test the trained DNN using multiple test sub-images derived from downsampled test images. In another example, in a recursive deep Q-network (RDQN) with a local attention mechanism positioned between a convolutional neural network (CNN) and a long-short-term memory (LSTM), the CNN generates multiple feature maps from an input image. The local attention mechanism applies hard attention to the multiple generated feature maps by selecting a subset of the generated feature maps. The local attention mechanism applies soft attention to a selected subset of the generated feature maps by assigning weights to the selected subset of the generated feature maps to obtain weighted feature maps. The weighted feature maps are stored in the LSTM. Q-values are calculated for different actions based on the weighted feature maps stored in the LSTM.

Description

Technical Field

[0001] Embodiments of the present invention are in the field of data processing, including image processing, graphics processing, and machine learning. More specifically, embodiments of the present invention relate to methods and systems for budgeted and simplified training of deep neural networks (DNNs). Background Art

[0002] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, more recently, portions of graphics processors have been made programmable, enabling such processors to support a wide variety of operations for processing vertex and fragment data.

[0003] To further increase performance, graphics processors typically implement processing techniques such as pipeline operations that attempt to process as much graphics data as possible in parallel across different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as often as possible to increase processing efficiency. A general overview of the software and hardware for a SIMT architecture can be found in Shane Cook's CUDA Programming , Chapter 3, pp. 37–51 (2013).

[0004] Machine learning has been successful in solving a wide variety of tasks. The computations that occur when training and using machine learning algorithms (e.g., neural networks) naturally lend themselves to efficient parallel implementation. Consequently, parallel processors such as general-purpose graphics processing units (GPGPUs) have played a significant role in the practical implementation of deep neural networks. Parallel graphics processors with a single-instruction, multiple-thread (SIMT) architecture are designed to maximize the amount of parallel processing within the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as often as possible to increase processing efficiency. The efficiency provided by parallel machine learning algorithm implementations allows the use of high-capacity networks and enables these networks to be trained on larger datasets.

[0005] Deep neural networks (DNNs) can perform deep machine learning, useful in computer vision and image recognition applications, due to their feature recognition capabilities. DNNs consist of layers with nodes organized into a set of "filters" that act as feature detectors. The output of each set of filters is propagated to nodes in successive layers of the network. DNN processing can be computationally intensive at each layer with multiple nodes, requiring multiple parameters to be calculated for image detection and processing applications. Furthermore, training and learning DNNs can be extensive, requiring a large amount of training data and parameters if the number of layers and nodes is deep. Therefore, improved training and learning techniques for DNNs are needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The drawings illustrate examples, and therefore exemplary embodiments, and are not to be considered limiting in scope.

[0007] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the exemplary embodiments described herein.

[0008] Figures 2A-2D A parallel processor assembly according to an exemplary embodiment is illustrated.

[0009] Figures 3A-3B is a block diagram of a graphics multiprocessor according to an exemplary embodiment.

[0010] Figures 4A-4F An exemplary architecture is illustrated in which multiple graphics processing units (GPUs) are communicatively coupled to multiple multi-core processors.

[0011] Figure 5 A graphics processing pipeline according to an exemplary embodiment is illustrated.

[0012] Figure 6 Illustrated is a machine learning software stack according to an exemplary embodiment.

[0013] Figure 7 A highly parallel general purpose graphics processing unit is illustrated according to an exemplary embodiment.

[0014] Figure 8 A multi-GPU computing system is illustrated according to an exemplary embodiment.

[0015] Figures 9A-9B The layers of an exemplary deep neural network are illustrated.

[0016] Figure 10 An exemplary recurrent neural network is illustrated.

[0017] Figure 11Illustrated is an exemplary embodiment of the training and deployment of a deep neural network.

[0018] Figure 12 is an exemplary block diagram illustrating distributed learning.

[0019] Figure 13 An exemplary inference system-on-chip (SOC) suitable for performing inference using a trained model is illustrated.

[0020] Figure 14 is an exemplary block diagram of a basic training and learning architecture of a deep neural network (DNN) training and learning system for receiving training data for learning and training the DNN.

[0021] Figure 15 An exemplary process for selecting image data for a learning machine is illustrated.

[0022] Figure 16A is an exemplary block diagram of a learning system that can implement budgeted training and learning techniques for DNNs.

[0023] Figures 16B-16C An exemplary flow chart illustrating operations for training and testing a DNN is shown.

[0024] Figure 17A is a block diagram of an improved deep recursive Q-network (DRQN) architecture according to an exemplary embodiment.

[0025] Figure 17B The diagram shows Figure 17A Flowchart of exemplary operation of the improved DRQN.

[0026] Figure 18A is a block diagram of an improved DRQN architecture according to another exemplary embodiment.

[0027] Figure 18B The diagram shows Figure 18A Flowchart of exemplary operation of the improved DRQN.

[0028] Figure 19 A block diagram of a processing system is illustrated according to an exemplary embodiment.

[0029] Figure 20 An exemplary block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor is illustrated.

[0030] Figure 21 An exemplary block diagram of a graphics processor is illustrated.

[0031] Figure 22A block diagram of a graphics processing engine of a graphics processor according to an exemplary embodiment is illustrated.

[0032] Figure 23 A block diagram of another exemplary embodiment of a graphics processor is illustrated.

[0033] Figure 24 Illustrated is thread execution logic comprising an array of processing elements employed in an exemplary embodiment of a graphics processing engine (GPE).

[0034] Figure 25 A block diagram illustrating a graphics processor instruction format according to an exemplary embodiment is illustrated.

[0035] Figure 26 A block diagram of an exemplary embodiment of a graphics processor is illustrated.

[0036] Figure 27A A block diagram illustrating a graphics processor command format according to an exemplary embodiment is illustrated.

[0037] Figure 27B A block diagram of a graphics processor command sequence is illustrated according to an exemplary embodiment.

[0038] Figure 28 An exemplary graphics software architecture for a data processing system is illustrated in accordance with an exemplary embodiment.

[0039] Figure 29 A block diagram of an IP core development system that may be used to fabricate an integrated circuit (IC) to perform operations is illustrated according to an exemplary embodiment.

[0040] Figure 30 Illustrated is a block diagram of an exemplary system-on-chip IC that can be manufactured using one or more IP cores according to an exemplary embodiment.

[0041] Figure 31 Illustrated is a block diagram of an exemplary graphics processor on a system-on-chip IC that may be manufactured using one or more IP cores according to an exemplary embodiment.

[0042] Figure 32 Illustrated is a block diagram of an exemplary add-on graphics processor for a system-on-chip IC that may be fabricated using one or more IP cores according to an exemplary embodiment. DETAILED DESCRIPTION

[0043] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0044] In some embodiments, the image capture device is a standalone device for capturing input images. However, the image capture device can be part of or a subcomponent of another computing device that requires image capture capabilities, such as a portable or handheld computing device with a digital camera for capturing images.

[0045] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent that the embodiments described herein can be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the exemplary embodiments.

[0046] Computing System Overview

[0047] Figure 1 1 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the exemplary embodiments described herein. Computing system 100 includes a processing subsystem 101 having one or more processors 102 and system memory 104 communicating via an interconnect path, which may include a memory hub 105. Memory hub 105 may be a separate component within a chipset assembly or may be integrated within the one or more processors 102. Memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. I / O subsystem 111 includes an I / O hub 107, which may enable computing system 100 to receive input from one or more input devices 108. Additionally, I / O hub 107 may enable a display controller, which may be included within the one or more processors 102, to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to I / O hub 107 may include local, internal, or embedded display devices.

[0048] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, PCI Express), or can be a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a compute-intensive parallel or vector processing system that includes a large number of processing cores and / or processing clusters, such as a many-integrated-core (MIC) processor. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 110B.

[0049] Within I / O subsystem 111, system storage unit 114 can be connected to I / O hub 107 to provide a storage mechanism for computing system 100. I / O switch 116 can be used to provide an interface mechanism to enable connection between I / O hub 107 and other components that can be integrated into the platform, such as network adapter 118 and / or wireless network adapter 119, and various other devices that can be added via one or more plug-in devices 120. Network adapter 118 can be an Ethernet adapter or another wired network adapter. Wireless network adapter 119 can include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0050] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 107. Any suitable protocol may be used, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or any other bus or point-to-point communication interface and / or protocol(s), such as the NV-Link high-speed interconnect or interconnect protocols known in the art. Figure 1 The communication paths that interconnect the various components in a system.

[0051] In one embodiment, the one or more parallel processors 112 are combined with circuits optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 are combined with circuits optimized for general-purpose processing while maintaining the basic computing architecture described in more detail herein. In yet another embodiment, components of the computing system 100 can be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processors 112, the memory hub 105, the (multiple) processors 102, and the I / O hub 107 can be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system.

[0052] It will be appreciated that the computing system 100 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s) 102, and the number of parallel processor(s) 112, can be modified as desired. For example, in some embodiments, the system memory 104 is connected directly to the processor(s) 102 rather than through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the processor(s) 102. In other alternative topologies, the parallel processor(s) 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102 rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 can be integrated into a single chip. Some embodiments may include two or more sets of processor(s) 102 attached via multiple sockets, which can be coupled to two or more instances of the parallel processor(s) 112.

[0053] Some of the specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. Additionally, some architectures may use different terminology for components related to the computer. Figure 1 For example, in some architectures, memory hub 105 may be referred to as a north bridge, while I / O hub 107 may be referred to as a south bridge.

[0054] Figure 2AThe parallel processor 200 is shown in accordance with an exemplary embodiment. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). Figure 1 A variation of the one or more parallel processors 112 is shown in FIG.

[0055] In one embodiment, parallel processor 200 includes parallel processing unit (PPU) 202. PPU includes I / O unit 204 that enables communication with other devices including other instances of PPU 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 connects to other devices via the use of a hub or switch interface such as memory hub 105. The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within PPU 202, I / O unit 204 is connected to a host interface 206 that receives commands related to performing processing operations and a memory crossbar switch 216 that receives commands related to performing memory operations.

[0056] When host interface 206 receives command buffers via I / O unit 204, host interface 206 can direct work operations for executing those commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210, which is configured to dispatch commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and in a valid state before dispatching tasks to its processing clusters. In one embodiment, scheduler 210 is implemented via firmware logic executed on a microcontroller. A microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work dispatch operations at both coarse and fine granularity, thereby enabling context switching and rapid preemption of threads executing on processing array 212. In one embodiment, host software can verify workloads for scheduling on processing array 212 via one of multiple graphics processing doorbells. The workload may then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0057] Processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, through cluster 214N). Each cluster 214A-214N of processing cluster array 212 may execute a large number of concurrent threads. Scheduler 210 may use various scheduling and / or work distribution algorithms to distribute work to clusters 214A-214N of processing cluster array 212, which may vary depending on the workload resulting from each type of program or computation. Scheduling may be handled dynamically by scheduler 210 or may be partially assisted by compiler logic during the compilation of program logic configured for execution by processing cluster array 212. In one embodiment, different clusters 214A-214N of processing cluster array 212 may be assigned to process different types of programs or to perform different types of computations.

[0058] Processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 can include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0059] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processors 200 are configured to perform graphics processing operations, processing cluster array 212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute graphics processing-related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing units 202 may transfer data from system memory via I / O units 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0060] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 214A-214N of processing cluster array 212. In some embodiments, portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing.

[0061] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, a processing task may include data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, and state parameters and commands defining how the data is to be processed (e.g., what program to execute). The scheduler 210 may be configured to obtain an index corresponding to a task or may receive an index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured in a valid state before initiating a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

[0062] Each of the one or more instances of parallel processing unit 202 can be coupled to parallel processor memory 222. Parallel processor memory 222 can be accessed via memory crossbar switch 216, which can receive memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar switch 216 can access parallel processor memory 222 via memory interface 218. Memory interface 218 can include multiple partition units (e.g., partition unit 220A, partition unit 220B, through partition unit 220N), each of which can be coupled to a portion of parallel processor memory 222 (e.g., memory cells). In one implementation, the number of partition units 220A-220N is configured to equal the number of memory cells, such that the first partition unit 220A has a corresponding first memory cell 224A, the second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not equal the number of memory devices.

[0063] In various embodiments, memory units 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 224A-224N may also include 3D stacked memory, including, but not limited to, high-bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of memory units 224A-224N may vary and may be selected from a variety of conventional designs. Render targets, such as frame buffers or texture maps, may be stored across memory units 224A-224N, allowing partition units 220A-220N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 222. In some embodiments, local instances of parallel processor memory 222 may be eliminated to support a unified memory design that utilizes system memory along with local cache memory.

[0064] In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 can process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. Memory crossbar 216 can be configured to route the output of each cluster 214A-214N to any partition unit 220A-220N or another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with memory interface 218 via memory crossbar 216 to read from or write to various external memory devices. In one embodiment, memory crossbar 216 has connections to memory interface 218 for communicating with I / O unit 204, as well as connections to local instances of parallel processor memory 222, thereby enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory that is not local to parallel processing unit 202. In one embodiment, the memory crossbar 216 may use virtual channels to separate traffic flows between the clusters 214A-214N and the partition units 220A-220N.

[0065] Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Even if different instances of parallel processing unit 202 have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences, the different instances may be configured to interoperate. For example, and in one embodiment, some instances of parallel processing unit 202 may include floating point units with higher precision than other instances. Systems incorporating one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0066] Figure 2B is a block diagram of a partition unit 220 according to an exemplary embodiment. In one embodiment, the partition unit 220 is Figure 2A2 is an example of one of the partition units 220A-220N. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (raster operations unit). The L2 cache 221 is a read / write cache configured to execute load and store operations received from the memory crossbar 216 and the ROP 226. The L2 cache 221 outputs read misses and urgent writeback requests to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory, such as the memory units 224A-224N of FIG. 2 (e.g., within the parallel processor memory 222).

[0067] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. ROP 226 then outputs processed graphics data, which is stored in graphics memory. In some embodiments, ROP 226 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0068] In some embodiments, ROP 226 is included in each processing cluster (e.g., Figure 2A 214N) rather than within partition unit 220. In such embodiments, read and write requests for pixel data rather than pixel fragment data are transmitted through memory crossbar 216. The processed graphics data may be displayed on a display device such as a Figure 1 100 ), is routed for further processing by the processor(s) 102 , or is routed for processing by the processor(s) 102 . Figure 2A Further processing is performed by one of the processing entities within the parallel processor 200.

[0069] Figure 2C is a block diagram of a processing cluster 214 within a parallel processing unit according to an exemplary embodiment. In one embodiment, a processing cluster is Figure 2A214N. A processing cluster 214 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific set of input data. In some embodiments, single instruction, multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction, multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster. Unlike the SIMD execution regime, in which all processing engines typically execute the same instructions, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will appreciate that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0070] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to SIMT parallel processors. Figure 2A The scheduler 210 receives instructions and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures may be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 may be included within the processing cluster 214. The graphics multiprocessor 234 may process data, and the data crossbar 240 may be used to distribute the processed data to one of multiple possible destinations, including other shader units. The pipeline manager 232 may facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via the data crossbar 240.

[0071] Each graphics multiprocessor 234 within a processing cluster 214 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). The function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. The function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0072] Instructions transmitted to processing cluster 214 constitute threads. A collection of threads executed across a collection of parallel processing engines is a thread group. Thread groups execute the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processing. A thread group can also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be performed in consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 234.

[0073] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 may forgo the internal cache memory and instead use the cache memory within the processing cluster 214 (e.g., L1 cache 308). Each graphics multiprocessor 234 also has access to a partitioning unit (e.g., L1 cache 308) that is shared among all processing clusters 214 and can be used to transfer data between threads. Figure 2A Graphics multiprocessor 234 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 may be used as global memory. Embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 may share common instructions and data, which may be stored in L1 cache 308.

[0074] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside in Figure 2A The MMU 245 is located within the memory interface 218. The MMU 245 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles (more on tiles below) and, optionally, to cache line indices. The MMU 245 may include a translation lookaside buffer (TLB) or cache, which may reside within the graphics multiprocessor 234, the L1 cache, or the processing cluster 214. Physical addresses are processed to maintain data access locality, allowing for efficient request interleaving between partition units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0075] In graphics and compute applications, the processing clusters 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 234, and retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 234 outputs a processed task to a data crossbar 240 to provide the processed task to another processing cluster 214 for further processing, or stores the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A preROP 242 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 234, directing the data to a ROP unit, which can communicate with a partition unit (e.g., a partition unit) as described herein. Figure 2A The preROP 242 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0076] It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within a processing cluster 214. Further, while only one processing cluster 214 is shown, the parallel processing units described herein may include any number of instances of a processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0077] Figure 2D A graphics multiprocessor 234 is shown according to an exemplary embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0078] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions into thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0079] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for operands for the data paths of the functional units connected to the graphics multiprocessor 324 (e.g., the GPGPU core 262, the load / store unit 266). In one embodiment, the register file 258 is divided between each of the functional units so that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is divided between the different warps being executed by the graphics multiprocessor 324.

[0080] The GPGPU cores 262 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions for the graphics multiprocessor 324. Depending on the embodiment, the GPGPU cores 262 may be architecturally similar or architecturally different. For example, and in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0081] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. SIMD instructions for the GPGPU core can be generated by the shader compiler at compile time, or can be automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for the SIMT execution model can be executed via a single SIMD instruction. For example, and in one embodiment, eight SIMT threads performing the same or similar operation can be executed in parallel via a single SIMD8 logic unit.

[0082] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfers between the GPGPU core 262 and the register file 258 have very low latency. The shared memory 270 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data transferred between the functional units and the texture unit 236. The shared memory 270 can also be used as a cache-managed program. In addition to automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0083] Figures 3A-3B Additional graphics multiprocessors are illustrated according to exemplary embodiments. The illustrated graphics multiprocessors 325, 350 are Figures 2C-2D The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0084] Figure 3A A graphics multiprocessor 325 is shown according to an additional exemplary embodiment. The graphics multiprocessor 325 includes Figures 2C-2DThe graphics multiprocessor 325 may include multiple additional instances of execution resource units associated with the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and texture unit(s) 344A-344B. The graphics multiprocessor 325 may also include multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, and GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units may have a common instruction cache 330, texture and / or data cache 342, and shared memory 346.

[0085] Various components can communicate via interconnect fabric 327. In one embodiment, interconnect fabric 327 includes one or more crossbar switches to enable communication between various components of graphics multiprocessor 325. In one embodiment, interconnect fabric 327 is a separate high-speed network fabric layer upon which each component of graphics multiprocessor 325 is stacked. Components of graphics multiprocessor 325 communicate with remote components via interconnect fabric 327. For example, GPGPU cores 336A-336B, 337A-337B, and 3378A-338B can each communicate with shared memory 346 via interconnect fabric 327. Interconnect fabric 327 can arbitrate communications within graphics multiprocessor 325 to ensure fair bandwidth distribution between components.

[0086] Figure 3B FIG3 shows a graphics multiprocessor 350 according to an additional exemplary embodiment. The graphics processor includes multiple sets of execution resources 356A-356D, wherein each set of execution resources includes multiple instruction units, register files, GPGPU cores and load storage units, such as Figure 2D and Figure 3A 360D for texture operations, while sharing the instruction cache 354 and shared memory 362. In one embodiment, the execution resources 356A-356D can share the instruction cache 354 and shared memory 362 as well as multiple instances of texture and / or data caches 358A-358B. The various components can be connected via Figure 3A The interconnect structure 327 communicates with a similar interconnect structure 352 .

[0087] Those skilled in the art will understand that Figure 1 、 2AThe architectures described in FIG3A-3B are illustrative and non-limiting with respect to the scope of the exemplary embodiments. Thus, the techniques described herein may be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (such as CPUs), and / or a plurality of parallel processing units (such as CPUs) without departing from the scope of the embodiments described herein. Figure 2A parallel processing unit 202), and one or more graphics processors or special processing units.

[0088] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0089] Technologies for GPU to host processor interconnection

[0090] Figure 4A The diagram illustrates an exemplary architecture in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, high-speed links 440-443 support communication throughputs of 4 GB / s, 30 GB / s, 80 GB / s, or higher, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the present invention are not limited to any particular communication protocol or throughput.

[0091] Additionally, and in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as those used for high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A All communications between the various system components shown in can be accomplished using the same protocols / links (eg, through a common interconnect fabric). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0092] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. Memory interconnects 430-431 and 450-453 can utilize the same or different memory access technologies. By way of example and not limitation, processor memory 401-402 and GPU memory 420-423 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the memory can be volatile memory and another portion can be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0093] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to specific memories 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across all of the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0094] Figure 4B4 shows additional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to an exemplary embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0095] The illustrated processor 407 includes multiple cores 460A-460D, each having a translation lookaside buffer 461A-461D and one or more caches 462A-462D. The cores may include various other components for executing instructions and processing data (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.), which are not shown to avoid obscuring the underlying principles of the present invention. Caches 462A-462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by the collection of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441 , which may include the processor memories 401 - 402 .

[0096] Coherence is maintained for data and instructions stored in the various caches 462A-462D, 456 and system memory 441 via inter-core communication over a coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail here to avoid obscuring the underlying principles of the present invention.

[0097] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the core. Specifically, the interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the high-speed link 440.

[0098] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N can each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N can comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a bit-block transfer engine. In other words, the graphics acceleration module can be a GPU having multiple graphics processing engines 431-432, N, or the graphics processing engines 431-432, N can be separate GPUs integrated into a common package, line card, or chip.

[0099] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 438 stores commands and data for efficient access by graphics processing engines 431-432, N. In one embodiment, data stored in cache 438 and graphics memory 433-434, N is kept coherent with core caches 462A-462D, 456 and system memory 411. As mentioned, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433-434, N (e.g., sending updates related to modifications / accesses of cache lines on processor caches 462A-462D, 456 to cache 438, and receiving updates from cache 438).

[0100] A set of registers 44 stores context data for threads executed by graphics processing engines 431-432, N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 can perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon a context switch, context management circuitry 448 can store current register values to a designated area in memory (e.g., identified by a context pointer). It can then restore the register values upon returning to that context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0101] In one implementation, the MMU 439 converts virtual / effective addresses from the graphics processing engine 431 into real / physical addresses in the system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executing on the processor 407, or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). The resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0102] Thus, the accelerator integrated circuit acts as a bridge to the system of graphics acceleration module 446 and provides address translation and system memory cache services. Additionally, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0103] Because the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, N so that they appear to the system as independent units.

[0104] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store instructions and data being processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0105] In one embodiment, to reduce data traffic on link 440, biasing techniques are used to ensure that the data stored in graphics memories 433-434, M is data that will be used most frequently by graphics processing engines 431-432, N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by a core (and preferably not graphics processing engines 431-432, N) within the core's caches 462A-462D, 456 and system memory 411.

[0106] Figure 4C Another exemplary embodiment is shown in which an accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via interfaces 437 and 435 (again, which may utilize any form of bus or interface protocol) over a high-speed link 440. The accelerator integrated circuit 436 may perform operations related to Figure 4B These operations are the same as those described, but given their close proximity to the coherency bus 462 and caches 462A-462D, 426, they may be performed at a higher throughput.

[0107] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model can include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0108] In one embodiment of a dedicated process model, graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. This single application can funnel other application requests to graphics engines 431-432, N, thereby providing virtualization within a VM / partition.

[0109] In a dedicated process programming model, graphics processing engines 431-432, N can be shared by multiple VM / application partitions. This shared model requires the hypervisor to virtualize graphics processing engines 431-432, N to allow access by each operating system. In a single-partition system without a hypervisor, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to each process or application.

[0110] For the shared programming model, the graphics acceleration module 446 or individual graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, process elements are stored in system memory 411 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, N (i.e., calling system software to add a process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0111] Figure 4D An exemplary accelerator integrated slice 490 is illustrated. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 436. An application-effective address space 482 within system memory 411 stores process elements 483. In one embodiment, process elements 483 are stored in response to GPU calls 481 from an application 480 executing on processor 407. Process elements 483 contain process status for the corresponding application 480. The work descriptor (WD) 484 contained in process element 483 can be a single job requested by the application, or it can contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the application's address space 482.

[0112] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N may be shared by all or a subset of processes in the system. Embodiments of the present invention include an infrastructure for establishing process state and sending WD 484 to graphics acceleration module 446 to start a job in a virtualized environment.

[0113] In one implementation, a dedicated process programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 446 or a separate graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition, and the operating system initializes the accelerator integrated circuit 436 for the owning process when the graphics acceleration module 446 is allocated.

[0114] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of work to be completed by one of the graphics processing engines of the graphics acceleration module 446. Data from the WD 484 can be stored in registers 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 446, as shown. For example, one embodiment of the MMU 439 includes segment / page walk circuitry for accessing the segment / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 can process interrupt events 492 received from the graphics acceleration module 446. When executing graphics operations, the effective addresses 493 generated by the graphics processing engines 431-432, N are converted by the MMU 439 into real addresses.

[0115] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431-432, N, and / or graphics acceleration module 446 and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integration slice 490. Example registers that can be initialized by a hypervisor are shown in Table 1.

[0116] Table 1 - Registers initialized by the hypervisor

[0117] .

[0118] Example registers that may be initialized by the operating system are shown in Table 2.

[0119] Table 2 - Registers initialized by the operating system

[0120] .

[0121] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information needed for the graphics processing engine 431-432, N to do its work, or it may be a pointer to a memory location where the application has set up a command queue for work to be done.

[0122] Figure 4E 4 shows additional details of an exemplary embodiment of a sharing model. This embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes a graphics acceleration module engine for an operating system 495.

[0123] The shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced sharing and graphics-directed sharing.

[0124] In this model, hypervisor 496 owns graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for graphics acceleration module 446 to support virtualization by hypervisor 496, it must adhere to the following requirements: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or graphics acceleration module 446 must provide a context save and restore mechanism. 2) Graphics acceleration module 446 guarantees that application job requests will complete within a specified amount of time, including any transition failures, or graphics acceleration module 446 provides the ability to preempt job processing. 3) When operating in a directed-sharing programming model, fairness must be guaranteed for graphics acceleration module 446 between processes.

[0125] In one embodiment, the shared model requires that application 480 make an operating system 495 system call using a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the form of a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure describing work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to an application setting an AMR. If the implementation of the accelerator integrated circuit 436 and graphics acceleration module 446 does not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Before placing the AMR into process element 483, hypervisor 496 may optionally apply the current privilege mask overwrite register (AMOR) value. In one embodiment, CSRP is one of registers 445 that contains the effective address of an area in the application's address space 482 for graphics acceleration module 446 to save and restore context state. This pointer is optional if state is not required to be saved between jobs or when a job is preempted. The context save / restore area can be pinned system memory.

[0126] Upon receiving the system call, the operating system 495 can verify that the application 480 has been registered and given permission to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 using the information shown in Table 3.

[0127] Table 3 - OS to hypervisor call parameters

[0128] .

[0129] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has registered and been given permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into a linked list of process elements for the corresponding type of graphics acceleration module 446. The process element may include the information shown in Table 4.

[0130] Table 4 - Process Element Information

[0131] .

[0132] In one embodiment, the hypervisor initializes the plurality of accelerator integration slice 490 registers 445 .

[0133] like Figure 4F As illustrated in FIG, an exemplary embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 401-402 and GPU memories 420-423, allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0134] In one embodiment, bias / coherency management circuitry 494A-494E within one or more of MMUs 439A-439E ensures cache coherency between the caches of the host processor (e.g., 405) and GPUs 410-413 and implements biasing techniques that indicate physical memory where certain types of data should be stored. Figure 4FMultiple instances of bias / coherence management circuits 494A- 494E are illustrated in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436 .

[0135] One embodiment allows GPU-attached memory 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without the typical performance drawbacks associated with system-wide cache coherence. The ability to access GPU-attached memory 420-423 as system memory without the burdensome cache coherence overhead provides a favorable operating environment for GPU offload. This arrangement allows host processor 405 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. Such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420-423 without cache coherence overhead can be critical to the execution time of offloaded computations. For example, in scenarios with a large amount of streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand setup, result access, and GPU computation all play a role in determining the effectiveness of GPU offload.

[0136] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure consisting of 1 or 2 bits per GPU-attached memory page (i.e., controlled at the granularity of a memory page). With or without a bias cache in GPUs 410-413, the bias table can be implemented in the stolen memory range of one or more GPU-attached memories 420-423 (e.g., to cache frequently / recently used bias table entries). Alternatively, the entire bias table can be maintained within the GPU.

[0137] In one implementation, the bias table entry associated with each access to GPU-attached memory 420-423 is accessed before the actual access to GPU memory, resulting in the following operations. First, local requests from GPUs 410-413 are forwarded directly to the corresponding GPU memory 420-423, where the GPUs 410-413 find their pages in the GPU bias. Local requests from the GPUs are forwarded to processor 405 (e.g., via a high-speed link as discussed above), where the GPUs find their pages in the host bias. In one embodiment, requests from processor 405 that find the requested pages in the host processor bias complete like normal memory reads. Alternatively, requests involving GPU-biased pages can be forwarded to GPUs 410-413. If the GPU is not currently using the page, the GPU can then convert the page to the host processor bias.

[0138] The bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[0139] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU directing it to change the bias state, and for certain transitions, performs a cache flush operation in the host. The cache flush operation is required for transitions from host processor 405 bias to GPU bias, but not the other way around.

[0140] In one embodiment, cache coherence is maintained by temporarily rendering GPU offset pages that are not cacheable by host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not immediately grant access, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is advantageous to ensure that the GPU offset pages are those pages that are needed by the GPU but not by host processor 405, and vice versa.

[0141] Graphics processing pipeline

[0142] Figure 5 5. A graphics processing pipeline 500 is illustrated according to an exemplary embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein, such as a graphics processor. Figure 2A parallel processor 200), which in one embodiment is Figure 1Various parallel processing systems can be implemented via parallel processing units (e.g., Figure 2A The graphics processing pipeline 500 may be implemented using one or more instances of the parallel processing unit 202 of FIG. For example, a shader unit (e.g., Figures 2C-2D The graphics multiprocessor 234 of the graphics multiprocessor 234 can be configured to perform the functions of one or more of the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operations unit 526 can also be performed by a processing cluster (e.g., Figure 2A 2 ). The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., such as a CPU) via a memory interface 528. Figure 2A The parallel processor memory 222 in the memory interface 528 may be Figure 2A An instance of the memory interface 218.

[0143] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes vertex shader programs, thereby lighting and transforming the vertex data as specified by the vertex shader programs. The vertex processing unit 504 reads data stored in cache, local, or system memory for use in processing vertex data, and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0144] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 500. Primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0145] The tessellation control processing unit 508 treats the input vertices as control points for a geometry patch. The control points are transformed from an input representation of the patch (e.g., the basis of the patch) into a representation suitable for use in surface estimation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometry patch. The tessellation factors apply to individual edges and quantify the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives, such as lines, triangles, or quads, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate vertex attributes and a surface representation for each vertex associated with the geometric primitive.

[0146] A second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform the graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to tessellate a graphics primitive into one or more new graphics primitives and calculate parameters for rasterizing the new graphics primitives.

[0147] In some embodiments, the geometry processing unit 516 can add or delete elements from the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, cull, and clip unit 520. The geometry processing unit 516 reads data stored in parallel processor memory or system memory for use in processing geometry data. The viewport scaling, cull, and clip unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0148] The rasterizer 522 can perform depth sorting and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels that are output to the raster operation unit 526. The fragment / pixel processing unit 524 can read data stored in either parallel processor memory or system memory for use in processing the fragment data. The fragment or pixel shader program can be configured to shade at a sample, pixel, tile, or other granularity based on the sampling rate configured for the processing unit.

[0149] Raster operations unit 526 is a processing unit that performs raster operations including, but not limited to, stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in graphics memory (e.g., as Figure 2A The parallel processor memory 222 in the embodiment of the present invention and / or Figure 1 The raster operations unit 526 may be configured to compress the z or color data written to memory and to decompress the z or color data read from memory.

[0150] Machine Learning Overview

[0151] Machine learning algorithms are algorithms that can learn from a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output a numerical value given an input; and pattern recognition algorithms can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0152] One exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating output in the output layer. Network nodes are fully connected to nodes in adjacent layers via edges, but there are no edges between nodes within each layer. Data received at nodes in the input layer of a feedforward network is propagated (i.e., "fed forward") to nodes in the output layer via an activation function, which calculates the state of the nodes in each successive layer of the network based on coefficients ("weights") associated with each of the edges connecting the layers. The output from a neural network algorithm can take various forms, depending on the specific model represented by the algorithm being executed.

[0153] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves selecting a network topology, using a set of training data representing the problem being modeled by the network, and adjusting weights until the network model performs with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and as the error signal propagates backward through the layers of the network, the weights associated with the connections are adjusted to minimize the error. The network is considered "trained" when the error for each output generated from an instance of the training data set is minimized.

[0154] The accuracy of a machine learning algorithm can be significantly affected by the quality of the dataset used to train the algorithm. The training process can be computationally intensive and can take a significant amount of time on conventional general-purpose processors. Therefore, many types of machine learning algorithms are trained using parallel processing hardware. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general-purpose graphics processing devices.

[0155] Figure 66 is a generalized diagram of a machine learning software stack 600. Machine learning applications 602 can be configured to train a neural network using a training dataset or to implement machine intelligence using a trained deep neural network. Machine learning applications 602 can include training and inference functionality for the neural network and / or specialized software that can be used to train the neural network prior to deployment. Machine learning applications 602 can implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0156] Hardware acceleration for machine learning applications 602 can be enabled via a machine learning framework 604. The machine learning framework 604 can provide a library of machine learning primitives. Machine learning primitives are basic operations that machine learning algorithms typically perform. Without the machine learning framework 604, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when new parallel processors are developed. Instead, machine learning applications can be configured to use primitives provided by the machine learning framework 604 to perform the necessary computations. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning framework 604 can also provide primitives to implement basic linear algebra subroutines, such as matrix and vector operations, performed by many machine learning algorithms.

[0157] The machine learning framework 604 can process input data received from the machine learning application 602 and generate appropriate input to the computation framework 606. The computation framework 606 can abstract the basic instructions provided to the GPGPU driver 608 to enable the machine learning framework 604 to take advantage of hardware acceleration via the GPGPU hardware 610 without requiring the machine learning framework 604 to be intimately familiar with the architecture of the GPGPU hardware 610. In addition, the computation framework 606 can enable hardware acceleration for the machine learning framework 604 across multiple types and generations of GPGPU hardware 610.

[0158] GPGPU machine learning acceleration

[0159] Figure 7 A highly parallel general-purpose graphics processing unit 700 is illustrated in accordance with an exemplary embodiment. In one embodiment, the general-purpose processing unit (GPGPU) 700 can be configured to be particularly efficient at processing the type of computational workload associated with training deep neural networks. Additionally, the GPGPU 700 can be directly linked to other instances of the GPGPU to create a multi-GPU cluster to improve the training speed of particularly deep neural networks.

[0160] GPGPU 700 includes a host interface 702 for enabling connection to a host processor. In one embodiment, host interface 702 is a PCI Express interface. However, the host interface may also be a vendor-specific communication interface or communication structure. GPGPU 700 receives commands from the host processor and distributes the execution threads associated with those commands to a set of compute clusters 706A-H using a global scheduler 704. Compute clusters 706A-H share a cache memory 708. Cache memory 708 can serve as a higher-level cache for the cache memory within compute clusters 706A-H.

[0161] GPGPU 700 includes memory 714A-B, which is coupled to compute clusters 706A-H via a set of memory controllers 712A-B. In various embodiments, memory 714A-B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM) (including graphics double data rate (GDDR) memory). In one embodiment, memory units 224A-N may also include 3D stacked memory (including, but not limited to, high bandwidth memory (HBM)).

[0162] In one embodiment, each computing cluster 706A-H includes a set of graphics multiprocessors, such as Figure 4A The graphics multiprocessor 400 of the compute cluster includes multiple types of integer and floating-point logic units that can perform computational operations at a range of precisions, including precisions suitable for machine learning computations. For example, and in one embodiment, at least a subset of the floating-point units in each of the compute clusters 706A-H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0163] Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanisms used by the computing cluster for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of GPGPU 700 communicate via a host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 709 that couples GPGPU 700 to a GPU link 710, which enables direct connections to other instances of the GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect to transmit and receive data to and from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 700 are located in separate data processing systems and communicate via a network device accessible via host interface 702. In one embodiment, GPU link 710 can be configured to enable connection to a host processor in addition to or as an alternative to host interface 702.

[0164] While the illustrated configuration of the GPGPU 700 can be configured to train neural networks, one embodiment provides an alternative configuration of the GPGPU 700 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, the GPGPU 700 includes fewer compute clusters 706A-H relative to the training configuration. Additionally, the memory technology associated with the memories 714A-B may differ between the inference configuration and the training configuration. In one embodiment, the inference configuration of the GPGPU 700 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which are commonly used during inference operations on deployed neural networks.

[0165] Figure 8 A multi-GPU computing system 800 is illustrated according to an exemplary embodiment. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A-806D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI express switch device that couples the processor 802 to a PCI express bus, through which the processor 802 can communicate with the set of GPGPUs 806A-D. Each of the plurality of GPGPUs 806A-D may be Figure 7GPGPU 700. GPGPUs 806A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 816. The high-speed GPU-to-GPU links may be connected via dedicated GPU links such as Figure 7 810) is connected to each of GPGPUs 806A-D. P2P GPU link 816 enables direct communication between each of GPGPUs 806A-D without requiring communication over a host interface bus to which processor 802 is connected. In the case of GPU-to-GPU traffic involving P2P GPU links, the host interface bus can still be used for system memory access or communication with other instances of multi-GPU computing system 800, for example, via one or more network devices. While GPGPUs 806A-D are connected to processor 802 via host interface switch 804 in the illustrated embodiment, in one embodiment, processor 802 includes direct support for P2P GPU link 816 and can connect directly to GPGPUs 806A-D.

[0166] Machine Learning Neural Network Implementation

[0167] The computing architecture provided by the embodiments described herein can be configured to perform parallel processing of a type particularly suitable for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with graph relationships. As is well known in the art, there are many types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as previously described.

[0168] A second exemplary type of neural network is the convolutional neural network (CNN). A CNN is a specialized feed-forward neural network designed to process data with a known grid-like topology, such as image data. As such, CNNs are commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by receptive fields found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. The computation used in a CNN involves applying the mathematical operation of convolution to each filter to produce that filter's output. Convolution is a specialized mathematical operation that performs two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function of the convolution can be called the input, while the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to a convolutional layer can be a multidimensional data array defining the various color components of the input image. The convolution kernel can be a multidimensional array of parameters, where the parameters are adapted through the training process for the neural network.

[0169] Recurrent neural networks (RNNs) are a type of feedforward neural network that includes feedback connections between layers. RNNs enable modeling of sequential data by sharing parameter data across different parts of the neural network. The RNN architecture includes loops. Loops represent the influence of a variable's current value on its own value at future times, as at least a portion of the RNN's output data is used as feedback for processing subsequent input in the sequence. This feature makes RNNs particularly useful for language processing due to the variable nature of language data.

[0170] The figures described below present exemplary feedforward, CNN, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any specific embodiment described herein, and that the concepts illustrated can be applied generally to deep neural networks and machine learning techniques in general.

[0171] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning performed using deep neural networks. In contrast to shallow neural networks that include only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output error compared to shallow machine learning techniques.

[0172] The deep neural networks used in deep learning typically include a front-end network to perform feature recognition coupled to a back-end network that represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representations provided to the model. Deep learning enables machine learning without requiring handcrafted feature engineering to be performed on the model. Instead, deep neural networks can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features into outputs. The mathematical model used by the network is generally specialized for the specific task to be performed, and different models will be used to perform different tasks.

[0173] Once a neural network is structured, a learning model can be applied to the network to train it to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the network's output error. Backpropagation of errors is a common method for training neural networks. An input vector is presented to the network for processing. The network's output is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. The error values are then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from these errors using algorithms such as stochastic gradient descent to update the neural network's weights.

[0174] Figures 9A-9B An exemplary convolutional neural network is illustrated. Figure 9A The diagram shows the various layers within a CNN. Figure 9A As shown in , an exemplary CNN for modeling image processing can receive an input 902 that describes the red, green, and blue (RGB) components of an input image. The input 902 can be processed by multiple convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The outputs from the multiple convolutional layers can optionally be processed by a set of fully connected layers 908. The neurons in the fully connected layers have full connections to all activations in the previous layer, as previously described for feedforward networks. The outputs from the fully connected layers 908 can be used to generate output results from the network. Activations within the fully connected layers 908 can be calculated using matrix multiplication rather than convolution. Not all CNN implementations use fully connected layers 906. For example, in some implementations, the convolutional layers 906 can generate the output of the CNN.

[0175] Convolutional layers are sparsely connected, unlike traditional neural network configurations found in fully connected layers 908. Traditional neural network layers are fully connected, so that every output unit interacts with every input unit. However, convolutional layers are sparsely connected because the output of the convolution of a domain (rather than the corresponding state value of each node in the domain) is input to the nodes of the subsequent layer, as shown. The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that allows CNNs to scale to process large images.

[0176] Figure 9BThe diagram illustrates exemplary computational stages within a convolutional layer of a CNN. Input 912 to a convolutional layer of the CNN can be processed in three stages of a convolutional layer 914. These three stages can include a convolution stage 916, a detector stage 918, and a pooling stage 920. The convolutional layer 914 can then output data to a subsequent convolutional layer. The final convolutional layer of the network can generate output feature map data or provide input to a fully connected layer, for example, to generate a classification value for input to the CNN.

[0177] In the convolution stage 916, the convolution layer 914 can perform several convolutions in parallel to produce a set of linear activations. The convolution stage 916 can include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as a local region associated with the neuron. The neuron calculates the dot product between the neuron's weight and the region in the local input to which the neuron is connected. The output from the convolution stage 916 defines a set of linear activations processed by successive stages of the convolution layer 914.

[0178] The linear activations can be processed by the detector stage 918. In the detector stage 918, each linear activation is processed by a nonlinear activation function. The nonlinear activation function increases the nonlinear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of nonlinear activation functions can be used. One specific type is the rectified linear unit (ReLU), which is defined as f ( x ) = max (0, x ) so that the activation threshold is zero.

[0179] The pooling stage 920 uses a pooling function that replaces the output of the convolution layer 906 with a summary statistic of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that small translations of the input do not change the pooled output. The invariance of local translations may be useful in scenarios where the presence of a feature in the input data is more important than the exact location of the feature. Various types of pooling functions can be used during the pooling stage 920, including maximum pooling, average pooling, and l2-norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such implementations perform a replacement, and the additional convolution stage has an increased stride relative to the previous convolution stage.

[0180] The output from the convolutional layer 914 may then be processed by the next layer 922. The next layer 922 may be an additional convolutional layer or one of the fully connected layers 908. For example, Figure 9AThe first convolutional layer 904 can output to the second convolutional layer 906, and the second convolutional layer can output to the first layer in the fully connected layer 908.

[0181] Figure 10 An exemplary recurrent neural network 1000 is illustrated. In a recurrent neural network (RNN), the network's previous state influences the output of the network's current state. RNNs can be built in a variety of ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given a previous word sequence. The illustrated RNN 1000 can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 for implementing a recursive function, a feedback mechanism 1005 for enabling "memory" of previous states, and an output layer 1006 for outputting a result. RNN 1000 operates on a time-step basis. The state of the RNN at a given time step is influenced by the previous time step via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1004. The second input (x2) can be processed by the hidden layer 1004 using the state information determined during the processing of the initial input (x1). The given state can be calculated as s t = f ( Ux t + Ws t-1 ),in U and W is the parameter matrix. Function f Typically nonlinear, such as the hyperbolic tangent function (Tanh) or the modified function f (x) = max( 0 , x However, the specific mathematical function used in hidden layer 1004 may vary depending on the specific implementation details of RNN 1000.

[0182] In addition to the basic CNN and RNN networks described, variations of those networks can also be enabled. An example RNN variant is the Long Short-Term Memory (LSTM) RNN. LSTM RNNs are able to learn long-term dependencies that may be necessary to process longer language sequences. A variant of CNN is the Convolutional Deep Belief Network, which has a structure similar to a CNN and is trained in a manner similar to a Deep Belief Network. A Deep Belief Network (DBN) is a generative neural network composed of multiple layers of random (stochastic) variables. A DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining a set of optimal initial weights for the neural network.

[0183] Figure 11 An exemplary training and deployment of a deep neural network is illustrated. Once a given network has been structured for a task, the neural network is trained using a training dataset 1102. Various training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6 The machine learning framework 604 can be configured as a training framework 604. The training framework 604 can be hooked up to the untrained neural network 1106 and enable the untrained neural network to be trained using the parallel processing resources described herein to generate a trained neural network 1108.

[0184] To start the training process, initial weights can be chosen randomly or by pre-training with a deep belief network. A training cycle is then performed in a supervised or unsupervised manner.

[0185] Supervised learning is a learning method in which training is performed as a mediation operation, such as when a training dataset 1102 includes inputs paired with their expected outputs, or when a training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs to a set of expected or desired outputs. Errors are then backpropagated through the system. The training framework 1104 can be adjusted to adjust the weights that control the untrained neural network 1106. The training framework 1104 can provide tools to monitor how well the untrained neural network 1106 is converging toward a model that is suitable for generating the correct answer based on the known input data. The training process occurs iteratively, adjusting the network's weights to improve the outputs generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning operations.

[0186] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1102 will include input data without any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the overall data set. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1107 that can perform operations useful in reducing the dimensionality of data. Unsupervised training can also be used to perform anomaly detection, which allows data points in the input data set to be identified that deviate from normal data patterns.

[0187] Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training dataset 1102 includes a mixture of labeled and unlabeled data from the same distribution. Incremental learning is a variation of supervised learning in which input data is continuously used to further train the model. Incremental learning enables a trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge instilled into the network during initial training.

[0188] Whether supervised or unsupervised, the training process for particularly deep neural networks can be too computationally intensive for a single computing node. The training process can be accelerated by using a distributed network of computing nodes rather than a single computing node.

[0189] Figure 12 is an exemplary block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes can each include one or more host processors and one or more general processing nodes, such as Figure 7 700. As illustrated, distributed learning can perform model parallelism 1202, data parallelism 1204, or a combination of model and data parallelism 1204.

[0190] In model parallelism 1202, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelism include the ability to scale to extremely large models. Separating the computations associated with different layers of a neural network enables training of very large neural networks where the weights for all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0191] In data parallelism 1204, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. While different approaches to data parallelism are possible, data parallel training methods all require techniques for combining the results and synchronizing the model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that updates to the model are transmitted instead of transmitting parameters from the nodes to the parameter server. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transmitted between nodes.

[0192] For example, combined model and data parallelism 1206 can be implemented in a distributed system where each compute node includes multiple GPUs. Each node can have a complete instance of the model, with separate GPUs within each node used to train different parts of the model.

[0193] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can both implement various techniques for reducing the overhead of distributed training, including techniques for enabling high-bandwidth GPU-to-GPU data transfer and accelerated remote data synchronization.

[0194] Example Machine Learning Applications

[0195] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from reproducing human visual capabilities (such as recognizing faces) to creating new categories of visual capabilities. For example, a computer vision application can be configured to identify sound waves from vibrations caused by objects visible in a video. Parallel processor-accelerated machine learning enables the use of significantly larger training data sets than were previously feasible to train computer vision applications, and enables the deployment of inference systems using low-power parallel processors.

[0196] Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described herein can enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0197] Deep neural networks accelerated by parallel processors have enabled machine learning methods for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely speech sequence given a sequence of input sounds. Accelerated machine learning using deep neural networks has enabled the replacement of hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0198] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automatic learning programs can use statistical inference algorithms to generate models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0199] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are generally highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 7 Highly parallel general purpose graphics processing unit 700 and Figure 8 The multi-GPU computing system 800 of FIG. In contrast, the deployed machine learning platform generally includes low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0200] Figure 13An exemplary inference system-on-chip (SOC) 1300 suitable for performing inference using trained models is illustrated. SOC 1300 may integrate processing components including a media processor 1302, a vision processor 1304, a GPGPU 1306, and a multi-core processor 1308. SOC 1300 may additionally include on-chip memory 1305, which may enable a shared on-chip data pool accessible by each of the processing components. The processing components may be optimized for low-power operation to enable deployment in a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, an implementation of SOC 1300 may be used as part of a master control system for an autonomous vehicle. Where SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards for the deployment jurisdiction.

[0201] During operation, the media processor 1302 and the vision processor 1304 can work in concert to accelerate computer vision operations. The media processor 1302 can enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1305. The vision processor 1304 can then parse the decoded video and perform preliminary processing operations on the decoded video frames in preparation for processing them using a trained image recognition model. For example, the vision processor 1304 can accelerate the convolution operations of a CNN used to perform image recognition on high-resolution video data, while the back-end model calculations are performed by the GPGPU 1306.

[0202] The multi-core processor 1308 may include control logic to facilitate sequencing and synchronization of shared memory operations and data transfers performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also function as an application processor to execute software applications that may utilize the inference computing capabilities of the GPGPU 1306. For example, at least a portion of navigation and driving logic may be implemented in software executing on the multi-core processor 1308. Such software may issue computational workloads directly to the GPGPU 1306, or may issue computational workloads to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306.

[0203] GPGPU 1306 may include a computing cluster, such as low-power configuration computing clusters 706A-706H within a highly parallel general-purpose graphics processing unit 700. The computing cluster within GPGPU 1306 may support instructions specifically optimized for performing inference computations on trained neural networks. For example, GPGPU 1306 may support instructions for performing low-precision computations, such as 8-bit and 4-bit integer vector operations.

[0204] Budgeted and simplified training of deep neural networks (DNNs)

[0205] Figure 14 1 is an exemplary block diagram of a basic training and learning architecture 1400 having a deep neural network (DNN) training and learning system 1404 for receiving training data 1402 for learning and training the DNN. The training data 1402 can be input images with any number of image samples (test samples), or related data and information used. These input images can be used for budgeted and simplified training and learning by the DNN training and learning system 1404. In some embodiments, the DNN training and learning system 1404 may include Figure 1-8 and 19-32 disclosed and described in the system and processor, or by Figure 1-8 In other embodiments, the DNN training and learning system 1404 may be implemented using the systems and processors disclosed and described in 19-32. Figure 6 and 7 Training data (input images) 1402 may include image samples in any number of formats, including a red-green-blue (RGB) format with R, G, and B channel values. Other examples include image samples in color space pixels (YUV) with luminance, color, and chrominance channel values.

[0206] In an exemplary embodiment, the DNN training and learning system 1404 is based on Figure 15 and 16A

[0014] In the exemplary embodiments, a budgeted training and learning technique for a DNN is implemented based on the description of

[0014] -16C. For these exemplary embodiments, a small set of pixels is processed to train the DNN. In this way, the input image size can be reduced, making it possible to train large DNNs with less memory requirements.

[0207] In other exemplary embodiments, the DNN training and learning system 1404 is based on Figures 17A-17B18A-18B , simplified training and learning techniques for DNNs, such as deep recurrent Q-networks (DRQNs), are implemented. For these exemplary embodiments, the advantages of soft and hard attention mechanisms for training DQRNs are combined, which are differentiable and computationally efficient.

[0208] Budgeted training of DNNs

[0209] Figure 15 An exemplary process 1500 for selecting image data for a learning machine 1610 is illustrated. In this example, a large input image 1502 having large array dimensions of width (W) and height (H) is sub-sampled. Large input image 1502 can include any type of image data and format, such as an RGB format having red, green, and blue channels and values, or a YUV format having luma, luminance, and color chroma channels and values. The output of sub-sampling large input image 1502 includes N smaller sub-sampled images, illustrated as sub-image 1 (1504-1) through sub-image N (1504-N). In this exemplary embodiment, sub-images 1 (1504-1) through sub-image N (1504-N) have smaller dimensions than large input image 1502. Among the sub-images (eg, sub-image 1 (1504-1) to sub-image N (1504-N)), one of them is randomly selected as a randomly selected sub-image 1506 and identified as a selected sub-image k (1508). Figures 16A-16C In an exemplary embodiment, the selected sub-image k (1508) is input and processed by the learning machine 1501. In an exemplary embodiment, the learning machine 1501 may include Figure 16A The learning system 1600 described in , and N and K can be integers.

[0210] Figure 16A is an exemplary block diagram of a learning system 1600 that can implement budgeted training and learning techniques for DNNs. In an exemplary embodiment, the learning system 1600 implements Figures 16B-16C Publicly available example training and learning techniques. Figure 16A , an image down sampler 1604 can down sample a large input image from the image data 1602 into multiple smaller sub-images (eg, Figure 151 through sub-image N (1504-N). In one embodiment, the downsampled images have a lower resolution than the input image (e.g., input image 1502) from image data 1602 and are grouped into batches. For example, one batch may include sub-images 1 and 2, and another batch may include sub-images 3 and 4, and so on, where sub-image N is placed in a batch with one or more other sub-images.

[0211] In an exemplary embodiment, batch selector 1606 selects one of the batches of sub-images and feeds it to trainer 1608. Batch selector 1606 may feed other batches to trainer 1608, including the final batch of sub-images N (1504-N). Trainer 1608 feeds the selected batch of sub-images to a powerful neural network 1610, which may be any type of deep neural network (DNN), such as a deep convolutional neural network (CNN). In an exemplary embodiment, powerful neural network 1610 processes the batch of sub-images from trainer 1608 and updates parameters (e.g., weights at nodes of layers in the network) based on the processed sub-images and the classifications obtained by the network. In this manner, powerful neural network 1610 is trained using training data 1602 to improve classification. The output of powerful neural network 1610 may be a classification result, which may be input to tester 1616.

[0212] Tester 1616 may also process test images from test data 1612. In one embodiment, a large test image from test data 612 is downsampled into smaller sub-images by image downsampler 1616. Image downsampler 1616 may pass one of the smaller sub-images to tester 1616, which may test the sub-image using a trained robust neural network 1610 trained using downsampled images 1 (1504-1) through N (1504-N) to obtain a test result. Examples of test results may include classification results for the tested sub-images. Tester 1616 forwards the test results to combiner 1618. In an exemplary embodiment, combiner 1618 combines all test results from training data 1602 and uses any number of methods (e.g., a voting method) to determine a final result 1619, which may be the best result among the test results. Exemplary embodiments use subsampled images that have lower image resolution than the full large input image, thereby reducing computational and memory requirements while leveraging the capabilities of powerful DNNs.

[0213] Figures 16B-16CAn exemplary flow chart of operations 1620 and 1650 for training and testing a DNN is illustrated. Figure 16B Following operation 1620, at operation 1622, the training image is randomly downsampled to generate low-resolution sub-images. For example, the training image may be divided into a plurality of sub-portions, and the sub-portions may be randomly selected to generate sub-images having a lower resolution than the training image. In this manner, the DNN can use multiple smaller images having lower resolution for training.

[0214] At operation 1624, the generated low-resolution sub-images are divided into batches for training. In one example, the batches can include sub-images from different input images, and the batches can be randomly selected for training. At operation 1626, the batches of sub-images are processed by a DNN (e.g., power neural network 1610) for training. For example, the DNN can process the first batch of sub-images to determine a classification result and can adjust the weights based on the classification result. The adjusted weights can then be used for the next batch of sub-images when training the DNN.

[0215] refer to Figure 16C At operation 1650, at operation 1652, the training image is randomly downsampled to generate low-resolution sub-images for testing by the DNN. The downsampling of the test image can be performed in the same manner as the downsampling of the training image. At operation 1654, one of the downsampled low-resolution sub-images is input to a learning machine (or DNN) to process the sub-image to obtain a test result. The test result can be a classification result of the sub-image processed by the learning machine. The other downsampled low-resolution sub-images can be input to the learning machine one at a time to obtain multiple test results. At operation 1656, the test results are combined, and a final result can be selected based on a voting method or any other type of method for selecting a final result among multiple results.

[0216] (Simplified training of DQRN)

[0217] Figures 17A-18BAn exemplary embodiment of simplified training for a deep recurrent Q-network (DRQN) is illustrated. DRQN combines a deep Q-network (DQN) with a long-short-term memory (LSTM). DQN is a type of deep neural network (DNN), such as a deep convolutional neural network (CNN), that utilizes Q-learning. Q-learning is a reinforcement learning technique that can be used to find the optimal action selection policy for any given state. DQN can provide human-level control policies for a variety of tasks, but suffers from long training times and a lack of long-term memory. DRQN combines DQN with an LSTM to gain long-term memory capabilities. DRQN can retain information from previous states and use it to predict better Q values.

[0218] Figures 17A-18B An exemplary embodiment of the present invention provides a simplified and improved DRQN that focuses on a relatively small information region of an input image, thereby reducing the parameters and computational operations required to train and test the DNN. For example, the DRQN is disclosed with an improved local attention mechanism that forms part of the DRQN, which can make decisions about the next action based on a selected region of the input image (i.e., the attended region) rather than the entire region of the input image. Local attention includes two parts: "soft attention" and "hard attention". Soft attention assigns soft weights to all inputs and is differentiable, and gradient-based methods can be used to train soft attention. Hard attention selects a small patch of the image to pay attention to at a time, which requires fewer parameters and is more computationally efficient, but it is not differentiable and is therefore more difficult to train than soft attention.

[0219] In the disclosed examples, an improved local attention for DRQN is provided, which combines the advantages of soft attention and hard attention and is differentiable and computationally efficient. The improved local attention for DRQN can be implemented in at least two exemplary embodiments, the at least two exemplary embodiments being: (1) the local attention mechanism (or network) is located between a convolutional neural network (CNN) and an LSTM (e.g., Figures 17A-17B ); and (2) Hierarchical Memory Network (HMN) located between CNN and LSTM (e.g., Figures 18A-18B ).

[0220] Figure 17A1700 is a block diagram of an improved DRQN architecture 1700 according to an exemplary embodiment. The improved DRQN architecture 1700 includes a local attention network 1708 located between a convolutional neural network (CNN) 1704 and a long-short temporal memory 1712. CNN 1704 may be configured and initialized by architecture configuration 1701. Training data 1702 may provide image data or input images (e.g., training samples) to CNN 1704. CNN 1704 may process the input images and extract feature maps of the input images, which are fed to a hard attention selector 1705 located within the local attention network 1708. In an exemplary embodiment, the hard attention selector 1706 selects a subset of feature maps and discards the rest. In this example, only a subset of the feature maps of the input image are passed to a soft attention allocator 1710, which assigns weights to only the subset of feature maps selected by the hard attention selector 1706 for use in training a DNN such as DRQN 1700. In this way, a smaller set of parameters (eg, weights) is required for training.

[0221] The output of the soft attention allocator (e.g., weighted feature maps) can be stored in LSTM 1712, where the hard attention selector 1706 can use the stored information to select the next feature map for the input image. The Q-value estimator 1714 can also use the information stored in LSTM 172 to output Q-values for different actions based on the weighted feature maps to an iteration manager 1713, which controls the iteration conditions. The iteration manager 1713 also manages the number of iterations or convergence of applying weights to the selected feature maps and deriving the resulting Q-values (e.g., an estimate of how valuable an action is). The iteration manager 1713 can output the final deep Q-network 1716.

[0222] Figure 17B The diagram shows Figure 17AFlowchart of exemplary operations 1720 of an improved DRQN. In an exemplary embodiment, at operation 1722, a current visual frame (input image) is received, and a set of feature maps (e.g., feature maps extracted from CNN 1704) is extracted. At operation 1724, a subset of the feature maps is selected (e.g., hard attention selector 1706 selects the subset of feature maps). At operation 1726, weights are assigned to the selected subset of feature maps, and weight parameters of unselected feature maps may be set to zero (0). At operation 1728, Q-values are calculated for different actions based on the weighted feature maps (e.g., Q-values are calculated by Q-estimation 1714). At operation 1730, a determination is made as to whether convergence or the number of iterations has been met, and if so, at operation 1732, the final deep Q-network 1716 is output. If not, operation 1720 returns to operation 1724, and operations 1724 through 1728 are repeated.

[0223] Figure 18A 1800 is a block diagram of an improved DRQN architecture 1800 according to another exemplary embodiment. Improved DRQN architecture 1800 includes a hierarchical memory network 1810 positioned between a convolutional neural network (CNN) 1804 and a long-short term memory (LSTM) 1816. In this example, CNN 1804 and LSTM 1816 serve as input and output modules, respectively, for hierarchical memory network 1810, which also provides local attention capabilities. CNN 1804 can be configured and initialized using architecture configuration 1801. Training data 1802 can provide input images (e.g., training samples) to CNN 1804. CNN 1804 can process the input images and extract feature maps of the input images.

[0224] Hierarchical memory network 1810 includes a writer 1808, a hierarchical memory 1806, and a local attention-based reader 1812. In an exemplary embodiment, hierarchical memory 1806 includes memory cells organized into groups and subgroups that provide a hierarchical structure for the memory groups. In some embodiments, hierarchical memory 1806 is a fast non-volatile memory device. Writer 1808 writes or stores the extracted feature maps from CNN 1804 into hierarchical memory 1806. In some examples, writer 1808 stores the feature maps in hierarchical memory 1806 sequentially or in any desired order. Local attention-based reader 1812 can read the feature maps in hierarchical memory 1806 and apply weights to the feature maps to provide weighted feature maps. In some examples, local attention-based reader 1812 reads only a selected subset of the groups of memory-related feature maps that require different weights or have any desired weights. In other examples, the local attention based reader 1812 can implement a search algorithm to retrieve the most relevant information and feature maps using the hierarchical memory structure of the hierarchical memory 1806. Any type of search algorithm can also be employed for the local attention based reader 1812.

[0225] The output of the local attention-based reader 1812 (e.g., weighted feature maps) can be stored in an LSTM 1816, where a Q-value estimator 1818 can use the stored information in the LSTM 1816 and the training data 1802 to output Q-values for different actions based on the weighted feature maps to an iteration manager 1714. The iteration manager 1814 manages the number of iterations or convergence of applying weights to selected feature maps and deriving the resulting Q-values (e.g., an estimate of how valuable an action is). The iteration manager 1814 can output a final deep Q-network 1820.

[0226] Figure 18B The diagram shows Figure 18AFlowchart of exemplary operations 1850 of an improved DRQN. In an exemplary embodiment, at operation 1852, a current visual frame (input image) is received, and a set of feature maps (e.g., feature maps extracted from CNN 1804) are extracted. At operation 1854, the feature maps are written (or stored) in hierarchical memory within a hierarchical memory network (e.g., hierarchical memory network 1810) (e.g., writer 1808 writes the feature maps from CNN 1804 to hierarchical memory 1806). At operation 1856, a selected subset of the feature maps is read from the hierarchical memory, and soft attention is applied to them (e.g., by local attention-based reader 1812) to generate weighted feature maps. At operation 1858, Q-values are calculated for different actions based on the weighted feature maps (e.g., by Q-value estimation 1818). At operation 1860, a decision is made as to whether convergence or the number of iterations has been met, and if so, at operation 1862, the final deep Q-network 1820 is generated. If not, operation 1850 returns to operation 1854 and operations 1854 to 1858 are repeated.

[0227] Graphics System Overview

[0228] Figure 19 is a block diagram of a processing system 1900 according to an exemplary embodiment. In various embodiments, system 1900 includes one or more processors 1902 and one or more graphics processors 1908, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1902 or processor cores 107. In one embodiment, system 1900 is a processing platform incorporated into a system-on-chip (SoC) integrated circuit for use in a mobile device, handheld device, or embedded device.

[0229] Embodiments of the system 1900 may include, or be incorporated into, a server-based gaming platform, a gaming console (including a gaming and media console, a mobile gaming console, a handheld gaming console, or an online gaming console). In some embodiments, the system 1900 is a mobile phone, a smartphone, a tablet computing device, or a mobile internet device. The data processing system 1900 may also include, be coupled to, or be integrated into a wearable device (such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device). In some embodiments, the data processing system 1900 is a television or set-top box device having one or more processors 1902 and a graphical interface generated by one or more graphics processors 1908.

[0230] In some embodiments, the one or more processors 1902 each include one or more processor cores 1907 for processing instructions that, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 1907 is configured to process a specific instruction set 1909. In some embodiments, the instruction set 1909 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 1907 may each process a different instruction set 1909, which may include instructions that facilitate emulation of other instruction sets. The processor cores 1907 may also include other processing devices, such as a digital signal processor (DSP).

[0231] In some embodiments, processor 1902 includes a cache memory 1904. Depending on the architecture, processor 1902 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of processor 1902. In some embodiments, processor 1902 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among processor cores 1907 using known cache coherence techniques. A register file 1906 is additionally included in processor 1902 and may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and an instruction pointer register). Some registers may be general-purpose registers, while others may be specific to the design of processor 1902.

[0232] In some embodiments, processor 1902 is coupled to a processor bus 1910 to transmit communication signals, such as address, data, or control signals, between processor 1902 and other components in system 1900. In one embodiment, system 100 utilizes an exemplary "hub" system architecture, including a memory controller hub 1916 and an input / output (I / O) controller hub 1930. Memory controller hub 1916 facilitates communication between memory devices and other components of system 1900, while I / O controller hub (ICH) 1930 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller hub 1916 is integrated within the processor.

[0233] The memory device 1920 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance to function as process memory. In one embodiment, the memory device 1920 may operate as system memory for the system 1900 to store data 1922 and instructions 1921 for use when the one or more processors 1902 execute applications or processes. The memory controller hub 1916 is also coupled to an optional external graphics processor 1912, which may communicate with the one or more graphics processors 1908 in the processor 1902 to perform graphics and media operations.

[0234] In some embodiments, ICH 1930 enables peripheral devices to connect to memory device 1920 and processor 1902 via a high-speed I / O bus. I / O peripherals include, but are not limited to, an audio controller 1946, a firmware interface 1928, a wireless transceiver 1926 (e.g., Wi-Fi, Bluetooth), a data storage device 1924 (e.g., a hard drive, flash memory, etc.), and a legacy I / O controller 1940 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1942 connect input devices, such as a keyboard and mouse 1944 combination. A network controller 1934 may also be coupled to ICH 1930. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 1910. It will be appreciated that the illustrated system 1900 is exemplary and non-limiting, as other types of differently configured data processing systems may also be used. For example, the I / O controller hub 1930 may be integrated within the one or more processors 1902 , or the memory controller hub 1916 and the I / O controller hub 1930 may be integrated into a separate external graphics processor, such as the external graphics processor 1912 .

[0235] Figure 20 is a block diagram of an exemplary embodiment of a processor 2000 having one or more processor cores 2002A- 2002N, an integrated memory controller 2014 , and an integrated graphics processor 2008 . Figure 20Those elements having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Processor 2000 may include additional cores up to and including additional core 2002N represented by a dashed box. Each of processor cores 2002A-2002N includes one or more internal cache units 2004A-2004N. In some embodiments, each processor core may also have access to one or more shared cache units 2006.

[0236] Internal cache units 2004A-2004N and shared cache unit 2006 represent a cache memory hierarchy within processor 2000. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core, and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, with the highest level of cache before external memory being categorized as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 2006 and 2004A-2004N.

[0237] In some embodiments, processor 2000 may also include a system agent core 2010 and a set of one or more bus controller units 216. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). System agent core 2010 provides management functions for various processor components. In some embodiments, system agent core 2010 includes one or more integrated memory controllers 2014 to manage access to various external memory devices (not shown).

[0238] In some embodiments, one or more of the processor cores 2002A-2002N include support for simultaneous multithreading. In such embodiments, the system agent core 210 includes components for coordinating and operating the cores 2002A-2002N during multithreaded processing. The system agent core 210 may additionally include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 2002A-2002N and the graphics processor 2008.

[0239] In some embodiments, processor 2000 additionally includes a graphics processor 2008 for performing graphics processing operations. In some embodiments, graphics processor 2008 is coupled with a set of shared cache units 2006 and a system agent core 2010, which includes one or more integrated memory controllers 2014. In some embodiments, a display controller 2011 is coupled to graphics processor 2008 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 2011 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within graphics processor 2008 or system agent core 2010.

[0240] In some embodiments, a ring-based interconnect 2012 is used to couple the internal components of the processor 2000. However, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art. In some embodiments, the graphics processor 208 is coupled to the ring interconnect 2012 via an I / O link 2013.

[0241] Exemplary I / O link 2013 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of processor cores 202A-202N, as well as graphics processor 208, utilizes embedded memory module 218 as a shared last-level cache.

[0242] In some embodiments, processor cores 2002A-2002N are homogeneous cores that execute the same instruction set architecture. In another embodiment, processor cores 2002A-2002N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 2002A-2002N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 2002A-2002N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In addition, processor 200 can be implemented on one or more chips or as a SoC integrated circuit having the illustrated components in addition to other components.

[0243] Figure 212 is a block diagram of a graphics processor 2100, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and using commands placed into processor memory. In some embodiments, the graphics processor 300 includes a memory interface 2114 for accessing memory. The memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0244] In some embodiments, the graphics processor 2100 also includes a display controller 2102 for driving display output data to a display device 2120. The display controller 2102 includes hardware for one or more overlapping planes of the display and the composition of multiple layers of video or user interface elements. In some embodiments, the graphics processor 2100 includes a video codec engine 306 for encoding, decoding, or transcoding media to, from, or between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421 M / VC-1 and Joint Photographic Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG) formats).

[0245] In some embodiments, the graphics processor 2100 includes a block image transfer (BLIT) engine 2104 for performing two-dimensional (2D) raster operations, including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of the graphics processing engine (GPE) 310. In some embodiments, the GPE 2110 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0246] In some embodiments, GPE 2110 includes a 3D pipeline 2112 for performing 3D operations, such as rendering three-dimensional images and scenes, using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 2112 includes programmable and fixed functional elements that perform various tasks within the element and / or spawn execution threads to 3D / media subsystem 315. While 3D pipeline 2112 can be used to perform media operations, embodiments of GPE 310 also include a media pipeline 2116 that is particularly useful for performing media operations, such as video post-processing and image enhancement.

[0247] In some embodiments, the media pipeline 2116 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of, or on behalf of, the video codec engine 2106. In some embodiments, the media pipeline 2116 additionally includes a thread generation unit to generate threads for execution on the 3D / media subsystem 2115. The generated threads perform computations for media operations on one or more graphics execution units included in the 3D / media subsystem 2115.

[0248] In some embodiments, the 3D / media subsystem 2115 includes logic for executing threads generated by the 3D pipeline 2112 and the media pipeline 2116. In one embodiment, the pipelines send thread execution requests to the 3D / media subsystem 2115, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2115 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and store output data.

[0249] Graphics processing engine

[0250] Figure 22 is a block diagram of a graphics processing engine 2210 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2210 is Figure 21 A version of the GPE 2210 is shown in FIG. Figure 22Elements having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such. For example, the 3D pipeline 2212 and media pipeline 2216 of FIG. 3 are illustrated. The media pipeline 2216 is optional in some embodiments of the GPE 2210 and may not be explicitly included within the GPE 410. For example, and in at least one embodiment, separate media and / or image processors are coupled to the GPE 2210.

[0251] In some embodiments, GPE 2210 is coupled to or includes a command streamer 2203, which provides a command stream to the 3D pipeline 2112 and / or the media pipeline 2116. In some embodiments, command streamer 2203 is coupled to memory, which may be system memory, or one or more of an internal cache and a shared cache. In some embodiments, command streamer 2203 receives commands from memory and sends them to the 3D pipeline 2112 and / or the media pipeline 2116. The commands are instructions retrieved from a ring buffer that stores commands for the 3D pipeline 2112 and the media pipeline 2116. In one embodiment, the ring buffer may additionally include a batch command buffer that stores batches of multiple commands. Commands for the 3D pipeline 2112 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 2112 and / or image data and memory objects for the media pipeline 2116. The 3D pipeline 2112 and the media pipeline 2116 process commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 2214 .

[0252] In various embodiments, the 3D pipeline 2112 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2214. The graphics core array 2214 provides a unified block of execution resources. The multi-purpose execution logic (e.g., execution units) within the graphics core array 2214 includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders.

[0253] In some embodiments, the graphics core array 2214 also includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution unit additionally includes general logic that can be programmed to perform parallel general computing operations. The general logic can be used with Figure 19 (multiple) processor cores 1907 or such Figure 20 The general logic within cores 2002A-2002N in the process performs processing operations in parallel or in combination.

[0254] Output data generated by threads executing on graphics core array 2214 can be output to memory in unified return buffer (URB) 2218. URB 2218 can store data for multiple threads. In some embodiments, URB 2218 can be used to send data between different threads executing on graphics core array 2214. In some embodiments, URB 2218 can also be used for synchronization between fixed-function logic within shared function logic 2220 and threads on the graphics core array.

[0255] In some embodiments, graphics core array 2214 is scalable such that the array includes a variable number of graphics cores, each core having a variable number of execution units based on the target power and performance level of GPE 2210. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0256] Graphics core array 2214 is coupled to shared function logic 2220, which includes multiple resources shared among the graphics cores in the graphics core array. Shared functions within shared function logic 2220 are hardware logic units that provide specialized, complementary functionality to graphics core array 2214. In various embodiments, shared function logic 2220 includes, but is not limited to, sampler 2221, math 2222, and inter-thread communication (ITC) 2223 logic. Additionally, some embodiments implement one or more caches 2225 within shared function logic 2220. Shared functions are implemented in situations where demand for a given specialized function is insufficient to include it within graphics core array 2214. Alternatively, a single instance of that specialized function is implemented as a separate entity within shared function logic 2220 and shared among execution resources within graphics core array 2214. The exact set of functions shared among and included within graphics core array 2214 varies between embodiments.

[0257] Figure 23 is a block diagram of another exemplary embodiment of a graphics processor 500 . Figure 23Elements having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0258] In some embodiments, graphics processor 2300 includes ring interconnect 2302, pipeline front end 2304, media engine 2337, and graphics cores 2380A-2380N. In some embodiments, ring interconnect 2302 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated into a multi-core processing system.

[0259] In some embodiments, the graphics processor 2300 receives batches of commands via a ring interconnect 2302. The incoming commands are interpreted by a command streamer 2303 in a pipeline front end 2304. In some embodiments, the graphics processor 2300 includes scalable execution logic for performing 3D geometry processing and media processing via graphics core(s) 2380A-2380N. For 3D geometry processing commands, the command streamer 2303 supplies the commands to a geometry pipeline 2336. For at least some media processing commands, the command streamer 2303 supplies the commands to a video front end 2334, which is coupled to a media engine 2337. In some embodiments, the media engine 2337 includes a video quality engine (VQE) 2330 for video and image post-processing and a multi-format encoding / decoding (MFX) 2333 engine for providing hardware-accelerated media data encoding and decoding. In some embodiments, both the geometry pipeline 2336 and the media engine 2337 generate execution threads for thread execution resources provided by at least one graphics core 2380A.

[0260] In some embodiments, graphics processor 2300 includes scalable thread execution resources featuring modular cores 2380A-2380N (sometimes referred to as core slices), each of which has multiple sub-cores 2350A-2350N, 2360A-2360N (sometimes referred to as core subslices). In some embodiments, graphics processor 2300 may have any number of graphics cores 2380A-2380N. In some embodiments, graphics processor 2300 includes graphics core 2380A, which has at least a first sub-core 2350A and a second sub-core 2360A. In other embodiments, the graphics processor is a low-power processor with a single sub-core (e.g., 2350A). In some embodiments, graphics processor 2300 includes multiple graphics cores 2380A-2380N, each of which includes a set of first sub-cores 2350A-2350N and a set of second sub-cores 2360A-2360N. Each of the first sub-cores 2350A-2350N includes at least a first set of execution units 2352A-2352N and a media / texture sampler 2354A-2354N. Each of the second sub-cores 2360A-2360N includes at least a second set of execution units 2362A-2362N and a sampler 2364A-2364N. In some embodiments, each of the sub-cores 2350A-2350N, 2360A-2360N shares a set of shared resources 2370A-2370N. In some embodiments, the shared resources include a shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0261] Execution Unit

[0262] Figure 24 Illustrated is thread execution logic 2400 comprising an array of processing elements employed in some exemplary embodiments of a GPE. Figure 24 Elements having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0263] In some embodiments, thread execution logic 2400 includes a shader processor 2402, a thread dispatcher 2404, an instruction cache 2406, a scalable execution unit array including a plurality of execution units 2408A-2408N, a sampler 2410, a data cache 2412, and a data port 2414. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 2408A, 2408B, 2408C, 2408D through 2408N-1 and 2408N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, thread execution logic 2400 includes one or more connections to a memory (such as system memory or cache memory) through one or more of the instruction cache 2406, the data port 2414, the sampler 2410, and the execution units 2408A-2408N. In some embodiments, each execution unit (e.g., 2408A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 2408A-2408N is scalable to include any number of individual execution units.

[0264] In some embodiments, execution units 2408A-2408N are primarily used to execute shader programs. Shader processor 2402 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2404. In one embodiment, thread dispatcher includes logic for arbitrating thread initiation requests from graphics and media pipelines and instantiating the requested threads on one or more execution units in execution units 2408A-2408N. For example, the geometry pipeline (e.g., Figure 23 2336) can dispatch vertex, tessellation, or geometry shaders to thread execution logic 2400 ( Figure 24 In some embodiments, the thread dispatcher 604 may also process runtime thread generation requests from executing shader programs.

[0265] In some embodiments, execution units 2408A-2408N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling execution of shader programs from graphics libraries (e.g., Direct3D and OpenGL) with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders). Each execution unit 2408A-2408N is capable of multi-issue single instruction, multiple data (SIMD) execution, and multi-threaded operation enables an efficient execution environment even with high-latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is multi-issue per clock cycle, with a pipeline capable of integer, single- and double-precision floating-point operations, SIMD branching, logical operations, transcendental operations, and other miscellaneous operations. When waiting for data from memory or one of the shared functions, dependency logic within execution units 2408A-2408N puts the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during the delay associated with vertex shader operations, the execution unit may execute operations of a pixel shader, a fragment shader, or another type of shader program that includes a different vertex shader.

[0266] Each execution unit in execution units 2408A-2408N operates on an array of data elements. The number of data elements is the "execution size," or the number of lanes used for an instruction. An execution lane is the logic used to perform data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, execution units 608A-608N support integer and floating point data types.

[0267] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as packed data types, and the execution unit will process various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit packed data elements (quad word (QW) sized data elements), eight separate 32-bit packed data elements (double word (DW) sized data elements), sixteen separate 16-bit packed data elements (word (W) sized data elements), or thirty-two separate 8-bit data elements (byte (B) sized data elements). However, different vector widths and register sizes are possible.

[0268] One or more internal instruction caches (e.g., 2406) are included in thread execution logic 2400 to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 2412) are included to cache thread data during thread execution. In some embodiments, a sampler 2410 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 2410 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution units.

[0269] During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2400 via thread spawning and dispatching logic. Once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2402 is invoked to further calculate output information and cause the results to be written to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the values of various vertex attributes to be interpolated across the rasterized objects. In some embodiments, the pixel processor logic within the shader processor 2402 then executes the pixel or fragment shader program provided by the application programming interface (API). To execute the shader program, the shader processor 2402 dispatches a thread to an execution unit (e.g., 2408A) via the thread dispatcher 2404. In some embodiments, the pixel shader 2402 uses texture sampling logic in the sampler 2410 to access texture data in a texture map stored in memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels from further processing.

[0270] In some embodiments, the data port 2414 provides a memory access mechanism for the thread execution logic 2400 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, the data port 614 includes or is coupled to one or more cache memories (e.g., data cache 2412) to cache data for memory access via the data port.

[0271] Figure 25 2 is a block diagram illustrating a graphics processor instruction format 2500 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid-line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include components that are optional or included only in a subset of instructions. In some embodiments, the described and illustrated instruction format 2500 are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations that result from instruction decoding once the instruction is processed.

[0272] In some embodiments, the graphics processor execution unit natively supports instructions in the 128-bit instruction format 2510. Depending on the selected instruction, instruction options, and the number of operands, a 64-bit compressed instruction format 2530 may be used for some instructions. The native 128-bit instruction format 2510 provides access to all instruction options, while some options and operations are restricted to the 64-bit instruction format 2530. The native instructions available in the 64-bit instruction format 2530 vary depending on the embodiment. In some embodiments, instructions are partially compressed using a set of index values in the index field 2513. The execution unit hardware references a set of compression tables based on the index values and uses the compression table output to reconstruct the native instruction in the 128-bit instruction format 2510.

[0273] For each format, the instruction opcode 2512 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel, each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2514 enables control of certain execution options, such as channel selection (e.g., prediction) and data channel ordering (e.g., swizzling). For instructions using the 128-bit instruction format 2510, the execution size field 2516 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 2516 is not available for use in the 64-bit compressed instruction format 2530.

[0274] Some execution unit instructions have up to three operands, including two source operands—src0 2520 and src1 2522—and a destination 2518. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., src2 2524), where the instruction opcode 2512 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0275] In some embodiments, the 128-bit instruction format 2510 includes an access / addressing mode field 2526 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0276] In some embodiments, the 128-bit instruction format 2510 includes an access / addressing mode field 2526 that specifies the addressing mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in the first mode, the instruction may use byte-aligned addressing for source and destination operands, and when in the second mode, the instruction may use 16-byte aligned addressing for all source and destination operands.

[0277] In one embodiment, the addressing mode portion of the access / addressing mode field 726 determines whether the instruction uses direct or indirect addressing. When direct register addressing mode is used, bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0278] In some embodiments, instructions are grouped based on the opcode 2512-bit field to simplify opcode decoding 2540. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the opcode type. The exact opcode grouping shown is only an example. In some embodiments, the move and logic opcode group 2542 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2542 shares the five most significant bits (MSBs), with move (mov) instructions taking the form 0000xxxxb and logic instructions taking the form 0001xxxxb. The flow control instruction group 2544 (e.g., call, jump (jmp)) includes instructions taking the form 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2546 includes a mix of instructions, including synchronization instructions (e.g., wait, send) taking the form 0011xxxxb (e.g., 0x30). The parallel math instruction group 2548 includes component-by-component arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 2548 performs arithmetic operations in parallel across the data lanes. The vector math group 750 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic on vector operands, such as dot product calculations.

[0279] Graphics pipeline

[0280] Figure 26 is a block diagram of another embodiment of a graphics processor 800 . Figure 26 Elements having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0281] In some embodiments, graphics processor 2600 includes a graphics pipeline 2620, a media pipeline 2630, a display engine 2640, thread execution logic 2650, and a render output pipeline 2670. In some embodiments, graphics processor 2600 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor 2600 via ring interconnect 2602. In some embodiments, ring interconnect 802 couples graphics processor 2600 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 802 are interpreted by command streamer 2603, which supplies instructions to individual components of graphics pipeline 2620 or media pipeline 2630.

[0282] In some embodiments, the command streamer 2603 directs the operation of the vertex fetcher 2605, which reads vertex data from memory and executes vertex processing commands provided by the command streamer 2603. In some embodiments, the vertex fetcher 805 provides vertex data to the vertex shader 2607, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 805 and the vertex shader 2607 execute vertex processing instructions by dispatching execution threads to execution units 2652A-2652B via the thread dispatcher 2631.

[0283] In some embodiments, execution units 2652A-2652B are arrays of vector processors with instruction sets for performing graphics and media operations. In some embodiments, execution units 2652A-2652B have an attached L1 cache 2651, which is specific to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0284] In some embodiments, graphics pipeline 2620 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 2611 configures the tessellation operations. A programmable domain shader 2617 provides back-end evaluation of the tessellation output. Tessellation controller 2613 operates under the direction of hull shader 2611 and contains dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model provided as input to graphics pipeline 2620. In some embodiments, if tessellation is not used, the tessellation components (e.g., hull shader 2611, tessellation controller 2613, and domain shader 2617) can be bypassed.

[0285] In some embodiments, the complete geometric object can be processed by the geometry shader 2619 via one or more threads dispatched to execution units 2652A-2652B, or can proceed directly to the clipper 2629. In some embodiments, the geometry shader operates on the entire geometric object rather than on vertices or vertex patches as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2619 receives input from the vertex shader 2607. In some embodiments, the geometry shader 2619 can be programmed by the geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0286] Before rasterization, the clipper 2629 processes the vertex data. The clipper 2629 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, the rasterizer and depth test component 2673 in the render output pipeline 2670 dispatches a pixel shader to convert the geometric object into its per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 2650. In some embodiments, the application can bypass the rasterizer and depth test component 2673 and access the unrasterized vertex data via the outflow unit 2623.

[0287] Graphics processor 2600 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some embodiments, execution units 2652A-2652B and associated cache(s) 2651, texture and media samplers 2654, and texture / sampler cache 2658 are interconnected via data ports 2656 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 2654, caches 2651, 2658, and execution units 2652A-2652B each have separate memory access paths.

[0288] In some embodiments, the render output pipeline 2670 includes a rasterizer and depth test component 2673, which converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. An associated render cache 2678 and depth cache 2679 are also available in some embodiments. A pixel operation component 2677 performs pixel-based operations on data, however, in some instances, pixel operations associated with 2D operations (e.g., using hybrid bit-block image transfers) are performed by the 2D engine 2641 or, at display time, by the display controller 2643 using overlapping display planes instead. In some embodiments, a shared L3 cache 2675 is available to all graphics components, allowing data to be shared without using main system memory.

[0289] In some embodiments, the graphics processor media pipeline 2630 includes a media engine 2637 and a video front end 2634. In some embodiments, the video front end 2634 receives pipeline commands from the command streamer 2603. In some embodiments, the media pipeline 2630 includes a separate command streamer. In some embodiments, the video front end 2634 processes the media commands before sending them to the media engine 2637. In some embodiments, the media engine 2637 includes thread generation functionality to generate threads for dispatching to the thread execution logic 2650 via the thread dispatcher 2631.

[0290] In some embodiments, graphics processor 2600 includes a display engine 840. In some embodiments, display engine 2640 is external to processor 2600 and coupled to the graphics processor via ring interconnect 2602 or some other interconnect bus or structure. In some embodiments, display engine 2640 includes a 2D engine 2641 and a display controller 2643. In some embodiments, display engine 2640 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, display controller 2643 is coupled to a display device (not shown), which can be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0291] In some embodiments, the graphics pipeline 2620 and the media pipeline 2630 can be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor converts API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for all of the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulkan graphics and computing APIs from the Khronos Group. In some embodiments, support can also be provided for the Direct3D library from Microsoft. In some embodiments, a combination of these libraries can be supported. Support can also be provided for the Open Source Computer Vision Library (OpenCV). If a mapping can be made from the pipeline of a future API to the pipeline of the graphics processor, future APIs with compatible 3D pipelines will also be supported.

[0292] Graphics pipeline programming

[0293] Figure 27A is a block diagram illustrating a graphics processor command format 2700 according to some embodiments. Figure 27B is a block diagram illustrating a graphics processor command sequence 2710 according to an embodiment. Figure 27AThe solid-line boxes in illustrate components that are generally included in a graphics command, while the dashed lines include components that are optional or included only in a subset of the graphics command. Figure 27A The exemplary graphics processor command format 2700 includes a data field for identifying the target client 2702 of the command, a command operation code (opcode) 2704, and associated data for the command 2706. In some commands, a sub-opcode 2705 and a command size 2708 are also included.

[0294] In some embodiments, client 2702 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to coordinate further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads the opcode 2704 and sub-opcode 2705 (if present) to determine the operation to be performed. The client unit uses the information in the data field 2706 to execute the command. For some commands, an explicit command size 908 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, commands are aligned using multiples of double words.

[0295] Figure 27B An exemplary graphics processor command sequence 2710 is shown in the flowchart in FIG. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the illustrated command sequence to establish, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as embodiments are not limited to these specific commands or this command sequence. Furthermore, the commands can be issued as a batch of commands in a command sequence such that the graphics processor will process the sequence of commands at least partially simultaneously.

[0296] In some embodiments, graphics processor command sequence 910 may begin with a pipeline flush command 2712 to cause any active graphics pipeline to complete currently pending commands for that pipeline. In some embodiments, 3D pipeline 2722 and media pipeline 2724 are not operating simultaneously. A pipeline flush is performed to cause active graphics pipelines to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will suspend command processing until the active graphics engines complete pending operations and the associated read cache is invalidated. Optionally, any data marked as "dirty" in the render cache may be flushed to memory. In some embodiments, pipeline flush command 2712 may be used for pipeline synchronization or before placing the graphics processor into a low-power state.

[0297] In some embodiments, pipeline select command 2713 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, pipeline select command 2713 is required only once within an execution context before issuing pipeline commands, unless the context is issuing commands for both pipelines. In some embodiments, pipeline flush command 2712 is required immediately before a pipeline switch via pipeline select command 2713.

[0298] In some embodiments, pipeline control commands 2714 configure the graphics pipeline for operation and are used to program 3D pipeline 2722 and media pipeline 2724. In some embodiments, pipeline control commands 2714 configure pipeline states for the active pipeline. In one embodiment, pipeline control commands 2714 are used for pipeline synchronization and for flushing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0299] In some embodiments, commands for return buffer state 2716 are used to configure a set of return buffers for the corresponding pipeline to write data to. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers to which intermediate data is written during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, configuring return buffer state 2716 includes selecting the size and number of return buffers to be used for a set of pipeline operations.

[0300] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline determination 2720 , the command sequence is suitable for either the 3D pipeline 2722 starting in 3D pipeline state 2730 or the media pipeline 2724 starting in media pipeline state 2740 .

[0301] The commands used to configure the 3D pipeline state 930 include 3D state setup commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 2730 commands can also selectively disable or bypass certain pipeline elements if those elements are not to be used.

[0302] In some embodiments, the 3D primitive 2732 command is used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2732 command are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 2732 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 2732 command is used to perform vertex operations on the 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 2722 dispatches the shader execution thread to the graphics processor execution unit.

[0303] In some embodiments, the 3D pipeline 2722 is triggered via an execute 2734 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a "go" or "kick" command in a command sequence. In one embodiment, pipeline synchronization commands are used to trigger command execution to flush the command sequence through the graphics pipeline. The 3D pipeline performs geometry processing for 3D primitives. Once the operation is completed, the resulting geometry is rasterized and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0304] In some embodiments, when performing media operations, the graphics processor command sequence 2710 follows the media pipeline 2724 path. Generally, the specific use and manner of programming for the media pipeline 2724 depends on the media or compute operation to be performed. During media decoding, certain media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed and the media decoding can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0305] In some embodiments, the media pipeline 2724 is configured in a similar manner to the 3D pipeline 2722. A set of commands for configuring the media pipeline state 2740 is dispatched or placed into a command queue prior to the media object commands 2742. In some embodiments, the commands for the media pipeline state 2740 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the commands for the media pipeline state 2740 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0306] In some embodiments, media object commands 2742 supply a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer that contains the video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 2742. Once the pipeline state is configured and media object commands 2742 are queued, the media pipeline 924 is triggered via an execute command 2744 or an equivalent execute event (e.g., a register write). The output from the media pipeline 2724 can then be post-processed by operations provided by the 3D pipeline 2722 or the media pipeline 2724. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0307] Graphics software architecture

[0308] Figure 28An exemplary graphics software architecture for a data processing system 2800 according to some embodiments is illustrated. In some embodiments, the software architecture includes a 3D graphics application 2810, an operating system 2820, and at least one processor 2830. In some embodiments, processor 2830 includes a graphics processor 2832 and one or more general-purpose processor cores 2834. Both graphics application 2810 and operating system 2820 execute in system memory 1050 of the data processing system.

[0309] In some embodiments, the 3D graphics application 2810 includes one or more shader programs that include shader instructions 2812. The shader language instructions may be in a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 2814 in a machine language suitable for execution by the general-purpose processor core 2834. The application also includes graphics objects 1016 defined by vertex data.

[0310] In some embodiments, the operating system 2820 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. The operating system 1020 may support a graphics API 2822, such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system 2820 uses a front-end shader compiler 2824 to compile any shader instructions 2812 in HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation, or the application may perform shader precompilation. In some embodiments, during the compilation of the 3D graphics application 2810, high-level shaders are compiled into low-level shaders. In some embodiments, the shader instructions 2812 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0311] In some embodiments, the user-mode graphics driver 2826 includes a backend shader compiler 2827 for converting shader instructions 2812 into a hardware-specific representation. When the OpenGL API is in use, shader instructions 2812 in the GLSL high-level language are passed to the user-mode graphics driver 2826 for compilation. In some embodiments, the user-mode graphics driver 2826 uses operating system kernel-mode functionality 2828 to communicate with the kernel-mode graphics driver 2829. In some embodiments, the kernel-mode graphics driver 1029 communicates with the graphics processor 2832 to dispatch commands and instructions.

[0312] IP core implementation

[0313] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to fabricate logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model onto a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured such that the circuit performs the operations described in association with any of the embodiments described herein.

[0314] Figure 29 The block diagram illustrates an IP core development system 1100 that can be used to fabricate an integrated circuit to perform operations according to an embodiment. The IP core development system 1100 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SoC integrated circuits). A design facility 2930 can generate a software simulation 2910 of the IP core design in a high-level programming language (e.g., C / C++). Software simulation 2910 can be used to design, test, and verify the behavior of the IP core using a simulation model 2912. Simulation model 2912 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 2915 can then be created or synthesized from simulation model 2912. RTL design 2915 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers and includes associated logic executed using the modeled digital signals. In addition to RTL design 2915, lower-level designs at the logic or transistor level can also be created, designed, or synthesized. Therefore, the specific details of the initial design and simulation may vary.

[0315] The RTL design 2915 or equivalent can be further synthesized by the design facility into a hardware model 2920, which can be in hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. The IP core design can be stored using non-volatile memory 2940 (e.g., a hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 2965. Alternatively, the IP core design can be transmitted via a wired connection 2950 or a wireless connection 2960 (e.g., via the Internet). The manufacturing facility 2965 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0316] Exemplary System-on-Chip Integrated Circuit

[0317] Figure 30-32 An exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are illustrated. In addition to what is illustrated, other logic and circuitry may also be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0318] Figure 30 30 is a block diagram illustrating an exemplary system-on-chip integrated circuit 3000 that can be manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 1200 includes one or more application processors 3005 (e.g., CPUs), at least one graphics processor 3010, and may additionally include an image processor 3015 and / or a video processor 3020, any of which can be modular IP cores from the same or multiple different design facilities. The integrated circuit 3000 includes peripheral or bus logic that includes a USB controller 1225, a UART controller 3030, an SPI / SDIO controller 3035, and an I 2 S / I 2 The integrated circuit may also include a display device 3045 coupled to a High-Definition Multimedia Interface (HDMI) controller 1250 and a Mobile Industry Processor Interface (MIPI) display interface 3055. Storage may be provided by a flash memory subsystem 3060, which includes flash memory and a flash memory controller. A memory interface may be provided via a memory controller 1265 for accessing SDRAM or SRAM memory devices. Some integrated circuits may also include an embedded security engine 3070.

[0319] Figure 31is a block diagram illustrating an exemplary graphics processor 3110 of a system-on-chip integrated circuit that may be manufactured using one or more IP cores according to an embodiment. The graphics processor 3110 may be Figure 30 The graphics processor 3110 includes a vertex processor 3105 and one or more fragment processors 3115A-3115N (e.g., 3115A, 3115B, 3115C, 3115D through 3115N-1 and 3115N). The graphics processor 3110 can execute different shader programs via separate logic, such that the vertex processor 3105 is optimized to perform operations for vertex shader programs, while the one or more fragment processors 3115A-3115N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 3105 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processor(s) 3115A-3115N use the primitives and vertex data generated by the vertex processor 3105 to generate a frame buffer that is displayed on a display device. In one embodiment, the fragment processor(s) 3115A-3115N are optimized to execute fragment shader programs as provided for in the OpenGL API, which can be used to perform similar operations as pixel shader programs as provided for in the Direct 3D API.

[0320] The graphics processor 3110 additionally includes one or more memory management units (MMUs) 3120A-3120B, cache(s) 3125A-3125B, and interconnect(s) 3130A-3130B. The one or more MMUs 3120A-3120B provide virtual-to-physical address mappings for the graphics processor 3110, including for the vertex processor 3105 and / or fragment processor(s) 3115A-3115N, which may reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in the one or more caches 3125A-3125B. In one embodiment, the one or more MMUs 3120A-3120B may be synchronized with other MMUs within the system, including those associated with the graphics processor 3110. Figure 30 One or more MMUs associated with the one or more application processors 3005, image processor 3015, and / or video processor 3020 enable each processor 3005-3020 to participate in a shared or unified virtual memory system. According to an embodiment, the one or more circuit interconnects 3130A-3130B enable the graphics processor 3110 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0321] Figure 32 is a block diagram illustrating an additional exemplary graphics processor 3210 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with an embodiment. The graphics processor 3210 may be Figure 30 A variant of the graphics processor 3010. The graphics processor 3210 includes Figure 31 The one or more MMUs 3120A-3120B, cache(s) 3125A-3125B, and circuit interconnect(s) 3130A-3130B of the integrated circuit 3100.

[0322] The graphics processor 3210 includes one or more shader cores 3215A-3215N (e.g., 3215A, 3215B, 3215C, 3215D, 3215E, 3215F through 3215N-1 and 3215N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary among embodiments and implementations. In addition, the graphics processor 3210 includes an inter-core task manager 3205 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 3215A-3215N and a tiling unit 3218 for accelerating tiling operations for tiling-based rendering, where rendering operations for a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0323] Embodiments of the present invention include a method and system for budgeted and simplified training of deep neural networks (DNNs).

[0324] In one example, a method for a deep neural network (DNN) includes subsampling a training image into a plurality of training sub-images, randomly selecting the plurality of sub-images, and training the DNN using the plurality of randomly selected training sub-images to obtain a training result.

[0325] In one example, a method includes subsampling a test image into a plurality of test sub-images, randomly selecting a first test sub-image, and testing a trained DNN using the randomly selected first test image to obtain a first test result.

[0326] In one example, a method includes randomly selecting a second test sub-image, testing a trained DNN using the randomly selected second test image to obtain a second test result, and combining the first test result and the second test result to select one of the first test result and the second test result as a final result.

[0327] In one example, for one approach, each training sub-image has a smaller resolution than the training image.

[0328] In one example, for one approach, each test sub-image has a smaller resolution than the test image.

[0329] In one example, a system for a server includes a processing core, an I / O controller hub, and a graphics processor. The processing core has a deep neural network (DNN). The I / O controller hub is coupled to the processing core and provides the processing core with network, data storage, and DNN access. The graphics processor is coupled to the I / O controller hub and trains the DNN using multiple training sub-images derived from downsampled training images. The graphics processor also tests the trained DNN using multiple test sub-images derived from downsampled test images.

[0330] In one example, the graphics processor subsamples the test image into a plurality of test sub-images, randomly selects a first test sub-image, and tests the trained DNN using the randomly selected first test image to obtain a first test result.

[0331] In one example, the graphics processor randomly selects a second test sub-image. The graphics processor also tests the trained DNN using the randomly selected second test image to obtain a second test result. The graphics processor also combines the first test result and the second test result to select one of the first test result and the second test result as a final result.

[0332] In one example, for the system, each training sub-image has a smaller resolution than the training image.

[0333] In one example, for the system, each test sub-image has a smaller resolution than the test image.

[0334] In one example, a method for a recursive deep Q-network (RDQN) with a local attention mechanism between a convolutional neural network (CNN) and a long-short-term memory (LSTM) includes generating, by the CNN, a plurality of feature maps from an input image. Applying, by the local attention mechanism, hard attention to the plurality of generated feature maps by selecting a subset of the generated feature maps. Applying, by the local attention mechanism, soft attention to a selected subset of the generated feature maps by assigning weights to the selected subset of the generated feature maps to obtain weighted feature maps. Storing the weighted feature maps in the LSTM. Calculating Q-values for different actions based on the weighted feature maps stored in the LSTM.

[0335] In one example, a method includes determining whether an iteration condition is satisfied. If the iteration condition is satisfied, outputting a final deep Q network.

[0336] In one example, a method includes writing a generated feature map into a hierarchical memory.

[0337] In one example, a method includes reading a selected subset of generated feature maps in a hierarchical memory.

[0338] In one example, a system for a server includes a processing core, an I / O hub controller, and a graphics processor. The processing core has a recursive deep Q-network (RDQN) comprising a convolutional neural network (CNN) and a long-short-term memory (LSTM), wherein a local attention mechanism is located between the CNN and the LSTM, and wherein the CNN and the LSTM serve as input and output modules for the local attention mechanism with both soft and hard attention. The I / O hub controller is coupled to the processing core and provides the processing core with access to the network, data storage, LSTM, RDQN, CNN, and the local attention mechanism. The graphics processor is coupled to the I / O hub controller and processes an input image and multiple feature maps based on the input image. The graphics processor also applies hard attention to the multiple feature maps generated by selecting a subset of the generated feature maps. The graphics processor also applies soft attention to a selected subset of the generated feature maps by assigning weights to the selected subset of the generated feature maps to obtain weighted feature maps. The graphics processor also stores the weighted feature maps in the LSTM. The graphics processor also calculates Q-values for different actions based on the weighted feature maps stored in the LSTM.

[0339] In one example, the graphics processor determines whether an iteration condition is satisfied, and outputs a final deep Q-network if the iteration condition is satisfied.

[0340] In one example, the graphics processor writes the generated feature map into hierarchical memory.

[0341] In one example, the graphics processor reads a selected subset of the generated feature maps in the hierarchical memory.

[0342] The foregoing description and drawings should be regarded in an illustrative rather than a restrictive sense. It will be understood by those skilled in the art that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

Claims

1. A method for a deep neural network (DNN), comprising: Subsampling the training image into multiple training sub-images; dividing the plurality of training sub-images into batches of training sub-images, each batch including one or more of the plurality of training sub-images; as well as The DNN is trained using batches of randomly selected training sub-images, including: Randomly select the first batch of training sub-images; Processing a first batch of randomly selected training sub-images using the DNN; adjusting weights of the DNN based on a classification result determined by processing a first batch of the randomly selected training sub-images; Randomly select the second batch of training sub-images; processing a second batch of randomly selected training sub-images using the DNN; and The weights of the DNN are adjusted based on a second classification result determined by processing a second batch of the randomly selected training sub-images.

2. The method of claim 1, further comprising: Subsampling the test image into multiple test sub-images; Randomly select a first test sub-image; as well as The trained DNN is tested using a randomly selected first test image to obtain a first test result.

3. The method of claim 2, further comprising: Randomly select a second test sub-image; Testing the trained DNN using a randomly selected second test image to obtain a second test result; as well as The first test result and the second test result are combined to select one of the first test result and the second test result as a final result. The method of claim 1 , wherein each training sub-image has a smaller resolution than the training image. The method of claim 2 , wherein each test sub-image has a smaller resolution than the test image.

6. A system for a server, comprising: A processing core having a deep neural network DNN; an I / O controller hub coupled to the processing core and configured to provide network, data storage, and DNN access to the processing core; as well as A graphics processor coupled to the I / O controller hub and configured to The DNN is trained using batches of randomly selected training sub-images, including: Randomly select the first batch of training sub-images; Processing a first batch of randomly selected training sub-images using the DNN; adjusting weights of the DNN based on a classification result determined by processing a first batch of the randomly selected training sub-images; Randomly select the second batch of training sub-images; processing a second batch of randomly selected training sub-images using the DNN; and adjusting weights of the DNN based on a second classification result determined by processing a second batch of the randomly selected training sub-images; and The trained DNN is tested using multiple test sub-images derived from the downsampled test image.

7. The system of claim 6, wherein the graphics processor is configured to Subsample the test image into multiple test sub-images, Randomly select the first test sub-image, and The trained DNN is tested using a randomly selected first test image to obtain a first test result.

8. The system of claim 7, wherein the graphics processor is configured to Randomly select the second test sub-image, The trained DNN is tested using a randomly selected second test image to obtain a second test result, and the first test result and the second test result are combined to select one of the first test result and the second test result as a final result.

9. The system of claim 6, wherein each training sub-image has a smaller resolution than the training image.

10. The system of claim 7, wherein each test sub-image has a smaller resolution than the test image.

11. An apparatus for a deep neural network (DNN), comprising means for performing the steps of the method according to any one of claims 1 to 5.

12. A computer readable medium having stored thereon instructions which, when executed, cause a machine to perform the method according to any one of claims 1 to 5.

13. A computer program product having instructions which, when executed, cause a machine to perform the method according to any one of claims 1 to 5.

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