Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, a package body, and a redistribution layer. The semiconductor die has an active surface, a back surface, and a side surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the side surface of the semiconductor die. The package body covers the shielding layer and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the package body and electrically connected to the semiconductor die via the conductive bumps. The shielding layer is electrically connected to the redistribution layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor package and a method for manufacturing it, and to a semiconductor package comprising a shielding layer disposed on a side surface of a semiconductor die, and a method for manufacturing the semiconductor package. Background Technology

[0002] The package-level shielding process for semiconductor packaging includes: placing a semiconductor die on a substrate; forming an encapsulant on the substrate to cover the semiconductor die; forming a trench through the encapsulant to expose a portion of the redistribution layer (RDL) of the substrate; and then forming a shielding layer to cover the encapsulant and connect a portion of the RDL for grounding purposes. In this process, the trench depth must be precisely controlled to expose the RDL of the substrate. Furthermore, because the shielding layer covers the entire encapsulant, this process has a relatively low production rate. Summary of the Invention

[0003] In some embodiments, a semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, a package body, and a redistribution layer. The semiconductor die has an active surface, a backside surface, and a lateral surface. Conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The package body covers the shielding layer and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the package body and electrically connected to the semiconductor die via the conductive bumps. The shielding layer is electrically connected to the redistribution layer.

[0004] In some embodiments, a method for manufacturing a semiconductor package includes: (a) providing a semiconductor element comprising a plurality of conductive bumps; (b) forming a protective layer to cover the conductive bumps; (c) singulating the protective layer; and (d) forming a shielding layer on a side surface of the protective layer. Attached Figure Description

[0005] Various aspects of some embodiments of this disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0006] Figure 1 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0007] Figure 2 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0008] Figure 3 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0009] Figure 4 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0010] Figure 5 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0011] Figure 6 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0012] Figure 7 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0013] Figure 8 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0014] Figure 9 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0015] Figure 10 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0016] Figure 11 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0017] Figure 12 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0018] Figure 13 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0019] Figure 14 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0020] Figure 15 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0021] Figure 16 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0022] Figure 17 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0023] Figure 18 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0024] Figure 19 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0025] Figure 20 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0026] Figure 21 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0027] Figure 22 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0028] Figure 23 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0029] Figure 24 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0030] Figure 25 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0031] Figure 26 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0032] Figure 27 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0033] Figure 28 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0034] Figure 29 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0035] Figure 30 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0036] Figure 31 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0037] Figure 32 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0038] Figure 33 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0039] Figure 34 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0040] Figure 35 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0041] Figure 36 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0042] Figure 37 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0043] Figure 38 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0044] Figure 39 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0045] Figure 40 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0046] Figure 41 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0047] Figure 42 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0048] Figure 43 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0049] Figure 44 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0050] Figure 45 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0051] Figure 46 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0052] Figure 47 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0053] Figure 48 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0054] Figure 49 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0055] Figure 50 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0056] Figure 51 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0057] Figure 52 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0058] Figure 53 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0059] Figure 54 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0060] Figure 55This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0061] Figure 56 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0062] Figure 57 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0063] Figure 58 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0064] Figure 59 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0065] Figure 60 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0066] Figure 61 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0067] Figure 62 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0068] Figure 63 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0069] Figure 64 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0070] Figure 65 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0071] Figure 66 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0072] Figure 67 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0073] Figure 68 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0074] Figure 69 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0075] Figure 70 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0076] Figure 71 This describes one or more stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure. Detailed Implementation

[0077] Common reference numerals are used throughout the drawings and embodiments to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0078] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, define a relationship between the various embodiments and / or configurations discussed.

[0079] In a package-level shielding process, a semiconductor die is placed on a substrate, and a package is subsequently formed to cover the substrate and the semiconductor die. A sawing process is then performed to form trenches in the package, exposing the redistribution layer of the substrate from the package. Thus, a shielding layer can be formed to cover the package and the semiconductor die, and can be electrically connected to the redistribution layer for electromagnetic shielding purposes.

[0080] However, in the sawing process, the trench depth must be precisely controlled. Insufficiently deep trenches cannot expose the redistribution layer, thus preventing the subsequent shielding layer from grounding. On the other hand, excessively deep trenches can damage the redistribution layer, leading to redistribution failure. In some embodiments, the sawing process can be implemented using a saw blade, making it difficult to precisely control the trench depth. In some embodiments, the sawing process can be implemented using a laser, and a stop layer must be placed in the substrate to stop the laser. Typically, the stop layer is part of the outermost metal layer (i.e., the outermost redistribution layer). However, the thickness of the outermost metal layer can be about 10 μm or less, which may be insufficient to stop the laser. Additionally, the warpage of the substrate can be greater than 3 mm. Therefore, a laser beam with constant energy can create trenches of varying depths. That is, some trenches may not penetrate the package, while others may penetrate the outermost metal layer. Furthermore, since the shielding layer covers the entire package, the surface area of ​​which is larger than that of the semiconductor die, the production efficiency of the above processes is relatively low. Moreover, the shielding layer is formed by sputtering. However, trenches can have an aspect ratio greater than 8 (defined as the ratio of depth to width); therefore, the yield rate of sputtering may be less than 50%.

[0081] This disclosure at least solves the aforementioned problems and provides an improved semiconductor package, as well as improved techniques for manufacturing the semiconductor package. In the semiconductor package, a shielding layer is disposed on the side surface of the semiconductor die. Therefore, the aforementioned sawing process of the package body can be omitted. Since the shielding layer only covers the semiconductor die, the surface area of ​​which is smaller than that of the package body, the production efficiency of the semiconductor package can be improved.

[0082] Figure 1 The diagram illustrates a cross-sectional view of a semiconductor package 1 according to some embodiments of the present disclosure. The semiconductor package 1 includes at least one semiconductor die 2, a plurality of conductive bumps 3, a protection layer 11, a first adhesive layer 12, a shielding layer 4, a package body 5, a redistribution layer 6, an electrical component 17, a plurality of connecting elements 18, a metal layer 13, a supporting layer 14, a second adhesive layer 15, and a heat sink 16.

[0083] The semiconductor die 2 has an active surface 21, a back surface 22 opposite to the active surface 21, and a side surface 23 extending between the active surface 21 and the back surface 22. Figure 1Two semiconductor dies 2 are shown in a semiconductor package 1. However, the semiconductor package 1 may contain fewer than two or more semiconductor dies 2. Furthermore, these semiconductor dies 2 may be the same as or different from each other.

[0084] The conductive bump 3 is disposed on the active surface 21 of the semiconductor die 2 and is electrically connected to the semiconductor die 2. Figure 1 Four conductive bumps 3 are shown on each semiconductor die 2. However, the number of conductive bumps 3 is not limited to this. The conductive bumps 3 can be pillars or posts made of conductive material (e.g., copper). Each of the conductive bumps 3 includes a first end 31 and a second end 32 opposite to the first end 31. The second end 32 is disposed on and in contact with the active surface 21 of the semiconductor die 2. The first ends 31 of these conductive bumps 3 can be coplanar with each other.

[0085] A protective layer 11 is disposed on the active surface 21 of the semiconductor die 2 and covers the conductive bumps 3. For example, the protective layer 11 surrounds and contacts the edge surface of each of the conductive bumps 3. The protective layer 11 has a first surface 111, a second surface 112 opposite to the first surface 111, and a side surface 113 extending between the first surface 111 and the second surface 112. The second surface 112 is disposed on and contacts the active surface 21 of the semiconductor die 2. In some embodiments, the first surface 111 of the protective layer 11 is coplanar with a first end 31 of at least one of the conductive bumps 3. The side surface 113 of the protective layer 11 is coplanar with a side surface 23 of the semiconductor die 2. The material of the protective layer 11 may be selected from a curable photoimageable dielectric (PID) material, such as epoxy resin or polyimide (PI) containing a photoinitiator or other resin materials.

[0086] A first adhesive layer 12 is disposed on the back surface 22 of the semiconductor die 2. The first adhesive layer 12 has a first surface 121, a second surface 122 opposite to the first surface 121, and a side surface 123 extending between the first surface 121 and the second surface 122. The first surface 121 is disposed on and in contact with the back surface 22 of the semiconductor die 2. The side surface 123 of the first adhesive layer 12 is coplanar with the side surface 23 of the semiconductor die 2 and / or the side surface 113 of the protective layer 11. The first adhesive layer 12 may be part of a die attach film (DAF).

[0087] A shielding layer 4 is disposed on and covers the side surface 23 of the semiconductor die 2. In some embodiments, the shielding layer 4 is also disposed on and covers the side surface 113 of the protective layer 11 and / or the side surface 123 of the first adhesive layer 12. The shielding layer 4 has a first end 41, a second end 42, an inner surface 43, and an outer surface 44. The second end 42 is opposite to the first end 41. The inner surface 43 and the outer surface 44 extend between the first end 41 and the second end 42. The outer surface 44 is opposite to the inner surface 43. For example, the inner surface 43 of the shielding layer 4 contacts the side surface 23 of the semiconductor die 2, the side surface 113 of the protective layer 11, and / or the side surface 123 of the first adhesive layer 12. In some embodiments, the first end 41 of the shielding layer 4 is coplanar with the first end 31 of at least one of the first surface 111 of the protective layer 11 and / or the conductive bump 3. The second end 42 of the shielding layer 4 is coplanar with the second surface 122 of the first adhesive layer 12. The shielding layer 4 may be made of a conductive material (e.g., copper, stainless steel, or titanium) and may be formed by sputtering. The shielding layer 4 provides electromagnetic shielding to the side surface 23 of the semiconductor die 2.

[0088] The package 5 covers the shielding layer 4. For example, the package 5 surrounds and contacts the outer surface 44 of the shielding layer 4. The package 5 has a first surface 51 and a second surface 52 opposite to the first surface 51. The first surface 51 of the package 5 is coplanar with the first end 31 of at least one of the conductive bumps 3, the first surface 111 of the protective layer 11, and / or the first end 41 of the shielding layer 4. The second surface 52 of the package 5 is coplanar with the second surface 122 of the first adhesive layer 12 and / or the second end 42 of the shielding layer 4. The material of the package 5 may be an encapsulation compound with or without fillers.

[0089] The redistribution layer 6 is disposed on the first surface 51 of the package 5. The redistribution layer 6 may include at least one conductive layer containing traces and pads, and may further include at least one via for connection purposes. The line width / line space (L / S) of the redistribution layer 6 may be approximately 2 μm / 2 μm. For example, Figure 1 The redistribution layer 6 comprises three conductive layers 61, 62, and 63, which are electrically connected to each other through a plurality of vias. The redistribution layer 6 may further include an insulating structure 64 disposed between these conductive layers 61, 62, and 63. The redistribution layer 6 is electrically connected to the semiconductor die 2 via conductive bumps 3. For example, at least one of the conductive bumps 3 contacts the topmost conductive layer 61 of the redistribution layer 6. The redistribution layer 6 is also electrically connected to a shielding layer 4. Figure 1As shown, the first end 41 of the shielding layer 4 is in contact with the topmost conductive layer 61 of the re-fabricated layer 6.

[0090] Electrical component 17 and multiple connecting elements 18 are electrically connected to the redistribution layer 6, for example, to the bottom conductive layer 63 of the redistribution layer 6. Electrical component 17 can be a passive component, another semiconductor die, or an interposer. For example, such as... Figure 1 As shown, electrical component 17 is a bridge connector that includes internal circuitry 172 for electrically connecting two semiconductor dies 2. Electrical component 17 may further include a plurality of solders 173 for electrical connection to the redundancy layer 6, and an underfill 174 filling the space between electrical component 17 and redundancy layer 6. Connecting element 18 may be a solder bump electrically connected to the bottommost conductive layer 63 of redundancy layer 6 for external connection purposes.

[0091] like Figure 1 As shown, a metal layer 13, a support layer 14, a second adhesive layer 15, and a heat sink 16 are sequentially disposed on the second surface 52 of the package 5. The metal layer 13 may be made of a conductive metal (e.g., copper). For example, the support layer 14 may be a carrier made of silicon, metal, or glass, and the metal layer 13 may be a copper film or copper foil disposed on the carrier. The metal layer 13 provides electromagnetic shielding to the back surface 22 of the semiconductor die 2. The support layer 14 can balance the warpage caused by the insulating structure 64 of the redistribution layer 6 and / or the package 5. The heat sink 16 is disposed adjacent to the second surface 52 of the package 5 for heat dissipation and / or warpage balancing purposes. For example, the heat sink 16 is attached to the support layer 14 via the second adhesive layer 15. The heat sink 16 may be made of a conductive material (e.g., copper or stainless steel). The material of the second adhesive layer 15 can be any adhesive that can attach the heat sink 16 to the support layer 14, and can be the same as or different from the material of the first adhesive layer 12.

[0092] In semiconductor package 1, shielding layer 4 and metal layer 13 together provide electromagnetic shielding for semiconductor die 2. Since shielding layer 4 is formed on and covers semiconductor die 2, rather than on package body 5, the sawing process for forming trenches on the package body, as described in the package-level shielding process above, can be omitted. Furthermore, since the surface area of ​​semiconductor die 2 is much smaller than that of package body 5, the production efficiency of semiconductor package 1 is greater than that of the aforementioned package-level shielding process.

[0093] Figure 2A cross-sectional view of a semiconductor package 1a according to some embodiments of the present disclosure is illustrated. The semiconductor package 1a is similar to... Figure 1 The semiconductor package 1 shown in the figure omits the first adhesive layer 12, the metal layer 13 and the support layer 14 in the semiconductor package 1a, and the shielding layer 4a of the semiconductor package 1a further covers the back surface 22 of the semiconductor die 2.

[0094] like Figure 2 As shown, the shielding layer 4a includes a sidewall 45 and a top wall 46. The sidewall 45 has a first end 41, a second end 42, an inner surface 43, and an outer surface 44, similar to... Figure 1 The shielding layer 4 shown in the diagram. Sidewalls 45 are disposed on and cover the semiconductor die 2 and / or the protective layer 11. For example, the inner surface 43 faces and contacts the side surface 23 of the semiconductor and / or the side surface 113 of the protective layer 11. The first end 41 of the sidewall 45 of the shielding layer 4a is coplanar with the first end 31 of at least one of the first surface 111 of the protective layer 11 and / or the conductive bump 3. The top wall 46 is connected to the second end 42 of the sidewall 45. The top wall 46 is disposed on and contacts the back surface 22 of the semiconductor die 2. In some embodiments, the sidewalls 45 and the top wall 46 are formed concurrently and integrally. Therefore, there is no boundary between the sidewalls 45 and the top wall 46. In addition, the second surface 52 of the package 5 is coplanar with the top surface of the top wall 46 of the shielding layer 4a.

[0095] like Figure 2 As shown, since the metal layer 13 and the support layer 14 are omitted, the second adhesive layer 15 is disposed on and in contact with the second surface 52 of the package 5 and / or the top wall 46 of the shielding layer 46. The heat sink 16 is disposed adjacent to the second surface 52 of the package 5 and is attached to the package 5 by means of the second adhesive layer 15.

[0096] exist Figure 2 In the semiconductor package 1a shown, the sidewall 45 and topwall 46 of the shielding layer 4a provide electromagnetic shielding for the side surface 23 and back surface 22 of the semiconductor die 2, respectively.

[0097] Figure 3 This illustration shows a cross-sectional view of a semiconductor package 1b according to some embodiments of the present disclosure. The semiconductor package 1b is similar to... Figure 2 The semiconductor package 1a shown in the figure has the following features: the side surface 113b of the protective layer 11b in the semiconductor package 1b is not coplanar with the side surface 23 of the semiconductor die 2, and the sidewall 45 of the shielding layer 4b of the semiconductor package 1b further includes a first portion 451 and a second portion 452.

[0098] like Figure 3 As shown, the protective layer 11b covers the active surface 21 of the semiconductor die 2 and further covers a portion of the side surface 23 of the semiconductor die 2. Therefore, the side surface 113b of the protective layer 11b is not coplanar with the side surface 23 of the semiconductor die 2. The surface area of ​​the first surface 111 of the protective layer 11b is larger than the surface area of ​​the active surface 21 of the semiconductor die 2.

[0099] like Figure 3 As shown, the sidewall 45 of the shielding layer 4b includes a first portion 451 and a second portion 452. The first portion 451 includes a first end 41, and the second portion 452 includes a second end 42. The first portion 451 is disposed on and in contact with the side surface 113b of the protective layer 11b. The second portion 452 is disposed on and in contact with the side surface 23 of the semiconductor die 2. The area defined by the first portion 451 in the bottom view is larger than the area defined by the second portion 452 in the bottom view.

[0100] Figure 4 This illustration shows a cross-sectional view of a semiconductor package 1c according to some embodiments of the present disclosure. The semiconductor package 1c is similar to... Figure 2 The semiconductor package 1a shown in the diagram, except that the material of the protective layer 11 in the semiconductor package 1c is the same as the material of the package body 5, and the protective layer 11 and the package body 5 can be formed simultaneously. That is, in Figure 4 In the semiconductor package 1c shown, the protective layer 11 is part of the package body 5. In other words, the package body 5 is further disposed on the active surface 21 of the semiconductor die 2 and covers the conductive bumps 3.

[0101] Since the package 5 is further disposed on the active surface 21 of the semiconductor die 2 and surrounds the conductive bumps 3, the reliability of the semiconductor package 1c is improved.

[0102] Figure 5 This illustration shows a cross-sectional view of a semiconductor package 1d according to some embodiments of the present disclosure. The semiconductor package 1d is similar to... Figure 3 The semiconductor package 1b shown in the diagram has the following characteristics: the material of the protective layer 11b in the semiconductor package 1d is the same as that of the package body 5, and the protective layer 11b and the package body 5 can be formed simultaneously. That is, in... Figure 5 In the semiconductor package 1d shown, the protective layer 11b is part of the package body 5. In other words, the package body 5 is further disposed on the active surface 21 of the semiconductor die 2 and covers the conductive bumps 3.

[0103] Figures 6 to 19 This invention describes methods for manufacturing semiconductor packages according to some embodiments of the present disclosure. In some embodiments, the method is used for manufacturing semiconductor packages, for example... Figure 1 Semiconductor package 1 shown in the image.

[0104] See Figure 6 The device provides a semiconductor element, such as a wafer 70. The wafer 70 has a first surface 71 and a second surface 72 opposite to the first surface 71. The wafer 70 includes a plurality of conductive bumps 3 disposed on the first surface 71. The conductive bumps 3 may be posts or pillars made of a conductive material (e.g., copper). Each of the conductive bumps 3 includes a first end 31 and a second end 32 opposite to the first end 31. The second end 32 is disposed on and in contact with the first surface 71 of the wafer 70. In subsequent steps, the wafer 70 may be separated into a plurality of semiconductor dies 4. Figure 9 ).

[0105] See Figure 7 The second surface 72 of the wafer 70 is attached to the die bonding film 73. Subsequently, a protective layer 11 is formed on the first surface 71 of the wafer 70 to cover the conductive bumps 3. The protective layer 11 may be made of a cured PID material, such as epoxy resin or polyimide or other resin materials containing a photoinitiator. Figure 7 As shown, the first end 31 of each of the conductive bumps 3 is embedded in the protective layer 11. However, in other embodiments, the first end 31 of the conductive bump 3 may be exposed from the protective layer 11. Subsequently, the protective layer 11 is cured.

[0106] See Figure 8 A single-layer protective layer 11 is formed. For example, multiple grooves 75 are formed on and through the protective layer 11 using, for example, laser grooving technology. The protective layer 11 is divided into multiple individual protective layers 11 by the grooves 75. The protective layer 11 covers the conductive bumps 3, for example, surrounds and contacts each of the conductive bumps 3. The protective layer 11 has a first surface 111, a second surface 112 opposite to the first surface 111, and a side surface 113 extending between the first surface 111 and the second surface 112. The second surface 112 is disposed on and contacts the first surface 71 of the wafer 7. In some embodiments, laser grooving technology may also remove portions of the wafer 7 corresponding to the grooves 75.

[0107] See Figure 9A wafer 70 and a die bonding film 73 are placed on a dicing tape 76. The dicing tape 76 can be pressure-sensitive or UV-releasing. Next, semiconductor devices (e.g., wafer 70) are monomerized. For example, the wafer 70 is sawn into multiple semiconductor dies 2 along a groove 75. A first surface 71 and a second surface 72 of the wafer 70 respectively form an active surface 21 and a back surface 22 for each semiconductor die 2. The active surface 21 is opposite to the back surface 22. Each of the semiconductor dies 2 further has a side surface 23 exposed after the monomerization process. The side surface 23 extends between the active surface 21 and the back surface 22. The side surface 23 of the semiconductor die 2 may be coplanar with the side surface 113 of the protective layer 11. In some embodiments, the sawing process may further saw through the die bonding film 73 and form a groove 77 on the dicing tape 76. Thus, the die bonding film 73 is divided into a plurality of individual first adhesive layers 12 on the back surface 22 of the semiconductor die 2. Each first adhesive layer 12 has a first surface 121, a second surface 122 opposite to the first surface 121, and a side surface 123 extending between the first surface 121 and the second surface 122. The first surface 121 is disposed on and in contact with the back surface 22 of the semiconductor die 2. The side surface 123 of the first adhesive layer 12 is coplanar with the side surface 23 of the semiconductor die 2 and / or the side surface 113 of the protective layer 11.

[0108] See Figure 10 A shielding layer 4 is formed on the side surface 113 of the protective layer 11. In some embodiments, the shielding layer 4 is further formed on the side surface 23 of each of the semiconductor dies 2. The shielding layer 4 covers and contacts the semiconductor die 2 and the protective layer 11. The shielding layer 4 may be made of a conductive material (e.g., copper, stainless steel, or titanium) and may be formed by sputtering. In some embodiments, the shielding layer 4 may further cover and contact the side surface 123 of the first adhesive layer 12 and may extend into the groove 77 of the dicing strip 76. Figure 10 As shown, the trench defined by the side surface 113 of the protective layer 11, the side surface 23 of the semiconductor die 2, and the side surface 123 of the first adhesive layer 12 can have an aspect ratio (defined as the ratio of depth to width) of less than 8; therefore, the yield of sputtering the shielding layer 4 can be relatively high, for example, above 50%, 60%, or 70%. After forming the shielding layer 4, each of the semiconductor dies 2 is picked up from the dicing tape 76 to form a trench as shown in the figure. Figure 11 Semiconductor unit 78 is shown in the image.

[0109] See Figure 12A support layer 14 is provided, on which a metal layer 13 is disposed. The support layer 14 may be a carrier and may be made of silicon, metal, or glass. The metal layer 13 may be made of a conductive metal (e.g., copper). For example, the metal layer 13 may be a copper film or copper foil disposed on a carrier.

[0110] See Figure 13 ,Will Figure 11 The semiconductor unit 78 shown is disposed on the metal layer 13. The semiconductor unit 78 includes a semiconductor die 2, conductive bumps 3, a protective layer 11, a first adhesive layer 12, and a shielding layer 4. Figure 14 Two similar semiconductor cells 78 are shown. However, more or fewer semiconductor cells 78 may be placed on the metal layer 13, and they may be the same or different from each other. The back surface 22 of the semiconductor die 2 is attached to the metal layer 13 via a first adhesive layer 12.

[0111] See Figure 14 A package 5 is formed or disposed on a metal layer 13 to cover a semiconductor cell 78, the semiconductor cell 78 comprising a semiconductor element (e.g., a semiconductor die 2), conductive bumps 3, a protective layer 11, a first adhesive layer 12, and a shielding layer 4. The package 5 may be formed by a molding process. The material of the package 5 may be an encapsulation compound with or without fillers.

[0112] See Figure 15A grinding process is performed to remove a portion of the package 5, a portion of the shielding layer 4, and a portion of the protective layer 11. In some embodiments, the grinding process may further remove a portion of at least one of the conductive bumps 3. Therefore, a first end 31 of each of the conductive bumps 3 may be exposed from the protective layer 11, and a portion of the shielding layer 4 may also be exposed to form a first end 41 of the shielding layer 4. The first end 41 of the shielding layer 4 is thus coplanar with the first surface 111 of the protective layer 11 and / or the first end 31 of at least one of the conductive bumps 3. The shielding layer 4 further has a second end 42, an inner surface 43, and an outer surface 44. The second end 42 is opposite to the first end 41. The inner surface 43 and the outer surface 44 extend between the first end 41 and the second end 42. The outer surface 44 is opposite to the inner surface 43. For example, the inner surface 43 of the shielding layer 4 contacts the side surface 23 of the semiconductor die 2, the side surface 113 of the protective layer 11, and / or the side surface 123 of the first adhesive layer 12. The second end 42 of the shielding layer 4 is coplanar with the second surface 122 of the first adhesive layer 12. The shielding layer 4 provides electromagnetic shielding to the side surface 23 of the semiconductor die 2. The package 5 has a first surface 51 and a second surface 52 opposite to the first surface 51. The first surface 51 of the package 5 is coplanar with the first end 31 of at least one of the conductive bumps 3, the first surface 111 of the protective layer 11, and / or the first end 41 of the shielding layer 4. The second surface 52 of the package 5 is coplanar with the second surface 122 of the first adhesive layer 12 and / or the second end 42 of the shielding layer 4.

[0113] See Figure 16 A redistribution layer 6 is formed or disposed on the first surface 51 of the package 5. The redistribution layer 6 may include at least one conductive layer containing traces and pads, and may further include at least one via for connection between the conductive layers. The linewidth / spacing (L / S) of the redistribution layer 6 may be approximately 2 μm / 2 μm. For example, such as... Figure 16 As shown, the redistribution layer 6 comprises three conductive layers 61, 62, and 63, which are electrically connected to each other through a plurality of vias. The redistribution layer 6 may further include an insulating structure 64 disposed between these conductive layers 61, 62, and 63. The redistribution layer 6 is electrically connected to the semiconductor die 2 via conductive bumps 3. For example, at least one of the conductive bumps 3 contacts the topmost conductive layer 61 of the redistribution layer 6. The redistribution layer 6 is also electrically connected to a shielding layer 4. Figure 16 As shown, the first end 41 of the shielding layer 4 is in contact with the topmost conductive layer 61 of the re-fabricated layer 6.

[0114] See Figure 17 Electrical component 17 and multiple connecting elements 18 are disposed on and electrically connected to the redistribution layer 6. Electrical component 17 may be a passive component or another semiconductor die or insert. For example, such as... Figure 17 As shown, electrical component 17 is a bridge that includes internal circuitry 172 for electrically connecting two semiconductor dies 2. Electrical component 17 may further include a plurality of solders 173 for electrically connecting to the bottom conductive layer 63 of the overlay layer 6. Connecting element 18 may be electrically connected to the bottom conductive layer 63 of the overlay layer 6 for external connection purposes.

[0115] See Figure 18 A base adhesive 174 is placed between the electrical component 17 and the re-woven layer 6, and covers the solder 173.

[0116] See Figure 19 The heat sink 16 is attached to the support layer 14 via the second adhesive layer 15 for heat dissipation. That is, the heat sink 16 is placed on the second surface 52 adjacent to the package 5. The material of the second adhesive layer 15 can be any adhesive capable of attaching the heat sink 16 to the support layer 14, and can be the same as or different from the material of the first adhesive layer 12. Next, a sawing process is performed to cut the heat sink 16, the second adhesive layer 15, the support layer 14, the metal layer 13, the package 5, and the reel layer 6, thereby forming a structure as shown in the image. Figure 1 The semiconductor package 1 shown in the figure.

[0117] In the aforementioned method, the shielding layer 4 is formed before the package 5 is formed. Therefore, the shielding layer 4 can cover and contact the semiconductor die 2. Since the surface area of ​​the semiconductor die 2 is much smaller than the surface area of ​​the package 5, the production efficiency of the semiconductor package 1 is greater than that of the aforementioned package-level shielding process. Furthermore, the presence of the support layer 14 can prevent warping during the formation of the package 5 and / or the redistribution layer 6.

[0118] Figures 20 to 34 This invention describes methods for manufacturing semiconductor packages according to some embodiments of the present disclosure. In some embodiments, the method is used for manufacturing semiconductor packages, for example... Figure 2 Semiconductor package 1a is shown in the image.

[0119] See Figure 20 The device provides a semiconductor element, such as a wafer 70. The wafer 70 has a first surface 71 and a second surface 72 opposite to the first surface 71. The wafer 70 includes a plurality of conductive bumps 3 disposed on the first surface 71. The conductive bumps 3 may be posts or pillars made of a conductive material (e.g., copper). Each of the conductive bumps 3 includes a first end 31 and a second end 32 opposite to the first end 31. The second end 32 is disposed on and in contact with the first surface 71 of the wafer 70. In a subsequent step, the wafer 70 may be separated into a plurality of semiconductor dies.

[0120] See Figure 21A protective layer 11 is formed on the first surface 71 of the wafer 70 to cover the conductive bumps 3. The protective layer 11 may be made of a cured PID material, such as epoxy resin or polyimide or other resin materials containing a photoinitiator. Figure 21 As shown, the first end 31 of each of the conductive bumps 3 is embedded in the protective layer 11. However, in other embodiments, the first end 31 of the conductive bump 3 may be exposed from the protective layer 11. The protective layer 11 is then cured.

[0121] See Figure 22 A single-layer protective layer 11 is formed, for example, by laser grooving, into and through the protective layer 11. The protective layer 11 is divided into multiple individual protective layers 11 by the grooves 75. The protective layer 11 covers, for example, the conductive bumps 3, surrounding and contacting each of the conductive bumps 3. The protective layer 11 has a first surface 111, a second surface 112 opposite to the first surface 111, and a side surface 113 extending between the first surface 111 and the second surface 112. The second surface 112 is disposed on and in contact with the first surface 71 of the wafer 7.

[0122] See Figure 23 The wafer 70 and the protective layer 11 are disposed on the dicing tape 80, wherein the first surface 111 of the protective layer 11 contacts and is attached to the dicing tape 80. It should be noted that the dicing tape 80 is fixed in a frame.

[0123] See Figure 24 The semiconductor device (e.g., wafer 70) is monomerized. For example, wafer 70 is sawn into a plurality of semiconductor dies 2 along positions corresponding to recesses 75. A first surface 71 and a second surface 72 of wafer 70 form an active surface 21 and a back surface 22 for each semiconductor die 2, respectively. The active surface 21 is opposite to the back surface 22. Each of the semiconductor dies 2 further has a side surface 23 exposed after the monomerization process. The side surface 23 extends between the active surface 21 and the back surface 22. The side surface 23 of the semiconductor die 2 may be coplanar with the side surface 113 of the protective layer 11.

[0124] See Figure 25A shielding layer 4a is formed on the side surface 113 of the protective layer 11. In some embodiments, the shielding layer 4a is further formed on the side surface 23 and back surface 22 of each of the semiconductor dies 2. The shielding layer 4a covers the semiconductor die 2. The shielding layer 4a may be made of a conductive material (e.g., copper, stainless steel, or titanium) and may be formed by sputtering. The shielding layer 4a includes a sidewall 45 and a top wall 46. The sidewall 45 is disposed on and in contact with the side surface 23 and / or the side surface 113 of the protective layer 11 of the semiconductor die 2. The top wall 46 is disposed on and in contact with the back surface 22 of the semiconductor die 2. Then, each of the semiconductor dies 2 is picked up from the dicing tape 80, forming as shown in the figure. Figure 26 Semiconductor unit 78a shown in the figure.

[0125] See Figure 27 A carrier 81 is provided, on which a thermal release tape 82 is provided. The carrier 81 may be made of silicon, metal or glass, and may be the same as or different from the support layer 14 described above.

[0126] See Figure 28 ,Will Figure 26 The semiconductor unit 78a shown is mounted on a heat release strip 82. The semiconductor unit 78a includes a semiconductor die 2, conductive bumps 3, a protective layer 11, and a shielding layer 4a. Figure 28 Two similar semiconductor units 78a are shown. However, more or fewer semiconductor units 78a may be placed on the heat release band 82, and they may be the same or different from each other. The top wall 46 of the shielding layer 4a is attached to the heat release band 82.

[0127] See Figure 29 A package 5 is formed or disposed on a heat-release band 82 to cover a semiconductor cell 78a, the semiconductor cell 78a comprising a semiconductor element (e.g., a semiconductor die 2), conductive bumps 3, a protective layer 11, and a shielding layer 4a. The package 5 may be formed by a molding process. The material of the package 5 may be an encapsulation compound with or without fillers.

[0128] See Figure 30A polishing process is performed to remove a portion of the package 5, a portion of the shielding layer 4a, and a portion of the protective layer 11. In some embodiments, the polishing process may further remove a portion of at least one of the conductive bumps 3. Thus, a first end 31 of each of the conductive bumps 3 may be exposed from the protective layer 11, and a first end 41 of the sidewall 45 of the shielding layer 4a is formed to be coplanar with the first end 31 of the conductive bump 3. The first end 41 of the sidewall 45 of the shielding layer 4a is further coplanar with the first surface 111 of the protective layer 11. The sidewall 45 of the shielding layer 4a further has a second end 42, an inner surface 43, and an outer surface 44. The second end 42 is opposite to the first end 41. A top wall 46 is connected to the second end 42 of the sidewall 45. The inner surface 43 and the outer surface 44 extend between the first end 41 and the second end 42. The outer surface 44 is opposite to the inner surface 43. For example, the inner surface 43 of the sidewall 45 of the shielding layer 4a contacts the side surface 23 of the semiconductor die 2 and / or the side surface 113 of the protective layer 11. The shielding layer 4a provides electromagnetic shielding for the back surface 22 and side surface 23 of the semiconductor die 2. The package 5 has a first surface 51 and a second surface 52 opposite to the first surface 51. The first surface 51 of the package 5 is coplanar with the first end 31 of at least one of the conductive bumps 3, the first surface 111 of the protective layer 11, and / or the first end 41 of the sidewall 45 of the shielding layer 4a. The second surface 52 of the package 5 is coplanar with the second end 42 of the sidewall 45 of the shielding layer 4a and the top surface of the top wall 46 of the shielding layer 4a.

[0129] See Figure 31 A redistribution layer 6 is formed or disposed on the first surface 51 of the package 5. The redistribution layer 6 may include at least one conductive layer containing traces and pads, and may further include at least one via for connection between the conductive layers. The linewidth / spacing (L / S) of the redistribution layer 6 may be approximately 2 μm / 2 μm. For example, such as... Figure 31 As shown, the redistribution layer 6 comprises three conductive layers 61, 62, and 63, which are electrically connected to each other through a plurality of vias. The redistribution layer 6 may further include an insulating structure 64 disposed between these conductive layers 61, 62, and 63. The redistribution layer 6 is electrically connected to the semiconductor die 2 via conductive bumps 3. For example, at least one of the conductive bumps 3 contacts the topmost conductive layer 61 of the redistribution layer 6. The redistribution layer 6 is also electrically connected to a shielding layer 4a. Figure 31 As shown, the first end 41 of the sidewall 45 of the shielding layer 4a is in contact with the topmost conductive layer 61 of the re-fabricated layer 6.

[0130] See Figure 32 Electrical component 17 and multiple connecting elements 18 are disposed on and electrically connected to the redistribution layer 6. Electrical component 17 may be a passive component, another semiconductor die, or an insert. For example, such as... Figure 32As shown, electrical component 17 is a bridge that includes internal circuitry 172 for electrically connecting two semiconductor dies 2. Electrical component 17 may further include a plurality of solders 173 for electrically connecting to the bottom conductive layer 63 of the overlay layer 6. Connecting element 18 may be electrically connected to the bottom conductive layer 63 of the overlay layer 6 for external connection purposes.

[0131] See Figure 33 A base adhesive 174 is placed between the electrical component 17 and the re-woven layer 6, and covers the solder 173.

[0132] See Figure 34 The carrier 81 and heat release strip 82 are removed by exposing them to a heat source or UV source. Next, the heat sink 16 is attached to the second surface 52 of the package 5 via the second adhesive layer 15 for heat dissipation purposes. That is, the heat sink 16 is placed adjacent to the second surface 52 of the package 5. The material of the second adhesive layer 15 can be any adhesive capable of attaching the heat sink 16 to the second surface 52 of the package 5. Then, a sawing process is performed to cut the heat sink 16, the second adhesive layer 15, the package 5, and the reel layer 6, thereby forming a structure as shown in the image. Figure 2 The semiconductor package 1a shown in the figure.

[0133] In the aforementioned method, since the shielding layer 4a covers the back surface 22 and side surface 23 of the semiconductor die 2, the metal layer 13 can be omitted, and the carrier 81 can be removed. Therefore, Figure 2 The total thickness of the semiconductor package 1a shown in the image is less than [missing information]. Figure 1 The total thickness of semiconductor package 1 shown in the figure.

[0134] Figures 35 to 50 This invention describes methods for manufacturing semiconductor packages according to some embodiments of the present disclosure. In some embodiments, the method is used for manufacturing semiconductor packages, for example... Figure 3 Semiconductor package 1b is shown in the image.

[0135] See Figure 35 A carrier 83 is provided, on which a release membrane 84 is disposed. The carrier 83 and the release membrane 84 can interact with... Figure 27 The carrier 81 and the heat release band 82 shown in the image may be the same or different.

[0136] See Figure 36 A protective material 74 is coated onto the release membrane 84. The protective material 74 may be selected from PID materials, such as epoxy resin or polyimide or other resin materials containing a photoinitiator, and is not yet cured. See [link / reference] Figure 37A semiconductor element, such as one or more semiconductor dies 2, is provided. Each of the semiconductor dies 2 has an active surface 21, a back surface 22 opposite to the active surface 21, and a side surface 23 extending between the active surface 21 and the back surface 22. Each of the semiconductor dies 2 includes a plurality of conductive bumps 3 disposed on the active surface 21. The conductive bumps 3 may be posts or pillars made of a conductive material (e.g., copper). Each of the conductive bumps 3 includes a first end 31 and a second end 32 opposite to the first end 31. The second end 32 is disposed on and in contact with the active surface 21 of the semiconductor die 2. These semiconductor dies 2 may be the same or different from each other. The semiconductor dies 2 are then disposed on a protective material 74, wherein the conductive bumps 3 penetrate and are embedded in the protective material 74. Thus, the protective material 74 forms a protective layer 11b on the active surface 21 of the semiconductor die 2. The protective layer 11b covers and surrounds each of the conductive bumps 3 and may further cover a portion of the semiconductor die 2. For example, such as Figure 37 As shown, the protective layer 11b contacts a portion of the active surface 21 and the side surface 23 of the semiconductor die 2. Subsequently, the protective layer 11b can be cured.

[0137] See Figure 38 A single-layer protective layer 11b is formed. For example, a plurality of grooves 75 are formed on and through the protective layer 11 by means of, for example, laser grooving. The grooves 75 are formed between two adjacent semiconductor dies 2. The protective layer 11b is divided into a plurality of individual protective layers 11b by the grooves 75. The protective layer 11 has a first surface 111, a second surface 112 opposite to the first surface 111, and a side surface 113 extending between the first surface 111 and the second surface 112. The second surface 112 is disposed on and in contact with the active surface 21 of the semiconductor die 2. The first surface 112 of the protective layer 11 is coplanar with the second end 32 of at least one of the conductive bumps 3. The protective layer 11b further covers a portion of the side surface 23 of the semiconductor die 2. The side surface 113b of the protective layer 11b is not coplanar with the side surface 23 of the semiconductor die 2. The surface area of ​​the first surface 111 of the protective layer 11b is larger than the surface area of ​​the active surface 21 of the semiconductor die 2.

[0138] See Figure 39A shielding layer 4b is formed on the side surface 113 of the protective layer 11. In some embodiments, the shielding layer 4b is further formed on the side surface 23 and back surface 22 of each of the semiconductor dies 2. The shielding layer 4b covers the semiconductor die 2. The shielding layer 4b may be made of a conductive material (e.g., copper, stainless steel, or titanium) and may be formed by sputtering. The shielding layer 4a includes a sidewall 45 and a top wall 46. The sidewall 45 includes a first portion 451 and a second portion 452. The first portion 451 is disposed on and in contact with the side surface 113 of the protective layer 11. The second portion 452 is disposed on and in contact with the side surface 23 of the semiconductor die 2. The area defined by the first portion 451 in the bottom view is larger than the area defined by the second portion 452 in the bottom view. The top wall 46 is disposed on and in contact with the back surface 22 of the semiconductor die 2.

[0139] See Figure 40 The dicing tape 76 is attached to the back surface 22 of the semiconductor die 2. The dicing tape 76 can be pressure-sensitive or UV-release type.

[0140] See Figure 41 The carrier 83 and release film 84 are removed. Next, each of the semiconductor dies 2 is picked up from the dicing tape 85, forming as shown... Figure 42 The semiconductor cell 78b shown is an example. In this type of semiconductor cell 78b, the sidewall 45 of the shielding layer 4b has a first end 41 contained in a first portion 451 of the sidewall 45 and a second end 42 contained in a second portion 452 of the sidewall 45. The second end 42 is opposite to the first end 41. The first end 41 is coplanar with the first end 31 of at least one of the conductive bumps 3 and / or the first surface 111 of the protective layer 11b. The top wall 46 is connected to the second end 42 of the sidewall 45.

[0141] See Figure 43 A carrier 81 is provided, on which a heat release band 82 is provided. The carrier 81 may be made of silicon, metal or glass, and may be the same as or different from the support layer 14 described above.

[0142] See Figure 44 ,Will Figure 42 The semiconductor unit 78b shown is mounted on a heat release strip 82. The semiconductor unit 78b includes a semiconductor element (e.g., a semiconductor die 2), conductive bumps 3, a protective layer 11b, and a shielding layer 4b. Figure 44 Two similar semiconductor units 78b are shown. However, more or fewer semiconductor units 78b may be placed on the heat release band 82, and they may be the same or different from each other. The top wall 46 of the shielding layer 4b is attached to the heat release band 82.

[0143] See Figure 45Package 5 is formed or disposed on heat release tape 82 to cover semiconductor cell 78b, which includes semiconductor element (e.g., semiconductor die 2), conductive bumps 3, protective layer 11b, and shielding layer 4b. Package 5 can be formed by molding process. The material of package 5 can be an encapsulation compound with or without filler.

[0144] See Figure 46 A polishing process is performed to remove a portion of the package 5. In some embodiments, the polishing process may further remove a portion of at least one of the conductive bumps 3, a portion of the shielding layer 4b, and / or a portion of the protective layer 11b. A first end 31 of each of the conductive bumps 3 is exposed from the protective layer 11b, and a first end 41 of the sidewall 45 of the shielding layer 4b is coplanar with the first end 31 of the conductive bump 3. The first end 41 of the sidewall 45 of the shielding layer 4b is further coplanar with the first surface 111 of the protective layer 11b. The sidewall 45 of the shielding layer 4b further has an inner surface 43 and an outer surface 44. The inner surface 43 and the outer surface 44 extend between the first end 41 and the second end 42. The outer surface 44 is opposite to the inner surface 43. For example, the inner surface 43 of the first portion 451 of the sidewall 45 contacts the side surface 113b of the protective layer 11b, and the inner surface 43 of the second portion 452 of the sidewall 45 contacts the side surface 23 of the semiconductor die 2. The shielding layer 4b provides electromagnetic shielding for the back surface 22 and side surface 23 of the semiconductor die 2. The package 5 has a first surface 51 and a second surface 52 opposite to the first surface 51. The first surface 51 of the package 5 is coplanar with the first end 31 of at least one of the conductive bumps 3, the first surface 111 of the protective layer 11b, and / or the first end 41 of the sidewall 45 of the shielding layer 4b. The second surface 52 of the package 5 is coplanar with the second end 42 of the sidewall 45 of the shielding layer 4b and the top surface of the top wall 46 of the shielding layer 4b.

[0145] See Figure 47 A redistribution layer 6 is formed or disposed on the first surface 51 of the package 5. The redistribution layer 6 may include at least one conductive layer containing traces and pads, and may further include at least one via for connection between the conductive layers. The linewidth / spacing (L / S) of the redistribution layer 6 may be approximately 2 μm / 2 μm. For example, such as... Figure 47 As shown, the redistribution layer 6 comprises three conductive layers 61, 62, and 63, which are electrically connected to each other through a plurality of vias. The redistribution layer 6 may further include an insulating structure 64 disposed between these conductive layers 61, 62, and 63. The redistribution layer 6 is electrically connected to the semiconductor die 2 via conductive bumps 3. For example, at least one of the conductive bumps 3 contacts the topmost conductive layer 61 of the redistribution layer 6. The redistribution layer 6 is also electrically connected to a shielding layer 4b. Figure 47As shown, the first end 41 of the sidewall 45 of the shielding layer 4b is in contact with the topmost conductive layer 61 of the re-fabricated layer 6.

[0146] See Figure 48 Electrical component 17 and multiple connecting elements 18 are disposed on and electrically connected to the redistribution layer 6. Electrical component 17 may be a passive component, another semiconductor die, or an insert. For example, such as... Figure 48 As shown, electrical component 17 is a bridge that includes internal circuitry 172 for electrically connecting two semiconductor dies 2. Electrical component 17 may further include a plurality of solders 173 for electrically connecting to the bottom conductive layer 63 of the overlay layer 6. Connecting element 18 may be electrically connected to the bottom conductive layer 63 of the overlay layer 6 for external connection purposes.

[0147] See Figure 49 A base adhesive 174 is placed between the electrical component 17 and the re-woven layer 6, and covers the solder 173.

[0148] See Figure 50 The carrier 81 and heat release strip 82 are removed by exposing them to a heat source or UV source. Next, the heat sink 16 is attached to the second surface 52 of the package 5 via the second adhesive layer 15 for heat dissipation purposes. That is, the heat sink 16 is placed adjacent to the second surface 52 of the package 5. The material of the second adhesive layer 15 can be any adhesive capable of attaching the heat sink 16 to the second surface 52 of the package 5. Then, a sawing process is performed to cut the heat sink 16, the second adhesive layer 15, the package 5, and the reel layer 6, thereby forming a structure as shown in the image. Figure 3 The semiconductor package 1b shown in the figure.

[0149] Figures 51 to 61 This invention describes methods for manufacturing semiconductor packages according to some embodiments of the present disclosure. In some embodiments, the method is used for manufacturing semiconductor packages, for example... Figure 4 The semiconductor package 1c shown in the image illustrates the initial stage of the process and... Figures 20 to 25 The stages described herein are the same or similar. However, the protective layer 11 used in this method is removable, for example, an adhesive that is readily soluble in a solvent (e.g., water). Figure 51 Depicted in Figure 25 The stage following the stage described in the text.

[0150] See Figure 51 The semiconductor die 2 is remounted onto the dicing tape 76, wherein the top wall 46 of the shielding layer 4a is attached to the dicing tape 76.

[0151] See Figure 52The protective layer 11 is removed using a solvent (e.g., water). This exposes the conductive bumps 3 and the active surface 21 of the semiconductor die 2. Next, each of the semiconductor dies 2 is picked up from the dicing tape 76, forming a shape as shown. Figure 53 The semiconductor unit 78c shown in the figure.

[0152] See Figure 54 A carrier 81 is provided, on which a heat release band 82 is provided. The carrier 81 may be made of silicon, metal or glass, and may be the same as or different from the support layer 14 described above.

[0153] See Figure 55 ,Will Figure 53 The semiconductor unit 78c shown is mounted on a heat release strip 82. The semiconductor unit 78c includes a semiconductor die 2, conductive bumps 3 and a shielding layer 4a. Figure 55 Two similar semiconductor units 78c are shown. However, more or fewer semiconductor units 78c may be placed on the heat release band 82, and they may be the same or different from each other. The top wall 46 of the shielding layer 4a is attached to the heat release band 82.

[0154] See Figure 56 A package 5 is formed or disposed on a heat release band 82 to cover a semiconductor cell 78c, the semiconductor cell 78c comprising a semiconductor element (e.g., a semiconductor die 2), conductive bumps 3, and a shielding layer 4a. The package 5 can be formed by a molding process. The material of the package 5 can be an encapsulation compound with or without filler. The package 5 is further formed on the active surface 21 of the semiconductor die 2 and covers the conductive bumps 3 disposed on the active surface. For example, the package 5 contacts the active surface 21 of the semiconductor die 2 and contacts and surrounds the conductive bumps 3.

[0155] See Figure 57A polishing process is performed to remove a portion of the package 5 and a portion of the shielding layer 4a. In some embodiments, the polishing process may further remove a portion of at least one of the conductive bumps 3. Thus, a first end 31 of each of the conductive bumps 3 is exposed from the package 5, and a first end 41 of the sidewall 45 of the shielding layer 4a is formed to be coplanar with the first end 31 of the conductive bump 3. The sidewall 45 of the shielding layer 4a further has a second end 42, an inner surface 43, and an outer surface 44. The second end 42 is opposite to the first end 41. A top wall 46 is connected to the second end 42 of the sidewall 45. The inner surface 43 and the outer surface 44 extend between the first end 41 and the second end 42. The outer surface 44 is opposite to the inner surface 43. For example, the inner surface 43 of the sidewall 45 of the shielding layer 4a contacts the side surface 23 of the semiconductor die 2. The shielding layer 4a provides electromagnetic shielding for the back surface 22 and the side surface 23 of the semiconductor die 2. The package 5 has a first surface 51 and a second surface 52 opposite to the first surface 51. The first surface 51 of the package 5 is coplanar with the first end 31 of at least one of the conductive bumps 3 and / or the first end 41 of the shielding layer 4. The second surface 52 of the package 5 is coplanar with the second end 42 of the shielding layer 4a and the top surface of the top wall 46 of the shielding layer 4a.

[0156] See Figure 58 A redistribution layer 6 is formed or disposed on the first surface 51 of the package 5. The redistribution layer 6 may include at least one conductive layer containing traces and pads, and may further include at least one via for connection between the conductive layers. The linewidth / spacing (L / S) of the redistribution layer 6 may be approximately 2 μm / 2 μm. For example, such as... Figure 58 As shown, the redistribution layer 6 comprises three conductive layers 61, 62, and 63, which are electrically connected to each other through a plurality of vias. The redistribution layer 6 may further include an insulating structure 64 disposed between these conductive layers 61, 62, and 63. The redistribution layer 6 is electrically connected to the semiconductor die 2 via conductive bumps 3. For example, at least one of the conductive bumps 3 contacts the topmost conductive layer 61 of the redistribution layer 6. The redistribution layer 6 is also electrically connected to a shielding layer 4a. Figure 58 As shown, the first end 41 of the sidewall 45 of the shielding layer 4a is in contact with the topmost conductive layer 61 of the re-fabricated layer 6.

[0157] See Figure 59 Electrical component 17 and multiple connecting elements 18 are disposed on and electrically connected to the redistribution layer 6. Electrical component 17 may be a passive component, another semiconductor die, or an insert. For example, such as... Figure 59As shown, electrical component 17 is a bridge that includes internal circuitry 172 for electrically connecting two semiconductor dies 2. Electrical component 17 may further include a plurality of solders 173 for electrically connecting to the bottom conductive layer 63 of the overlay layer 6. Connecting element 18 may be electrically connected to the bottom conductive layer 63 of the overlay layer 6 for external connection purposes.

[0158] See Figure 60 A base adhesive 174 is placed between the electrical component 17 and the re-woven layer 6, and covers the solder 173.

[0159] See Figure 61 The carrier 81 and heat release strip 82 are removed by exposing them to a heat source or UV source. Next, the heat sink 16 is attached to the second surface 52 of the package 5 via the second adhesive layer 15 for heat dissipation purposes. That is, the heat sink 16 is placed adjacent to the second surface 52 of the package 5. The material of the second adhesive layer 15 can be any adhesive capable of attaching the heat sink 16 to the second surface 52 of the package 5. Then, a sawing process is performed to cut the heat sink 16, the second adhesive layer 15, the package 5, and the reel layer 6, thereby forming a structure as shown in the image. Figure 4 The semiconductor package 1c shown in the figure.

[0160] Figures 62 to 71 This invention describes methods for manufacturing semiconductor packages according to some embodiments of the present disclosure. In some embodiments, the method is used for manufacturing semiconductor packages, for example... Figure 5 The semiconductor package 1d shown in the image illustrates the initial stage of the process and... Figures 35 to 41 The stages described herein are the same or similar. However, the protective material 74 used in this method is removable, for example, an adhesive that is readily soluble in a solvent (e.g., water). Therefore, the protective layer 11b formed therefrom is also removable. Figure 62 Depicting Figure 41 The stage following the stage described in the text.

[0161] See Figure 62 The protective layer 11b is removed using a solvent (e.g., water). This exposes the conductive bumps 3 and the active surface 21 of the semiconductor die 2. Next, each of the semiconductor dies 2 is picked up from the dicing tape 76, forming a shape as shown. Figure 63 The semiconductor unit 78d shown in the figure.

[0162] See Figure 64 A carrier 81 is provided, on which a heat release band 82 is provided. The carrier 81 may be made of silicon, metal or glass, and may be the same as or different from the support layer 14 described above.

[0163] See Figure 65 ,Will Figure 63The semiconductor unit 78d shown is mounted on a heat release strip 82. The semiconductor unit 78d includes a semiconductor die 2, conductive bumps 3 and a shielding layer 4b. Figure 65 Two similar semiconductor units 78d are shown. However, more or fewer semiconductor units 78d may be placed on the heat release band 82, and they may be the same or different from each other. The top wall 46 of the shielding layer 4a is attached to the heat release band 82.

[0164] See Figure 66 A package 5 is formed or disposed on a heat release band 82 to cover a semiconductor cell 78d, the semiconductor cell 78d comprising a semiconductor element (e.g., a semiconductor die 2), conductive bumps 3, and a shielding layer 4b. The package 5 can be formed by a molding process. The material of the package 5 can be an encapsulation compound with or without filler. The package 5 is further formed on the active surface 21 of the semiconductor die 2 and covers the conductive bumps 3 disposed on the active surface. For example, the package 5 contacts the active surface 21 of the semiconductor die 2 and contacts and surrounds the conductive bumps 3.

[0165] See Figure 67 A polishing process is performed to remove a portion of the package 5. In some embodiments, the polishing process may further remove a portion of at least one of the conductive bumps 3 and / or a portion of the shielding layer 4b. Thus, a first end 31 of each of the conductive bumps 3 is exposed from the package 5. The first end 41 of the sidewall 45 of the shielding layer 4b is coplanar with the first end 31 of the conductive bump 3. The sidewall 45 of the shielding layer 4b further has an inner surface 43 and an outer surface 44. The inner surface 43 and the outer surface 44 extend between the first end 41 and the second end 42. The outer surface 44 is opposite to the inner surface 43. For example, the inner surface 43 of the second portion 452 of the sidewall 45 contacts the side surface 23 of the semiconductor die 2. The shielding layer 4b provides electromagnetic shielding for the back surface 22 and the side surface 23 of the semiconductor die 2. The package 5 has a first surface 51 and a second surface 52 opposite to the first surface 51. The first surface 51 of the package 5 is coplanar with the first end 31 of at least one of the conductive bumps 3 and / or the first end 41 of the sidewall 45 of the shielding layer 4b. The second surface 52 of the package 5 is coplanar with the second end 42 of the sidewall 45 of the shielding layer 4b and the top surface of the top wall 46 of the shielding layer 4b.

[0166] See Figure 68 A redistribution layer 6 is formed or disposed on the first surface 51 of the package 5. The redistribution layer 6 may include at least one conductive layer containing traces and pads, and may further include at least one via for connection between the conductive layers. The linewidth / spacing (L / S) of the redistribution layer 6 may be approximately 2 μm / 2 μm. For example, such as... Figure 68As shown, the redistribution layer 6 comprises three conductive layers 61, 62, and 63, which are electrically connected to each other through a plurality of vias. The redistribution layer 6 may further include an insulating structure 64 disposed between these conductive layers 61, 62, and 63. The redistribution layer 6 is electrically connected to the semiconductor die 2 via conductive bumps 3. For example, at least one of the conductive bumps 3 contacts the topmost conductive layer 61 of the redistribution layer 6. The redistribution layer 6 is also electrically connected to a shielding layer 4b. Figure 68 As shown, the first end 41 of the sidewall 45 of the shielding layer 4b is in contact with the topmost conductive layer 61 of the re-fabricated layer 6.

[0167] See Figure 69 Electrical component 17 and multiple connecting elements 18 are disposed on and electrically connected to the redistribution layer 6. Electrical component 17 may be a passive component, another semiconductor die, or an insert. For example, such as... Figure 69 As shown, electrical component 17 is a bridge that includes internal circuitry 172 for electrically connecting two semiconductor dies 2. Electrical component 17 may further include a plurality of solders 173 for electrically connecting to the bottom conductive layer 63 of the overlay layer 6. Connecting element 18 may be electrically connected to the bottom conductive layer 63 of the overlay layer 6 for external connection purposes.

[0168] See Figure 70 A base adhesive 174 is placed between the electrical component 17 and the re-woven layer 6, and covers the solder 173.

[0169] See Figure 71 The carrier 81 and heat release strip 82 are removed by exposing them to a heat source or UV source. Next, the heat sink 16 is attached to the second surface 52 of the package 5 via the second adhesive layer 15 for heat dissipation purposes. That is, the heat sink 16 is placed adjacent to the second surface 52 of the package 5. The material of the second adhesive layer 15 can be any adhesive capable of attaching the heat sink 16 to the second surface 52 of the package 5. Then, a sawing process is performed to cut the heat sink 16, the second adhesive layer 15, the package 5, and the reel layer 6, thereby forming a structure as shown in the image. Figure 5 The semiconductor package 1d shown in the figure.

[0170] Unless otherwise stated, spatial descriptions such as "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "above," "below," "upper part," "above," "below," etc., indicate relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantage of the embodiments of this disclosure is not deviated from this arrangement.

[0171] As used herein, the terms “approximately,” “generally,” “a large number,” and “about” are used to describe and explain minor variations. When used in conjunction with an event or situation, the terms may refer to examples where the event or situation occurred precisely or where it occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same or equal.

[0172] If the displacement between two surfaces does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar.

[0173] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple indicators. In the description of some embodiments, a component provided “on” or “above” another component may cover the case where the preceding component is directly on the following component (e.g., in physical contact with the following component), and the case where one or more intermediate components are located between the preceding and following components.

[0174] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials typically indicate those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Generally, conductive materials have a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with conductivity of S / m. The conductivity of the material may vary with temperature. Unless otherwise specified, the conductivity of the material is measured at room temperature.

[0175] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that this range format is used for convenience and brevity and should be interpreted flexibly, including not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within that range, as if each numerical value and subrange were explicitly specified.

[0176] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Artistic representations in this disclosure may differ from actual equipment due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically described. This specification and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A semiconductor package comprising: A semiconductor die having an active surface, a back surface, and a side surface; Multiple conductive bumps are disposed on the active surface of the semiconductor die; A shielding layer is disposed on the side surface of the semiconductor die, the shielding layer having a first end and a second end opposite to the first end; An encapsulation body covering the shielding layer and having a first surface and a second surface opposite to the first surface, wherein the first end and the second end of the shielding layer are coplanar with the first surface and the second surface of the encapsulation body, respectively; A redistribution layer is disposed on the first surface of the package and electrically connected to the semiconductor die via the conductive bumps, wherein the shielding layer is electrically connected to the redistribution layer; A first adhesive layer has a first surface, a second surface opposite to the first surface, and a side surface extending between the first surface and the second surface. The first surface is disposed on and in contact with the back side surface of the semiconductor die. The side surface is coplanar with the side surface of the semiconductor die. A shielding layer is disposed on the side surface of the semiconductor die and the side surface of the first adhesive layer. The second end of the shielding layer is coplanar with the second surface of the first adhesive layer. A metal layer is disposed on the first adhesive layer, and the bottom surface of the metal layer contacts the second end of the shielding layer, the second surface of the first adhesive layer and the second surface of the package. The shielding layer and the metal layer together provide electromagnetic shielding for the semiconductor die. A support layer is disposed on the metal layer, and the side surface of the support layer is coplanar with the side surface of the metal layer; as well as A heat sink is disposed on the second surface adjacent to the package, and the side surface of the heat sink is coplanar with the outer surface of the package.

2. The semiconductor package of claim 1, wherein the first end of the shielding layer is coplanar with the end of each of the conductive bumps.

3. The semiconductor package according to claim 1, wherein the first end of the shielding layer is in contact with the redistribution layer.

4. The semiconductor package of claim 1, wherein the shielding layer does not cover the back surface of the semiconductor die.

5. The semiconductor package of claim 1, wherein the package comprises a first portion and a second portion, the first portion covering the shielding layer, the second portion covering the conductive bumps, and the first portion and the second portion being formed simultaneously.

6. The semiconductor package of claim 5, wherein the shielding layer separates the first portion and the second portion of the package.

7. The semiconductor package of claim 1, further comprising a protective layer covering the conductive bumps, wherein the protective layer is made of the same material as the package body.

8. The semiconductor package of claim 7, wherein the end of the shielding layer is coplanar with the surface of the protective layer, and the protective layer horizontally overlaps the package body.

9. The semiconductor package of claim 8, wherein the shielding layer covers the side surface of the protective layer and the protective layer is perpendicular to and does not overlap with the package body.

10. The semiconductor package of claim 1, further comprising an electrical component electrically connected to the redistribution layer and perpendicularly overlapping the first end of the shielding layer.

Images