A bit line structure and semiconductor memory
By using the wire layer as a mask in semiconductor memory to etch the contact layer, the problem of cumbersome and high cost of semiconductor memory processes is solved, the process reduction and cost reduction are achieved, and the quality and efficiency of material filling are improved. .
Patent Information
- Application Number
- CN201910875708.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2019-09-17
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2039-09-17
AI Technical Summary
The existing semiconductor memory process is complicated, resulting in high production costs, and there is a need to improve process efficiency and reduce costs.
A bit line structure is adopted, wherein the bit line includes a contact layer and a wire layer arranged in sequence from the substrate. The wire layer serves as a mask to etch the contact layer to obtain a contact layer with a cross-sectional width smaller than the wire layer, avoiding the preparation of the etching alone. The step of etching the contact layer is to reduce the process and reduce costs.
The semiconductor memory process is effectively reduced, the production cost is reduced, and the material filling quality and efficiency are improved through auxiliary layers, reducing the chance of voids appearing.
Smart Images
Figure CN110556359B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor storage technology, and more specifically, to a bit line structure and a semiconductor memory. Background Art
[0002] Nowadays, computers, mobile phones and other electronic devices cannot do without memory. Memory is a device that can store data and read the data according to the address code. Memory is divided into two categories: magnetic memory and semiconductor memory. Among them, the basic structure of semiconductor memory is the memory cell array and other circuits. The memory cell array is the main body of the semiconductor memory. Each memory cell is located at the intersection of the word line and the bit line to store data; the others are the address code buffer at the input end, the row decoder, the read amplifier, the column decoder and the output buffer. When the semiconductor memory reads the data, the address code signal must first be sent to the row decoder through the address code buffer and enter the word line. The row decoder selects a word line, and then the data obtained on a bit line is amplified by the read amplifier, and the column decoder selects one of the read amplifiers, and the amplified signal is output through the multi-channel output buffer. When writing data, the data must first be sent to the bit line selected by the column decoder, and then stored in the storage unit where the bit line and the word line intersect.
[0003] Semiconductor memories are now widely used in the electronics industry due to their advantages of small size, multiple functions, low manufacturing cost, etc. Although semiconductor memories have the above advantages, their manufacturing process is complicated and needs to be improved. Summary of the invention
[0004] In view of this, the present invention provides a bit line structure and a semiconductor memory, which effectively solve the existing technical problems, shorten the manufacturing process of the semiconductor memory, and reduce the manufacturing cost.
[0005] To achieve the above purpose, the technical solution provided by the present invention is as follows:
[0006] A bit line structure comprising:
[0007] substrate;
[0008] A plurality of bit lines are located on the substrate, wherein the bit lines include a contact layer and a conductor layer which are sequentially stacked starting from the substrate, a vertical projection of the contact layer on the substrate is located within a vertical projection of the conductor layer on the substrate, and a width of the contact layer in a cross section is smaller than a width of the conductor layer in a cross section.
[0009] Optionally, the bit line structure further includes: an auxiliary layer wrapping a side surface of the contact layer.
[0010] Optionally, the auxiliary layer is an oxide layer.
[0011] Optionally, the oxide layer is made of SiO2.
[0012] Optionally, a ratio of a total width of the auxiliary layer and the contact layer in a cross section to a width of the conductor layer in a cross section is in a range of 0.9-1.1.
[0013] Optionally, the conductive line layer includes a first bit line conductive sublayer, a second bit line conductive sublayer and a bit line cap film sublayer stacked in sequence starting from the contact layer.
[0014] Accordingly, the present invention further provides a semiconductor memory, comprising:
[0015] A substrate comprising a plurality of active regions defined by a device isolation layer;
[0016] An insulating layer located on a side of the substrate having the device isolation layer, wherein a plurality of bit line contact grooves are formed on the insulating layer, and the bit line contact grooves expose the active area;
[0017] A plurality of first bit lines are formed on the surface of the insulating layer facing away from the substrate, and a second bit line is formed in the bit line contact groove, wherein the first bit line and the second bit line both include a contact layer and a conductor layer which are sequentially stacked starting from one side of the substrate, a vertical projection of the contact layer on the substrate is located within a vertical projection of the conductor layer on the substrate, and a width of the contact layer in a cross section is smaller than a width of the conductor layer in a cross section.
[0018] Optionally, the semiconductor memory further includes: an auxiliary layer wrapping the side surface of the contact layer.
[0019] Optionally, the auxiliary layer is an oxide layer.
[0020] Optionally, the oxide layer is made of SiO2.
[0021] Optionally, a ratio of a total width of the auxiliary layer and the contact layer in a cross section to a width of the conductor layer in a cross section is in a range of 0.9-1.1.
[0022] Optionally, the conductive line layer includes a first bit line conductive sublayer, a second bit line conductive sublayer and a bit line cap film sublayer stacked in sequence starting from the contact layer.
[0023] Optionally, a top surface of the contact layer of the second bit line facing away from the substrate is higher than a surface of the insulating layer facing away from the substrate.
[0024] Optionally, a top surface of the contact layer of the second bit line facing away from the substrate is flush with a top surface of the contact layer of the first bit line facing away from the substrate.
[0025] Optionally, a top surface of a conductive line layer of the first bit line facing away from the substrate is flush with a top surface of a conductive line layer of the second bit line facing away from the substrate.
[0026] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:
[0027] The present invention provides a bit line structure and a semiconductor memory, comprising: a substrate; a plurality of bit lines located on the substrate, wherein the bit lines include a contact layer and a conductor layer which are sequentially stacked starting from the substrate, a vertical projection of the contact layer on the substrate is located within a vertical projection of the conductor layer on the substrate, and a width of the contact layer in a cross section is smaller than a width of the conductor layer in a cross section.
[0028] As can be seen from the above content, the technical solution provided by the present invention uses the conductor layer as a mask when manufacturing the bit line structure, and then etches the material structure layer where the contact layer is located, and finally prepares a contact layer with a cross-sectional width smaller than the conductor layer. Since the conductor layer is used as a mask, there is no need to separately prepare a corresponding mask layer when etching the contact layer, thereby reducing the process of the bit line structure, that is, reducing the process of the semiconductor memory, and reducing the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.
[0030] Figure 1 A schematic diagram of a bit line structure provided in an embodiment of the present application;
[0031] Figure 2 A schematic diagram of another bit line structure provided in an embodiment of the present application;
[0032] Figure 3 A schematic diagram of a structure of another bit line structure provided in an embodiment of the present application;
[0033] Figure 4 A schematic diagram of the structure of a semiconductor memory provided in an embodiment of the present application;
[0034] Figure 5 A schematic diagram of the structure of another semiconductor memory provided in an embodiment of the present application;
[0035] Figure 6A schematic diagram of the structure of another semiconductor memory provided in an embodiment of the present application;
[0036] Figure 7 A schematic diagram of the structure of another semiconductor memory provided in an embodiment of the present application;
[0037] Figure 8 A schematic diagram of the structure of another semiconductor memory provided in an embodiment of the present application. DETAILED DESCRIPTION
[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0039] As described in the background technology, today, computers, mobile phones and other electronic devices cannot do without memory, which is a device that can store data and read the data according to the address code. The memory is divided into two categories: magnetic memory and semiconductor memory. Since semiconductor memory has many advantages such as small size, multiple functions and low manufacturing cost, it is widely used in the electronics industry. Although semiconductor memory has many advantages mentioned above, its manufacturing process is cumbersome and needs to be improved.
[0040] Based on this, the embodiment of the present application provides a bit line structure and a semiconductor memory, which effectively solves the existing technical problems, reduces the process of semiconductor memory, and reduces the production cost. To achieve the above purpose, the technical solution provided by the embodiment of the present application is as follows, specifically combined with Figures 1 to 8 The technical solution provided in the embodiments of the present application is described in detail.
[0041] refer to Figure 1 FIG. 1 is a schematic diagram of a bit line structure provided in an embodiment of the present application, wherein the bit line structure includes:
[0042] Base 100;
[0043] A plurality of bit lines are located on the substrate 100, wherein the bit lines include a contact layer 210 and a wire layer 220 which are sequentially stacked starting from the substrate, a vertical projection of the contact layer 210 on the substrate 100 is located within a vertical projection of the wire layer 220 on the substrate 210, and a width d1 of the contact layer 210 in a cross section is smaller than a width d2 of the wire layer 220 in a cross section.
[0044] In one embodiment of the present application, the substrate provided by the present application may include a silicon substrate, a germanium substrate and / or a silicon germanium substrate, etc., and the present application does not make any specific limitation on this. Wherein, the bit line is formed on the substrate, and after the contact material structure layer and the wire material structure layer are formed in sequence, the wire structure material layer is first etched to obtain a wire layer, and then the contact material layer is etched using the wire layer as a mask to obtain a contact layer having a cross-sectional width smaller than the wire layer.
[0045] It can be understood that the technical solution provided in the embodiment of the present application uses the wire layer as a mask when manufacturing the bit line structure, and then etches the material structure layer where the contact layer is located, and finally prepares a contact layer with a cross-sectional width smaller than the wire layer. Since the wire layer is used as a mask, there is no need to separately prepare a corresponding mask layer when etching the contact layer, thereby reducing the process of the bit line structure, that is, reducing the process of the semiconductor memory, and reducing the manufacturing cost.
[0046] For further reference, Figure 2 , which is a schematic structural diagram of another bit line structure provided in an embodiment of the present application, wherein the bit line structure includes: a substrate 100;
[0047] A plurality of bit lines are located on the substrate 100, wherein the bit lines include a contact layer 210 and a wire layer 220 which are sequentially stacked starting from the substrate, a vertical projection of the contact layer 210 on the substrate 100 is located within a vertical projection of the wire layer 220 on the substrate 210, and a width d1 of the contact layer 210 in a cross section is smaller than a width d2 of the wire layer 220 in a cross section.
[0048] Furthermore, the bit line structure provided in the embodiment of the present application further includes: an auxiliary layer 300 wrapping the side surface of the contact layer 210 .
[0049] Understandable, such as Figure 2 As shown, the contact layer 210 provided in the embodiment of the present application is also wrapped with an auxiliary layer 300 on the outside, and then when the material is filled 400 on the bit line structure having one side of the bit line, the auxiliary layer 300 wraps the contact layer 210, so that the width d3 of the structural layer below the conductor layer (compared with the structural layer when only having the contact layer 210 but no auxiliary layer 300) is increased, thereby reducing the area that needs to be filled on the outside of the auxiliary layer 300 (such as the dotted box in the figure), reducing the difficulty of filling the material on the outside of the auxiliary layer 300, reducing the probability of voids when the outside of the auxiliary layer 300 is filled with material, and improving the filling quality.
[0050] In one embodiment of the present application, the auxiliary layer provided by the present application may be an oxide layer. In the present embodiment of the present application, the auxiliary layer made of oxide may be obtained by performing oxidation-reduction on the outer side of the contact layer, and the present application does not make any specific restrictions on this. It should be noted that in other embodiments of the present application, the auxiliary layer may also be made of other materials and may also be made by other types of processes, which needs to be specifically designed according to the actual application.
[0051] Optionally, the material of the oxide layer provided in the embodiment of the present application is SiO 2. The material of the contact layer provided in the embodiment of the present application can be polysilicon, and then the outer side of the contact layer made of polysilicon is subjected to oxidation-reduction treatment to finally obtain an auxiliary layer made of SiO 2.
[0052] Furthermore, in order to improve production efficiency and ensure that the probability of voids occurring when the outer side of the auxiliary layer is filled with material is lower, the total width of the auxiliary layer and the contact layer in the cross section provided in the embodiment of the present application is in the range of 0.9-1.1, including the endpoint values, to the width of the conductor layer in the cross section.
[0053] refer to Figure 3 As shown, it is a structural schematic diagram of another bit line structure provided in an embodiment of the present application, wherein the conductive line layer 220 provided in the embodiment of the present application includes a first bit line conductive sublayer 221, a second bit line conductive sublayer 222 and a bit line cover film sublayer 223 stacked in sequence starting from the contact layer 210.
[0054] In one embodiment of the present application, the materials of the first bit line conducting sublayer and the second bit line conducting sublayer provided by the present application may be the same or different, and the present application does not make any specific restrictions on this. Among them, any of the first bit line conducting sublayer and the second bit line conducting sublayer may include a polysilicon layer, a conductive metal nitride layer (such as titanium nitride, tantalum nitride, tungsten nitride, etc.), a metal layer (such as a single layer formed by any one of tungsten, titanium, tantalum, etc. or a stacked layer formed by multiple layers), a conductive alloy (such as a combination of multiple alloys of tungsten, titanium, tantalum, etc.), etc. In addition, the bit line cap film sublayer provided in the embodiment of the present application may include but is not limited to a silicon nitride film.
[0055] Accordingly, the present application embodiment also provides a semiconductor memory, referring to Figure 4 FIG. 1 is a schematic diagram of the structure of another semiconductor memory provided in an embodiment of the present application, wherein the semiconductor memory includes:
[0056] A substrate 10, wherein the substrate 10 includes a plurality of active regions 12 defined by a device isolation layer 11;
[0057] An insulating layer 20 is located on a side of the substrate 10 having the device isolation layer 11, and a plurality of bit line contact grooves are formed on the insulating layer 20, wherein the bit line contact grooves expose the active area 12;
[0058] A plurality of first bit lines 31 are formed on the surface of the insulating layer 20 facing away from the substrate 10, and a second bit line 32 is formed in the bit line contact groove, wherein the first bit line 31 and the second bit line 32 both include a contact layer 331 and a wire layer 332 which are sequentially stacked starting from one side of the substrate 10, the vertical projection of the contact layer 331 on the substrate 10 is located within the vertical projection of the wire layer 332 on the substrate 10, and the width d4 of the contact layer 331 in the cross section is smaller than the width d5 of the wire layer 332 in the cross section.
[0059] In one embodiment of the present application, the substrate provided by the present application may include a silicon substrate, a germanium substrate and / or a silicon germanium substrate, etc., and the present application does not make specific restrictions on this. Among them, the device isolation layer is filled between the active areas, and the material of the device isolation layer is an insulating material, such as silicon oxide, silicon nitride and / or silicon oxynitride, etc. The bit line provided by the present application is formed on the substrate, and specifically can be: after the contact material structure layer and the wire material structure layer are formed in sequence, the wire structure material layer is first etched to obtain a wire layer, and then the wire layer is used as a mask to etch the contact material layer to obtain a contact layer with a cross-sectional width smaller than the wire layer.
[0060] It should be noted that the semiconductor memory provided in the embodiment of the present application also includes structures such as word lines, which is the same as the prior art, so this application will not elaborate on this.
[0061] It can be understood that the technical solution provided in the embodiment of the present application uses the wire layer as a mask when manufacturing the bit line structure, and then etches the material structure layer where the contact layer is located, and finally prepares a contact layer with a cross-sectional width smaller than the wire layer. Since the wire layer is used as a mask, there is no need to separately prepare a corresponding mask layer when etching the contact layer, thereby reducing the process of the bit line structure, that is, reducing the process of the semiconductor memory, and reducing the manufacturing cost.
[0062] For further reference, Figure 5 , which is a schematic structural diagram of another semiconductor memory provided by an embodiment of the present application, wherein the semiconductor memory comprises: a substrate 10, wherein the substrate 10 comprises a plurality of active regions 12 defined by a device isolation layer 11;
[0063] An insulating layer 20 is located on a side of the substrate 10 having the device isolation layer 11, and a plurality of bit line contact grooves are formed on the insulating layer 20, wherein the bit line contact grooves expose the active area 12;
[0064] A plurality of first bit lines 31 are formed on the surface of the insulating layer 20 facing away from the substrate 10, and a second bit line 32 is formed in the bit line contact groove, wherein the first bit line 31 and the second bit line 32 both include a contact layer 331 and a wire layer 332 which are sequentially stacked starting from one side of the substrate 10, the vertical projection of the contact layer 331 on the substrate 10 is located within the vertical projection of the wire layer 332 on the substrate 10, and the width d4 of the contact layer 331 in the cross section is smaller than the width d5 of the wire layer 332 in the cross section.
[0065] Furthermore, the semiconductor memory provided in the embodiment of the present application further includes: an auxiliary layer 30 wrapping the side surface of the contact layer 331 .
[0066] Understandable, such as Figure 5 As shown, the contact layer 331 provided in the embodiment of the present application is also wrapped with an auxiliary layer 30 on the outside, and then when the material is filled 40 on the bit line structure having one side of the bit line, the auxiliary layer 30 wraps the contact layer 331, so that the width d6 of the structural layer below the conductor layer (compared with the structural layer when only having the contact layer 331 but no auxiliary layer 30) is increased, thereby reducing the area that needs to be filled on the outside of the auxiliary layer 30 (such as the dotted box in the figure), reducing the difficulty of filling the material on the outside of the auxiliary layer 30, reducing the probability of voids when the outside of the auxiliary layer 30 is filled with material, and improving the filling quality.
[0067] In one embodiment of the present application, the auxiliary layer provided by the present application may be an oxide layer. In the present embodiment of the present application, the auxiliary layer made of oxide may be obtained by performing oxidation-reduction on the outer side of the contact layer, and the present application does not make any specific restrictions on this. It should be noted that in other embodiments of the present application, the auxiliary layer may also be made of other materials and may also be made by other types of processes, which needs to be specifically designed according to the actual application.
[0068] Optionally, the material of the oxide layer provided in the embodiment of the present application is SiO 2. The material of the contact layer provided in the embodiment of the present application can be polysilicon, and then the outer side of the contact layer made of polysilicon is subjected to oxidation-reduction treatment to finally obtain an auxiliary layer made of SiO 2.
[0069] Furthermore, in order to improve production efficiency and ensure that the probability of voids occurring when the outer side of the auxiliary layer is filled with material is lower, the total width of the auxiliary layer and the contact layer in the cross section provided in the embodiment of the present application is in the range of 0.9-1.1, including the endpoint values, to the width of the conductor layer in the cross section.
[0070] refer to Figure 6As shown, it is a structural schematic diagram of another semiconductor memory provided in an embodiment of the present application, wherein the conductive line layer 332 provided in the embodiment of the present application includes a first bit line conductive sublayer 3321, a second bit line conductive sublayer 3322 and a bit line cover film sublayer 3323 which are stacked in sequence starting from the contact layer 331.
[0071] In one embodiment of the present application, the materials of the first bit line conducting sublayer and the second bit line conducting sublayer provided by the present application may be the same or different, and the present application does not make any specific restrictions on this. Among them, any of the first bit line conducting sublayer and the second bit line conducting sublayer may include a polysilicon layer, a conductive metal nitride layer (such as titanium nitride, tantalum nitride, tungsten nitride, etc.), a metal layer (such as a single layer formed by any one of tungsten, titanium, tantalum, etc. or a stacked layer formed by multiple layers), a conductive alloy (such as a combination of multiple alloys of tungsten, titanium, tantalum, etc.), etc. In addition, the bit line cap film sublayer provided in the embodiment of the present application may include but is not limited to a silicon nitride film.
[0072] refer to Figure 7 As shown, it is a schematic diagram of the structure of another semiconductor memory provided in an embodiment of the present application, wherein the top surface of the contact layer 331 of the second bit line 32 provided in the embodiment of the present application facing away from the substrate 10 is higher than the surface of the insulating layer 20 facing away from the substrate 10.
[0073] It can be understood that after the bit line contact groove is formed on the insulating layer and the substrate, the contact material structure layer can be manufactured on one side of the insulating layer, wherein, after the contact material structure layer completely fills the bit line contact groove and is higher than the preset height range of the insulating layer, the wire material structure layer is continued to be manufactured on the contact material structure layer, and then the contact layer and the wire layer are manufactured separately, and finally the top surface of the contact layer of the second bit line located in the bit line contact groove is higher than the surface of the insulating layer.
[0074] refer to Figure 8 As shown, it is a schematic diagram of the structure of another semiconductor memory provided in an embodiment of the present application, wherein the top surface of the contact layer 331 of the second bit line 32 provided in the embodiment of the present application facing away from the substrate 10 is flush with the top surface of the contact layer 331 of the first bit line 31 facing away from the substrate 10.
[0075] It can be understood that after the bit line contact grooves are formed on the insulating layer and the substrate, a contact material structure layer can be manufactured on one side of the insulating layer, wherein the contact material structure layer is a flat structure layer that completely fills the bit line contact grooves and is higher than a preset height of the insulating layer; a wire material structure layer is continued to be manufactured on the contact material structure layer, and then a contact layer and a wire layer are manufactured separately, and finally a structure in which the top surfaces of the contact layers of the first bit line and the second bit line are flush is obtained.
[0076] like Figure 7As shown in or 8, in one embodiment of the present application, the top surface of the conductor layer 332 of the first bit line 31 provided in the present application facing away from the substrate 10 is flush with the top surface of the conductor layer 332 of the second bit line 32 facing away from the substrate 10, and the present application does not make any specific restrictions on this.
[0077] An embodiment of the present application provides a bit line structure and a semiconductor memory, comprising: a substrate; a plurality of bit lines located on the substrate, wherein the bit lines include a contact layer and a conductor layer stacked in sequence starting from the substrate, a vertical projection of the contact layer on the substrate is located within a vertical projection of the conductor layer on the substrate, and a width of the contact layer in a cross section is smaller than a width of the conductor layer in a cross section.
[0078] As can be seen from the above content, the technical solution provided by the embodiment of the present application uses the conductive wire layer as a mask when manufacturing the bit line structure, and then etches the material structure layer where the contact layer is located, and finally prepares a contact layer with a cross-sectional width smaller than the conductive wire layer. Since the conductive wire layer is used as a mask, there is no need to separately prepare a corresponding mask layer when etching the contact layer, thereby reducing the process of the bit line structure, that is, reducing the process of the semiconductor memory, and reducing the manufacturing cost.
[0079] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A bit line structure, characterized in that: include: substrate; A plurality of bit lines on the substrate, wherein the bit lines include a contact layer and a wire layer stacked in sequence from the substrate, a vertical projection of the contact layer on the substrate is within a vertical projection of the wire layer on the substrate, and a width of the contact layer in a cross section is smaller than a width of the wire layer in a cross section; The auxiliary layer is located on the side of the contact layer, and the total width of the auxiliary layer and the contact layer in the cross section is greater than the width of the wire layer in the cross section.
2. The bit line structure according to claim 1, characterized in that: The bit line structure further includes an auxiliary layer wrapping a side surface of the contact layer.
3. The bit line structure according to claim 1, characterized in that: The auxiliary layer is an oxide layer.
4. The bit line structure according to claim 3, characterized in that: The material of the oxide layer is SiO2.
5. The bit line structure according to claim 1, wherein: The ratio of the total width of the auxiliary layer and the contact layer in the cross section to the width of the conductor layer in the cross section is in the range of 0.9-1.
1.
6. The bit line structure according to claim 1, wherein: The conductive line layer includes a first bit line conductive sublayer, a second bit line conductive sublayer and a bit line cap film sublayer which are sequentially stacked from the contact layer.
7. A semiconductor memory, characterized in that: include: A substrate comprising a plurality of active regions defined by a device isolation layer; An insulating layer located on a side of the substrate having the device isolation layer, wherein a plurality of bit line contact grooves are formed on the insulating layer, and the bit line contact grooves expose the active area; A plurality of first bit lines formed on a surface of the insulating layer facing away from the substrate, and a second bit line formed in the bit line contact groove, wherein the first bit line and the second bit line both include a contact layer and a wire layer sequentially stacked from one side of the substrate, a vertical projection of the contact layer on the substrate is located within a vertical projection of the wire layer on the substrate, and a width of the contact layer in a cross section is smaller than a width of the wire layer in a cross section; The auxiliary layer is located on the side of the contact layer, and the total width of the auxiliary layer and the contact layer in the cross section is greater than the width of the wire layer in the cross section.
8. The semiconductor memory according to claim 7, wherein: The semiconductor memory further includes an auxiliary layer wrapping a side surface of the contact layer.
9. The semiconductor memory according to claim 7, wherein: The auxiliary layer is an oxide layer.
10. The semiconductor memory according to claim 9, wherein: The material of the oxide layer is SiO2.
11. The semiconductor memory according to claim 7, wherein: The ratio of the total width of the auxiliary layer and the contact layer in the cross section to the width of the conductor layer in the cross section is in the range of 0.9-1.
1.
12. The semiconductor memory according to claim 7, wherein: The conductive line layer includes a first bit line conductive sublayer, a second bit line conductive sublayer and a bit line cap film sublayer which are sequentially stacked from the contact layer.
13. The semiconductor memory according to claim 7, wherein: A top surface of the contact layer of the second bit line facing away from the substrate is higher than a surface of the insulating layer facing away from the substrate.
14. The semiconductor memory according to claim 7, wherein: A top surface of the contact layer of the second bit line facing away from the substrate is flush with a top surface of the contact layer of the first bit line facing away from the substrate.
15. The semiconductor memory according to claim 7, wherein: A top surface of a conductive line layer of the first bit line facing away from the substrate is flush with a top surface of a conductive line layer of the second bit line facing away from the substrate.