Fully differential transimpedance amplifier circuit and communication device

Abstract

The present disclosure relates to a transimpedance amplifier circuit and a communication device. A transimpedance amplifier circuit includes: a first amplifier circuit, a second amplifier circuit, and an amplifier. The first amplifier circuit has an input terminal and an output terminal. The first amplifier circuit is configured to obtain an input current through the input terminal and generate an output voltage at the output terminal. The second amplifier circuit has an input terminal and an output terminal. The second amplifier circuit is configured to obtain an input current through the input terminal and generate an output voltage at the output terminal. The amplifier has a first input terminal and a second input terminal, the first input terminal is connected to the output terminal of the first amplifier circuit and the second input terminal is connected to the output terminal of the second amplifier circuit. A communication device has a receiving device, and the receiving device includes the above-mentioned fully differential transimpedance amplifier circuit.

Description

Technical Field

[0001] This application relates to an amplifier circuit, and more particularly to a fully differential transimpedance amplifier circuit and a communication device. Background Art

[0002] The following description and examples are not considered prior art by virtue of their inclusion in this section.

[0003] A transimpedance amplifier (TIA) is typically used to convert an input current signal into a corresponding output voltage signal. A transimpedance amplifier is typically used to receive a current signal from a previous-stage detection circuit, and the current signal output from the previous-stage detection circuit is received by the transimpedance amplifier and converted into a corresponding voltage signal that can be processed by a processor in the subsequent stage of the transimpedance amplifier. Among them, the previous-stage detection circuit is usually a sensor device, and the subsequent-stage processor is usually used to process the voltage signal. Summary of the Invention

[0004] One embodiment of the present disclosure provides a fully differential transimpedance amplifier circuit, including: a first amplifier circuit, a second amplifier circuit, and an amplifier. The first amplifier circuit has an input terminal and an output terminal. The first amplifier circuit is configured to obtain an input current through the input terminal and generate an output voltage at the output terminal. The second amplifier circuit has an input terminal and an output terminal. The second amplifier circuit is configured to obtain an input current through the input terminal and generate an output voltage at the output terminal. The amplifier has a first input terminal and a second input terminal, the first input terminal is connected to the output terminal of the first amplifier circuit, and the second input terminal is connected to the output terminal of the second amplifier circuit.

[0005] Another embodiment of the present disclosure provides a communication device, which has a receiving device, and the receiving device includes the above-mentioned fully differential transimpedance amplifier circuit. Brief Description of the Drawings

[0006] Figure 1 Shown is a schematic circuit diagram of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure.

[0007] Figure 2 Shown is a schematic circuit diagram of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure.

[0008] Figure 3 Shown is a schematic circuit diagram of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure.

[0009] Figure 4 Shown is a schematic circuit diagram of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure.

[0010] Figure 5The figure shows a schematic diagram of the circuit structure of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure.

[0011] Figure 6 The figure shows a schematic diagram of the circuit structure of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure.

[0012] Figure 7 The figure shows a schematic diagram of the circuit structure of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure.

[0013] Figure 8 The figure shows a schematic diagram of the circuit structure of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure. Detailed implementation manners

[0014] Embodiments of the present disclosure provide many different embodiments or examples for implementing different features of the embodiments of the present disclosure. Specific examples of components and arrangements will be described below to simplify the embodiments of the present disclosure.

[0015] For ease of description, "first", "second", "third", etc. may be used herein to distinguish different components of a figure or a series of figures. "First", "second", "third", etc. are not intended to describe corresponding components.

[0016] As Figure 1 The figure shows a schematic diagram of the structure of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure. The transimpedance amplifier circuit includes a first amplifier circuit, a second amplifier circuit, and a negative feedback circuit. According to an embodiment of the present disclosure, the first amplifier circuit includes an input terminal, an output terminal V OUT1 , a first transistor M 1A , a second transistor M 2A , a first resistor R FA , a second resistor R LA , and a DC source I 1A ; the first amplifier circuit includes an input terminal, an output terminal V OUT2 , a first transistor M 1B , a second transistor M 2B , a first resistor R FB , a second resistor R LB , and a DC source I 1B ; and the negative feedback circuit includes a first amplifier OP A , a second amplifier OP B , a third transistor M 3A , and a fourth transistor M 3B .

[0017] According to an embodiment of the present disclosure, the gate of the first transistor M 1A of the first amplifier circuit can be used as the first input terminal of the fully differential transimpedance amplifier circuit (or the input terminal of the first amplifier circuit), and the first transistor M of the first amplifier circuit1A The drain of the fully differential transimpedance amplifier circuit can be used as the first output terminal V OUT1 (or the output end of the first amplifier circuit). The first transistor M of the first amplifier circuit 1A The gate is configured to receive a photosensitive device (photodiode) PD A The input current i INA The photoelectric sensing device PD A The other end is connected to the first power supply terminal V DD1 Connect the first power supply terminal V DD1 Used to give photoelectric sensing device PD A Provides working voltage. The first resistor R of the first amplifier circuit FA Connected to the first transistor M 1A The gate of the second transistor M 2A The first transistor M of the first amplifier circuit 1A The source of the first transistor M is connected to the ground terminal. 1A The drain of the second resistor R LA One end of the second resistor R LA The other end of is connected to a current source. According to an embodiment of the present disclosure, the current source has a transistor M 4 . Transistor M 4 The gate is connected to the bias voltage terminal V BIA , transistor M 4 The source is connected to the second power supply terminal V DD2 , transistor M 4 The drain is connected to the second resistor R LA The second transistor M of the first amplifier circuit 2A The gate of the first transistor M 1A The drain of the second transistor M 2A The drain terminal and the first power supply terminal V DD1 Connection. DC source I 1A Connected in series to the second transistor M 2A between the source and the ground terminal GND.

[0018] According to an embodiment of the present disclosure, the first transistor M of the second amplifier circuit 1B The gate of the fully differential transimpedance amplifier circuit can be used as the first input terminal (or the input terminal of the second amplifier circuit) of the fully differential transimpedance amplifier circuit and the first transistor M of the second amplifier circuit 1B The drain of the fully differential transimpedance amplifier circuit can be used as the second output terminal V OUT2(or the output terminal of the second amplifier circuit). The structure and connection of the second amplifier circuit are substantially the same as those of the first amplifier circuit. According to an embodiment of the present disclosure, the signals received by the input terminals of the first amplifier circuit and the second amplifier circuit (or the first input terminal and the second input terminal of the fully differential transimpedance amplifier circuit) are differential signals; and the output terminals V OUT1 and V OUT2 (or the first output terminal and the second output terminal of the fully differential transimpedance amplifier circuit) output differential signals.

[0019] The gate of the first transistor M 1B of the second amplifier circuit is configured to receive the input current i B provided by the photo-sensing device (photo-diode) PD INB . The other end of the photo-sensing device PD B is connected to the first power supply terminal V DD1 , and the first power supply terminal V DD1 is used to provide the operating voltage for the photo-sensing device PD B . The first resistor R FB of the second amplifier circuit is connected between the gate of the first transistor M 1B and the source of the second transistor M 2B . The source of the first transistor M 1B of the first amplifier circuit is connected to the ground terminal, and the drain of the first transistor M 1B is connected to one end of the second resistor R LB , and the other end of the second resistor R LB is connected to the current source. According to an embodiment of the present disclosure, the current source has a transistor M 4 . The drain of the transistor M 4 is connected to one end of the second resistor R LB . The gate of the second transistor M 2B of the second amplifier circuit is connected to the drain of the first transistor M 1B , and the drain of the second transistor M 2B is connected to the first power supply terminal V DD1 . The DC source I 1B is connected in series between the source of the second transistor M 2B and the ground terminal GND.

[0020] The first amplifier OP A of the negative feedback circuit includes a first input terminal (such as the end marked "-" in Figure 1 ), a second input terminal (such as the end marked "+" in Figure 1 ) and an output terminal. The first input terminal is connected to the output terminal V OUT1 of the first amplifier circuit, and the second input terminal is connected to the reference voltage V REFConnection. The second amplifier OP of the negative feedback circuit B includes a first input terminal (such as Figure 1 the terminal marked "-" in the figure), a second input terminal (such as Figure 1 the terminal marked "+" in the figure), and an output terminal. The first input terminal is connected to the output terminal V of the second amplifier circuit OUT2 , the second input terminal is connected to the reference voltage V REF . The third transistor M of the negative feedback circuit 3A has a source, a drain, and a gate. Among them, the gate of the third transistor M 3A is connected to the output terminal of the first amplifier OP A , the source of the third transistor M 3A is connected to the ground terminal GND, and the drain of the third transistor M 3A is connected to the gate of the first transistor M of the first amplifier circuit 1A . The fourth transistor M of the negative feedback circuit 3B has a source, a drain, and a gate. Among them, the gate of the fourth transistor M 3B is connected to the output terminal of the second amplifier OP B , the source of the fourth transistor M 3B is connected to the ground terminal GND, and the drain of the fourth transistor M 3B is connected to the gate of the first transistor M of the second amplifier circuit 1B .

[0021] The fully differential transimpedance amplifier circuit converts the optical signals sensed by the photoelectric induction device PD A and PD B into current signals i INA and i INB , as the differential input current signals of the fully differential transimpedance amplifier circuit, and outputs the amplified differential voltage signals from the output terminals V OUT1 and V OUT2 . The fully differential transimpedance amplifier circuit realizes the linear amplification of the current signal. The photoelectric signals received by the photoelectric induction device usually have a very large dynamic range. When the input current is large and exceeds the input range of the fully differential transimpedance amplifier circuit, the linearity performance of the fully differential transimpedance amplifier circuit will be reduced, thus limiting the application of the fully differential transimpedance amplifier circuit. For example, when the input currents i INA and i INB of the fully differential transimpedance amplifier increase, the currents passing through the first resistors R FA and R FB increase, thereby increasing the voltages across the first resistors R FA and R FB , and the drains of the first transistors M 1A and M 1B and the second resistor RLA and R LB the current I in the branch where it is located 2A and I 2B increases, and the voltage difference across the second resistor R LA and R LB increases, causing the output voltage of the output terminal V of the amplifier circuit OUT1 and V OUT2 to decrease, resulting in a decline in linearity performance. Due to the existence of the first amplifier OP A and the first amplifier OP B , by setting the reference voltage V REF and applying the reference voltage V REF to the voltage difference between the output terminal V OUT1 and V OUT2 and amplifying it, the current of the third transistor M 3A and the fourth transistor M 3B is controlled to reduce the current flowing through the first resistor R FA and R FB , causing the voltage across the first resistor R FA and R FB to drop, thereby compensating for and offsetting the increase in the voltage at the gates of the first transistors M 1A and M 1B to achieve negative feedback. Therefore, Figure 1 the negative feedback circuit of the fully differential transimpedance amplifier circuit can improve the linearity of the fully differential transimpedance amplifier circuit and increase the linear input range when the input current increases, and vice versa. In other words, Figure 1 the negative feedback circuit can be connected to the first amplifier circuit and the second amplifier circuit and is configured to adjust the voltage at the input terminal according to the difference between the output voltage of the output terminal V INA and i INB when the input current i OUT1 and V OUT2 changes and the reference voltage V REF .

[0022] As Figure 1 shown, the negative feedback circuit consists of two sets of circuits operating independently (such as the first amplifier OP A and the third transistor M 3A connecting the input terminal of the first amplifier circuit to the output terminal V OUT1 , while the second amplifier OP B and the fourth transistor M 3B connecting the input terminal of the second amplifier circuit to the output terminal V OUT2 ), so the offset or error of the fully differential transimpedance amplifier circuit cannot be completely eliminated and requires a large power consumption. In addition, due to the third transistor M 3A and the fourth transistor M 3BThe drains are respectively connected to the input ends of the first amplifying circuit and the second amplifying circuit, thus increasing the input noise of the fully differential transimpedance amplifying circuit and reducing the bandwidth of the fully differential transimpedance amplifying circuit.

[0023] As Figure 2 shown is a schematic structural diagram of a fully differential transimpedance amplifying circuit according to an embodiment of the present disclosure. Figure 2 The fully differential transimpedance amplifying circuit in Figure 1 is similar to the fully differential transimpedance amplifying circuit in Figure 2 The negative feedback circuit only includes an amplifier OP 1 , and the drains of the third transistor M 3A and the fourth transistor M 3B are connected to one end of the first resistors R FA and R FB .

[0024] The amplifier OP 1 of the negative feedback circuit includes a first input end, a second input end, a third input end, a first output end and a second output end. The first input end of the amplifier OP 1 is connected to the output end V OUT1 of the first amplifying circuit, the second input end is connected to the reference voltage V REF , and the third input end is connected to the output end V OUT2 of the second amplifying circuit. The first output end of the amplifier OP 1 is connected to the gate of the third transistor M 3A , and the second output end is connected to the gate of the fourth transistor M 3B . The source of the third transistor M 3A of the negative feedback circuit is connected to the ground terminal GND, and the drain of the third transistor M 3A is connected to one end of the first resistor R FA of the first amplifying circuit. The source of the fourth transistor M 3B of the negative feedback circuit is connected to the ground terminal GND, and the drain of the fourth transistor M 3B is connected to one end of the first resistor R FB of the second amplifying circuit.

[0025] The optoelectronic signals received by the optoelectronic sensing device usually have a very large dynamic range. When the input current is large and exceeds the input range of the fully differential transimpedance amplifying circuit, the linearity performance of the fully differential transimpedance amplifying circuit will be reduced, thus limiting the application of the fully differential transimpedance amplifying circuit. For example, when the input currents i INA and i INB of the fully differential transimpedance amplifier increase, through the first resistors R FA and R FBThe current increases, causing the voltage across the first resistor R FA and R FB to increase. The voltage across the drain of the first transistors M 1A and M 1B and the current I LA and R LB in the branch where they are located increase. The voltage difference across the second resistors R 2A and I 2B increases, causing the output voltage of the output terminals V LA and R LB of the amplifier circuit to decrease, resulting in a decline in linearity performance. Due to the presence of the amplifier OP OUT1 and V OUT2 , by setting the reference voltage V 1 and amplifying the voltage difference between the reference voltage V REF and the output terminals V REF and V OUT1 and V OUT2 , the gate voltages of the third transistors M 3A and the fourth transistors M 3B are controlled to reduce the voltage between the drain and source of the third transistors M 3A and the fourth transistors M 3B , thereby compensating for and offsetting the increase in the voltage of the gates of the first transistors M 1A and M 1B to achieve negative feedback. Therefore, Figure 2 The negative feedback circuit of the fully differential transimpedance amplifier circuit can improve the linearity of the fully differential transimpedance amplifier circuit and increase the linear input range when the input current increases, and vice versa. In other words, Figure 2 The negative feedback circuit can be connected to the first amplifier circuit and the second amplifier circuit and is configured to adjust the voltage of the input terminal according to the difference between the output voltage of the output terminals V INA and i INB and the reference voltage V OUT1 and V OUT2 when the input current i REF changes.

[0026] As Figure 2 shown, the output terminals V OUT1 and V OUT2 of the fully differential transimpedance amplifier circuit share an amplifier OP 1 , which can enable the fully differential transimpedance amplifier circuit to operate evenly and greatly reduce (even basically eliminate) the offset or error of the fully differential transimpedance amplifier circuit. In addition, since Figure 2 the fully differential transimpedance amplifier circuit only requires one amplifier OP 1 , it is Figure 1The fully differential transimpedance amplifier circuit can have low power consumption. In addition, since Figure 2 the third transistor M of the fully differential transimpedance amplifier circuit 3A and the fourth transistor M 3B have drains that are not directly connected to the input terminals of the first amplifier circuit and the second amplifier circuit, the input noise of the fully differential transimpedance amplifier circuit can be reduced, and the bandwidth of the fully differential transimpedance amplifier circuit can be increased.

[0027] As Figure 3 shown is a schematic diagram of the circuit structure of the fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure. Figure 3 The fully differential transimpedance amplifier circuit in Figure 2 is similar to the fully differential transimpedance amplifier circuit in Figure 3 , and the main difference is that: 5A the first amplifier circuit of 5B also includes a fifth transistor M 5A , and the second amplifier circuit also includes a fifth transistor M 5A . The fifth transistor M 1A of the first amplifier circuit includes a source, a drain, and a gate. The source of the fifth transistor M 5A is connected to the drain of the first transistor M LA . The drain of the fifth transistor M 5A is connected to the first terminal of the second resistor R BA . The gate of the fifth transistor M 5B is connected to the bias voltage terminal V 5B and is used to receive a bias voltage. The fifth transistor M 1B of the second amplifier circuit includes a source, a drain, and a gate. The source of the fifth transistor M 5B is connected to the drain of the first transistor M LB . The drain of the fifth transistor M 5B is connected to the first terminal of the second resistor R BB . The gate of the fifth transistor M

[0028] where the bias voltage terminals V BA and V BB can be connected to an external bias circuit. The first transistor M 1A and the fifth transistor M 5A of the first amplifier circuit form a cascode amplification structure, and the first transistor M 1B and the fifth transistor M 5B of the second amplifier circuit form a cascode amplification structure, where the cascode amplification structure is a cascode structure. By setting the fifth transistors M 5A and M 5B to reduce the first transistor M1A and M 1B the impedance of the drain of, further improving the linearity of the fully differential transimpedance amplifier circuit.

[0029] Such as Figure 4 shown is a schematic circuit structure diagram of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure. Figure 4 The fully differential transimpedance amplifier circuit in Figure 3 is similar to the fully differential transimpedance amplifier circuit in 2A , and the main difference is that: the first amplifier circuit further includes an amplifier OP 2B . The input terminal of the amplifier OP 2A of the first amplifier circuit is connected to the source of the fifth transistor M 5A , and the output terminal of the amplifier OP 2A is connected to the gate of the fifth transistor M 5A . The input terminal of the amplifier OP 2B of the second amplifier circuit is connected to the source of the fifth transistor M 5B , and the output terminal of the amplifier OP 2B is connected to the gate of the fifth transistor M 5B .

[0030] The amplifier OP 2A of the first amplifier circuit and the fifth transistor M 5A form a negative feedback loop, and the first transistor M 1A , the fifth transistor M 5A and the amplifier OP 2A form a Regulated Cascode amplifier structure, where the Regulated Cascode amplifier structure is a regulated cascode structure. The amplifier OP 2B of the second amplifier circuit and the fifth transistor M 5B form a negative feedback loop, and the first transistor M 1B , the fifth transistor M 5B and the amplifier OP 2B form a Regulated Cascode amplifier structure, where the Regulated Cascode amplifier structure is a regulated cascode structure. This can further reduce the impedance of the drains of the first transistor M 1A and M 1B , and attenuate the adverse ripple voltage at the drains of the first transistor M 1A and M 1B , further improving the linearity of the fully differential transimpedance amplifier circuit.

[0031] Such as Figure 5 shown is a schematic circuit structure diagram of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure.Figure 5 The fully differential transimpedance amplifier circuit in Figure 2 is similar to the fully differential transimpedance amplifier circuit in 2A . The main difference is that the drain of the second transistor M of the first amplifier circuit 2B and the drain of the second transistor M of the second amplifier circuit 4B are connected to a current source. According to an embodiment of the present disclosure, the current source has a transistor M 4B . The gate of the transistor M BIB is connected to the bias voltage terminal V 4B , the source of the transistor M DD2 is connected to the second power supply terminal V 4B , and the drain of the transistor M 2A is connected to the drain of the second transistor M of the first amplifier circuit 2B and the drain of the second transistor M of the second amplifier circuit 4B . By adding the transistor M

[0032] As Figure 6 shown is a schematic diagram of the circuit structure of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure. Figure 6 The fully differential transimpedance amplifier circuit in Figure 3 combines the fully differential transimpedance amplifier circuit in Figure 5 with the fully differential transimpedance amplifier circuit in Figure 2 . For example, compared with the fully differential transimpedance amplifier circuit in Figure 6 , the fully differential transimpedance amplifier circuit in 5A also includes fifth transistors M 5B and M 4B , and transistor M Figure 6 . Therefore, the fully differential transimpedance amplifier circuit in Figure 2 can simultaneously have the advantages and effects of the fully differential transimpedance amplifier circuits in 3 and 5.

[0033] As Figure 7 shown is a schematic diagram of the circuit structure of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure. Figure 7 The fully differential transimpedance amplifier circuit in Figure 4 combines the fully differential transimpedance amplifier circuit in Figure 5 with the fully differential transimpedance amplifier circuit in Figure 2 . For example, compared with the fully differential transimpedance amplifier circuit in Figure 7 , the fully differential transimpedance amplifier circuit in 5A also includes fifth transistors M 5B and M 2A , amplifiers OP 2B and OP 4BTherefore, Figure 7 the fully differential transimpedance amplifier circuit in Figure 2 can simultaneously have 4 the advantages and effects of the fully differential transimpedance amplifier circuits in

[0034] For example, Figure 8 shown is a schematic circuit diagram of a fully differential transimpedance amplifier circuit according to an embodiment of the present disclosure. Figure 8 The fully differential transimpedance amplifier circuit in Figure 4 is similar to the fully differential transimpedance amplifier circuit in Figure 8 The amplifier OP in 1 has only two input terminals, which are respectively connected to the output terminals V OUT1 and V OUT2 of the fully differential transimpedance amplifier circuit. Among them, the output voltage of the amplifier OP 1 is a differential voltage signal.

[0035] In an embodiment of the present disclosure, the fully differential transimpedance amplifier circuit is formed using a CMOS process, a BiCMOS process, or a bipolar process, but is not limited thereto. The fully differential transimpedance amplifier circuit can be implemented in a single integrated device or using discrete components, and the specific implementation method can be selected according to the actual situation.

[0036] In summary, some embodiments of the present disclosure have at least the following effects: improving the linear input range and linearity of the fully differential transimpedance amplifier circuit, reducing the power consumption of the fully differential transimpedance amplifier circuit, and increasing the bandwidth of the fully differential transimpedance amplifier circuit. In addition, the circuit implementation conditions are simple.

[0037] An embodiment of the present disclosure further provides a communication device, which has a transmitting device and a receiving device, and the receiving device includes the above-mentioned Figures 1 to 8 transimpedance amplifier.

[0038] In some embodiments of the present disclosure, the receiving device can be an optical receiver, but is not limited thereto. For example, the fully differential transimpedance amplifier circuit can be used as the front end of a mixer.

[0039] Throughout this specification, references to "an embodiment of the present disclosure" or similar terms mean that a particular feature, structure, or characteristic described in connection with other embodiments is included in at least one embodiment and may not necessarily be present in all embodiments. Therefore, the corresponding occurrences of the phrase "an embodiment of the present disclosure" or similar terms throughout this specification do not necessarily refer to the same embodiment. In addition, the described particular features, structures, or characteristics of any particular embodiment can be combined with one or more other embodiments in any suitable manner. It should be understood that other variations and modifications of the embodiments described and illustrated herein are possible in view of the teachings herein and will be considered part of the spirit and scope of the present disclosure.

[0040] The technical content and features of this disclosure have been disclosed above. However, those skilled in the art may still make various substitutions and modifications that do not depart from the spirit of this disclosure based on the teachings and revelations of this disclosure. Therefore, the protection scope of this disclosure should not be limited to the content disclosed in the embodiments, but should include various substitutions and modifications that do not depart from this disclosure and are covered by the claims of this patent application.

Claims

1. A fully differential transimpedance amplifier circuit, comprising: A first amplifier circuit having an input terminal and an output terminal, the first amplifier circuit being configured to obtain an input current through the input terminal and generate an output voltage at the output terminal; A second amplifier circuit having an input terminal and an output terminal, the second amplifier circuit being configured to obtain an input current through the input terminal and generate an output voltage at the output terminal; and An amplifier having a first input terminal and a second input terminal, the first input terminal being connected to the output terminal of the first amplifier circuit and the second input terminal being connected to the output terminal of the second amplifier circuit; wherein the amplifier has a third input terminal configured to receive a reference voltage; The amplifier has a first output terminal configured to generate a first output signal according to the voltage difference between the first input terminal and the third input terminal; and The amplifier has a second output terminal configured to generate a second output signal according to the voltage difference between the second input terminal and the third input terminal.

2. The fully differential transimpedance amplifier circuit according to claim 1, wherein The amplifier is configured to adjust the voltage of the input terminal of the amplifier according to the first output signal when the input current obtained by the first amplifier circuit changes; and / or The amplifier is configured to adjust the voltage of the input terminal of the amplifier according to the second output signal when the input current obtained by the second amplifier circuit changes.

3. The fully differential transimpedance amplifier circuit according to claim 1, which further comprises: A first transistor, the gate of the first transistor being connected to the first output terminal of the amplifier, the source of the first transistor being connected to the ground terminal, and the drain of the first transistor being connected to the input terminal of the amplifier via a first resistor; and A second transistor, the gate of the second transistor being connected to the second output terminal of the amplifier, the source of the second transistor being connected to the ground terminal, and the drain of the second transistor being connected to the input terminal of the second amplifier via a second resistor.

4. The fully differential transimpedance amplifier circuit according to claim 1, wherein: The first amplifier circuit includes: A first transistor, the gate of the first transistor being connected to the input terminal of the first amplifier circuit, and the source of the first transistor being connected to the ground terminal; A second transistor, the gate of the second transistor being connected to the output terminal of the first amplifier circuit; A first resistor connected between the first input terminal and the source of the second transistor; and A second resistor, a first terminal of the second resistor being connected to the gate of the second transistor, and a second terminal of the second resistor being connected to a first current source; and The second amplifier circuit includes: A third transistor, the gate of the third transistor being connected to the input terminal of the second amplifier circuit, and the source of the third transistor being connected to the ground terminal; A fourth transistor, the gate of the fourth transistor being connected to the output terminal of the second amplifier circuit; A third resistor connected between the input terminal of the second amplifier circuit and the source of the fourth transistor; and A fourth resistor, a first terminal of the fourth resistor is connected to the gate of the fourth transistor, and a second terminal of the fourth resistor is connected to the first current source.

5. The fully differential transimpedance amplifier circuit according to claim 4, further comprising a second current source connected to the drain of the second transistor and the drain of the fourth transistor.

6. The fully differential transimpedance amplifier circuit according to claim 4, wherein the fully differential transimpedance amplifier circuit further comprises: A fifth transistor, a source of the fifth transistor is connected to a drain of the first transistor, and a drain of the fifth transistor is connected to a first terminal of the second resistor; and A sixth transistor, a source of the sixth transistor is connected to a drain of the third transistor, and a drain of the sixth transistor is connected to a first terminal of the fourth resistor.

7. The fully differential transimpedance amplifier circuit according to claim 6, wherein the fully differential transimpedance amplifier circuit further comprises: A first inverter amplifier, an input terminal of the first inverter amplifier is connected to the source of the fifth transistor, and an output terminal of the first inverter amplifier is connected to the gate of the fifth transistor; and A second inverter amplifier, an input terminal of the second inverter amplifier is connected to the source of the sixth transistor, and an output terminal of the second inverter amplifier is connected to the gate of the sixth transistor.

8. The fully differential transimpedance amplifier circuit according to any one of claims 1-7, wherein the fully differential transimpedance amplifier circuit further comprises: A first photo-sensing device, connected to the input terminal of the first amplifier circuit and configured to provide the input current to the first amplifier circuit; A second photo-sensing device, connected to the input terminal of the second amplifier circuit and configured to provide the input current to the second amplifier circuit.

9. The fully differential transimpedance amplifier circuit according to any one of claims 1-7, wherein, the fully differential transimpedance amplifier circuit is formed using a CMOS process, a BiCMOS process or a bipolar process.

10. A communication device having a receiving device, the receiving device comprising the fully differential transimpedance amplifier circuit according to any one of claims 1-9.

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