The location of the register in which the fault address is stored is incorporated into the memory device

Abstract

A memory device, comprising: a memory bank including a first memory cell connected to a first column selection line and a second memory cell connected to a second column selection line; a first column decoder selecting the first memory cell by sending a first column selection signal through the first column selection line in a first direction; and a second column decoder selecting the second memory cell by sending a second column selection signal through the second column selection line in a second direction opposite to the first direction. The first column decoder comprises a first register storing a first failure column address of the first memory cell, and a second register storing a second failure column address of the second memory cell.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2018-0066980 filed on June 11, 2018 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Apparatuses and devices consistent with the present disclosure relate to a memory device, and more particularly, to a memory device in which locations of registers storing failed addresses are merged. Background Art

[0004] Memory devices are widely used in electronic devices such as mobile devices, computers, etc. With the development of manufacturing process technology, the capacity of memory devices is increasing. With the development of miniaturization process technology, the number of failed memory cells of memory devices is gradually increasing. In order to repair the failed memory cells, the memory device may include redundant memory cells and registers storing failed addresses indicating the locations of the failed memory cells.

[0005] As the capacity of the memory device increases, the size of the memory cell array in the memory device may gradually increase. The memory device may include a circuit that drives the memory cell array on both sides. In the case where the register storing the fault address is deployed in all the above circuits, the area of ​​the memory device will increase. Summary of the invention

[0006] One aspect is to provide a memory device in which locations of registers storing failed addresses are merged.

[0007] According to an aspect of an exemplary embodiment, a memory device may include a memory bank including a first memory cell connected to a first column selection line and a second memory cell connected to a second column selection line; a first column decoder that selects the first memory cell by sending a first column selection signal through the first column selection line in a first direction; and a second column decoder that selects the second memory cell by sending a second column selection signal through the second column selection line in a second direction opposite to the first direction. The first column decoder may include: a first register that stores a first failed column address of the first memory cell; and a second register that stores a second failed column address of the second memory cell.

[0008] According to another aspect of the exemplary embodiment, a memory device may include a memory bank including a first memory cell connected to a first word line and a second memory cell connected to a second word line; a first row decoder that selects the first memory cell by sending a first row selection signal through the first word line in a first direction; and a second row decoder that selects the second memory cell by sending a second row selection signal through the second word line in a second direction opposite to the first direction. The first row decoder may include: a first register that stores a first failure row address of the first memory cell; and a second register that stores a second failure row address of the second memory cell.

[0009] According to another aspect of the exemplary embodiment, a memory device may include a first memory body, the first memory body including a first memory cell connected to a first column selection line, a first input / output line of the first memory cell being arranged in the first memory body; a second memory body, which includes a second memory cell connected to a second column selection line, the second input / output line of the second memory cell being arranged in the second memory body; a first column decoder, configured to select the first memory cell by sending a first column selection signal through the first column selection line in a first direction and perform a first data input / output on the first memory cell through the first input / output line; and a second column decoder, configured to select the second memory cell by sending a second column selection signal through the second column selection line in a second direction opposite to the first direction and perform a second data input / output on the second memory cell through the second input / output line, wherein the first column decoder includes: a first register, configured to store a first fault column address of the first memory cell in the first memory body; and a second register, configured to store a second fault column address of the second memory cell in the second memory body. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a memory device according to an exemplary embodiment;

[0011] Figure 2 is a diagram showing a method according to an exemplary embodiment Figure 1 A block diagram of a first column decoder and a second column decoder of a memory device;

[0012] Figure 3 is a diagram showing a method according to an exemplary embodiment Figure 1 A block diagram of a memory bank of a memory device;

[0013] Figure 4 is a detailed diagram showing a method according to an exemplary embodiment Figure 3 A block diagram of a memory bank;

[0014] Figure 5is a detailed diagram showing a method according to an exemplary embodiment Figure 4 A block diagram of a memory bank;

[0015] Figure 6 is a block diagram illustrating a memory device according to another exemplary embodiment;

[0016] Figure 7 is a diagram showing a method according to an exemplary embodiment Figure 6 A block diagram of a first row decoder and a second row decoder of a memory device;

[0017] Figure 8 is a block diagram illustrating a memory device according to another exemplary embodiment;

[0018] Fig. 9 is a block diagram illustrating a memory device according to another exemplary embodiment; and

[0019] Fig.10 is a block diagram illustrating a memory device according to another exemplary embodiment. DETAILED DESCRIPTION

[0020] Below, exemplary embodiments may be described in detail and clearly so that those having ordinary skill in the art can easily realize the inventive concept.

[0021] Figure 1 Memory device 100 may include a bank 110 , a first column decoder 120 , and a second column decoder 130 .

[0022] The memory body 110 may be a memory cell array including memory cells arranged or deployed along the X-axis and the Y-axis perpendicular to the X-axis. The memory cell MC may be connected to a word line WL and a bit line BL, wherein the word line WL is parallel to the X-axis and the bit line BL is parallel to the Y-axis. For example, the memory cell may include a dynamic random access memory (DRAM) cell, a static random access memory (SRAM) cell, a NAND flash memory cell, a NOR flash memory cell, a resistive random access memory (RRAM) cell, a ferroelectric random access memory (FRAM) cell, a phase change random access memory (PRAM) cell, a thyristor random access memory (TRAM) cell, and at least one of a magnetic random access memory (MRAM) cell. The following description provides a memory cell as a DRAM cell. However, this is only an example, and the inventive concept is not limited to the DRAM cell as described above. The memory bank 110 may include a first region 111 accessed by the first column decoder 120 and a second region 112 accessed by the second column decoder 130. Memory cells selected by the first column decoder 120 may be arranged or disposed in the first region 111. Memory cells selected by the second column decoder 130 may be arranged or disposed in the second region 112.

[0023] The first column decoder 120 may decode the input column address ICA, and may generate a first column selection signal based on the result of decoding the ICA. The first column decoder 120 may send the first column selection signal in the direction of the Y axis through the first column selection line CSL1, and may select a memory cell corresponding to the input column address ICA. The first column decoder 120 may drive, select, or activate the first column selection line CSL1 in the Y axis direction. Each of the first column selection lines CSL1 may be connected to at least one bit line.

[0024] The second column decoder 130 can decode the input column address ICA, and can generate a second column selection signal based on the result of decoding the ICA. The second column decoder 130 can send a second column selection signal through the second column selection line CSL2 in a direction opposite to the Y-axis direction (e.g., the positive Y-axis direction), and can select a memory cell corresponding to the input column address ICA. The second column decoder 130 can drive the second column selection line CSL2 in a direction opposite to the Y-axis direction. The same input column address ICA can be input to the first column decoder 120 and the second column decoder 130.

[0025] In the case of the related art in which the memory bank is driven only by a single column decoder, for example, in the case in which the memory bank 110 is driven only by the first column decoder 120 and not by the second column decoder 130, the first column decoder 120 should select the memory cells of the second region 112 and the memory cells of the first region 111, that is, all the memory cells of the memory bank 110. To this end, the first column decoder 120 should drive a column selection line whose length corresponds to the vertical length of the memory bank 110 (that is, the length on the Y axis). However, as the size of the memory bank 110 increases, the load of the column selection line may increase. In particular, for example, since the voltage of the column selection line (or the voltage of the column selection signal) is used to turn on or off the transistor connected to the bit line, the voltage may transition from the ground voltage to the power supply voltage, and vice versa. That is, as the size of the memory bank 110 increases, the driving capability of the first column decoder 120 with respect to the column selection line may deteriorate. Thus, the memory device 100 according to an exemplary embodiment may include a first column decoder 120 and a second column decoder 130, which drive one memory bank 110 in two directions (e.g., in opposite directions). The first column decoder 120 and the second column decoder 130 may be opposite to each other with respect to the memory bank 110, or may face each other with respect to the memory bank 110, the memory bank 110 may be inserted between the first column decoder 120 and the second column decoder 130, and the first column decoder 120 and the second column decoder 130 may be located at opposite sides or both sides of the memory bank 110, respectively.

[0026] refer to Figure 1 , the first column decoder 120 may include a first register 121, which stores a first failure column address FCA1 for repairing the first column selection line CSL1. When the input column address ICA matches the first failure column address FCA1, the first column decoder 120 may drive a redundant column selection line (not shown) instead of driving a column selection line corresponding to the input column address ICA.

[0027] The first column decoder 120 may further include a second register 122, which stores a second failed column address FCA2 for repairing the second column select line CSL2. When the input column address ICA matches the second failed column address FCA2, the second column decoder 130 may drive a redundant column select line (not shown) instead of driving a column select line corresponding to the input column address ICA.

[0028] In some exemplary embodiments, the first column decoder 120 may include a first register 121 for repairing the first column selection line CSL1 and a second register 122 for repairing the second column selection line CSL2, but the second column decoder 130 may not include the second register 122. Thus, the first column decoder 120 may share or merge a write circuit that writes the first fault column address FCA1 and the second fault column address FCA2 to the first register 121 and the second register 122, respectively. Moreover, the first column decoder 120 may share or merge a comparison circuit that compares the input column address ICA with the first fault column address FCA1 and a comparison circuit that compares the input column address ICA with the second fault column address FCA2. By sharing the write circuit and the comparison circuit and by simplifying the second column decoder 130, the area of ​​the memory device 100 may be reduced.

[0029] Figure 2 is a diagram showing a method according to an exemplary embodiment Figure 1 A block diagram of a first column decoder and a second column decoder of a memory device of FIG. Figure 1 describe Figure 2 The memory device 100 may include a memory bank 110, a first column decoder 120, a second column decoder 130, a row decoder 140, a command (CMD) decoder 150, and an antifuse array 160. Figure 1 The memory bank 110 is described, and thus a repeated description is omitted for the sake of brevity.

[0030] The first column decoder 120 may include a first register 121, a second register 122, a comparison circuit 125, a first redundant column select line (RCSL) enable circuit 126, a first column select line (CSL) enable circuit 127, and a fail column address (FCA) write circuit 128. Figure 1 The first register 121 and the second register 122 are described, and thus duplicate descriptions are omitted for the sake of brevity.

[0031] The comparison circuit 125 may compare the input column address ICA with one of the first and second fail column addresses FCA1 and FCA2. The first column decoder 120 may share or merge a comparison circuit comparing the input column address ICA with the first and second fail column addresses FCA1 and FCA2.

[0032] When the row decoder 140 selects the memory cell of the first region 111, the comparison circuit 125 may compare the input column address ICA with the first fail column address FCA1. When the input column address ICA matches the first fail column address FCA1, the comparison circuit 125 may generate a first hit signal Hit1. When the row decoder 140 selects the memory cell of the second region 112, the comparison circuit 125 may compare the input column address ICA with the second fail column address FCA2. When the input column address ICA matches the second fail column address FCA2, the comparison circuit 125 may generate a second hit signal Hit2.

[0033] The comparison circuit 125 may send the second hit signal Hit2 to the second column decoder 130. Based on the yield, area, and repair efficiency of the memory device 100, the first column decoder 120 may include one or more first registers 121 and one or more second registers 122. For example, in a case where the first register 121 and the second register 122 are distributed within the first column decoder 120, the comparison circuit 125 may send the second hit signal Hit2 to the second column decoder 130 across / through the memory body 110. For another example, in a case where the first register 121 and the second register 122 are concentrated in an area adjacent to both the first column decoder 120 and the row decoder 140, the comparison circuit 125 may send the second hit signal Hit2 to the second column decoder 130 across / through the row decoder 140. Depending on the number of the first register 121 and the second register 122, the first column decoder 120 may include one or more comparison circuits 125. Figure 2 , in which only one second hit signal Hit2 is transmitted to the second column decoder 130 . However, the one or more comparison circuits 125 may transmit one or more second hit signals (ie, buses) to the second column decoder 130 .

[0034] When the row decoder 140 activates one of the word lines of the first area 111, the first register 121 may provide the first fail column address FCA1 to the comparison circuit 125. When the row decoder 140 activates one of the word lines of the second area 112, the second register 122 may provide the second fail column address FCA2 to the comparison circuit 125. Whether each of the first register 121 and the second register 122 provides a related address may be determined depending on the position of the word line activated by the row decoder 140. The first fail column address FCA1 and the second fail column address FCA2 may be completely identical to or different from each other.

[0035] In an exemplary embodiment, it is assumed that at least one of the memory cells to be selected through the first column selection line CSL1 is a failed memory cell, and the column address corresponding to the first column selection line CSL1 is stored in the register 121 as the first failed column address FCA1. When a read command or a write command for the memory cell to be selected through the first column selection line CSL1 is input to the memory device 100, the comparison circuit 125 may activate the first hit signal Hit1. When the first hit signal Hit1 is activated, the first redundant column selection line (RCSL) enable circuit 126 may transmit the first redundant column selection signal in the Y-axis direction through the first redundant column selection line RCSL1. On the contrary, the first column selection line (CSL) enable circuit 127 may not transmit the first column selection signal in the Y-axis direction through the first column selection line CSL1.

[0036] Different from the above assumption, when the first hit signal Hit1 is not activated and one of the word lines of the first area 111 is activated by the row decoder 140, depending on the input column address ICA, the first column selection line (CSL) enable circuit 127 can send a first column selection signal in the Y-axis direction through the first column selection line CSL1. Figure 2 The first column select line CSL1 can be Figure 1 one of the first column select lines CSL1.

[0037] In summary, the first column decoder 120 may generate the first hit signal Hit1 based on the result of comparing the input column address ICA with the first fail column address FCA1. The first column decoder 120 may select a redundant memory cell through the first redundant column selection line RCSL1 by using the first hit signal Hit1, replacing the memory cell corresponding to the first fail column address FCA1 among the memory cells of the first region 111. That is, by using the first redundant column selection line RCSL1, the first column decoder 120 may select the memory cells other than the memory cells indicated by the first fail column address FCA1 in the first region 111 as redundant memory cells.

[0038] The fail column address (FCA) write circuit 128 may write the first fail column address FCA1 and the second fail column address FCA2 transmitted from the antifuse array 160 into the first register 121 and the second register 122, respectively. In addition to the first fail column address (FCA1) and the second fail column address FCA2, the fail column address (FCA) write circuit 128 may also write any other fail column address transmitted from the antifuse array 160 into any other register (not shown). For example, the fail column address (FCA) write circuit 128 may include a shift register that sequentially writes bits of the fail column address into a certain register.

[0039] The first column decoder 120 includes a fail column address (FCA) write circuit 128, but the second column decoder 130 does not include the fail column address (FCA) write circuit 128. The first column decoder 120 may share or merge a fail column address (FCA) write circuit that writes the first fail column address FCA1 to the first register 121 and a fail column address (FCA) write circuit that writes the second fail column address FCA2 to the second register 122.

[0040] The second column decoder 130 may include a second redundant column selection line (RCSL) enable circuit 136 and a second column selection line (CSL) enable circuit 137. In an exemplary embodiment, it is assumed that at least one of the memory cells that may be selected through the second column selection line CSL2 is a failed memory cell, and a column address corresponding to the second column selection line CSL2 is stored in the second register 122 as a second failed column address FCA2. When a read command or a write command for a memory cell to be selected through the second column selection line CSL2 is input to the memory device 100, the comparison circuit 125 may activate the second hit signal Hit2. When the second hit signal Hit2 generated by the comparison circuit 125 of the first column decoder 120 is activated, the second redundant column selection line (RCSL) enable circuit 136 may transmit the second redundant column selection signal in a direction opposite to the Y-axis direction through the second redundant column selection line RCSL2. That is, the second redundant column selection line (RCSL) enable circuit 136 may be implemented exactly the same as the first redundant column selection line (RCSL) enable circuit 126, except that the second redundant column selection line (RCSL) enable circuit 136 uses the second hit signal Hit2. When the second hit signal Hit2 is activated, the second column selection line (CSL) enable circuit 137 may not transmit the second column selection signal in the direction opposite to the Y-axis direction through the second column selection line CSL2.

[0041] Unlike the above assumption, when the second hit signal Hit2 is not activated and one of the word lines of the second area 112 is activated by the row decoder 140, the second column selection line (CSL) enable circuit 137 may send a second column selection signal in the opposite direction to the Y-axis direction through the second column selection line CSL2. Figure 2 The second column select line CSL2 is Figure 1 The second column select line (CSL) enable circuit 137 may be implemented identically to the first column select line (CSL) enable circuit 127.

[0042] In an exemplary embodiment, it is assumed that all of the first hit signals Hit1 and the second hit signals Hit2 are deactivated, and the same input column address ICA is provided to each of the first column decoder 120 and the second column decoder 130, respectively. The first redundant column selection line (RCSL) enable circuit 126 and the second redundant column selection line (RCSL) enable circuit 136 do not operate. When one of the word lines of the first region 111 is activated, the first column selection line (CSL) enable circuit 127 may transmit a first column selection signal in the Y-axis direction through the first column selection line CSL1. When one of the word lines of the second region 112 is activated, the second column selection line (CSL) enable circuit 137 may transmit a second column selection signal in the direction opposite to the Y-axis direction through the second column selection line CSL2.

[0043] In summary, the first column decoder 120 may generate the second hit signal Hit2 based on the result of comparing the input column address ICA with the second fail column address FCA2. The second column decoder 130 may select a redundant memory cell through the second redundant column selection line RCSL2 by using the second hit signal Hit2, replacing the memory cell corresponding to the second fail column address FCA2 among the memory cells of the second region 112. That is, the second column decoder 130 may select the memory cells of the second region 112 other than the memory cells corresponding to the second fail column address FCA2 as redundant memory cells. When the memory cells to be selected through the second column selection line CSL2 do not include the fail memory cells, the second column decoder 130 may select the memory cells through the second column selection line CSL2.

[0044] The row decoder 140 may decode the input row address IRA and may generate a row selection signal based on the result of the decoding. The row decoder 140 may transmit the row selection signal in the X-axis direction through the word line WL and may select a memory cell corresponding to the input row address IRA. The row decoder 140 may drive the word line WL in the X-axis direction. Figure 1-Figure 2Unlike the exemplary embodiment shown in , in some exemplary embodiments where the row decoder 140 is located on the left side of the memory bank 110, the row decoder 140 may drive the word line WL in a direction opposite to the X-axis direction. Data input / output associated with the memory cell selected by the row decoder 140 may be performed by the first column decoder 120 and the second column decoder 130 depending on the position of the selected memory cell.

[0045] The command (CMD) decoder 150 may control the first column decoder 120, the second column decoder 130, and the row decoder 140 in response to a command and an address CMD / ADD received from the outside of the memory device 100. The command (CMD) decoder 150 may control the first column decoder 120 and the second column decoder 130 in response to a read command, a write command, etc., and may transmit an input column address ICA to the first column decoder 120 and the second column decoder 130. The command (CMD) decoder 150 may control the row decoder 140 in response to an activate command, a precharge command, a refresh command, etc., and may transmit an input row address IRA to the row decoder 140. In an exemplary embodiment, the command (CMD) decoder 150 may be located closer to the first column decoder 120 than to the second column decoder 130, so that the first column decoder 120 is relatively closer to the command (CMD) decoder 150 than the second column decoder 130. Thus, the first column decoder 120 may be referred to as a "center column decoder" and the second column decoder 130 may be referred to as an "edge column decoder".

[0046] In an exemplary embodiment, the command (CMD) decoder 150 may generate a column selection line main signal CSLM in response to a read command or a write command. Figure 1-Figure 2 Unlike the example shown in , in some exemplary embodiments, the column selection line main signal CSLM may be generated by the first column decoder 120. When the first hit signal Hit1 is not activated before receiving the column selection line main signal CSLM, the first redundant column selection line (RCSL) enable circuit 126 may not transmit the first redundant column selection signal through the first redundant column selection line RCSL1. As in the above description, when the second hit signal Hit2 is not activated before receiving the column selection line main signal CSLM, the second redundant column selection line (RCSL) enable circuit 136 may not transmit the second redundant column selection signal through the second redundant column selection line RCSL2.

[0047] In an exemplary embodiment, the command (CMD) decoder 150 may transmit the column selection line main signal CSLM to the first redundant column selection line (RCSL) enable circuit 126 and the second redundant column selection line (RCSL) enable circuit 136 through the row decoder 140 or the memory bank 110, so that the time when the first redundant column selection line (RCSL) enable circuit 126 receives the column selection line main signal CSLM is the same as or similar to the time when the second redundant column selection line (RCSL) enable circuit 136 receives the column selection line main signal CSLM. Thus, the margin between the second hit signal Hit2 and the column selection line main signal CSLM when the second register 122 and the comparison circuit 125 are located in the first column decoder 120 may be the same as or similar to the margin between the second hit signal Hit2 and the column selection line main signal CSLM when the second register 122 and the comparison circuit 125 are located in the second column decoder 130.

[0048] The antifuse array 160 may provide or send a first fault column address FCA1 and a second fault column address FCA2 to a fault column address (FCA) write circuit 128. The antifuse array 160 may include antifuses in which the first fault column address FCA1 and the second fault column address FCA2 are programmed. The antifuse may be programmed from a high resistance state to a low resistance state (or vice versa). The programming operation of the antifuse may be performed when the dielectric of the antifuse is ruptured or not ruptured. Any other non-volatile memory cell such as a one-time programmable (OTP) memory cell may be used instead of the antifuse. For example, the antifuse array 160 may permanently store a fault row address FRA and a fault column address FCA (including a first fault column address FCA1 and a second fault column address FCA2) of the memory device 100.

[0049] Figure 3 is a diagram showing a method according to an exemplary embodiment Figure 1 A block diagram of a memory bank of a memory device. Figure 1 and Figure 2 Describe together Figure 3 The memory device 100 may include a memory bank 110, a first column decoder 120, and a second column decoder 130. Figure 1 The first column decoder 120 and the second column decoder 130 are described, and thus repeated descriptions will be omitted for the sake of brevity.

[0050] The memory cells connected to the first word line WL1 may be arranged in the first region 111 of the memory bank 110. The memory cells connected to the second word line WL2 may be arranged in the second region 112 of the memory bank 110. The number of memory cells connected to each of the first word line WL1 and the second word line WL2 is merely an example. One or more word lines may be further arranged in the first region 111 and the second region 112.

[0051] The switch 116_11 may electrically connect the first bit line BL1s and the local input / output line LIO1 depending on the voltage level of the first column selection line CSL1 or the first column selection signal. The switch 116_12 may electrically connect the first redundant bit line RBL1 and the local input / output line LIO1 depending on the voltage level of the first redundant column selection line RCSL1 or the first redundant column selection signal. The switch 116_21 may electrically connect the second bit line BL2 and the local input / output line LIO2 depending on the voltage level of the second column selection line CSL2 or the second column selection signal. The switch 116_22 may electrically connect the second redundant bit line RBL2 and the local input / output line LIO2 depending on the voltage level of the second redundant column selection line RCSL2 or the second redundant column selection signal. The switches 116_11, 116_12, 116_21, and 116_22 may be implemented identically to one another and may include one or more NMOS transistors, one or more PMOS transistors, or a combination of NMOS transistors and PMOS transistors. Connected to Figure 3 The number of bit lines for each of the switches 116_11 , 116_12 , 116_21 , and 116_22 shown in FIG. 1 is an example.

[0052] In an exemplary embodiment, the memory body 110 may further include a sense amplifier (not shown) that amplifies a voltage difference between the first bit line BL1 and the first bit bar line BLB1 (not shown). According to the open bit line structure, the first bit line BL1 and the first bit bar line BLB1 (not shown) may be located above and below the sense amplifier, respectively. The other bit lines RBL1, BL2, and RBL2 may be located the same as the first bit line BL1.

[0053] The input / output circuit 117_1 may perform data input / output between a local input / output line LIO1 and a global input / output line GIO. The input / output circuit 117_1 may include a PMUXON transistor, and when the memory device 100 receives a write command, the PMUXON transistor provides write data sent through the global input / output line GIO to the local input / output line LIO1. The input / output circuit 117_1 may include a local sense amplifier (LSA) or a switch, and when the memory device 100 receives a read command, the local sense amplifier (LSA) or the switch provides read data sent through the local input / output line LIO1 to the global input / output line GIO. The input / output circuit 117_2 may perform data input / output between the local input / output line LIO2 and the global input / output line GIO. The input / output circuits 117_1 and 117_2 may be implemented substantially identically to each other.

[0054] The first column decoder 120 may further include a write driver and input / output sense amplifier (WDRV&IOSA) 129. The write driver and input / output sense amplifier (WDRV&IOSA) 129 may perform an operation of writing data to or reading data from a memory cell through a global input / output line GIO, an input / output circuit 117_1, a local input / output line LIO1, a switch 116_11, and a first bit line BL1. When a failed memory cell is included in the above-mentioned memory cell, the write driver and input / output sense amplifier (WDRV&IOSA) 129 may write data to a redundant memory cell, or may read data stored in a redundant memory cell, through a global input / output line GIO, an input / output circuit 117_1, a local input / output line LIO1, a switch 116_12, and a first redundant bit line RBL1.

[0055] As in the above description, the write driver and input / output sense amplifier (WDRV&IOSA) 129 can perform an operation of writing data to or reading data from a memory cell through the global input / output line GIO, the input / output circuit 117_2, the local input / output line LIO2, the switch 116_21, and the second bit line BL2. When a failed memory cell is included in the above-mentioned memory cell; through the global input / output line GIO, the input / output circuit 117_2, the local input / output line LIO2, the switch 116_22, and the second redundant bit line RBL2, the write driver and input / output sense amplifier (WDRV&IOSA) 129 can write data to the redundant memory cell or can read data stored in the redundant memory cell.

[0056] In summary, memory cells located in the second region 112 may be selected by the second column decoder 130, but data input / output associated with the memory cells located in the second region 112 may be performed by the first column decoder 120. Memory cells connected to the first word line WL1 and memory cells connected to the second word line WL2 may share the global input / output line GIO.

[0057] In an exemplary embodiment, the number of each set consisting of a global input / output line GIO and a write driver and input / output sense amplifier (WDRV&IOSA) 129 may be determined depending on the following conditions supported by the memory device 100: the number of data input / output pads, burst length, etc. The number of each set consisting of a first column selection line CSL1 and a first column selection line (CSL) enable circuit 127 and the number of each set consisting of a second column selection line CSL2 and a second column selection line (CSL) enable circuit 137 may be determined depending on the following conditions of the memory device 100: capacity, page size, column address range, etc. Moreover, the memory body 110 may also include memory cells, redundant memory cells, bit lines, redundant bit lines, switches, local input / output lines, input / output circuits, and global input / output lines, which are Figure 3 Not shown.

[0058] In an exemplary embodiment, when at least one of the memory cells selected by the first word line WL1 and the first column selection line CSL1 fails, the first failure column address FCA1 may be stored in the first register 121. When at least one of the memory cells selected by the second word line WL2 and the second column selection line CSL2 fails, the second failure column address FCA2 may be stored in the second register 122. In the case where the column address corresponding to the first column selection line CSL1 and the column address corresponding to the second column selection line CSL2 are the same, the first failure column address FCA1 may be the same as the second failure column address FCA2. Of course, in the case where the column address corresponding to the first column selection line CSL1 and the column address corresponding to the second column selection line CSL2 are different, the first failure column address FCA1 may be different from the second failure column address FCA2.

[0059] Figure 4 is a detailed diagram showing a method according to an exemplary embodiment Figure 3 A block diagram of a memory bank of a memory device. Figures 1 to 3 describe Figure 4 The memory cells of the third region 113 of the memory bank 110 may be positioned between the first region 111 and the second region 112 with respect to the Y-axis and in a central region of the memory bank 110 .

[0060] Memory cells of the first region 111 may be selected only by the first column decoder 120. Memory cells of the second region 112 may be selected only by the second column decoder 130. In contrast, memory cells of the third region 113 may be selected by the first column decoder 120 or the second column decoder 130. Memory cell 113_1 among memory cells connected to the third word line WL3 may be selected by the first column decoder 120, and memory cell 113_2 among memory cells connected to the third word line WL3 may be selected by the second column decoder 130.

[0061] As in the memory cells of the first and second regions 111 and 112, the write driver and input / output sense amplifier (WDRV&IOSA) 129 may perform data input / output on the memory cells of the third region 113. However, the write driver and input / output sense amplifier (WDRV&IOSA) 129 may perform data input / output on the memory cells connected to the third word line WL3 through the global input / output line GIO, the input / output circuits 117_1 and 117_2, the local input / output lines LIO31 and LIO32, the switches 116_31 and 116_33, and the third bit line BL3. When a failed memory cell is included in the above-mentioned memory cells, the write driver and input / output sense amplifier (WDRV&IOSA) 129 can perform data input / output on the redundant memory cells connected to the third word line WL3 through the global input / output line GIO, input / output circuits 117_1 and 117_2, local input / output lines LIO31 and LIO32, switches 116_32 and 116_34, and the third redundant bit line RBL3.

[0062] The memory cells of the third region 113 may be part of the memory bank 110 and may be arranged substantially the same as the memory cells of the first region 111 and the second region 112. The first column decoder 120 and the second column decoder 130 should operate to select the memory cells of the third region 113. For example, in order to select the memory cells connected to the third word line WL3 after the third word line WL3 is activated, the first column selection line (CSL) enable circuit 127 and the second column selection line (CSL) enable circuit 137 may simultaneously drive the first column selection line CSL1 and the second column selection line CSL2.

[0063] Assume that the memory cells selected by the third word line WL3 and the first column selection line CSL1 and the second column selection line CSL2 include at least one faulty memory cell, and the faulty memory cell is repaired (i.e., column repair) by activating or selecting the first redundant column selection line RCSL1 and the second redundant column selection line RCSL2 instead of the first column selection line CSL1 and the second column selection line CSL2. In this case, the first column decoder 120 may not need to include both a register storing a column address corresponding to the first column selection line CSL1 and a register storing a column address corresponding to the second column selection line CSL2, and these registers may be shared or merged. Since the first column selection line CSL1 and the second column selection line CSL2 are activated at the same time, the first column decoder 120 may also include a third register 123 storing a column address corresponding to the first column selection line CSL1 and the second column selection line CSL2 as a third faulty column address FCA3. Here, the first to third faulty column addresses FCA1 to FCA3 may be the same as or different from each other. The third register 123 may receive a signal indicating whether one of the word lines belonging to the third region 113 is activated from the row decoder 140 , and may then provide the third fail column address FCA3 to the comparison circuit 125 .

[0064] When the input column address ICA matches the third fail column address FCA3, the comparison circuit 125 may generate a third hit signal Hit3. The first redundant column selection line (RCSL) enable circuit 126 and the second redundant column selection line (RCSL) enable circuit 136 may respectively activate the first redundant column selection line RCSL1 and the second redundant column selection line RCSL2 by using the third hit signal Hit3. The first column selection line (CSL) enable circuit 127 and the second column selection line (CSL) enable circuit 137 may not activate the first column selection line CSL1 and the second column selection line CSL2 based on the activated third hit signal Hit3.

[0065] In summary, the first column decoder 120 may generate the third hit signal Hit3 based on the result of comparing the input column address ICA with the third fail column address FCA3. The first column decoder 120 may select a redundant memory cell through the first redundant column selection line RCSL1 by using the third hit signal Hit3, instead of the memory cell corresponding to the third fail column address FCA3 among the memory cells 113_1 of the third region 113. That is, the first column decoder 120 may select the memory cells of the third region 113 other than the memory cells corresponding to the third fail column address FCA3 as redundant memory cells. The second column decoder 130 may select a redundant memory cell through the second redundant column selection line RCSL2 by using the third hit signal Hit3, instead of the memory cell corresponding to the third fail column address FCA3 among the memory cells 113_2 of the third region 113. That is, the second column decoder 130 may select the memory cells of the third region 113 other than the memory cells corresponding to the third fail column address FCA3 as redundant memory cells.

[0066] Figure 5 is a detailed diagram showing a method according to an exemplary embodiment Figure 4 A block diagram of a memory bank of a memory device. Figures 1 to 4 describe Figure 5 The memory cells of the fourth region 114 of the memory bank 110 may be located adjacent to the first column decoder 120. The memory cells of the fifth region 115 of the memory bank 110 may be located adjacent to the second column decoder 130. The memory cells of the fourth region 114 and the memory cells of the fifth region 115 may be located at edge regions of the memory bank 110, respectively, with respect to the Y axis.

[0067] The memory cells of the fourth region 114 may be selected by the first column decoder 120. The memory cells of the fifth region 115 may be selected by the second column decoder 130. However, according to the above-described open bit line structure, each of the number of memory cells connected to the fourth word line WL4 of the fourth region 114 and the number of memory cells connected to the fifth word line WL5 of the fifth region 115 may be, for example, half the number of memory cells connected to any word line of the first region 111 to the third region 113. The memory cells of the fourth region 114 and the memory cells of the fifth region 115 may be selected together. Figure 2 The row decoder 140 may simultaneously activate the fourth word line WL4 and the fifth word line WL5 in response to the active command or the refresh command. The first column decoder 120 and the second column decoder 130 may simultaneously drive the first column selection line CSL1 and the second column selection line CSL2.

[0068] As in the memory cells of the first to third regions 111 to 113, the write driver and input / output sense amplifier (WDRV&IOSA) 129 may perform data input / output on the memory cells of the fourth and fifth regions 114 and 115. The write driver and input / output sense amplifier (WDRV&IOSA) 129 may perform data input / output on the memory cells connected to the fourth and fifth word lines WL4 and WL5 through the global input / output line GIO, the input / output circuits 117_1 and 117_2, the local input / output lines LIO4 and LIO5, the switches 116_41 and 116_51, and the fourth and fifth bit lines BL4 and BL5. When a failed memory cell is included in the above-mentioned memory cell, the write driver and input / output sense amplifier (WDRV&IOSA) 129 can perform data input / output on the redundant memory cells connected to the fourth word line WL4 and the fifth word line WL5 through the global input / output line GIO, the input / output circuits 117_1 and 117_2, the local input / output lines LIO4 and LIO5, the switches 116_42 and 116_52, and the fourth redundant bit line RBL4 and the fifth redundant bit line RBL5.

[0069] Assume that at least one of the memory cells selected by the fourth word line WL4 and the fifth word line WL5 and the first column selection line CSL1 and the second column selection line CSL2 fails, and the failed memory cell is repaired (i.e., column repair) by activating the first redundant column selection line RCSL1 and the second redundant column selection line RCSL2 instead of the first column selection line CSL1 and the second column selection line CSL2. In this case, the first column decoder 120 may not need to include both a register storing a column address corresponding to the first column selection line CSL1 and a register storing a column address corresponding to the second column selection line CSL2, and the registers may be shared or merged. Since the first column selection line CSL1 and the second column selection line CSL2 are activated at the same time, the first column decoder 120 may also include a fourth register 124, which stores the column address corresponding to the first column selection line CSL1 and the second column selection line CSL2 as a fourth failed column address FCA4. Here, the fourth fail column address FCA4 may be the same as the first to third fail column addresses FCA1 to FCA3, may be completely the same as a portion of the first to third fail column addresses FCA1 to FCA3, or may be different from the first to third fail column addresses FCA1 to FCA3. The fourth register 124 may receive a signal indicating whether a portion of the word lines belonging to the fourth region 114 and the fifth region 115 are activated from the row decoder 140, and may then provide the fourth fail column address FCA4 to the comparison circuit 125.

[0070] When the input column address ICA matches the fourth fail column address FCA4, the comparison circuit 125 may generate a fourth hit signal Hit4. The first redundant column selection line (RCSL) enable circuit 126 and the second redundant column selection line (RCSL) enable circuit 136 may respectively activate the first redundant column selection line RCSL1 and the second redundant column selection line RCSL2 by using the fourth hit signal Hit4. The first column selection line (CSL) enable circuit 127 and the second column selection line (CSL) enable circuit 137 may not activate the first column selection line CSL1 and the second column selection line CSL2 based on the activated fourth hit signal Hit4.

[0071] In summary, the first column decoder 120 may generate the fourth hit signal Hit4 based on the result of comparing the input column address ICA with the fourth fail column address FCA4. The first column decoder 120 may select a redundant memory cell through the first redundant column selection line RCSL1 by using the fourth hit signal Hit4, instead of the memory cell corresponding to the fourth fail column address FCA4 in the memory cell 114_1 of the fourth region 114. That is, the first column decoder 120 may select the memory cell of the fourth region 114 other than the memory cell corresponding to the fourth fail column address FCA4 as a redundant memory cell. The second column decoder 130 may select a redundant memory cell through the second redundant column selection line RCSL2 by using the fourth hit signal Hit4, instead of the memory cell corresponding to the fourth fail column address FCA4 in the memory cell 115_1 of the fifth region 115. That is, the second column decoder 130 may select the memory cell of the fifth region 115 other than the memory cell corresponding to the fourth fail column address FCA4 as a redundant memory cell.

[0072] Figure 6 2 is a block diagram showing a memory device according to another exemplary embodiment. The memory device 200 may include a memory bank 210, a first row decoder 220, and a second row decoder 230. The memory bank 210 may be connected to a reference Figure 1 The memory cell arrays described are essentially the same.

[0073] The memory bank 210 may include a first region 211 accessed by the first row decoder 220 and a second region 212 accessed by the second row decoder 230. Memory cells selected by the first row decoder 220 may be arranged in the first region 211. Memory cells selected by the second row decoder 230 may be arranged in the second region 212. Memory cells of the memory bank 210 may be divided into the first region 211 and the second region 212 based on the X-axis direction and the direction opposite to the X-axis direction, which are directions in which the first row decoder 220 and the second row decoder 230 are driven, respectively.

[0074] The first row decoder 220 may decode the input row address IRA, and may generate a first row selection signal based on the result of the decoding. The first row decoder 220 may send the first row selection signal in the X-axis direction through the first word line WL1, and may select a memory cell. The first row decoder 220 may drive the first word line WL1 in the X-axis direction. The second row decoder 230 may decode the input row address IRA, and may generate a second row selection signal based on the result of the decoding; the second row decoder 230 may send the second row selection signal in the opposite direction to the X-axis direction, and may select a memory cell. The second row decoder 230 may drive the second word line WL2 in the opposite direction to the X-axis direction. The input row addresses received by the first row decoder 220 and the second row decoder 230 may be the same as each other.

[0075] In the case of the related art where the memory bank 210 is driven only by the first row decoder 220 and not by the second row decoder 230, the first row decoder 220 should select the memory cells of the second region 212 and the memory cells of the first region 211, that is, all the memory cells of the memory bank 210. To this end, the first row decoder 220 should drive a word line whose length corresponds to the horizontal length of the memory bank 210 (that is, the length on the X-axis). However, as the size of the memory bank 210 increases, the load of the word line of the first row decoder 220 may increase. In particular, since the voltage of the word line is used to turn on or off the cell transistor, the voltage may, for example, transition from a voltage lower than the ground voltage to a voltage higher than the power supply voltage, and vice versa. That is, as the size of the memory bank 210 increases, the driving capability of the first row decoder 220 relative to the word line may deteriorate. The memory device 200 according to an exemplary embodiment may include a first row decoder 220 and a second row decoder 230, which drive one memory bank 210 in two directions (for example, in opposite directions). As in the first column decoder 120 and the second column decoder 130, the first row decoder 220 and the second row decoder 230 may be opposite to each other with respect to the memory bank 210, or may face each other with respect to the memory bank 210. The memory bank 210 may be interposed between the first row decoder 220 and the second row decoder 230.

[0076] refer to Figure 6 , the first row decoder 220 may include a first register 221 storing a first fail row address FRA1 for repairing the first word line WL1. When the input row address IRA matches the first fail row address FRA1, the first row decoder 220 may drive the redundant word lines instead of driving the word lines (some of the first word lines WL1) corresponding to the input row address IRA matching the first fail row address FRA1.

[0077] The first row decoder 220 may include a second register 222 storing a second fail row address FRA2 for repairing the second word line WL2, and a first register 221. When the input row address IRA matches the second fail row address FRA2, the second row decoder 230 may drive a redundant word line (not shown) instead of driving word lines (some of the second word lines WL2) corresponding to the input row address IRA matching the second fail row address FRA2.

[0078] The first row decoder 220 may include a first register 221 for repairing the first word line WL1 and a second register 222 for repairing the second word line WL2. Thus, the first row decoder 220 may share or merge write circuits for writing the first fault row address FRA1 and the second fault row address FRA2 into the first register 221 and the second register 222, respectively. Moreover, the first row decoder 220 may share or merge a comparison circuit for comparing the input row address IRA with the first fault row address FRA1 and a comparison circuit for comparing the input row address IRA with the second fault row address FRA2. The second row decoder 230 may not include the second register 222. By sharing the write circuit and the comparison circuit and simplifying the second row decoder 230, the area of ​​the memory device 200 may be reduced.

[0079] Figure 7 It is shown Figure 6 Reference will be made to a block diagram of a first and second row decoder of a memory device. Figure 6 describe Figure 7 The memory device 200 may include a memory bank 210, a first row decoder 220, a second row decoder 230, a column decoder 240, a command (CMD) decoder 250, and an antifuse array 260. Figure 1 The memory bank 210 is described, and thus a repeated description is omitted for the sake of brevity.

[0080] The first row decoder 220 may include a first register 221, a second register 222, a comparison circuit 225, a first redundant word line (RWL) enable circuit 226, a first word line (WL) enable circuit 227, and a fail row address (FRA) write circuit 228. Figure 6 The first register 221 and the second register 222 are described, so the repeated description will be omitted for the sake of brevity. Figure 2 As in the memory device 100 of FIG. 1 , the memory device 200 may include a comparison circuit 225. In some example embodiments, the second row decoder 230 does not include a comparison circuit.

[0081] The comparison circuit 225 can be used with Figure 2The comparison circuit 225 functions in a similar manner to the comparison circuit 125 of FIG. The comparison circuit 225 may compare the input row address IRA with the first fault row address FRA1, and may compare the input row address IRA with the second fault row address FRA2. For example, the above comparison operations may be performed simultaneously. The first register 221 and the second register 222 may provide the first fault row address FRA1 and the second fault row address FRA2 to the comparison circuit 225 under the control of the command (CMD) decoder 250, wherein the command decoder 250 operates in response to an activation command or a refresh command. When the input row address IRA matches the first fault row address FRA1, the comparison circuit 225 may generate a first hit signal Hit1. When the input row address IRA matches the second fault row address FRA2, the comparison circuit 225 may generate a second hit signal Hit2.

[0082] In an exemplary embodiment, the comparison circuit 225 may send the second hit signal Hit2 to the second row decoder 230. Figure 2 The first column decoder 120 of the present invention may include one or more first registers 221 and one or more second registers 222. For example, in the case where the first register 221 and the second register 222 are distributed in the first row decoder 220, the comparison circuit 225 may send the second hit signal Hit2 to the second row decoder 230 across / through the memory bank 210. For another example, in the case where the first register 221 and the second register 222 are concentrated in an area adjacent to both the first row decoder 220 and the column decoder 240, the comparison circuit 225 may send the second hit signal Hit2 to the second row decoder 230 across / through the column decoder 240.

[0083] In an exemplary embodiment, the first row decoder 220 may include one or more comparison circuits 225 depending on the number of the first registers 221 and the second registers 222. Figure 7 , in which only one second hit signal Hit2 is transmitted to the second row decoder 230. However, the one or more comparison circuits 225 may transmit one or more second hit signals (ie, second hit buses) to the second row decoder 230.

[0084] The first redundant word line (RWL) enable circuit 226 and the first word line (WL) enable circuit 227 may operate similarly to the first redundant column select line (RCSL) enable circuit 126 and the first column select line (CSL) enable circuit 127. When the first hit signal Hit1 is activated, the first redundant word line (RWL) enable circuit 226 may transmit the first redundant row select signal in the X-axis direction through the first redundant word line RWL1 and may activate the first redundant word line RWL1 in the X-axis direction. When the first hit signal Hit1 is activated, the first word line (WL) enable circuit 227 may not activate the first word line WL1. When the first hit signal Hit1 is not activated, the first word line (WL) enable circuit 227 may transmit the first row select signal in the X-axis direction through the first word line WL1 and may activate the first word line WL1 in the X-axis direction depending on the input row address IRA. Figure 7 The first word line WL1 may be Figure 6 one of the first word lines WL1.

[0085] In an exemplary embodiment, it is assumed that at least one of the memory cells that can be selected by the first word line WL1 fails, and a row address corresponding to the first word line WL1 is stored as a first fail row address FRA1 in the first register 221. Even if an activation command or a refresh command for the memory cells selected by the first word line WL1 is input to the memory device 200, the first word line (WL) enable circuit 227 does not activate the first word line WL1 because the comparison circuit 225 activates the first hit signal Hit1.

[0086] In summary, the first row decoder 220 may generate the first hit signal Hit1 based on the result of comparing the input row address IRA with the first fail row address FRA1. The first row decoder 220 may select the redundant memory cells connected to the first redundant word line RWL1 by using the first hit signal Hit1, instead of the memory cells corresponding to the first fail row address FRA1 among the memory cells of the first region 211. That is, the first row decoder 220 may select the memory cells of the first region 211 other than the memory cells corresponding to the first fail row address FRA1 as redundant memory cells. When the memory cells connected to the first word line WL1 corresponding to the input row address IRA do not include the failed memory cells, the first row decoder 220 may select the memory cells connected to the first word line WL1.

[0087] The fail row address (FRA) write circuit 228 may write the first fail row address FRA1 and the second fail row address FRA2 transmitted from the antifuse array 260 to the first register 221 and the second register 222, respectively. The operation of the fail row address (FRA) write circuit 228 may be similar to Figure 2The operation of the fail column address (FCA) write circuit 128 is described below, and repeated discussion is omitted for the sake of brevity.

[0088] The second row decoder 230 may include a second redundant word line (RWL) enable circuit 236 and a second word line (WL) enable circuit 237. When the second hit signal Hit2 generated by the comparison circuit 225 of the first row decoder 220 is activated, the second redundant word line (RWL) enable circuit 236 may transmit a second redundant row selection signal in a direction opposite to the X-axis direction through the second redundant word line RWL2, and may drive the second redundant word line RWL2 in a direction opposite to the X-axis direction. The second redundant word line (RWL) enable circuit 236 may be implemented identically to the first redundant word line (RWL) enable circuit 226, except that the second redundant word line (RWL) enable circuit 236 uses the second hit signal Hit2.

[0089] When the second hit signal Hit2 is activated, the second word line (WL) enable circuit 237 may not activate the second word line WL2. When the second hit signal Hit2 is not activated, the second word line (WL) enable circuit 237 may transmit a second row selection signal in a direction opposite to the X-axis direction through the second word line WL2 and may activate the second word line WL2 in a direction opposite to the X-axis direction depending on the input row address IRA. Figure 7 The second word line WL2 may be Figure 6 The second word line (WL) enable circuit 237 may be implemented identically to the first word line (WL) enable circuit 227, except that the second word line (WL) enable circuit 237 uses the second hit signal Hit2.

[0090] Assume that at least one of the memory cells that can be selected by the second word line WL2 fails, and the row address corresponding to the second word line WL2 is stored as the second fail row address FRA2 in the second register 222. Even if an activation command or a refresh command for the memory cells selected by the second word line WL2 is input to the memory device 200, since the comparison circuit 225 activates the second hit signal Hit2, the second word line (WL) enable circuit 237 does not transmit the second row selection signal through the second word line WL2.

[0091] In summary, the first row decoder 220 may generate the second hit signal Hit2 based on the result of comparing the input row address IRA with the second fail row address FRA2. The second row decoder 230 may select the redundant memory cells connected to the second redundant word line RWL2 by using the second hit signal Hit2, instead of the memory cells corresponding to the second fail row address FRA2 among the memory cells of the second region 212. That is, the second row decoder 230 may select the memory cells of the second region 212 other than the memory cells corresponding to the second fail row address FRA2 as redundant memory cells. When the memory cells connected to the second word line WL2 corresponding to the input row address IRA do not include the failed memory cells, the second row decoder 230 may select the memory cells connected to the second word line WL2.

[0092] Similar to the first column decoder 120, the column decoder 240 can decode the input column address ICA and can generate a column selection signal based on the decoded result. The column decoder 240 can send the column selection signal in the Y-axis direction through the column selection line CSL. The column decoder 240 can drive the column selection line CSL in the Y-axis direction. Data input / output can be performed on the memory cell selected by the first row decoder 220 and the second row decoder 230 and the column decoder 240.

[0093] The operation of the command (CMD) decoder 250 may be similar to Figure 2 The command (CMD) decoder 150 may generate a word line main signal WLM in response to an activation command or a refresh command. Figure 6-Figure 7 , the word line main signal WLM may be generated by the first row decoder 220. When the first hit signal Hit1 is not activated before receiving the word line main signal WLM, the first redundant word line (RWL) enable circuit 226 may not be able to send the first redundant row selection signal through the first redundant word line RWL1. As in the above description, when the second hit signal Hit2 is not activated before receiving the word line main signal WLM, the second redundant word line (RWL) enable circuit 236 may not be able to send the second redundant row selection signal through the second redundant word line RWL2.

[0094] In an exemplary embodiment, the command (CMD) decoder 250 may transmit the word line master signal WLM to the first redundant word line (RWL) enable circuit 226 and the second redundant word line (RWL) enable circuit 236 through the column decoder 240 or the memory bank 210, so that the time when the first redundant word line (RWL) enable circuit 226 receives the word line master signal WLM is the same as or similar to the time when the second redundant word line (RWL) enable circuit 236 receives the word line master signal WLM. The second redundant word line (RWL) enable circuit 236 may receive the second hit signal Hit2 and the word line master signal WLM through the memory bank 210 or the column decoder 240, respectively. Thus, the margin between the second hit signal Hit2 and the word line main signal WLM when the second register 222 and the comparison circuit 225 are located within the first row decoder 220 may be the same as or similar to the margin between the second hit signal Hit2 and the word line main signal WLM when the second register 222 and the comparison circuit 225 are located within the second row decoder 230 .

[0095] In an exemplary embodiment, the command (CMD) decoder 250 may be located closer to the first row decoder 220 than to the second row decoder 230, such that the first row decoder 220 is relatively closer to the command (CMD) decoder 250 than the second row decoder 230. Thus, the first row decoder 220 may be referred to as a "center row decoder" and the second row decoder 230 may be referred to as an "edge row decoder."

[0096] The antifuse array 260 may provide or send the first fail row address FRA1 and the second fail row address FRA2 to the fail row address (FRA) write circuit 228. The operation of the antifuse array 260 may be similar to Figure 2 The operation of the antifuse array 160 is described below, and thus repeated descriptions are omitted for the sake of brevity.

[0097] Figure 8 is a block diagram showing a memory device according to another exemplary embodiment. Figures 1 to 7 describe Figure 8 The memory device 300 may include a memory bank 310, a first column decoder 320, a second column decoder 330, a first row decoder 340, and a second row decoder 350. The memory cells of the memory bank 310 may be divided into regions selected by the first column decoder 320, the second column decoder 330, and the first row decoder 340, and the second row decoder 350. The memory bank 310 may be a reference Figure 1 The memory cell array is described above, and thus repeated descriptions are omitted for the sake of brevity.

[0098] The first column decoder 320 may include a first register 321 and a second register 322, which store a first fail column address FCA1 and a second fail column address FCA2, respectively. The first column decoder 320 and the second column decoder 330 may be connected to the reference Figures 1 to 5 The first column decoder 120 and the second column decoder 130 are described to be substantially the same and may be opposite to each other with respect to the memory bank 310 or may face each other with respect to the memory bank 310. The memory bank 310 may be inserted between the first column decoder 320 and the second column decoder 330. The first row decoder 340 may include a first register 341 and a second register 342, which store a first failure row address FRA1 and a second failure row address FRA2, respectively. The first row decoder 340 and the second row decoder 350 may be connected to the reference Figure 6 and Figure 7 The first row decoder 220 and the second row decoder 230 are described to be substantially the same and may be opposite to each other with respect to the memory bank 310 or may face each other with respect to the memory bank 310. The memory bank 310 may be interposed between the first row decoder 340 and the second row decoder 350.

[0099] Fig. 9 Memory device 400 may include a first memory bank 410 , a first column decoder 420 , a first row decoder 430 , a second memory bank 460 , a second column decoder 470 , and a second row decoder 480 .

[0100] The first memory bank 410 may be a reference Figure 1 The second memory bank 460 may be a memory cell array independent of the first memory bank 410, and the memory cell array described in the embodiment of the present invention may be a memory cell array independent of the first memory bank 410. Figure 1 Therefore, for the sake of brevity, repeated descriptions are omitted. Fig. 9 As shown in FIG. 4 , the address transmission paths for accessing the first memory bank 410 and the second memory bank 460 may be shared or may not be shared. The addresses sent to access the memory cells of the first memory bank 410 and the second memory bank 460 are independent of each other.

[0101] The operations of the first row decoder 430 and the second row decoder 480 may be similar to the operations of the first row decoder 140 and the second row decoder 240 described above, respectively, and thus repeated descriptions are omitted for the sake of brevity. The operations of the first column decoder 420 may be similar to the operations of the first column decoder 120 described above, and thus repeated descriptions are omitted for the sake of brevity. The operations of the second column decoder 470 may be similar to the operations of the second column decoder 130 described above, and thus repeated descriptions are omitted for the sake of brevity. Figures 2 to 5Similar to the global input / output lines described above, the input / output lines controlled by the first column decoder 420 may be arranged in the first memory bank 410. Figures 2 to 5 Similar to the global input / output lines described above, the input / output lines controlled by the second column decoder 470 may be arranged in the second memory bank 460. The input / output lines of the first memory bank 410 and the input / output lines of the second memory bank 460 are independent of each other.

[0102] The first column decoder 420 may select a memory cell of the first memory bank 410 by transmitting a first column selection signal through a first column selection line CSL1 in the Y-axis direction, and may perform data input / output to the selected memory cell through an input / output line of the first memory bank 410. The second column decoder 470 may select a memory cell of the second memory bank 460 by transmitting a second column selection signal through a second column selection line CSL2 in a direction opposite to the Y-axis direction, and may perform data input / output to the selected memory cell through an input / output line of the second memory bank 460. The first column decoder 420 and the second column decoder 470 may be opposite to each other with respect to the first memory bank 410 and the second memory bank 460, or may face each other with respect to the first memory bank 410 and the second memory bank 460. The first memory bank 410 and the second memory bank 460 may be interposed between the first column decoder 420 and the second column decoder 470.

[0103] In an exemplary embodiment, the first column decoder 420 may include a first register 421 for repairing the first column selection line CSL1. The first column decoder 420 may include a second register 422 for repairing the second column selection line CSL2. Figure 2 When the first region 111 corresponds to the first memory bank 410, the operation of the first column decoder 420 may be similar to the operation of the first column decoder 120, and thus repeated descriptions are omitted for the sake of brevity. Figure 2 When the second area 112 corresponds to the second memory bank 460, the operation of the second column decoder 470 may be similar to the operation of the second column decoder 130, and therefore repeated descriptions are omitted for the sake of brevity. Since the write circuit for writing the first failure column address FCA1 and the second failure column address FCA2 is shared or merged, and since the comparison circuit for comparing the input column address ICA with the first failure column address FCA1 and the comparison circuit for comparing the input column address ICA with the second failure column address FCA2 are shared and merged, the area of ​​the memory device 400 may be reduced.

[0104] Fig.105 is a block diagram illustrating a memory device according to another exemplary embodiment. The memory device 500 may include a first memory bank 510, a first row decoder 520, a first column decoder 530, a second memory bank 560, a second row decoder 570, and a second column decoder 580. The first memory bank 510 and the second memory bank 560 may be connected to Fig. 9 The first memory bank 410 and the second memory bank 460 are substantially the same, and thus repeated descriptions are omitted for the sake of brevity. Each of the first column decoder 530 and the second column decoder 580 may be connected to Figure 7 The column decoders 240 of the memory device 500 are substantially the same, so repeated descriptions are omitted for the sake of brevity. The differences between the memory device 500 and the memory device 400 will be described.

[0105] The first row decoder 520 and the second row decoder 570 may be opposite to each other relative to the first memory bank 510 and the second memory bank 560, or may face each other relative to the first memory bank 510 and the second memory bank 560. The first memory bank 510 and the second memory bank 560 may be inserted between the first row decoder 520 and the second row decoder 570. The first row decoder 520 may include a first register 521 for repairing the first word line WL1. The first row decoder 520 may include a second register 522 for repairing the second word line WL2. Figure 6 When the first region 211 corresponds to the first memory bank 510, the operation of the first row decoder 520 may be similar to the operation of the first row decoder 220, and thus repeated descriptions are omitted for the sake of brevity. Figure 6 When the second region 212 of the memory cell 560 corresponds to the second memory cell 560, the operation of the second row decoder 570 may be similar to the operation of the second row decoder 230, and thus repeated descriptions are omitted for the sake of brevity. Since a write circuit for writing the first fail row address FRA1 and the second fail row address FRA2 is shared or merged, and since a comparison circuit for comparing the input row address IRA with the first fail row address FRA1 and a comparison circuit for comparing the input row address IRA with the second fail row address FRA2 are shared and merged, the area of ​​the memory device 500 may be reduced.

[0106] The memory devices 100, 200, 300, 400, and 500 according to various exemplary embodiments may merge the location of the register storing the failed address. Thus, the area of ​​the memory devices 100, 200, 300, 400, and 500 may be reduced.

[0107] While the present innovative concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present innovative concept as set forth in the following claims.

Claims

1. A memory device, comprising: a memory bank including a first memory cell connected to a first column select line and a second memory cell connected to a second column select line; a first column decoder configured to select the first memory cell by sending a first column select signal through the first column select line in a first direction; as well as a second column decoder configured to select the second memory cell by sending a second column select signal through the second column select line in a second direction opposite to the first direction, The first column decoder comprises: a first register configured to store a first failing column address of the first memory cell; as well as A second register is configured to store a second failing column address of the second memory cell.

2. The memory device of claim 1 , wherein the first column decoder further comprises: A comparison circuit is configured to compare an input column address with one of the first fail column address and the second fail column address.

3. The memory device of claim 2, wherein the first column decoder is configured to: generating a first hit signal based on a result of comparing the input column address with the first fail column address; and A first redundant memory cell is selected by using the first hit signal to replace a memory cell corresponding to the first failed column address among the first memory cells.

4. The memory device of claim 2, wherein the first column decoder is configured to: generating a second hit signal based on a result of comparing the input column address with the second fail column address; and sending the second hit signal to the second column decoder, and Wherein the second column decoder is configured as: A second redundant memory cell is selected by using the second hit signal to replace a memory cell corresponding to the second failed column address among the second memory cells.

5. The memory device of claim 2, further comprising: a command decoder configured to send the input column address to the first column decoder and the second column decoder, The command decoder is located closer to the first column decoder than to the second column decoder.

6. The memory device of claim 1, further comprising: an antifuse array, wherein the first fail column address and the second fail column address are programmed, The first column decoder further comprises: A write circuit is configured to write the first fail column address sent from the antifuse array to the first register, and write the second fail column address sent from the antifuse array to the second register.

7. The memory device of claim 1, wherein the memory bank further comprises: a third memory cell connected to a third word line and selected by the first column decoder; as well as a fourth memory cell connected to the third word line and selected by the second column decoder, The first column decoder further comprises: a third register configured to store third failing column addresses of the third memory cell and the fourth memory cell; and a comparison circuit configured to compare an input column address with the third fail column address, Wherein the first column decoder is configured as: generating a third hit signal based on a result of comparing the input column address with the third fail column address; sending the third hit signal to the second column decoder; and A third redundant memory cell is selected by using the third hit signal to replace a memory cell corresponding to the third failed column address among the third memory cells, and Wherein the second column decoder is configured as: A fourth redundant memory cell is selected by using the third hit signal transmitted from the first column decoder, replacing a memory cell corresponding to the third failed column address among the fourth memory cells.

8. The memory device of claim 1, wherein the memory bank further comprises: a fifth memory cell connected to a fourth word line and selected by the first column decoder; as well as a sixth memory cell connected to a fifth word line selected simultaneously with the fourth word line and selected by the second column decoder, The first column decoder further comprises: a fourth register configured to store fourth failing column addresses of the fifth memory cell and the sixth memory cell; and a comparison circuit configured to compare an input column address with the fourth fail column address, Wherein the first column decoder is configured as: generating a fourth hit signal based on a result of comparing the input column address with the fourth fail column address; sending the fourth hit signal to the second column decoder; and A fifth redundant memory cell is selected by using the fourth hit signal to replace a memory cell corresponding to the fourth failed column address among the fifth memory cells, and Wherein the second column decoder is configured as: A sixth redundant memory cell is selected by using the fourth hit signal transmitted from the first column decoder, replacing a memory cell corresponding to the fourth failed column address among the sixth memory cells.

9. The memory device of claim 1, wherein input / output lines of the first memory cell and the second memory cell are arranged in the memory bank, and The first column decoder performs data input / output on the first memory unit and the second memory unit through the input / output line.

10. A memory device comprising: a memory bank including a first memory cell connected to a first word line and a second memory cell connected to a second word line; a first row decoder configured to select the first memory cell by sending a first row select signal through the first word line in a first direction; as well as a second row decoder configured to select the second memory cell by sending a second row selection signal through the second word line in a second direction opposite to the first direction, Wherein the first row decoder comprises: a first register configured to store a first failing row address of the first memory cell; as well as A second register is configured to store a second failing row address of the second memory cell.

11. The memory device of claim 10, wherein the first row decoder further comprises: A comparison circuit is configured to compare an input row address with one of the first fail row address and the second fail row address.

12. The memory device of claim 11 , wherein the first row decoder is configured to: generating a first hit signal based on a result of comparing the input row address with the first fail row address; and A first redundant memory cell is selected by using the first hit signal to replace a memory cell corresponding to the first failed row address among the first memory cells.

13. The memory device of claim 11 , wherein the first row decoder is configured to: generating a second hit signal based on a result of comparing the input row address with the second fail row address; and sending the second hit signal to the second row decoder, and Wherein the second row decoder is configured as: A second redundant memory cell is selected by using the second hit signal to replace a memory cell corresponding to the second failed row address among the second memory cells.

14. The memory device of claim 11, further comprising: a command decoder configured to send the input row address to the first row decoder and the second row decoder, Wherein, the command decoder is located closer to the first row decoder than to the second row decoder.

15. The memory device of claim 10, further comprising: an antifuse array, wherein the first fail row address and the second fail row address are programmed, Wherein the first row decoder further comprises: A write circuit is configured to write the first fail row address sent from the antifuse array to the first register, and write the second fail row address sent from the antifuse array to the second register.

16. A memory device comprising: a first memory bank including a first memory cell connected to a first column selection line, a first input / output line of the first memory cell being arranged in the first memory bank; a second memory bank including a second memory cell connected to a second column selection line, a second input / output line of the second memory cell being arranged in the second memory bank; a first column decoder configured to select the first memory cell by sending a first column selection signal through a first column selection line in a first direction and perform first data input / output on the first memory cell through the first input / output line; as well as a second column decoder configured to select the second memory cell by sending a second column selection signal through a second column selection line in a second direction opposite to the first direction and perform second data input / output on the second memory cell through the second input / output line, The first column decoder comprises: a first register configured to store a first failing column address of the first memory cell in the first memory bank; as well as A second register is configured to store a second failing column address of the second memory cell in the second memory bank.

17. The memory device of claim 16, wherein the first column decoder further comprises: A comparison circuit is configured to compare the input column address with one of the first fail column address and the second fail column address.

18. The memory device of claim 17, wherein the first column decoder is configured to: generating a first hit signal based on a result of comparing the input column address with the first fail column address; and A first redundant memory cell is selected by using the first hit signal to replace a memory cell corresponding to the first failed column address among the first memory cells.

19. The memory device of claim 17, wherein the first column decoder is configured to: generating a second hit signal based on a result of comparing the input column address with the second fail column address; and sending the second hit signal to the second column decoder, and Wherein the second column decoder is configured as: A second redundant memory cell is selected by using the second hit signal to replace a memory cell corresponding to the second failed column address among the second memory cells.

20. The memory device of claim 16, further comprising: an antifuse array, wherein the first fail column address and the second fail column address are programmed, The first column decoder further comprises: A write circuit is configured to write the first fail column address sent from the antifuse array to the first register, and write the second fail column address sent from the antifuse array to the second register.

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