Semiconductor device, semiconductor package, and method for manufacturing semiconductor device

Abstract

A semiconductor device, a semiconductor package and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises: a first structure, the first structure comprises a first conductive pattern, the first conductive pattern is exposed at an upper portion of the first structure; a molding layer, the molding layer covers the first conductive pattern; a second structure, the second structure is located on the molding layer; and a through via, the through via passes through the second structure and the molding layer, the through via is electrically connected to the first conductive pattern, the through via comprises a first via portion located in the second structure and a second via portion located in the molding layer, the second via portion is connected to the first via portion, the upper portion of the second via portion has a first width, and the middle portion of the second via portion has a second width greater than the first width.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0068289 filed on June 14, 2018 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept relates to a semiconductor device including a through via, a semiconductor package, and / or a method of manufacturing the same. Background Art

[0004] Recently, the demand for lighter, smaller, faster, multifunctional and / or highly reliable products (e.g., mobile phones or laptop computers) in the electronics industry is increasing. In order to meet these requirements, research on semiconductor packaging technology is constantly being carried out. Integrated circuits manufactured using traditional wire bonding technology have some disadvantages, such as signal loss, relatively high power consumption and / or design restrictions on bonding wires. Therefore, a semiconductor chip stack has been developed and an integrated circuit packaging technology that is vertically connected to each other using through silicon vias (TSVs) has been developed to overcome the shortcomings of wire bonding technology. According to this technology, compared with wire bonding technology, highly integrated circuits can be realized on the same unit space and / or shorter circuit-to-circuit connections can be realized. Recently, various studies are being conducted to improve the reliability and electrical characteristics of semiconductor packages manufactured using TSV technology. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide semiconductor devices having enhanced reliability.

[0006] Some example embodiments of the inventive concepts provide a semiconductor package having enhanced reliability.

[0007] Some example embodiments of the inventive concepts provide methods of fabricating semiconductor devices having enhanced reliability.

[0008] According to an example embodiment of the inventive concept, a semiconductor device includes: a first structure, the first structure including a first conductive pattern, the first conductive pattern being exposed at an upper portion of the first structure; a mold layer, the mold layer covering the first conductive pattern; a second structure, the second structure being located on the mold layer; and a through via, the through via passing through the second structure and the mold layer, the through via being electrically connected to the first conductive pattern, the through via including a first via portion located in the second structure and a second via portion located in the mold layer, the second via portion being connected to the first via portion, an upper portion of the second via portion having a first width, and a middle portion of the second via portion having a second width greater than the first width.

[0009] According to an example embodiment of the present invention, a semiconductor package includes: a first semiconductor chip, the first semiconductor chip including a first conductive pattern, the first conductive pattern being exposed at an upper portion of the first semiconductor chip; a mold layer, the mold layer contacting the first conductive pattern and covering the first semiconductor chip; a second semiconductor chip, the second semiconductor chip being located on the mold layer; and a through via, the through via passing through the second semiconductor chip and the mold layer, the through via being electrically connected to the first conductive pattern, the through via including a first via portion located in the second semiconductor chip and a second via portion located in the mold layer, the second via portion being connected to the first via portion, an upper portion of the second via portion having a first width, and a middle portion of the second via portion having a second width greater than the first width.

[0010] According to an example embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a preliminary structure, the preliminary structure including a first structure, a mold layer, and a second structure, the first structure including a first conductive pattern, the first conductive pattern being exposed at an upper portion of the first structure, the mold layer covering the first conductive pattern, and the second structure being located on the mold layer; etching the second structure to form a first hole exposing the mold layer; etching the mold layer to form a second hole exposing the first conductive pattern and overlapping the first hole; and forming a through-via filling the first hole and the second hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A A cross-sectional view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated.

[0012] Figure 1B Shows the display Figure 1A Magnified view of a portion of IB.

[0013] Figures 2A to 2G FIG. 1 shows a method of manufacturing a device having a plurality of Figure 1A A cross-sectional view of a semiconductor device of the method of the cross-section.

[0014] FIG. 3A to FIG. 3D Cross-sectional views of semiconductor devices according to some other example embodiments of the inventive concepts are shown.

[0015] Figure 4 A cross-sectional view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated.

[0016] Figure 5 A cross-sectional view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated.

[0017] Figure 6 A cross-sectional view showing a semiconductor package according to example embodiments of the inventive concepts is illustrated. DETAILED DESCRIPTION

[0018] Some example embodiments of the present inventive concept will now be described in detail with reference to the accompanying drawings to help clearly explain the present inventive concept.

[0019] Figure 1A A cross-sectional view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 1B Shows the display Figure 1A Magnified view of a portion of IB.

[0020] Reference Figure 1A and Figure 1B , a semiconductor device 300 according to an example embodiment may include a first structure 100 and a second structure 200 stacked on the first structure 100. The semiconductor device 300 may be a component of a semiconductor package. The first structure 100 may be a first semiconductor chip or include a first semiconductor chip. The second structure 200 may be a second semiconductor chip or include a second semiconductor chip. The first structure 100 may include a first semiconductor substrate 1, a first transistor 5 disposed on the first semiconductor substrate 1, a first interlayer dielectric structure 10 having a plurality of dielectric layers and covering the first transistor 5, a first interconnection line 12 disposed in the first interlayer dielectric structure 10, and a first conductive pattern 14 electrically connected to the first interconnection line 12. The first conductive pattern 14 may be exposed at an upper portion of the first structure 100. The first semiconductor substrate 1 may be, for example, a single crystal silicon substrate or include, for example, a single crystal silicon substrate. The first interlayer dielectric structure 10 may include a plurality of dielectric layers, the plurality of dielectric layers including, for example, at least two or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous low-k dielectric layer. The first interconnection line 12 and the first conductive pattern 14 may include metal (eg, aluminum, copper, or tungsten).

[0021] The second structure 200 may include a second semiconductor substrate 22 and a second interlayer dielectric layer 20 . Figure 1A It is shown that the second semiconductor substrate 22 is disposed on the second interlayer dielectric layer 20, but the second semiconductor substrate 22 and the second interlayer dielectric layer 20 may exchange their positions with each other. Although not shown, the second transistor may be disposed on the second semiconductor substrate 22. The second interlayer dielectric structure 20 may have a plurality of dielectric layers. Although not shown, a multilayer second interconnect line may be disposed in the second interlayer dielectric layer 20. The first capping layer 24 may be disposed on the second semiconductor substrate 22. The second semiconductor substrate 22 may be, for example, a single crystal silicon substrate or include, for example, a single crystal silicon substrate. The second interlayer dielectric structure 20 may include a plurality of layers, the plurality of layers including, for example, at least two or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous low-k dielectric layer.

[0022] The mold layer 150 may be arranged between the first structure 100 and the second structure 200. The mold layer 150 may include a material having an etching selectivity relative to a material (e.g., silicon, silicon nitride, silicon oxide, silicon oxynitride) constituting at least the second structure 200. The mold layer 150 may include a polymeric material. For example, the mold layer 150 may have a low dielectric constant equal to or less than about 3. The mold layer 150 may include, for example, at least one of a fluorine-based polymer, a fluorocarbon polymer, a polar polymer, and a non-polar polymer. The mold layer 150 may include a non-conductive film (NCF), a thermosetting resin, or a photocurable resin. The mold layer 150 may be a viscous adhesive layer or include a viscous adhesive layer.

[0023] The first hole 26a may be provided in the second structure 200. The second hole 26b may be provided in the mold layer 150 and overlap the first hole 26a. The width of the first hole 26a may decrease as it approaches the mold layer 150. The second hole 26b may have a curved side surface. For example, the side surface of the second hole 26b may have a sidewall profile similar to a portion of an elliptical shape.

[0024] The through-via TSV may be disposed in the first hole 26a and the second hole 26b. The through-via TSV may include a first via portion 32a1 disposed in the first hole 26a and a second via portion 32a2 and a third via portion 32a3 disposed in the second hole 26b. The first via portion 32a1, the second via portion 32a2, and the third via portion 32a3 may be connected into a single integral body. The second via portion 32a2 may have a first width W1 at its upper portion and a second width W2 at its middle portion (see Figure 1B). The first width W1 may be smaller than the second width W2. The third via portion 32a3 may be adjacent to the first conductive pattern 14. The third via portion 32a3 may have a third width W3 at its bottom end. The third width W3 may be smaller than the second width W2. The through via TSV may include a metal, such as aluminum, copper, and / or tungsten. The second via portion 32a2 and the third via portion 32a3 may also be collectively referred to as a landing pad.

[0025] The via insulating pattern 28a may cover the sidewall of each of the first hole 26a and the second hole 26b. The via insulating pattern 28a may have a portion disposed between the second via portion 32a2 and the first conductive pattern 14. The via diffusion interruption pattern 30a may include a first portion disposed between the through via TSV and the via insulating pattern 28a and a second portion disposed between the through via TSV and the first conductive pattern 14. The via insulating pattern 28a may be formed of a dielectric layer (e.g., a silicon layer, a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer). The via diffusion interruption pattern 30a may include a metal nitride layer, e.g., a titanium nitride layer, a tungsten nitride layer, or a tantalum nitride layer.

[0026] The second conductive pattern 34 may be disposed on the through-hole via TSV. The second cover layer 36 may be disposed on the first cover layer 24 and partially expose the second conductive pattern 34 therethrough. The second conductive pattern 34 may include a metal, such as aluminum, copper, and / or tungsten. The first cover layer 24 may be formed of a dielectric layer (e.g., a silicon nitride layer or a silicon oxide layer) or include a dielectric layer (e.g., a silicon nitride layer or a silicon oxide layer). The second cover layer 36 may be formed of, for example, a silicon nitride layer or a polyimide layer or include, for example, a silicon nitride layer or a polyimide layer.

[0027] Figures 2A to 2G FIG. 1 shows a method of manufacturing a device having a plurality of Figure 1A A cross-sectional view of a semiconductor device of the method of the cross-section.

[0028] Reference Figure 2A, a first structure 100 can be provided. The first structure 100 may include a first semiconductor substrate 1, a first transistor 5 disposed on the first semiconductor substrate 1, a first interlayer dielectric structure 10 having a plurality of dielectric layers and covering the first transistor 5, a first interconnection line 12 disposed in the first interlayer dielectric structure 10, and a first conductive pattern 14 electrically connected to the first interconnection line 12. The first conductive pattern 14 may be exposed at the upper portion of the first structure 100. A mold layer 150 may be formed on the first structure 100. The mold layer 150 may be formed of a polymer material. For example, the mold layer 150 may have a low dielectric constant equal to or less than about 3. The mold layer 150 may include, for example, at least one of a fluorine-based polymer, a fluorocarbon polymer, a polar polymer, and a non-polar polymer. The mold layer 150 may include a non-conductive film (NCF), a thermosetting resin, or a photocurable resin. The mold layer 150 may be a viscous adhesive layer or include a viscous adhesive layer.

[0029] The formation of the mold layer 150 may include: coating a thermosetting resin solution or a polymer resin solution on the first structure 100, and then providing heat or light to cure the thermosetting resin solution or the polymer resin solution. In some example embodiments, the mold layer 150 may be an adhesive layer that can be attached to the first structure 100. The second structure 200 may be connected to the first structure 100 through the mold layer 150. The second structure 200 may include a second semiconductor substrate 22 and a second interlayer dielectric layer 20. In order to bond the second structure 200 to the mold layer 150, a plasma treatment using oxygen or the like may be performed on the surface of the mold layer 150. Therefore, the mold layer 150 may have an increased bonding energy at its surface. After the second structure 200 is placed on the mold layer 150, the second structure 200 may be heat-pressed and bonded to the mold layer 150. When the mold layer 150 is an adhesive layer, the second structure 200 may adhere to the mold layer 150.

[0030] Reference Figure 2B , a first capping layer 24 may be formed on the second structure 200. The first capping layer 24 may be patterned using a mask pattern (not shown). The second structure 200 may be etched using the first capping layer 24 and the mask pattern (not shown) as an etching mask to form a first hole 26a exposing the mold layer 150. At this stage, the second semiconductor substrate 22 and the second interlayer dielectric layer 20 may be continuously etched. During the formation of the first hole 26a, the mask pattern (not shown) may be completely etched and removed. An anisotropic etching process may be used to etch the second structure 200. When etching the second structure 200, the mold layer 150 may be used as an etching stop layer.

[0031] Reference Figure 2C, the mold layer 150 can be etched at the portion exposed by the first hole 26a, so the second hole 26b can be formed to expose the first conductive pattern 14. The etching of the mold layer 150 can be performed by using an isotropic etching process in which a first etchant is used. The first etchant may include a material having a contact angle of about 10 to 65 degrees relative to the second structure 200 including a silicon layer, a silicon oxide layer and a silicon nitride layer and the mold layer 150. The first etchant may include, for example, at least one of isopropyl alcohol and acetone. The shape of the second hole 26b can be determined by controlling or selecting the thickness of the mold layer 150, the concentration of the first etchant, the contact angle of the first etchant, the duration of the first etchant, etc. The second hole 26b can be formed to have a rounded sidewall. Because the mold layer 150 is etched by an isotropic etching process, etching damage or significant etching damage will not be caused to the surface of the first conductive layer 14 during the isotropic etching process. Therefore, the problem of not opening or incomplete etching can be solved. The isotropic etching process may have the effect of cleaning the surface of the first conductive pattern 14 exposed by the second hole 26b. As a result, the cleaning process may be omitted, thereby simplifying the manufacturing process. In addition, the manufacturing yield may be improved.

[0032] Reference Figure 2D , you can Figure 2C A via dielectric layer 28 is conformally formed on the resulting structure. The via dielectric layer 28 may be formed of at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The via dielectric layer 28 may cover the inner sidewalls of the first hole 26a and the second hole 26b and the top surface of the first conductive pattern 14.

[0033] Reference Figure 2E The via dielectric layer 28 may undergo an anisotropic etching process to form a via insulating pattern 28a, thereby exposing a top surface of the first capping layer 24 and exposing a portion of a top surface of the first conductive pattern 14. A portion of the via insulating pattern 28a may contact the top surface of the first conductive pattern 14.

[0034] Reference Figure 2F , you can Figure 2E A via diffusion interruption layer 30 is conformally formed on the resulting structure. A via conductive layer 32 may be stacked on the via diffusion interruption layer 30 to fill the first hole 26a and the second hole 26b. The via diffusion interruption layer 30 may include a metal nitride layer, for example, a titanium nitride layer, a tantalum nitride layer, or a tungsten nitride layer.

[0035] Reference Figure 2GA chemical mechanical polishing (CMP) process may be performed to remove the via diffusion interruption layer 30 and the via conductive layer 32 formed on the first capping layer 24, thereby forming a via diffusion interruption pattern 30a and a through via TSV disposed in the first and second holes 26a and 26b.

[0036] Return to reference Figure 1A , a second conductive pattern 34 and a second capping layer 36 may be formed on the through-hole via TSV. The second conductive pattern 34 may be formed by depositing a conductive layer and patterning the conductive layer. A portion of the second conductive pattern 34 may be shaped like a redistribution layer. For example, the portion of the second conductive pattern 34 may extend to be electrically connected to at least one second interconnect line (not shown) provided in the second structure 200. A second capping material (not shown) may be provided on the second conductive pattern 34 and on the first capping layer 24, and the second capping material may be patterned to define a second capping layer 36, thereby exposing the second conductive pattern 34 through the second capping layer 36. The second capping layer 36 may be formed of, for example, a silicon nitride layer or a polyimide layer. The semiconductor device 300 may be manufactured by the above process.

[0037] FIG. 3A to FIG. 3D Cross-sectional views of semiconductor devices according to some other example embodiments of the inventive concepts are shown.

[0038] Reference Figure 3A In the semiconductor device 300a according to example embodiments, the through via TSV may not include Figure 1A Therefore, the via insulating pattern 28a may not be arranged between the first conductive pattern 14 and the second via portion 32a2 of the through via TSV. Other configurations may be the same as those described above. Figure 1A and Figure 1B The configuration described is the same or substantially similar. Due to the increase in the contact area between the through via TSV and the first conductive pattern 14, the semiconductor device 300a according to this example embodiment can have a reduced contact resistance. Therefore, the semiconductor device 300a can have improved contact reliability. As a result, the power consumption of the semiconductor device 300a can be reduced, and its reliability can be improved.

[0039] Reference Figure 3B In the semiconductor device 300b according to the example embodiment, the thickness of the mold layer 150 may be relatively small. The sidewall profile of the second hole 26b may vary according to the thickness of the mold layer 150. For example, the second hole 26b may have a sidewall profile similar to a portion of a trapezoid or a semicircle. Other configurations may be similar to those described above with reference to Figure 1A and Figure 1B The structures described are the same or substantially similar.

[0040] Reference Figure 3C In the semiconductor device 300c according to example embodiments, the through via TSV may not include Figure 3B Therefore, the via insulating pattern 28a may not be arranged between the first conductive pattern 14 and the second via portion 32a2 of the through via TSV. Other configurations may be the same as those described above. Figure 3A The structures described are the same or substantially similar.

[0041] Reference Figure 3D In the semiconductor device 300d according to example embodiments, in the second structure 200, the via insulating pattern 28a may partially contact the bottom surface of the second interlayer dielectric layer 20. Other configurations may be the same as those described above with reference to Figure 3A The structures described are the same or substantially similar.

[0042] like Figure 1A and FIG. 3A to FIG. 3D As shown, by controlling or selecting at least one of the thickness of the mold layer 150, the conditions of the anisotropic etching process, the concentration of the etchant used in the isotropic etching process, and the contact angle and duration of the etchant, the through-via TSV can be formed into various shapes. In this way, the shape and size of the second via portion 32a2 of the through-via TSV can be controlled. Therefore, the contact reliability can be improved, and the contact resistance can be reduced by ensuring a sufficient contact area.

[0043] Figure 4 A cross-sectional view of a semiconductor device according to example embodiments of the inventive concepts is illustrated.

[0044] Reference Figure 4 , a semiconductor device 300e according to an example embodiment may include a second structure 200a and a first structure 100a located on the second structure 200a. The second structure 200a may include a semiconductor substrate 1, a device isolation layer 3, a transistor 5, and a first interlayer dielectric layer 10a, and the first interlayer dielectric layer 10a covers the semiconductor substrate 1, the device isolation layer 3, and the transistor 5. The second structure 200a may also include a first covering layer 24a covering the bottom surface of the semiconductor substrate 1. A mold layer 15 may be disposed between the first structure 100a and the second structure 200a. The mold layer 15 may be disposed on the first interlayer dielectric layer 10a. The mold layer 15 may include, for example, a polymer layer or a silicon nitride layer.

[0045] The first structure 100a may include conductive patterns 14 and 12a to 12d, a second interlayer dielectric layer 10b covering the conductive patterns 14 and 12a to 12d, a third interlayer dielectric layer 10c and a fourth interlayer dielectric layer 10d, and an upper passivation layer 13. The conductive patterns 14 and 12a to 12d may include a first conductive pattern 14, a second conductive pattern 12a, a third conductive pattern 12b, a fourth conductive pattern 12c and a fifth conductive pattern 12d. The first conductive pattern 14 and the second conductive pattern 12a may be located at the same level and spaced apart from each other. The second conductive pattern 12a may be electrically connected to the transistor 5.

[0046] The conductive pad 16 may be disposed on the fifth conductive pattern 12d. The upper conductive pillar 17 may be disposed on and in contact with the conductive pad 16. The upper conductive bump 18 may be disposed on and in contact with the upper conductive pillar 17.

[0047] The through via TSV may pass through the second structure 200a and the mold layer 15, and contact the first conductive pattern 14. For example, the through via TSV may have a Figure 3C The through via TSV may include a first via portion 32a1 disposed in a first hole 26a formed in the second structure 200a and a second via portion 32a2 disposed in a second hole 26b formed in the mold layer 15. The via insulating pattern 28a may include portions covering respective sidewalls of the first hole 26a and the second hole 26b. The via diffusion interruption pattern 30a may be disposed between the via insulating pattern 28a and the through via TSV.

[0048] The redistribution pattern 35 may be disposed under the first cover layer 24a. The redistribution pattern 35 may contact the through via TSV. The first cover layer 24a may be covered by the second cover layer 37. The redistribution pattern 35 may have a portion in contact with the lower conductive pillar 38. The lower conductive pillar 38 may pass through the second cover layer 37 and protrude outward. The lower conductive bump 39 may be disposed under the lower conductive pillar 38 and may contact the lower conductive pillar 38. Other structural features may be the same as those of reference 1. Figure 1A and Figure 1B The structural features described are the same or substantially similar.

[0049] The following describes the manufacturing Figure 4A method for forming a semiconductor device 300e. A device isolation layer 3 may be formed in a semiconductor substrate 1. A transistor 5 may be formed on the semiconductor substrate 1. A first interlayer dielectric layer 10a may be formed to cover the semiconductor substrate 1. A mold layer 15 may be formed on the first interlayer dielectric layer 10a. A first conductive pattern 14 and a second conductive pattern 12a may be formed on the mold layer 15. A second interlayer dielectric layer 10b, a third conductive pattern 12b, a third interlayer dielectric layer 10c, a fourth conductive pattern 12c, a fourth interlayer dielectric layer 10d, and a fifth conductive pattern 12d may be sequentially formed on the first conductive pattern 14 and the second conductive pattern 12a. An upper passivation layer 13 may be formed on the fifth conductive pattern 12d and on the fourth interlayer dielectric layer 10d, and then the upper passivation layer 13 may be patterned to expose the fifth conductive pattern 12d. A conductive pad 16 may be formed on the upper passivation layer 13 to contact the fifth conductive pattern 12d. An upper conductive pillar 17 and an upper conductive bump 18 may be sequentially formed on the conductive pad 16 .

[0050] A first capping layer 24a may be formed on the bottom surface of the semiconductor substrate 1. The first capping layer 24a and the second structure 200a may be anisotropically etched in sequence to form a first hole 26a exposing the mold layer 15. An isotropic etching process may be performed to etch the mold layer 15 exposed by the first hole 26a, thereby forming a second hole 26b exposing the first conductive pattern 14. Figure 2D to Figure 2G The through-via TSV may be formed by a process that is the same as or substantially similar to the process described above. A redistribution pattern 35 may be formed under the first cover layer 24a to contact the through-via TSV. A second cover layer 37 may be formed under the first cover layer 24a, and the second cover layer 37 may cover the redistribution pattern 35. A lower conductive pillar 38 and a lower conductive bump 39 may be formed on the redistribution pattern 35.

[0051] Figure 5 A cross-sectional view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated.

[0052] Reference Figure 5 , the semiconductor device 300f according to the embodiment may include a mold layer 15a disposed in the first interlayer dielectric layer 10a. The mold layer 15a may be made of Figure 1A and Figure 1B The second structure 200a may include a semiconductor substrate 1 and a device isolation layer 3. The through via TSV may pass through the mold layer 15a and the semiconductor substrate 1 and the device isolation layer 3 of the second structure 200a, and contact the first conductive pattern 14. Other structural features may be the same as those described above with reference to Figure 4 The through via TSV may have the same or substantially similar structural features as described above. Figure 3AThe through vias TSV shown have the same or substantially similar shapes.

[0053] Figure 5 The manufacturing of the semiconductor device 300f can be similar to Figure 4 The manufacturing of the semiconductor device 300e may be different from the manufacturing of the semiconductor device 300e in that the mold layer 15a is formed in the first interlayer dielectric structure 10a.

[0054] Figure 6 A cross-sectional view of a semiconductor package according to example embodiments of the inventive concepts is illustrated.

[0055] Reference Figure 6 , a semiconductor package 1000 according to an example embodiment may include a first semiconductor chip 100c, a second semiconductor chip 200c mounted below the first semiconductor chip 100c, and a third semiconductor chip 400 mounted below the second semiconductor chip 200c. The first semiconductor chip 100c, the second semiconductor chip 200c, and the third semiconductor chip 400 may have different functions from each other. The first semiconductor chip 100c and the second semiconductor chip 200c may have the same width as each other. The sidewalls of the first semiconductor chip 100c and the sidewalls of the second semiconductor chip 200c may be vertically aligned with each other. The mold layer 150 may be arranged between the first semiconductor chip 100c and the second semiconductor chip 200c.

[0056] The first semiconductor chip 100c may be, for example, an image sensor chip or include, for example, an image sensor chip. The second semiconductor chip 200c may be, for example, a logic chip driving the first semiconductor chip 100c or include, for example, a logic chip driving the first semiconductor chip 100c. The third semiconductor chip 400 may be, for example, a memory chip such as a dynamic random access memory (DRAM) or include, for example, a memory chip such as a dynamic random access memory (DRAM).

[0057] The first semiconductor chip 100c may include a first semiconductor substrate 110 and a first dielectric structure 120 disposed on the first semiconductor substrate 110. In some example embodiments, the first semiconductor chip 100c may be turned upside down so that the first semiconductor substrate 110 may face upwardly to the first dielectric layer 120 disposed thereon. The first dielectric structure 120 may be composed of a plurality of layers including, for example, at least two or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous low-k dielectric layer. The first semiconductor substrate 110 may be provided with a deep device isolation layer DTI separating unit pixels UP from each other. Although not shown, the first semiconductor substrate 110 may include a plurality of photodiode regions therein, each of which is provided on a corresponding one of the unit pixels UP.

[0058] The first passivation layer 132 may cover the top surface of the first semiconductor substrate 110. The first upper conductive pad 130 may be disposed on the first semiconductor substrate 110 and exposed by the first passivation layer 132. The first passivation layer 132 may be, for example, a silicon nitride layer or a polyimide layer or include, for example, a silicon nitride layer or a polyimide layer. The first passivation layer 132 may be provided with color filters CF respectively corresponding to the unit pixels UP thereon. The color filters CF may be provided in an array shape, and the microlenses MR may be provided in an array shape on the color filters CF, respectively. The first semiconductor substrate 110 may be provided with a transfer gate TG thereon, each transfer gate TG transferring charges generated in the photodiode region. The first dielectric structure 120 may include a plurality of first interconnect lines 122 electrically connected to each other therein. The first dielectric structure 120 may be provided with a first lower conductive pad 14a electrically connected to the first interconnect line 122 thereon or therein. The first semiconductor substrate 110 may be provided with a first through-path TSV1 on its edge region. Each first through-via TSV1 may pass through a portion of the first semiconductor substrate 110 and the first dielectric layer 120 and be electrically connected to the corresponding first interconnect line 122. The first through-via dielectric layer 112 may be disposed at a position adjacent to the first through-via TSV1. The first through-via dielectric layer 112 may be spaced apart from the first through-via TSV1. Although not shown, the first through-via dielectric layer 112 may surround the first through-via TSV1 when viewed in a top view. The first through-via dielectric layer 112 may insulate the first through-via TSV1 from the rest of the first semiconductor substrate 110. The first through-via dielectric layer 112 may penetrate the first semiconductor substrate 110. The bottom surface of the first lower conductive pad 14a may be coplanar with the bottom surface of the first dielectric layer 120.

[0059] The second semiconductor chip 200c may include a second semiconductor substrate 1a and a second dielectric structure 220 disposed on the second semiconductor substrate 1a. The second dielectric structure 220 may be composed of a plurality of layers including, for example, at least two or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous low-k dielectric layer. A plurality of transistors (not shown) may be disposed on the second semiconductor substrate 1a. The transistors may be electrically connected to a plurality of second interconnect lines 222 disposed in the second dielectric layer 220 and electrically connected to each other. A second through-via TSV2 may be disposed on an edge region of the second semiconductor chip 200c. Each second through-via TSV2 may penetrate the second semiconductor chip 200c and the mold layer 150 to connect to a corresponding first lower conductive pad 14a. The second through-via TSV2 may be connected to the reference Figure 1A and Figure 1BThe redistribution pattern 35 may be disposed on the second dielectric layer 220 and electrically connected to the second through via TSV2 and the second interconnection line 222. The bottom surface of the second dielectric layer 220 may be covered by the second passivation layer 205.

[0060] The third semiconductor chip 400 may include a third semiconductor substrate 310 and a third dielectric structure 320 disposed on the third semiconductor substrate 310. The third dielectric structure 320 may be composed of a plurality of layers including at least two or more of, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous low-k dielectric layer. A plurality of third interconnect lines 322 may be disposed in the third dielectric structure 320, and a capacitor including a bottom electrode BE is provided. The third dielectric structure 320 may have a top surface. The third conductive pad 301 may be disposed on the top surface of the third dielectric structure 320 and electrically connected to the third interconnect line 322. The third passivation layer 305 may cover the top surface of the third dielectric layer 320. The third conductive pad 301 and the redistribution pattern 35 may be connected to each other by a connecting member 450.

[0061] because Figure 6 The semiconductor package 1000 is constructed so that the second semiconductor chip 200c includes a redistribution pattern 35, so the third semiconductor chip 400 can be a flip chip bonded to the second semiconductor chip 200c. In addition, the first semiconductor chip 100c and the second semiconductor chip 200c can be connected to each other through the second through-path TSV2. Therefore, a reduced connection length can be provided between the first semiconductor chip 100c, the second semiconductor chip 200c and the third semiconductor chip 400, so that the semiconductor package 1000 can improve the operating speed and the readout speed. In addition, as described above, the semiconductor package 1000 can have an improved contact reliability of the second through-path TSV2. When the third semiconductor chip 400 is a dynamic random access memory (DRAM) chip, the position and size of the input / output terminal can be standardized so as to mass produce and reduce manufacturing costs. In this case, the logic chip and the DRAM chip can be different in terms of the size and position of the input / output terminal. According to some example embodiments of the inventive concepts, the second semiconductor chip 200 c used as a logic chip may include the redistribution pattern 35 , and thus the degree of freedom of wiring of connections between the second semiconductor chip 200 c and the third semiconductor chip 400 may be improved.

[0062] According to the present invention, the second structure can be etched using the mold layer as an etch stop layer, and the mold layer can be etched by using an isotropic etching process to expose the underlying conductive pattern. Therefore, etching damage to the surface of the underlying conductive pattern can be prevented or reduced, and / or the non-opening problem or incomplete etching problem can also be suppressed or mitigated. Therefore, the semiconductor device and the semiconductor package can have improved reliability.

[0063] Although the inventive concept has been described in conjunction with some example embodiments shown in the accompanying drawings, it will be appreciated by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and basic features of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made to the example embodiments without departing from the scope and spirit of the inventive concept.

Claims

1. A semiconductor device, comprising: a first structure, the first structure comprising a first conductive pattern, the first conductive pattern being exposed at an upper portion of the first structure; a molding layer, wherein the molding layer covers the first conductive pattern; a second structure, the second structure being located on the molding layer; a through via, the through via passing through the second structure and the mold layer, the through via being electrically connected to the first conductive pattern, the through via comprising: a first passage portion, the first passage portion being located in the second structure, and a second via portion, the second via portion being located in the mold layer, the second via portion being connected to the first via portion, an upper portion of the second via portion having a first width, and a middle portion of the second via portion having a second width greater than the first width; as well as A via insulating pattern including a first portion between the through via and the second structure and a second portion between the through via and the mold layer, the via insulating pattern including a third portion disposed between the second via portion and the first conductive pattern.

2. The semiconductor device according to claim 1, wherein The through via further includes a third via portion connected to the second via portion, the third via portion being adjacent to the first structure, and a bottom end of the third via portion having a third width smaller than the second width.

3. The semiconductor device according to claim 1, wherein The molding layer includes a polymer material having a dielectric constant equal to or less than 3.

4. The semiconductor device according to claim 1, wherein The first structure also includes: a plurality of first interlayer dielectric layers; and A plurality of first interconnection lines are respectively located in the plurality of first interlayer dielectric layers and electrically connected to the first conductive patterns.

5. The semiconductor device according to claim 4, wherein: The first structure also includes: a first semiconductor substrate covered by the plurality of first interlayer dielectric layers; and A first transistor is located between the plurality of first interlayer dielectric layers and the first semiconductor substrate.

6. The semiconductor device according to claim 1, wherein: The second structure comprises: a second semiconductor substrate; and At least one insulating layer is disposed on the second semiconductor substrate and in contact with the second semiconductor substrate.

7. A semiconductor package, comprising: a first semiconductor chip, the first semiconductor chip comprising a first conductive pattern, the first conductive pattern being exposed at an upper portion of the first semiconductor chip; a molding layer, the molding layer being in contact with the first conductive pattern and covering the first semiconductor chip; a second semiconductor chip, the second semiconductor chip being located on the molding layer; as well as a through via, the through via passing through the second semiconductor chip and the molding layer, the through via being electrically connected to the first conductive pattern, the through via comprising: a first via portion, the first via portion being located in the second semiconductor chip, and a second via portion, the second via portion being located in the mold layer, the second via portion being connected to the first via portion, an upper portion of the second via portion having a first width, and a middle portion of the second via portion having a second width greater than the first width; The first passage portion and the second passage portion constitute the through passage as one body, and the second passage portion has a curved side surface.

8. The semiconductor package according to claim 7, wherein: The through via further includes a third via portion connected to the second via portion, the third via portion being adjacent to the first semiconductor chip, and a bottom end of the third via portion having a third width smaller than the second width.

9. The semiconductor package according to claim 7, further comprising: A via insulating pattern including a first portion between the through via and the second semiconductor chip and a second portion between the through via and the mold layer, the via insulating pattern including a third portion disposed between the second via portion and the first conductive pattern.

10. The semiconductor package according to claim 7, wherein: The molding layer includes a polymer material having a dielectric constant equal to or less than 3.

11. The semiconductor package according to claim 7, further comprising: A third semiconductor chip is bonded to the second semiconductor chip.

12. A method for manufacturing a semiconductor device, the method comprising: forming a preliminary structure, the preliminary structure comprising: a first structure, the first structure comprising a first conductive pattern, the first conductive pattern being exposed through an upper portion of the first structure; a molding layer, the molding layer covering the first conductive pattern; and a second structure, the second structure being located on the molding layer; etching the second structure to form a first hole exposing the mold layer; etching the mold layer to form a second hole exposing the first conductive pattern and overlapping the first hole; and forming a through-via filling the first hole and the second hole, The method further includes: forming a via insulation pattern covering a side wall of each of the first hole and the second hole and a portion of a top surface of the first conductive pattern, the via insulation pattern including a first portion located between the through via and the second structure and a second portion located between the through via and the molding layer, the via insulation pattern including a third portion arranged between the through via and the first conductive pattern.

13. The method according to claim 12, wherein: Etching the second structure includes etching the second structure using an anisotropic etching process, Etching the mold layer includes etching the mold layer using an isotropic etching process.

14. The method according to claim 12, wherein: Etching the mold layer forms the second hole having a sidewall profile similar to a portion of an ellipse, a trapezoid, or a semicircle.

15. The method according to claim 12, wherein: Etching the mold layer is performed using a first etchant including a material having a contact angle of 10 to 65 degrees with respect to a surface of each of the second structure and the mold layer.

16. The method according to claim 15, wherein: The first etchant includes at least one of isopropyl alcohol and acetone.

17. The method according to claim 12, wherein: Forming the preliminary structure includes: forming the molding layer on the first structure; and The second structure is bonded to the molding layer.

18. The method according to claim 17, wherein: Joining the second structure to the molding layer includes: performing plasma treatment on the molding layer; and One of the mold layer and the second structure is heat-pressed against the other of the mold layer and the second structure.

19. The method according to claim 12, wherein: Forming the preliminary structure includes: Forming the second structure, the forming the second structure comprising: forming a transistor on a semiconductor substrate; and forming a first interlayer dielectric layer to cover the transistor; forming the mold layer on the first interlayer dielectric layer; and The first structure is formed on the mold layer, and the forming of the first structure includes: forming the first conductive pattern on the mold layer; and forming a second interlayer dielectric layer covering the first conductive pattern.

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