Chip package and method for manufacturing the same

Abstract

A chip package comprises an integrated circuit component, a heat-conducting layer, an insulating encapsulant and a redistribution wiring structure. The integrated circuit component comprises an amorphous semiconductor portion located at a rear surface of the integrated circuit component. The heat-conducting layer covers the amorphous semiconductor portion of the integrated circuit component, wherein the thermal conductivity of the heat-conducting layer is greater than or substantially equal to 10 W / mK. The insulating encapsulant encapsulates the integrated circuit component and the heat-conducting layer in a lateral direction. The redistribution wiring structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution wiring structure is electrically connected to the integrated circuit component.

Description

Technical Field

[0001] The embodiment of the present invention relates to a chip package and a manufacturing method thereof. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continued increase in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). In large part, this increase in integration density comes from the continuous reduction in the minimum feature size, which enables more smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize a smaller area than previous packages. Some smaller types of packages for semiconductor components include quad flat packages (QFP), pin grid array (PGA) packages, ball grid array (BGA) packages, and the like.

[0003] Currently, integrated fan-out packages are becoming increasingly popular due to their compactness. Heat generated from integrated circuit components of the integrated fan-out packages cannot be effectively dispersed due to the low thermal conductivity (eg, k<1 W / mK) of the die attach film. Summary of the invention

[0004] According to an embodiment of the present invention, a method for making a chip package includes: bonding an integrated circuit component to a carrier by means of a first thermal paste, wherein the thermal conductivity of the first thermal paste is in the range of about 10 W / mK to about 250 W / mK; forming an insulating encapsulation body to encapsulate the integrated circuit component bonded to the carrier; and forming a redistribution wiring structure on the insulating encapsulation body and the integrated circuit component, wherein the redistribution wiring structure is electrically connected to the integrated circuit component.

[0005] According to an embodiment of the present invention, a method for making a chip package includes: providing an integrated circuit component, on which a metal layer is formed; bonding the integrated circuit component to a carrier through a die bonding film so that the metal layer is located between the integrated circuit component and the die bonding film, wherein the thermal conductivity of the metal layer is greater than the thermal conductivity of the die bonding film; forming an insulating package to encapsulate the integrated circuit component bonded to the carrier; and forming a redistribution wiring structure on the insulating package and the integrated circuit component, wherein the redistribution wiring structure is electrically connected to the integrated circuit component.

[0006] According to an embodiment of the present invention, a chip package includes an integrated circuit component, a heat-conducting layer, an insulating encapsulant, and a redistribution wiring structure. The integrated circuit component includes an amorphous semiconductor portion located at a rear surface of the integrated circuit component. The heat-conducting layer covers the amorphous semiconductor portion of the integrated circuit component, wherein the thermal conductivity of the heat-conducting layer is in a range of about 10 W / mK to about 250 W / mK. The insulating encapsulant encapsulates the integrated circuit component and the heat-conducting layer. The redistribution wiring structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution wiring structure is electrically connected to the integrated circuit component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 15 A process flow for fabricating an integrated fan-out package according to some embodiments of the present disclosure is shown.

[0009] Figures 16 to 30 A process flow for fabricating an integrated fan-out package according to some alternative embodiments of the present disclosure is shown.

[0010] Fig.31 An integrated fan-out package according to some embodiments of the present disclosure is schematically illustrated.

[0011] Fig.32 An integrated fan-out package according to some alternative embodiments of the present disclosure is schematically illustrated.

[0012] [Explanation of Symbols]

[0013] 100: chip;

[0014] 100': thinned wafer;

[0015] 110, 110a: semiconductor substrate;

[0016] 110 ′: thinning the semiconductor substrate;

[0017] 110S: amorphous semiconductor part;

[0018] 120: conductive pad;

[0019] 130, 130a: passivation layer;

[0020] 132, 142: contact opening;

[0021] 140, 140a: rear passivation layer;

[0022] 150: conductive column;

[0023] 160, 160a, 160a': protective layer;

[0024] 200: integrated circuit components;

[0025] 210: Insulation material;

[0026] 210': insulation enclosure;

[0027] B: Conductive characteristics;

[0028] BP: conductive bump;

[0029] C: carrier;

[0030] DAF, DAF1: die bonding film;

[0031] DB: peeling layer;

[0032] DT: cutting tape;

[0033] M, M1: metal layer;

[0034] P1, P11: packaging structure;

[0035] P2: semiconductor devices;

[0036] RDL: redistribution line structure;

[0037] ST: sawing tape;

[0038] TP: thermal paste;

[0039] TP1: first thermal paste;

[0040] TP2: second thermal paste;

[0041] TV: conductive perforation;

[0042] UF: Underfill. DETAILED DESCRIPTION

[0043] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0044] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0045] The present disclosure may also include other features and processes. For example, a test structure may be included to help perform verification testing on three-dimensional (3D) packages or three-dimensional integrated circuits (3DIC) devices. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate to enable testing of the three-dimensional package or three-dimensional integrated circuit, use of probes and / or probe cards, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method including intermediate verification of a known good die to improve yield and reduce costs.

[0046] Figures 1 to 15 A process flow for fabricating an integrated fan-out package according to some embodiments of the present disclosure is shown.

[0047] Reference Figure 1, a wafer 100 is provided, the wafer 100 includes a plurality of semiconductor dies or integrated circuit components 200 arranged in an array. Before a wafer dicing process is performed on the wafer 100, the integrated circuit components 200 of the wafer 100 are connected to each other. In some embodiments, the wafer 100 may include a semiconductor substrate 110, a plurality of conductive pads 120 formed on the semiconductor substrate 110, and a passivation layer 130. The passivation layer 130 is formed on the semiconductor substrate 110 and has a plurality of contact openings 132, so that the conductive pads 120 are partially exposed by the contact openings 132 of the passivation layer 130. For example, the semiconductor substrate 110 may be a silicon substrate, which includes active components (e.g., transistors, etc.) and passive components (e.g., resistors, capacitors, inductors, etc.) formed in the silicon substrate; the conductive pad 120 may be an aluminum pad, a copper pad, or other suitable metal pads; and the passivation layer 130 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials.

[0048] like Figure 1 As shown, in some embodiments, the wafer 100 may further include a post-passivation layer 140 formed on the passivation layer 130. The post-passivation layer 140 covers the passivation layer 130 and has a plurality of contact openings 142. The conductive pads 120 exposed by the contact openings 132 of the passivation layer 130 may be partially exposed by the contact openings 142 of the post-passivation layer 140. For example, the post-passivation layer 140 may be a polyimide (PI) layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed of other suitable polymers.

[0049] Reference Figure 2, a plurality of conductive pillars 150 are formed on the conductive pads 120. In some embodiments, the conductive pillars 150 are electroplated on the conductive pads 120. The electroplating process of the conductive pillars 150 is described in detail below. First, a seed layer can be sputtered onto the post-passivation layer 140 and onto the conductive pads 120 exposed by the contact openings 142. Next, a patterned photoresist layer (not shown) can be formed on the seed layer by photolithography, wherein the patterned photoresist layer exposes a portion of the seed layer corresponding to the conductive pads 120. The wafer 100 including the patterned photoresist layer formed thereon can be immersed in a plating solution in a plating bath, so that the conductive pillars 150 are electroplated on the portion of the seed layer corresponding to the conductive pads 120. After the electroplated conductive pillars 150 are formed, the patterned photoresist layer is stripped. Afterwards, by using the conductive pillars 150 as a hard mask, the portion of the seed layer not covered by the conductive pillars 150 may be removed by, for example, etching until the post passivation layer 140 is exposed. In some embodiments, the electroplated conductive pillars 150 may be electroplated copper pillars.

[0050] Reference Figure 3 After forming the conductive pillar 150, a protective layer 160 is formed on the post-passivation layer 140 to cover the conductive pillar 150. In some embodiments, the protective layer 160 may be a polymer layer having a thickness sufficient to encapsulate and protect the conductive pillar 150. For example, the protective layer 160 may be a polybenzoxazole (PBO) layer, a polyimide (PI) layer, or other suitable polymers. In some alternative embodiments, the protective layer 160 may be made of an inorganic material.

[0051] Reference Figure 3 and Figure 4 After forming the protective layer 160, a back-side grinding process is performed on the rear surface of the wafer 100. During the back-side grinding process, the semiconductor substrate 110 is ground by a grinding wheel so that a thinned wafer 100' is formed. The thinned wafer 100' includes a thinned semiconductor substrate 110', a conductive pad 120 formed on the thinned semiconductor substrate 110', a passivation layer 130, a rear passivation layer 140, a conductive column 150, and a protective layer 160. After performing the back-side grinding process, as shown in FIG. Figure 4 As shown, an amorphous semiconductor portion 110S (e.g., an amorphous silicon layer) formed by a backside grinding process is formed at the rear surface of the thinned semiconductor substrate 110'. In some embodiments, the thickness of the amorphous semiconductor portion 110S may be in a range of about 10 nanometers to about 50 nanometers. In addition, the grit size of the grinding wheel used to grind the semiconductor substrate 110 may be in a range of about 3 micrometers to about 15 micrometers.

[0052] Reference Figure 5After performing the backside grinding process, the thinned wafer 100' is mounted on the dicing tape DT so that the rear surface of the thinned semiconductor substrate 110' is adhered to the dicing tape DT. In some embodiments, the dicing tape DT may support the thinned wafer 100' mounted on the dicing tape DT and temporarily adhere to the rear surface of the thinned wafer 100'.

[0053] Reference Figure 5 and Figure 6 After the thinned wafer 100' is mounted on the dicing tape DT, a wafer dicing process is performed on the thinned wafer 100' to separate the integrated circuit components 200 in the thinned wafer 100' from each other. After the singulation process, a plurality of singulated integrated circuit components 200 bonded together with the dicing tape DT are formed. Figure 6 As shown, each of the singulated integrated circuit components 200 includes a semiconductor substrate 110a, a conductive pad 120 formed on the semiconductor substrate 110a, a passivation layer 130a, a rear passivation layer 140a, a conductive pillar 150, and a protective layer 160a. The materials and properties of the semiconductor substrate 110a, the passivation layer 130a, the rear passivation layer 140a, and the protective layer 160a are the same as those of the semiconductor substrate 110, the passivation layer 130, the rear passivation layer 140, and the protective layer 160. Therefore, a detailed description of the semiconductor substrate 110a, the passivation layer 130a, the rear passivation layer 140a, and the protective layer 160a in the singulated integrated circuit components 200 is omitted.

[0054] During the backside grinding process and the wafer dicing process, the protection layer 160 can fully protect the conductive pillars 150 of the integrated circuit component 200. In addition, the conductive pillars 150 of the singulated integrated circuit component 200 can be protected from damage by subsequent processes (e.g., a picking-up and placing process, a molding process, etc. of the singulated integrated circuit component 200).

[0055] Reference Figure 6 and Figure 7 , providing a carrier C having a peeling layer DB formed thereon. In some embodiments, the carrier C is a glass substrate, and the peeling layer DB is a light-to-heat conversion (LTHC) release layer formed on the glass substrate. In some alternative embodiments, a dielectric layer (not shown) may be formed on the peeling layer DB so that the peeling layer DB is located between the carrier C and the dielectric layer. For example, the dielectric layer is a polybenzoxazole (PBO) layer formed on the peeling layer DB.

[0056] After providing a carrier C with a stripping layer DB formed thereon, a plurality of conductive through-holes TV are formed on the stripping layer DB. In some embodiments, the plurality of conductive through-holes TV may be formed by sputtering of a seed layer, photoresist coating, photolithography, electroplating of through-holes, photoresist stripping, and patterning of the seed layer. For example, the conductive through-holes TV include copper posts or other suitable metal posts.

[0057] like Figure 6 and Figure 7 As shown, in some embodiments, one of the singulated integrated circuit components 200 is picked up from the dicing tape DT and placed on the peeling layer DB, the singulated integrated circuit component 200 including the semiconductor substrate 110a, the conductive pad 120, the passivation layer 130a, the rear passivation layer 140a, the conductive pillar 150, and the protective layer 160a. In some alternative embodiments, more than one singulated integrated circuit component 200 is picked up from the dicing tape DT and placed on the peeling layer DB, wherein the singulated integrated circuit components 200 placed on the peeling layer DB may be arranged in an array. When the singulated integrated circuit components 200 placed on the peeling layer DB are arranged in an array, the conductive through-vias TV may be classified into respective groups and the number of singulated integrated circuit components 200 corresponds to the number of groups of the conductive through-vias TV.

[0058] The singulated integrated circuit component 200 is attached or adhered to the peeling layer DB by the first thermal paste TP1, wherein the thermal conductivity (k) of the first thermal paste TP1 is greater than or substantially equal to 10 W / mK. In some embodiments, the first thermal paste TP1 can be formed on the peeling layer DB by dispensing or other suitable processes. For example, the thermal conductivity (k) of the first thermal paste TP1 can be in the range of about 10 W / mK to about 250 W / mK. In addition, the material of the first thermal paste TP1 can be a polymer paste containing metal powder.

[0059] like Figure 7 As shown, for example, the top surface of the protective layer 160a is higher than the top surface of the conductive through-hole TV, and the top surface of the protective layer 160a is higher than the top surface of the conductive pillar 150. However, the present disclosure is not limited thereto. In some alternative embodiments, the top surface of the protective layer 160a may be substantially aligned with the top surface of the conductive through-hole TV, and the top surface of the protective layer 160a is higher than the top surface of the conductive pillar 150.

[0060] Reference Figure 8, an insulating material 210 is formed on the peeling layer DB to cover the singulated integrated circuit component 200 and the conductive through via TV. In some embodiments, the insulating material 210 is a molding compound formed by a molding process. For example, the top surface of the protective layer 160a of the singulated integrated circuit component 200 is covered by the insulating material 210. In other words, the top surface of the protective layer 160a of the singulated integrated circuit component 200 is not exposed but protected by the insulating material 210. In some embodiments, the insulating material 210 includes epoxy resin or other suitable dielectric materials.

[0061] Reference Figure 8 and Fig. 9 , the insulating material 210 is ground until the top surface of the conductive pillar 150, the top surface of the conductive through hole TV, and the top surface of the protective layer 160a are exposed. In some embodiments, the insulating material 210 is ground by a mechanical grinding process and / or a chemical mechanical polishing (CMP) process. After the insulating material 210 is ground, an insulating encapsulation 210' is formed. During the grinding process of the insulating material 210, some portions of the protective layer 160a are ground to form the protective layer 160a'. In some embodiments, during the grinding process of the insulating material 210 and the protective layer 160a, some portions of the conductive through hole TV and some portions of the conductive pillar 150 are also slightly ground.

[0062] like Fig. 9 As shown, the insulating encapsulation body 210' encapsulates the sidewalls of the singulated integrated circuit component 200 in the lateral direction, and the insulating encapsulation body 210' is penetrated by the conductive through-via TV. In other words, the singulated integrated circuit component 200 and the conductive through-via TV are embedded in the insulating encapsulation body 210'. It should be noted that the top surface of the conductive through-via TV, the top surface of the insulating encapsulation body 210', the top surface of the conductive pillar 150, and the top surface of the protective layer 160a' are substantially at the same level.

[0063] Reference Fig.10 After forming the insulating encapsulation body 210' and the protective layer 160a', a redistribution wiring structure RDL is formed on the top surface of the conductive through-via TV, on the top surface of the insulating encapsulation body 210', on the top surface of the conductive pillar 150, and on the top surface of the protective layer 160a'. The redistribution wiring structure RDL is made to be electrically connected to one or more connectors located below. Here, the aforementioned connectors may be the conductive pillars 150 of the singulated integrated circuit component 200 and / or the conductive through-via TV embedded in the insulating encapsulation body 210'. The redistribution wiring structure RDL may include a plurality of redistribution wiring lines and a plurality of patterned dielectric layers alternately stacked, such as Fig.10As shown. For example, the redistribution wiring may be a copper wiring and the material of the patterned dielectric layer may include polyimide (PI), polybenzoxazole (PBO) or other suitable dielectric polymers. In addition, the conductive through via TV is electrically connected to the singulated integrated circuit component 200 through the redistribution line structure RDL.

[0064] Reference Fig.11 After forming the redistribution wiring structure RDL, a plurality of conductive features B are formed, and the plurality of conductive features B are electrically connected to the redistribution wiring structure RDL. The conductive features B are disposed on the redistribution wiring structure RDL and arranged in an array. In some embodiments, the conductive features B may be conductive balls (e.g., solder balls) arranged in an array. Fig.11 As shown, a package structure P1 is manufactured on a peeling layer DB carried by a carrier C. The package structure P1 includes a first thermal paste TP1, a singulated integrated circuit component 200, a conductive through-via TV, an insulating encapsulation body 210 ′, a redistribution line structure RDL and a conductive feature B.

[0065] Reference Fig.12 , the peeling layer DB and the carrier C are peeled off from the package structure P1, so that the bottom surface of the conductive through-via TV, the bottom surface of the insulating encapsulation body 210' and the surface of the first thermal paste TP1 are peeled off from the carrier C and exposed. The bottom surface of the insulating encapsulation body 210' and the exposed surface of the first thermal paste TP1 are substantially at the same level. In some embodiments, external energy (such as ultraviolet laser, visible light or heat) may be applied to the peeling layer DB so that the package structure P1 and the peeling layer DB carried by the carrier C can be separated.

[0066] Reference Fig.13 After the stripping process is performed, the package structure P1 can be flipped (turned upside down) and mounted on the sawing tape ST so that the conductive feature B of the package structure P1 is adhered to the sawing tape ST. In some embodiments, the sawing tape ST can support the above-mentioned package structure P1 mounted on the sawing tape ST and temporarily adhere to the conductive feature B of the package structure P1. Since the thermal conductivity (k) of the first thermal paste TP1 is high (i.e., greater than or substantially equal to 10 W / mK), the first thermal paste TP1 can effectively conduct and disperse the heat generated from the singulated integrated circuit component 200. Therefore, it is not necessary to remove the first thermal paste TP1 to enhance the heat dissipation performance of the package structure P1.

[0067] Reference Fig.14, a second thermal paste TP2 may be formed to cover the exposed surface of the first thermal paste TP1, wherein the thermal conductivity (k) of the second thermal paste TP2 is greater than or substantially equal to 10 W / mK. For example, the thermal conductivity (k) of the second thermal paste TP2 may be in a range of about 10 W / mK to about 250 W / mK. In some embodiments, the thermal conductivity (k) of the first thermal paste TP1 may be substantially equal to the thermal conductivity (k) of the second thermal paste TP2. In some alternative embodiments, the thermal conductivity (k) of the first thermal paste TP1 may be greater than or less than the thermal conductivity (k) of the second thermal paste TP2. Since the thermal conductivity (k) of both the first thermal paste TP1 and the second thermal paste TP2 is high (i.e., greater than or substantially equal to 10 W / mK), the first thermal paste TP1 and the second thermal paste TP2 may effectively conduct and disperse the heat generated from the singulated integrated circuit component 200.

[0068] like Fig.14 As shown, the first thermal paste TP1 is embedded in the insulating encapsulation 210' and the first thermal paste TP1 contacts the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110'. In some embodiments, the second thermal paste TP2 may be thicker than the first thermal paste TP1. In some alternative embodiments, the second thermal paste TP2 may be thinner than the first thermal paste TP1. In some other embodiments, the thickness of the first thermal paste TP1 and the second thermal paste TP2 may be substantially the same. For example, the thickness of the first thermal paste TP1 may be in the range of about 1 micron to about 100 microns, and the thickness of the second thermal paste TP2 may be in the range of about 1 micron to about 100 microns. In addition, the second thermal paste TP2 may not only cover the surface of the first thermal paste TP1, but may also partially cover the surface of the insulating encapsulation 210'. However, the distribution of the second thermal paste TP2 is not limited thereto.

[0069] When at least one of the first thermal paste TP1 and the second thermal paste TP2 contains metal particles (e.g., copper particles), the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110' can capture the metal particles contained in the first thermal paste TP1 and / or the second thermal paste TP2. In other words, when at least one of the first thermal paste TP1 and the second thermal paste TP2 contains metal particles, the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110' can serve as a diffusion barrier for the metal particles. Therefore, the package structure P1 can easily pass the high temperature operating life (HTOL) test.

[0070] In some alternative embodiments, the preparation of the second thermal paste TP2 may be omitted, such as Fig.31 shown.

[0071] like Fig.14As shown, the combination of the first thermal paste TP1 and the second thermal paste TP2 can be regarded as a thermal conductive layer covering the amorphous semiconductor portion 110S of the singulated integrated circuit component 200. In some alternative embodiments, when the second thermal paste TP2 is omitted, the thermal conductive layer only includes the first thermal paste TP1.

[0072] Reference Fig.15 , a semiconductor device P2 is provided and placed on the package structure P1 to electrically connect the semiconductor device P2 to the conductive via TV. The semiconductor device P2 is electrically connected to the integrated circuit component 200 via the conductive via TV and the redistribution line structure RDL. In some embodiments, the semiconductor device P2 may be electrically connected to the conductive via TV of the package structure P1 via a plurality of conductive bumps BP. For example, the conductive bump BP may be a micro bump, a controlled collapse chip connection (C4) bump, etc.

[0073] In some embodiments, the semiconductor device P2 may be a memory device (e.g., DRAM) including a conductive bump BP on its bottom surface. For example, the semiconductor device P2 is a ball grid array (BGA) type package. In the semiconductor device P2, at least one memory chip may be mounted on a BGA circuit board, electrically connected to the BGA board via bonding wires and encapsulated by a molding compound. Before the semiconductor device P2 is mounted on the package structure P1, a solder material may be applied to the conductive through-hole TV of the package structure P1 by, for example, a stencil printing process, and then the semiconductor device P2 including the conductive bump BP is placed on the conductive through-hole TV. Afterwards, a reflow process is performed to form a solder joint between the semiconductor device P2 and the conductive through-hole TV of the package structure P1.

[0074] After performing the above-mentioned reflow process, an underfill glue UF is formed between the package structure P1 and the semiconductor device P2 to encapsulate the second thermal paste TP2 and the conductive bump BP. In some embodiments, the material of the underfill glue UF may include an epoxy resin containing a filler and the thermal conductivity of the underfill glue UF may be less than about 1W / mK. The underfill glue UF encapsulates the conductive bump BP in the lateral direction and acts as a stress buffer to minimize fatigue of the conductive bump BP caused by the mismatch of the coefficient of thermal expansion (CTE) between the package structure P1 and the semiconductor device P2.

[0075] After forming the bottom filler UF, a sawing process is performed on the package structure P1 to form a plurality of package-on-package (PoP) structures that have been singulated. After performing the sawing process of the package structure P1, the singulated package-on-package (PoP) structures are bonded together with the sawing tape ST. In addition, the bottom filler UF can ensure the reliability of the package-on-package (PoP) structure including the package structure P1 and the semiconductor device P2.

[0076] Figures 16 to 30 A process flow for fabricating an integrated fan-out package according to some alternative embodiments of the present disclosure is shown.

[0077] Reference Fig.16 , a wafer 100 is provided, the wafer 100 includes a plurality of semiconductor dies or integrated circuit components 200 arranged in an array. Before performing a wafer cutting process on the wafer 100, the integrated circuit components 200 of the wafer 100 are connected to each other. In some embodiments, the wafer 100 may include a semiconductor substrate 110, a plurality of conductive pads 120 formed on the semiconductor substrate 110, and a passivation layer 130. The passivation layer 130 is formed on the semiconductor substrate 110 and has a plurality of contact openings 132, so that the conductive pads 120 are partially exposed by the contact openings 132 of the passivation layer 130. For example, the semiconductor substrate 110 may be a silicon substrate, the silicon substrate including active components (e.g., transistors, etc.) and passive components (e.g., resistors, capacitors, inductors, etc.) formed in the silicon substrate; the conductive pads 120 may be aluminum pads, copper pads, or other suitable metal pads; and the passivation layer 130 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials.

[0078] like Fig.16 As shown, in some embodiments, the wafer 100 may further include a rear passivation layer 140 formed on the passivation layer 130. The rear passivation layer 140 covers the passivation layer 130 and has a plurality of contact openings 142. The conductive pads 120 exposed by the contact openings 132 of the passivation layer 130 may be partially exposed by the contact openings 142 of the rear passivation layer 140. For example, the rear passivation layer 140 may be a polyimide (PI) layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed of other suitable polymers.

[0079] Reference Fig.17, a plurality of conductive pillars 150 are formed on the conductive pad 120. In some embodiments, the conductive pillars 150 are electroplated on the conductive pad 120. The electroplating process of the conductive pillars 150 is described in detail below. First, the seed layer can be sputtered onto the back passivation layer 140 and the conductive pad 120 exposed by the contact opening 142. Then, a patterned photoresist layer (not shown) can be formed on the seed layer by photolithography, wherein the patterned photoresist layer exposes a portion of the seed layer corresponding to the conductive pad 120. The wafer 100 can be immersed in the electroplating solution in the form of an electroplating tank, and the wafer 100 includes a patterned photoresist layer formed thereon, so that the conductive pillars 150 are electroplated on the portion of the seed layer corresponding to the conductive pad 120. After the electroplated conductive pillars 150 are formed, the patterned photoresist layer is stripped. Thereafter, by using the conductive pillars 150 as a hard mask, the portion of the seed layer not covered by the conductive pillars 150 can be removed, for example, by etching until the back passivation layer 140 is exposed. In some embodiments, the electroplated conductive pillars 150 may be electroplated copper pillars.

[0080] Reference Fig.18 After forming the conductive pillar 150, a protective layer 160 is formed on the post-passivation layer 140 to cover the conductive pillar 150. In some embodiments, the protective layer 160 may be a polymer layer having a thickness sufficient to encapsulate and protect the conductive pillar 150. For example, the protective layer 160 may be a polybenzoxazole (PBO) layer, a polyimide (PI) layer, or other suitable polymers. In some alternative embodiments, the protective layer 160 may be made of an inorganic material.

[0081] Reference Fig.18 and Fig.19 After forming the protective layer 160, a backside grinding process is performed on the rear surface of the wafer 100. During the backside grinding process, the semiconductor substrate 110 is ground so that a thinned wafer 100' is formed. The thinned wafer 100' includes a thinned semiconductor substrate 110', a conductive pad 120 formed on the thinned semiconductor substrate 110', a passivation layer 130, a rear passivation layer 140, a conductive column 150, and a protective layer 160. After performing the backside grinding process, as shown in FIG. Fig.19 As shown, an amorphous semiconductor portion 110S (eg, an amorphous silicon layer) formed by a backside grinding process is formed at the rear surface of the thinned semiconductor substrate 110'. In some embodiments, the thickness of the amorphous semiconductor portion 110S may be in a range of about 10 nanometers to about 50 nanometers.

[0082] After performing the backside grinding process, a metal layer M is formed on the rear surface of the thinned semiconductor substrate 110'. For example, a metal is formed on the rear surface of the thinned semiconductor substrate 110' by sputtering or other suitable deposition processes. The metal layer M covers and contacts the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110'. The metal layer M serves as a protective layer to protect the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110' from being damaged or removed by a subsequently performed process. The thickness of the metal layer M may be less than about 5000 angstroms. For example, the thickness of the metal layer M may be in the range of about 3000 angstroms to about 5000 angstroms. In some embodiments, the metal layer M may be a single metal layer (e.g., a copper layer, a silver layer, a titanium layer, or a nickel layer) or a multi-layer metal layer, and the thermal conductivity of the metal layer M may be greater than or substantially equal to 20 W / mK. For example, the thermal conductivity of the metal layer M may be in the range of about 20 W / mK to about 406 W / mK.

[0083] Reference Fig. 20 , after forming the metal layer M, a dicing tape DT including a die attach film DAF is provided and the thinned wafer 100' is mounted on the die attach film DAF carried by the dicing tape DT so that the metal layer M formed on the rear surface of the thinned semiconductor substrate 110' is adhered to the die attach film DAF on the dicing tape DT. In some embodiments, the dicing tape DT may support the thinned wafer 100' mounted on the dicing tape DT and the die attach film DAF may be temporarily adhered to the metal layer M formed on the rear surface of the thinned wafer 100'. In addition, the material of the die attach film DAF may be adhesive and the thermal conductivity (k) of the die attach film DAF may be less than or substantially equal to 1 W / mK. In some embodiments, the thermal conductivity (k) of the die attach film DAF may be in the range of about 0.01 W / mK to about 1 W / mK.

[0084] Reference Fig. 20 and Fig.21 After the thinned wafer 100' is mounted on the dicing tape DT, a wafer dicing process is performed on the thinned wafer 100', the metal layer M and the die attach film DAF to separate the integrated circuit components 200 in the thinned wafer 100' from each other. After the singulation process, a plurality of singulated integrated circuit components 200, a plurality of singulated metal layers M1 and a plurality of singulated die attach films DAF1 are formed, wherein the singulated metal layer M1 is located between the singulated die attach films DAF1 and the singulated integrated circuit components 200. Fig.21As shown, each of the singulated integrated circuit components 200 includes a semiconductor substrate 110a, a conductive pad 120 formed on the semiconductor substrate 110a, a passivation layer 130a, a rear passivation layer 140a, a conductive pillar 150, and a protective layer 160a. The singulated metal layer M1 covers the rear surface of the semiconductor substrate 110a, and the singulated die attach film DAF1 is adhered to the singulated metal layer M1. The materials and properties of the semiconductor substrate 110a, the passivation layer 130a, the rear passivation layer 140a, and the protective layer 160a are the same as those of the semiconductor substrate 110, the passivation layer 130, the rear passivation layer 140, and the protective layer 160. Therefore, a detailed description of the semiconductor substrate 110a, the passivation layer 130a, the rear passivation layer 140a, and the protective layer 160a in the singulated integrated circuit component 200 is omitted.

[0085] During the backside grinding process and the wafer dicing process, the protective layer 160 can sufficiently protect the conductive pillars 150 of the singulated integrated circuit component 200. In addition, the conductive pillars 150 of the singulated integrated circuit component 200 can be protected from damage by subsequently performed processes (e.g., a pick-and-place process, a molding process, etc. of the singulated integrated circuit component 200).

[0086] Reference Fig.21 and Fig. 22 , providing a carrier C having a peeling layer DB formed thereon. In some embodiments, the carrier C is a glass substrate, and the peeling layer DB is a light-to-heat conversion (LTHC) release layer formed on the glass substrate. In some alternative embodiments, a dielectric layer (not shown) may be formed on the peeling layer DB so that the peeling layer DB is located between the carrier C and the dielectric layer. For example, the dielectric layer is a polybenzoxazole (PBO) layer formed on the peeling layer DB.

[0087] After providing a carrier C with a stripping layer DB formed thereon, a plurality of conductive vias TV are formed on the stripping layer DB. In some embodiments, the plurality of conductive vias TV may be formed by sputtering of a seed layer, photoresist coating, photolithography, electroplating of the vias, photoresist stripping, and patterning of the seed layer. For example, the conductive vias TV include copper pillars or other suitable metal pillars.

[0088] like Fig.21 and Fig. 22As shown, in some embodiments, one of the singulated integrated circuit components 200 is picked up from the dicing tape DT and placed on the peeling layer DB. In some alternative embodiments, more than one singulated integrated circuit component 200 is picked up from the dicing tape DT and placed on the peeling layer DB, wherein the singulated integrated circuit components 200 placed on the peeling layer DB may be arranged in an array. When the singulated integrated circuit components 200 placed on the peeling layer DB are arranged in an array, the conductive through vias TV may be classified into respective groups and the number of singulated integrated circuit components 200 corresponds to the number of groups of the conductive through vias TV.

[0089] The singulated integrated circuit assembly 200 is attached or adhered to the peeling layer DB through the singulated die attach film DAF1, wherein the thermal conductivity (k) of the singulated die attach film DAF1 is less than or substantially equal to 1 W / mK. In some embodiments, the thermal conductivity (k) of the singulated die attach film DAF1 may be in the range of about 0.01 W / mK to about 1 W / mK. In addition, the material of the singulated die attach film DAF1 may be adhesive.

[0090] like Fig. 22 As shown, for example, the top surface of the protective layer 160a is higher than the top surface of the conductive through-hole TV, and the top surface of the protective layer 160a is higher than the top surface of the conductive pillar 150. However, the present disclosure is not limited thereto. In some alternative embodiments, the top surface of the protective layer 160a may be substantially aligned with the top surface of the conductive through-hole TV, and the top surface of the protective layer 160a is higher than the top surface of the conductive pillar 150.

[0091] Reference Fig.23 , an insulating material 210 is formed on the peeling layer DB to cover the singulated integrated circuit component 200 and the conductive through via TV. In some embodiments, the insulating material 210 is a molding compound formed by a molding process. For example, the top surface of the protective layer 160a of the singulated integrated circuit component 200 is covered by the insulating material 210. In other words, the top surface of the protective layer 160a of the singulated integrated circuit component 200 is not exposed but protected by the insulating material 210. In some embodiments, the insulating material 210 includes epoxy resin or other suitable dielectric materials.

[0092] Reference Fig.23 and Fig.24, the insulating material 210 is ground until the top surface of the conductive pillar 150, the top surface of the conductive through-hole TV, and the top surface of the protective layer 160a are exposed. In some embodiments, the insulating material 210 is ground by a mechanical grinding process and / or a chemical mechanical polishing (CMP) process. After the insulating material 210 is ground, an insulating encapsulation 210' is formed. During the grinding process of the insulating material 210, some portions of the protective layer 160a are ground to form the protective layer 160a'. In some embodiments, during the grinding process of the insulating material 210 and the protective layer 160a, some portions of the conductive through-hole TV and some portions of the conductive pillar 150 are also slightly ground.

[0093] like Fig.24 As shown, the insulating encapsulation body 210' encapsulates the sidewalls of the singulated integrated circuit component 200 in the lateral direction, and the insulating encapsulation body 210' is penetrated by the conductive through-via TV. In other words, the singulated integrated circuit component 200 and the conductive through-via TV are embedded in the insulating encapsulation body 210'. It should be noted that the top surface of the conductive through-via TV, the top surface of the insulating encapsulation body 210', the top surface of the conductive pillar 150, and the top surface of the protective layer 160a' are substantially at the same level.

[0094] Reference Fig.25 After forming the insulating encapsulation body 210' and the protective layer 160a', a redistribution wiring structure RDL is formed on the top surface of the conductive through-via TV, on the top surface of the insulating encapsulation body 210', on the top surface of the conductive pillar 150, and on the top surface of the protective layer 160a'. The redistribution wiring structure RDL is made to be electrically connected to one or more connectors located below. Here, the aforementioned connectors may be the conductive pillars 150 of the singulated integrated circuit component 200 and / or the conductive through-via TV embedded in the insulating encapsulation body 210'. The redistribution wiring structure RDL may include a plurality of redistribution wiring lines and a plurality of patterned dielectric layers alternately stacked, such as Fig.25 As shown. For example, the redistribution wiring may be a copper wiring and the material of the patterned dielectric layer may include polyimide (PI), polybenzoxazole (PBO) or other suitable dielectric polymers. In addition, the conductive through via TV is electrically connected to the singulated integrated circuit component 200 through the redistribution line structure RDL.

[0095] Reference Fig.26 After forming the redistribution wiring structure RDL, a plurality of conductive features B are formed, and the plurality of conductive features B are electrically connected to the redistribution wiring structure RDL. The conductive features B are disposed on the redistribution wiring structure RDL and arranged in an array. In some embodiments, the conductive features B may be conductive balls (e.g., solder balls) arranged in an array. Fig.26As shown, a packaging structure P11 is manufactured on a peeling layer DB carried by a carrier C. The packaging structure P11 includes a singulated metal layer M1, a singulated die bonding film DAF1, a singulated integrated circuit component 200, a conductive via TV, an insulating encapsulation body 210', a redistribution line structure RDL and a conductive feature B.

[0096] Reference Fig. 27 , the peeling layer DB and the carrier C are peeled off from the package structure P11, so that the bottom surface of the conductive through hole TV, the bottom surface of the insulating encapsulation body 210' and the surface of the singulated die bonding film DAF1 are peeled off from the carrier C and exposed. The bottom surface of the insulating encapsulation body 210' and the exposed surface of the singulated die bonding film DAF1 are substantially at the same level. In some embodiments, external energy (such as ultraviolet laser, visible light or heat) can be applied to the peeling layer DB to separate the package structure P11 from the peeling layer DB carried by the carrier C.

[0097] Reference Fig.28 , after performing the stripping process, the package structure P11 can be flipped (turned upside down) and mounted on the sawing tape ST so that the conductive feature B of the package structure P11 is adhered to the sawing tape ST. In some embodiments, the sawing tape ST can support the above-mentioned package structure P11 mounted on the sawing tape ST and temporarily adhere to the conductive feature B of the package structure P11. Since the thermal conductivity (k) of the singulated die bonding film DAF1 is low (i.e., less than or substantially equal to 1 W / mK), the singulated die bonding film DAF1 may not be able to effectively conduct and disperse the heat generated from the singulated integrated circuit component 200. Therefore, the singulated die bonding film DAF1 can be removed until the singulated metal layer M1 is exposed to enhance the heat dissipation performance of the package structure P11. For example, the singulated die bonding film DAF1 can be removed by dry etching (e.g., plasma treatment) or other suitable removal processes. When the singulated die attach film DAF1 is removed, the singulated metal layer M1 may protect the amorphous semiconductor portion 110S ( Fig.29 shown) are not damaged or removed.

[0098] Reference Fig.29After removing the singulated die attach film DAF1, a thermal paste TP may be formed by dispensing or other suitable processes to cover the exposed surface of the singulated metal layer M1, wherein the thermal conductivity (k) of the thermal paste TP is greater than or substantially equal to 10 W / mK. For example, the thermal conductivity (k) of the thermal paste TP is in the range of about 10 W / mK to about 250 W / mK. In some embodiments, the thermal conductivity (k) of the thermal paste TP may be less than the thermal conductivity (k) of the singulated metal layer M1. In some alternative embodiments, the thermal conductivity (k) of the thermal paste TP may be greater than or substantially equal to the thermal conductivity (k) of the singulated metal layer M1. Since the thermal conductivity (k) of both the thermal paste TP and the singulated metal layer M1 is high (i.e., greater than or substantially equal to 10 W / mK), the thermal paste TP and the singulated metal layer M1 may effectively conduct and disperse the heat generated from the singulated integrated circuit component 200.

[0099] like Fig.29 As shown, the individualized metal layer M1 is embedded in the insulating encapsulation 210' and contacts the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110'. In addition, the thermal paste TP covers the individualized metal layer M1 and the thermal paste TP is partially embedded in the insulating encapsulation 210'. In some embodiments, the thermal paste TP may be thicker than the individualized metal layer M1. For example, the thickness of the thermal paste TP may be in the range of about 1 micron to about 100 microns. In some alternative embodiments, the thermal paste TP may be thinner than the individualized metal layer M1. In some other embodiments, the thickness of the thermal paste TP and the individualized metal layer M1 may be substantially the same. In addition, the thermal paste TP may not only cover the surface of the individualized metal layer M1, but may also partially cover the surface of the insulating encapsulation 210'. However, the distribution of the thermal paste TP is not limited thereto.

[0100] When the thermal paste TP contains metal particles (e.g., copper particles), the singulated metal layer M1 may serve as a diffusion barrier for the metal particles. In addition, the amorphous semiconductor portion 110S of the thinned semiconductor substrate 110' may capture metal particles from the singulated metal layer M1 and may serve as a diffusion barrier for metal particles diffused from the singulated metal layer M1. Therefore, the package structure P11 may easily pass a high temperature operating life (HTOL) test.

[0101] In some alternative embodiments, the preparation of thermal paste TP may be omitted, such as Fig.32 shown.

[0102] like Fig.29As shown, the combination of the singulated metal layer M1 and the thermal paste TP can be regarded as a thermal conductive layer covering the singulated amorphous semiconductor portion 110S of the integrated circuit component 200. In some alternative embodiments, when the formation of the thermal paste TP is omitted, the thermal conductive layer only includes the singulated metal layer M1.

[0103] Reference Fig.30 , a semiconductor device P2 is provided and placed on a package structure P11 to electrically connect the semiconductor device P2 to the conductive through via TV. The semiconductor device P2 is electrically connected to the singulated integrated circuit component 200 via the conductive through via TV and the redistribution wiring structure RDL. In some embodiments, the semiconductor device P2 may be electrically connected to the conductive through via TV of the package structure P11 via a plurality of conductive bumps BP. For example, the conductive bumps BP may be micro bumps, controlled collapse die connection (C4) bumps, etc.

[0104] In some embodiments, the semiconductor device P2 may be a memory device (e.g., DRAM) including a conductive bump BP on its bottom surface. Before mounting the memory device on the package structure P11, solder material may be applied to the conductive through-hole TV of the package structure P11 by, for example, a screen printing process, and then the semiconductor device P2 including the conductive bump BP is placed on the conductive through-hole TV. Afterwards, a reflow process is performed to form a solder joint between the semiconductor device P2 and the conductive through-hole TV of the package structure P11.

[0105] After performing the above-mentioned reflow process, an underfill glue UF is formed between the package structure P11 and the semiconductor device P2 to encapsulate the thermal paste TP and the conductive bump BP. In some embodiments, the material of the underfill glue UF may include an epoxy resin containing a filler and the thermal conductivity of the underfill glue UF may be less than about 1W / mK. The underfill glue UF encapsulates the conductive bump BP in the lateral direction and acts as a stress buffer to minimize fatigue of the conductive bump BP caused by the mismatch of the coefficient of thermal expansion (CTE) between the package structure P11 and the semiconductor device P2.

[0106] After forming the bottom filler UF, a sawing process is performed on the package structure P11 to form a plurality of individualized stacked package (PoP) structures. After performing the sawing process of the package structure P11, the individualized stacked package (PoP) structures are adhered together with the sawing tape ST. In addition, the bottom filler UF can ensure the reliability of the stacked package (PoP) structure including the package structure P11 and the semiconductor device P2.

[0107] According to some embodiments of the present disclosure, there is provided a method for making a chip package comprising the following steps. An integrated circuit component is bonded to a carrier by a first thermal paste, wherein the thermal conductivity of the first thermal paste is in the range of about 10 W / mK to about 250 W / mK. An insulating encapsulation is formed to encapsulate the integrated circuit component bonded to the carrier. A redistribution wiring structure is formed on the insulating encapsulation and the integrated circuit component, wherein the redistribution wiring structure is electrically connected to the integrated circuit component. In an embodiment, the method further comprises: before forming the insulating encapsulation, forming a plurality of conductive perforations on the carrier, so that the plurality of conductive perforations are encapsulated by the insulating encapsulation, wherein after forming the redistribution wiring structure, the plurality of conductive perforations are electrically connected to the integrated circuit component via the redistribution wiring structure. In an embodiment, the method further includes: after forming the redistribution wiring structure, peeling the first thermal paste and the insulating encapsulant from the carrier; and electrically connecting the semiconductor device to the plurality of conductive through-holes so that the first thermal paste is located between the integrated circuit component and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit component via the plurality of conductive through-holes and the redistribution wiring structure. In an embodiment, the method further includes: forming an underfill between the integrated circuit component and the semiconductor device to cover the first thermal paste. In an embodiment, the method further includes: after forming the redistribution wiring structure, peeling the first thermal paste and the insulating encapsulant from the carrier to expose the surface of the first thermal paste; forming a second thermal paste on the exposed surface of the first thermal paste, wherein the thermal conductivity of the second thermal paste is greater than or substantially equal to 10W / mK; and electrically connecting the semiconductor device to the plurality of conductive through-holes so that the first thermal paste and the second thermal paste are located between the integrated circuit component and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit component via the plurality of conductive through-holes and the redistribution wiring structure. In an embodiment, the method further comprises: forming an underfill between the integrated circuit component and the semiconductor device to encapsulate the second thermal paste. In an embodiment, the integrated circuit component comprises an amorphous semiconductor portion located at a rear surface of the integrated circuit component, and the amorphous semiconductor portion of the integrated circuit component contacts the first thermal paste.

[0108] According to some embodiments of the present disclosure, a method for making a chip package is provided, comprising the following steps. An integrated circuit component is provided, on which a metal layer is formed. The integrated circuit component is bonded to a carrier through a die bonding film so that the metal layer is located between the integrated circuit component and the die bonding film, wherein the thermal conductivity of the metal layer is greater than the thermal conductivity of the die bonding film. An insulating encapsulation is formed to encapsulate the integrated circuit component bonded to the carrier. A redistribution wiring structure is formed on the insulating encapsulation and the integrated circuit component, wherein the redistribution wiring structure is electrically connected to the integrated circuit component. In an embodiment, the method further comprises: before forming the insulating encapsulation, forming a plurality of conductive perforations on the carrier, so that the plurality of conductive perforations are encapsulated by the insulating encapsulation, wherein after forming the redistribution wiring structure, the plurality of conductive perforations are electrically connected to the integrated circuit component via the redistribution wiring structure. In an embodiment, the method further comprises: after forming the redistribution wiring structure, peeling the die bonding film and the insulating encapsulant from the carrier; and removing the die bonding film to expose the metal layer; electrically connecting the semiconductor device to the plurality of conductive perforations so that the die bonding film is located between the integrated circuit component and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit component via the plurality of conductive perforations and the redistribution wiring structure. In an embodiment, the method further comprises: forming a bottom filler between the integrated circuit component and the semiconductor device to cover the metal layer. In an embodiment, the method further comprises: after forming the redistribution wiring structure, peeling the die bonding film and the insulating encapsulant from the carrier to expose the die bonding film; removing the die bonding film to expose the metal layer; forming thermal paste on the metal layer; and electrically connecting the semiconductor device to the plurality of conductive perforations so that the metal layer and the thermal paste are located between the integrated circuit component and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit component via the plurality of conductive perforations and the redistribution wiring structure. In an embodiment, the method further comprises: forming an underfill between the integrated circuit component and the semiconductor device to encapsulate the thermal paste. In an embodiment, the integrated circuit component comprises an amorphous semiconductor portion located at a rear surface of the integrated circuit component, and the amorphous semiconductor portion of the integrated circuit component contacts the metal layer. In an embodiment, the thermal conductivity of the metal layer is in a range of about 20 W / mK to about 406 W / mK.

[0109] According to some embodiments of the present disclosure, a chip package is provided, the chip package comprising an integrated circuit component, a heat-conducting layer, an insulating encapsulant and a redistribution wiring structure. The integrated circuit component comprises an amorphous semiconductor portion located at a rear surface of the integrated circuit component. The heat-conducting layer covers the amorphous semiconductor portion of the integrated circuit component, wherein the thermal conductivity of the heat-conducting layer is in the range of about 10 W / mK to about 250 W / mK. The insulating encapsulant encapsulates the integrated circuit component and the heat-conducting layer. The redistribution wiring structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution wiring structure is electrically connected to the integrated circuit component. In an embodiment, the heat-conducting layer comprises a first thermal paste, the first thermal paste contacts the amorphous semiconductor portion of the integrated circuit component. In an embodiment, the heat-conducting layer comprises a first thermal paste and a second thermal paste. The first thermal paste contacts the amorphous semiconductor portion of the integrated circuit component, and the thermal conductivity of the first thermal paste is in the range of about 10 W / mK to about 250 W / mK. A second thermal paste covers the first thermal paste, wherein the thermal conductivity of the second thermal paste is in the range of about 10 W / mK to about 250 W / mK. In an embodiment, the thermally conductive layer includes a metal layer, the metal layer contacts the amorphous semiconductor portion of the integrated circuit component, and the thermal conductivity of the metal layer is in the range of about 20 W / mK to about 406 W / mK. In an embodiment, the thermally conductive layer includes a metal layer and a thermal paste. The metal layer contacts the amorphous semiconductor portion of the integrated circuit component. The thermal paste covers the metal layer, wherein the thermal paste is partially embedded in the insulating encapsulation.

[0110] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

Claims

1. A chip package, characterized in that: include: an integrated circuit component including an amorphous semiconductor portion located at a rear surface of the integrated circuit component; a thermally conductive layer covering the amorphous semiconductor portion of the integrated circuit component, wherein the thermal conductivity of the thermally conductive layer is in the range of 10 W / mK to 250 W / mK; An insulating encapsulation body, encapsulating the integrated circuit component and the heat-conducting layer; a redistribution wiring structure disposed on the insulating package and the integrated circuit component, wherein the redistribution wiring structure is electrically connected to the integrated circuit component; a semiconductor device disposed on the integrated circuit component and the insulating package, wherein the semiconductor device is electrically connected to the integrated circuit component; A plurality of conductive through-holes penetrate the insulating enclosure; as well as A plurality of conductive bumps are disposed between the semiconductor device and the plurality of conductive through-holes, wherein the semiconductor device is electrically connected to the integrated circuit component through the plurality of conductive bumps, the plurality of conductive through-holes and the redistribution line structure.

2. The chip package according to claim 1, characterized in that: The thermally conductive layer includes a first thermal paste, the first thermal paste contacts the amorphous semiconductor portion of the integrated circuit component.

3. The chip package according to claim 1, characterized in that: The heat conducting layer comprises: a first thermal paste contacting the amorphous semiconductor portion of the integrated circuit component, the first thermal paste having a thermal conductivity ranging from 10 W / mK to 250 W / mK; and A second thermal paste covers the first thermal paste, wherein the thermal conductivity of the second thermal paste is in the range of 10 W / mK to 250 W / mK.

4. The chip package according to claim 1, wherein: The heat conducting layer comprises a metal layer, the metal layer contacts the amorphous semiconductor portion of the integrated circuit component, and the thermal conductivity of the metal layer is in a range of 20 W / mK to 406 W / mK.

5. The chip package according to claim 1, characterized in that: The heat conducting layer comprises: a metal layer contacting the amorphous semiconductor portion of the integrated circuit component; and A thermal paste covers the metal layer, wherein the thermal paste is partially embedded in the insulating enclosure.

6. The chip package according to claim 5, characterized in that: The interface between the metal layer and the thermal paste is lower than the top surface of the insulating enclosure.

7. A chip package, characterized in that: include: Integrated circuit components; a metal layer, comprising a bottom surface and a top surface opposite to the bottom surface, wherein the bottom surface of the metal layer contacts the rear surface of the integrated circuit component; an insulating encapsulation body, laterally encapsulating the integrated circuit component and the metal layer, the insulating encapsulation body comprising a first surface and a second surface opposite to the first surface, wherein the top surface of the metal layer is lower than the first surface of the insulating encapsulation body; a redistribution wiring structure disposed on the second surface of the insulating package and on the front surface of the integrated circuit component, wherein the redistribution wiring structure is electrically connected to the integrated circuit component; a semiconductor device disposed on the integrated circuit component and the insulating package, wherein the semiconductor device is electrically connected to the integrated circuit component; A plurality of conductive through-holes penetrate the insulating enclosure; as well as A plurality of conductive bumps are disposed between the semiconductor device and the plurality of conductive through-holes, wherein the semiconductor device is electrically connected to the integrated circuit component through the plurality of conductive bumps, the plurality of conductive through-holes and the redistribution line structure.

8. The chip package according to claim 7, characterized in that: The thermal conductivity of the metal layer is in the range of 20 W / mK to 406 W / mK.

9. The chip package according to claim 7, further comprising: An underfill glue laterally encapsulates the plurality of conductive bumps, wherein the underfill glue contacts the top surface of the metal layer.

10. The chip package according to claim 7, characterized in that: A first shortest distance between the metal layer and the semiconductor device is greater than a second shortest distance between the insulating encapsulation body and the semiconductor device.

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