Contact fabrication for undercut mitigation
By forming a titanium or titanium-tungsten barrier layer and a tin seed layer on the conductive characteristics of microelectronic devices, and combining the reaction of copper structures to form bronze materials, the undercut problem is solved, and a conductive contact structure with low impedance and high mechanical integrity is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TEXAS INSTRUMENTS INC
- Filing Date
- 2019-06-17
- Publication Date
- 2026-06-05
Smart Images
Figure CN110660764B_ABST
Abstract
Description
Background Technology
[0001] Microelectronic devices, such as integrated circuits and discrete devices, include one or more electronic components, such as transistors, capacitors, inductors, etc. Microelectronic device packages have one or more externally accessible connections for eventual soldering to the user's printed circuit board (PCB). Various microelectronic device package types are available, including structures with pins or pads, and flip-chip packages. Flip-chip packages use bonding wires to solder conductive contacts on a semiconductor die to conductive features on a lead frame for electrical connections to pins or pads, or to solder die contacts to a product substrate or chip carrier. Low-impedance connections between conductive contacts and the electronics within the semiconductor die are desirable. However, undercutting during the formation of conductive contacts on the semiconductor die can increase impedance and / or reduce the mechanical integrity of the conductive contact structure. Undercutting problems can arise due to the faster etching of sputtered seed copper compared to the plated copper on the die contact pillars or posts caused by galvanic corrosion of the sputtered seed copper formed on the underlying barrier layer. Summary of the Invention
[0002] The described example provides a method for manufacturing a contact structure, including forming a titanium or tungsten titanate barrier layer on a conductive feature of a wafer or die, forming a tin seed layer on the barrier layer, and forming a copper structure on the seed layer above the conductive feature. The method further includes heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing exposed portions of the seed layer, and removing exposed portions of the barrier layer. A further description provides a microelectronic device including an electronic component, a metallization structure, and a contact structure disposed on or within a semiconductor substrate of a wafer or die. The contact structure includes a barrier layer at least partially disposed on a conductive feature of the metallization structure, a copper structure extending at least partially outward from a side of the metallization structure, and a bronze material disposed between the barrier layer and the copper structure. Attached Figure Description
[0003] Figure 1 This is a partial cross-sectional side view of a microelectronic device with a contact structure containing bronze material between a barrier layer and a copper pillar structure.
[0004] Figure 2 This is a flowchart of a method for manufacturing microelectronic devices and their contact structures.
[0005] Figures 3-13 It is based on Figure 2 A partial cross-sectional side view of a microelectronic device that has undergone manufacturing processes.
[0006] Figure 14 It is a partial cross-sectional side view of a microelectronic device, in which bonding wires are welded to the contact structure.
[0007] Figure 15 It is a partial cross-sectional side view of a microelectronic device, in which the contact structure is soldered to a flip-chip substrate.
[0008] Figure 16 This is a partial cross-sectional side view of a packaged integrated circuit microelectronic device, in which bonding wires are soldered between the contact structure and the lead frame in the molded package. Detailed Implementation
[0009] In the accompanying drawings, the same reference numerals always denote the same elements, and various features are not necessarily drawn to scale. In the following discussion and claims, the terms "including / includes," "having / has," "with," or variations thereof are intended to be included in a manner similar to the term "comprising," and therefore should be interpreted as "including but not limited to...". Furthermore, the term "couple" is intended to include indirect or direct electrical or mechanical connections or combinations thereof. For example, if a first device is coupled to or with a second device, the connection can be a direct electrical connection or an indirect electrical connection via one or more intermediate devices and connections.
[0010] Figure 1 A microelectronic device 100 is illustrated, comprising electronic components 101 (e.g., metal-oxide-semiconductor (MOS) transistors) disposed on or within a semiconductor substrate 102. While the example microelectronic device 100 is an integrated circuit having multiple components 101, other microelectronic device embodiments may include a single electronic component. In one example, the semiconductor substrate 102 is a silicon wafer, a silicon-on-insulator (SOI) substrate, or other semiconductor structure. One or more isolation structures 103 are formed on selected portions of the upper surface of the substrate 102. In some examples, the isolation structure 103 may be a shallow trench isolation (STI) feature or a field oxide (FOX) structure.
[0011] Multilayer metallization structures 104 and 106 are disposed above substrate 102. The metallization structure includes a first dielectric structure layer 104 formed above substrate 102 and a multilayer upper metallization structure 106. In one example, the first dielectric structure layer 104 is a front metal dielectric (PMD) layer disposed above the upper surfaces of component 101 and substrate 102. In one example, the first dielectric structure layer 104 includes silicon dioxide (SiO2) deposited on component 101, substrate 102, and isolation structure 103. In one example, the upper metallization structure 106 is a multilayer structure. In one example, the multilayer structure is formed into a multilayer metallization structure using integrated circuit manufacturing processes. Figure 1 Example 6 shows a top metallization structure 106, including a first layer 108, referred to herein as an intermediate layer or interlayer dielectric (ILD) layer. Different numbers of layers may be used in different embodiments. In one example, the first ILD layer 108 and the other ILD layers of the top metallization structure 106 are formed of silicon dioxide (SiO2) or other suitable dielectric materials. In some embodiments, the individual layers of the multilayer top metallization structure 106 are formed in two stages, including an intrametallic dielectric (IMD, not shown) sublayer and an ILD sublayer covering the IMD sublayer. Individual IMD and ILD sublayers may be formed of any suitable one or more dielectric materials, such as SiO2-based dielectric materials.
[0012] Tungsten or other conductive contacts 110 extend through selective portions of the first dielectric structure layer 104. Subsequent ILD layers in the first ILD layer 108 and the upper metallization structure 106 include conductive metallized interconnect structures 112, such as aluminum formed on the top surface of the underlying layer. In this example, the first layer 108 and subsequent ILD layers also include conductive vias 113, such as tungsten, providing electrical connections from the metallization features 112 of a single layer to the overlying metallization layer. Figure 1 An example includes a second layer 114 disposed above a first layer 108. The second ILD layer 108 includes conductive interconnect structures 112 and vias 113. The illustrated structure also includes metallization layers with corresponding dielectric layers 115, 116, and 117, and an uppermost or topmost metallization layer 118. A substrate 102, electronic components 101, a first dielectric structure layer 104, and an upper metallization structure 106 constitute a wafer or die 120 having an upper side or surface 121. In this example, each individual layer 115-118 includes a conductive interconnect structure 112 and an associated via 113.
[0013] The top metallization layer 118 includes two example conductive features 119, such as an uppermost aluminum via. The conductive features 119 are located on the side or surface of the upper side 121 of the wafer or die 120 at the top of the uppermost metallization layer 118. Any number of conductive features 119 may be provided. One or more of the conductive features 119 may be electrically coupled to the electronic component 101. In one example, the upper ILD dielectric layer 118 is covered by one or more protective layers (e.g., protective outer coating (PO) and / or passivation layers, not shown), such as silicon nitride (SiN), silicon oxynitride (SiO2), etc. x N y The protective layer may be made of silicon dioxide (SiO2) or other materials. In one example, one or more protective layers include one or more openings that expose a portion of the conductive feature 119 to allow the feature 119 to be electrically connected to the corresponding contact structure.
[0014] Figure 1 The microelectronic device 100 also includes two example contact structures 132. Each contact structure 132 is electrically coupled to a corresponding conductive feature 119. Each contact structure 132 includes a barrier layer 122, which, together with a copper structure 126, is at least partially disposed on the corresponding conductive feature 119, extending at least partially outward from the upper side 121 of the wafer or die 120 (e.g., on...). Figure 1 Extending upwards. The single contact structure 132 also includes a bronze material 124 disposed between the barrier layer 122 and the copper structure 126. In one example, the bronze material layer 124 has a thickness of 300 μm or more and 800 μm or less (e.g., along...). Figure 1 (in the vertical or Y-axis direction). In one example, the barrier layer 122 comprises titanium (Ti) or titanium-tungsten (TiW). In one example, the thickness of the barrier layer 122 is less than the thickness of the bronze material layer 124.
[0015] In one example, copper structure 126 provides copper pillars or posts for subsequent soldering to a flip chip substrate or chip carrier, or for soldering to bonding wires during packaging. In one example, bronze material 124 provides conductive coupling between copper structure 126 and barrier layer 122. In one example, the lateral dimensions of barrier layer 122, bronze material 124, and copper structure 126 (e.g., along...) Figure 1 The x-axis direction of the two structures is approximately equal to each other. In particular, due to the reduction or elimination of the undercut of the bronze material 124 below the copper structure 126 during manufacturing, the lateral dimensions of the bronze material 124 and the copper structure 126 are substantially equal in one embodiment. This facilitates low-impedance coupling of the copper structure 126 to the conductive features 119 of the wafer or die 120.
[0016] In one example, contact structure 132 also includes solder 130, such as tin-silver (SnAg) on or above copper structure 126, but this is not required in all possible implementations. In one example, contact structure 132 also includes a diffusion barrier layer 128, such as a nitride material disposed between copper structure 126 and solder 130, but other implementations in which diffusion barrier layer 128 and / or solder 130 are omitted are also possible. In another example, copper structure 126 is directly soldered to a chip carrier substrate or bonding wire using solder supplied during the packaging process.
[0017] Figure 2 A method 200 for manufacturing microelectronic devices is shown, for example... Figure 1 Device 100. Example method 200 includes a process or method for manufacturing the contact structure of an electronic device, for example... Figure 1 The contact structure 132. Figures 3-13The processing at various intermediate stages of manufacturing is shown to manufacture according to method 200. Figure 1 Device 100. Method 200 begins at 202 with the fabrication of one or more electronic components on and / or in a substrate. Any suitable semiconductor processing step may be used at 202 to fabricate one or more electronic components on and / or in a semiconductor substrate 102. For example, the processing at 202 may include fabricating one or more transistors 101 on and / or in a semiconductor substrate 102, such as... Figure 3 As shown. In one example, the fabrication at 202 includes fabricating additional structural features, such as... Figure 3 The isolation structure 103 shown is illustrated. Figure 2 Method 200 also includes fabricating a metallization structure above the substrate at 204 (e.g., Figure 3 The first dielectric structure layer 104 and the upper metallization structure 106 are located above the middle substrate 102. In some examples, the construction of the metallization structure at 204 may further include at least partially fabricating one or more additional electronic components (e.g., resistors, inductors, capacitors, transformers, not shown) within the metallization structure. In one example, the treatment at 202 and 204 provides, for example, Figure 3 The wafer shown is 120.
[0018] Figure 2 Further processing at positions 206-226 provides a method for fabricating contact structures, such as... Figure 1 The contact structure 132 in the example. In this example, method 200 includes forming a barrier layer at least partially on the conductive features of wafer 120 at location 204. Figure 4 An example is shown, which includes performing a sputtering or electroplating deposition process 400 to deposit a barrier layer 122 on the upper side surface 121 of a wafer 120. In one example, the deposition process 400 forms a titanium or titanium-tungsten material barrier layer 122 on the wafer side surface 121, which extends at least partially over the conductive features 119 of the wafer 120.
[0019] Method 200 also includes forming a seed layer on the barrier layer at 208. Figure 5An example is shown, including performing a deposition process 500 to form a tin (Sn) seed layer 123 on a barrier layer 122. In one example, the deposition process 500 forms a tin seed layer 123 with a thickness of 300 μm or more and 800 μm or less. In one example, process 500 is a sputtering process that deposits tin directly onto a TiW or Ti barrier layer 122. In another example, an electroplating deposition process 500 can be used to form the tin seed layer 123 on the barrier layer 122. In one example, the seed layer 123 provides a conductive material to facilitate subsequent electroplating to form a copper structure (e.g., Figure 1 (Copper structure 126 in the example). Furthermore, using tin in the seed layer 123 facilitates the subsequent formation of bronze over the barrier layer 122 (e.g., Figure 1 The use of sputtered copper (124) for the seed layer, and further facilitates the removal of portions of the bronze 124 without significant undercut. In this respect, using sputtered copper for the seed layer can lead to undesirable undercut during subsequent etching, where the etching process preferentially removes the sputtered copper seed layer material at a higher etch rate than overlaid copper. According to process 200, using deposited tin and subsequently formed bronze for the seed layer material advantageously reduces or mitigates undercut and facilitates the construction of a low-impedance contact structure to allow for low-impedance electrical coupling to the conductive features 119 of wafer 120 during subsequent packaging operations.
[0020] Method 200 in Figure 2 The process continues, wherein copper pillars or pillar structures are formed above the deposited seed layer at locations 210, 212, and 214. One example embodiment includes forming a photoresist layer at 210 and patterning the photoresist layer at 212 to form openings for the pillars. Figure 6 An example deposition process 600 is shown for depositing and patterning a photoresist material layer 602 on a tin seed layer 123. In one example, the photoresist layer 602 is patterned at 212 using a photolithography process that selectively removes portions of the photoresist material 602 to expose a portion of the tin seed layer 123 above the conductive feature 119 of the wafer 120. In one example, the lateral (X-axis) width of the openings in the photoresist layer 602 typically extends coexisting with the lateral width of the conductive feature 119 of the wafer 120, although this is not required in all possible implementations. The copper structure formation in this example includes depositing copper material on the exposed portion of the tin seed layer 123 above the conductive feature at 214. Figure 7An example is shown, comprising performing an electroplating deposition process 700, which forms a copper structure 126 in an opening of a photoresist 602. Process 700 forms the copper structure 126 on an exposed portion of a seed layer 123 above a conductive feature 119 of a wafer 120. As previously described, the initial use of a tin barrier layer 123 directly beneath the deposited copper structure 126, and the subsequent reaction forming bronze 124 beneath the electroplated copper structure 126, advantageously mitigates or avoids undercutting in subsequent etching steps during the fabrication of the microelectronic device 100. Furthermore, the use of a thin tin barrier layer 123 (e.g., 300 μm to 800 μm) advantageously mitigates or avoids the formation of Kirkendall voids at the interface between the copper pillar structure 126 and the tin seed layer 123.
[0021] In one example, the contact structure 132 also includes a diffusion barrier layer (e.g., Figure 1 128), and solder (e.g., 130) above the deposited copper structure 126. In this example, method 200 also includes... Figure 2 A diffusion barrier layer is formed at 216 locations. Figure 8 An example process 800 is shown for forming a diffusion barrier layer 128 on a portion of a copper structure 126 exposed by photoresist 602. In one example, process 800 forms a nickel (Ni) diffusion barrier layer 128 on the exposed portion of the copper structure 126. In another example, the formation of the diffusion barrier layer at 216 is omitted.
[0022] exist Figure 2 In one example, method 200 also includes forming solder on a diffusion barrier layer (if included) at 218, or forming solder directly on an exposed portion of the copper structure 126 at 218. Figure 9 An example process 900 is shown, which forms solder (e.g., tin-silver or SnAg) 130 on a diffusion barrier layer 128 above a copper structure 126. In one example, the solder 130 is formed at 218 by electroplating process 900. In another example, solder deposition at 218 and diffusion barrier layer formation at 216 are omitted.
[0023] Figure 2 Method 200 continues at 220, where the remaining resist layer is removed. Figure 10A photoresist removal process 1000 (e.g., selective etching) is illustrated to remove photoresist material 602 from wafer 120. Although the example method 200 shown and described above uses a damascene-type process to form a copper structure 126 using patterned photoresist 602, other processing steps can also be used to form a conductive copper structure on a seed layer above the conductive features 119 of wafer 120. Furthermore, although the illustrated example wafer 120 includes multiple conductive features 119 and corresponding contact structures 132, other embodiments in which only a single contact structure 132 is formed are possible, and other examples in which more than two contact structures 132 are possible.
[0024] exist Figure 2 Continuing at 222, method 200 further includes heating the seed layer 123 and the copper structure 126 to form a bronze material 124 between the barrier layer 122 and the copper structure 126. Figure 11 An example is shown in which the annealing process 1100 is performed at a temperature sufficient to react the deposited tin seed layer 123 with the overlying electroplated copper 126 to form a bronze material 124 between the underlying barrier layer 122 and the overlying electroplated copper structure 126 above the corresponding conductive feature 119 of the wafer 120. In one example, the annealing process 1100 causes tin and copper to diffuse at the interface of the copper pillar structure 126, resulting in the formation of the bronze material 124, as shown. Figure 11 As shown.
[0025] Method 200 also includes in Figure 2 At point 224, the exposed portion of the remaining tin seed layer 123 is removed to expose a portion of the barrier layer 122. Figure 12 An example of performing an etching process 1200 is shown, which etches the exposed tin seed layer 123. (See example...) Figure 12As shown, process 1200 selectively removes the exposed portion of the tin seed layer 123 to expose a portion of the barrier layer 122. In one example, the etching process 1200 uses an acidic stripping solution (e.g., Enstrip TL-105 from Enthone, where no current is required by immersing the wafer 120 in the solution). The etching process 1200 selectively removes the exposed portion of the tin seed layer 123 from the portion beneath the barrier layer 122. In another example, the tin seed layer 123 is selectively removed at 224 by immersion in a hot solution of potassium hydroxide or sodium hydroxide, while substantially not removing copper 126. Alternatively, Enstrip TL-105 (from Enthone) can be used by immersing a working sample in this solution, and no current is required. Other selective etching processes 1200 can be used, for example, using solutions designed to remove tin from copper and copper alloys. The process 1200 selectively removes the remaining (e.g., unreacted) seed layer material 123 and the previously diffused bronze material 124 between the copper 126 and the Ti / TiW barrier layer 122 to mitigate or avoid undercutting problems found in the process of replacing the seed layer with a sputtered copper seed layer (not shown).
[0026] exist Figure 2 The intermediate process 200 continues at 226, where the exposed barrier layer 122 is removed. Figure 13 An example of using a selective etching process 1300 is shown, which removes exposed portions of the barrier layer 122 between contact structures 132. The microelectronic device fabrication process 200 ends at 228 with die singulation (e.g., separating wafer 120 into two or more dies) and packaging of each individual microelectronic device die. Figure 14 An example packaged microelectronic device 100 undergoing a packaging process 1400 is shown, in which bonding wires 1402 are soldered to a constructed contact structure 132 using solder 1404. Figure 15 Another example is shown of a microelectronic device 100 undergoing a flip-chip bonding process 1500, which bonds a constructed contact structure 132 to a conductive pad or feature 1504 of a flip-chip substrate 1502.
[0027] The completed microelectronic device 100 may include other features such as molded or ceramic packaging materials, lead frames, solder bumps, etc. Figure 16 An example integrated circuit (IC) 1600 including microelectronic device 100 is shown. This example includes bonding wire 1402 (e.g., the one above). Figure 14The bonding wires 1402 and the lead frame electrical conductors 1602 (e.g., leads, pins, or pads) are soldered between the contact structure 132 and the lead frame. Example IC 1600 also includes a molded package material 1604 (e.g., plastic) that encapsulates the die 120, contact structure 132, bonding wires 1402, and a portion of the electrical conductors 1602. Example electrical conductors 1602 are IC pins or pads that can be soldered to a main printed circuit board (PCB, not shown).
[0028] The examples above illustrate only a few possible embodiments of various aspects of this disclosure, and equivalent changes and / or modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. Modifications are possible in the described embodiments, and other embodiments are also possible within the scope of the claims.
Claims
1. A method for manufacturing a contact structure, the method comprising: At least partially, a barrier layer is formed on the conductive features of the wafer or die; A seed layer comprising tin is formed at least partially on the barrier layer; A copper structure is formed on the seed layer above the conductive features of the wafer or die to expose a portion of the seed layer; The seed layer and the copper structure are heated to form a bronze material between the barrier layer and the copper structure; Remove the exposed portion of the seed layer to expose a portion of the barrier layer; as well as Remove the exposed portion of the barrier layer.
2. The method according to claim 1, wherein the barrier layer comprises titanium or titanium-tungsten.
3. The method according to claim 2, wherein forming the copper structure on the seed layer comprises: A resist layer is formed on the seed layer; Pattern the resist layer to expose a portion of the seed layer above the conductive features of the wafer or die; Copper material is deposited on the exposed portion of the seed layer; as well as The resist layer is removed before heating the seed layer and the copper structure.
4. The method of claim 3, wherein depositing the copper material on the exposed portion of the seed layer comprises performing an electroplating process that deposits the copper material on the exposed portion of the seed layer.
5. The method of claim 2, wherein removing the exposed portion of the seed layer comprises: An etching process is performed using an acidic stripping solution, which selectively removes the exposed portion of the seed layer from the lower portion of the barrier layer.
6. The method of claim 1, wherein forming the copper structure on the seed layer comprises: A resist layer is formed on the seed layer; Pattern the resist layer to expose a portion of the seed layer above the conductive features of the wafer or die; as well as Copper material is deposited on the exposed portion of the seed layer; as well as The resist layer is removed before heating the seed layer and the copper structure.
7. The method of claim 6, wherein removing the exposed portion of the seed layer comprises: An etching process is performed using an acidic stripping solution, which selectively removes the exposed portion of the seed layer from the lower portion of the barrier layer.
8. The method of claim 1, wherein removing the exposed portion of the seed layer comprises: An etching process is performed using an acidic stripping solution, which selectively removes the exposed portion of the seed layer from the lower portion of the barrier layer.
9. The method according to claim 1, further comprising: Solder is formed on or above the copper structure.
10. The method of claim 9, further comprising: A diffusion barrier layer is formed on the copper structure; as well as The solder is formed on the diffusion barrier layer above the copper structure.
11. A microelectronic device, comprising: Electronic components, which are disposed on or within a semiconductor substrate of a wafer or die; Metallized structures, including conductive features; and Contact structure, including: A barrier layer, which is at least partially disposed on the conductive feature, A seed layer, at least partially located on the barrier layer, the seed layer comprising tin; A copper structure that extends at least partially outward from the side of the metallized structure, and A bronze material is disposed between the barrier layer and the copper structure.
12. The microelectronic device of claim 11, wherein the barrier layer comprises titanium or titanium-tungsten.
13. The microelectronic device according to claim 12, wherein, The contact structure also includes solder on or above the copper structure.
14. The microelectronic device according to claim 13, wherein, The contact structure also includes a diffusion barrier layer disposed between the copper structure and the solder.
15. The microelectronic device of claim 11, wherein the contact structure further comprises solder on or above the copper structure.
16. The microelectronic device according to claim 15, wherein, The contact structure also includes a diffusion barrier layer disposed between the copper structure and the solder.
17. A method for manufacturing a microelectronic device, the method comprising: Fabrication of electronic components on or in a semiconductor substrate; Fabricating a metallization structure over the semiconductor substrate, including fabricating conductive features of a wafer or die along the side of the metallization structure; Manufacturing contact structures includes: A titanium or titanium-tungsten barrier layer is formed at least partially on the conductive feature. A tin seed layer is formed at least partially on the barrier layer. A copper structure is formed on the seed layer above the conductive features of the wafer or die to expose a portion of the seed layer. The seed layer and the copper structure are heated to form a bronze material between the barrier layer and the copper structure. The seed layer is etched using an etching process that selectively removes exposed portions of the seed layer to expose a portion of the barrier layer. Remove the exposed portion of the barrier layer; as well as The contact structure is soldered to the bonding wire or flip chip substrate.
18. The method of claim 17, wherein forming the copper structure on the seed layer comprises: A resist layer is formed on the seed layer; Pattern the resist layer to expose a portion of the seed layer above the conductive features of the wafer or die; Copper material is deposited on the exposed portion of the seed layer; as well as The resist layer is removed before heating the seed layer and the copper structure.
19. The method of claim 17, further comprising: Solder is formed on or above the copper structure.
20. The method of claim 19, further comprising: A diffusion barrier layer is formed on the copper structure; as well as The solder is formed on the diffusion barrier layer.
21. A contact structure, comprising: At least partially on the conductive features of the wafer or die; A seed layer, at least partially on the barrier layer, the seed layer comprising tin; as well as A copper structure on the seed layer above the conductive features of the wafer or die; as well as Bronze material between the barrier layer and the copper structure.
22. The contact structure according to claim 21, wherein the barrier layer comprises titanium or titanium-tungsten.
23. The contact structure according to claim 22, wherein the copper structure on the seed layer comprises: A resist layer on the seed layer, exposing a portion of the seed layer; as well as Copper material on the exposed portion of the seed layer.
24. The contact structure of claim 23, wherein the copper material on the exposed portion of the seed layer comprises electroplated copper material on the exposed portion of the seed layer.
25. The contact structure of claim 23, wherein the exposed portion of the seed layer is removed from the lower portion of the barrier layer.
26. The contact structure according to claim 21, wherein the copper structure on the seed layer comprises: A resist layer on the seed layer, exposing a portion of the seed layer; The exposed portion of the seed layer above the conductive feature of the wafer or die; as well as Copper material on the exposed portion of the seed layer.
27. The contact structure of claim 26, wherein the selective lower portion of the blocking layer is removed.
28. The contact structure of claim 21, wherein a selective portion of the exposed seed layer is removed from the lower portion of the barrier layer.
29. The contact structure according to claim 21, further comprising: Solder on or above the copper structure.
30. The contact structure according to claim 29, further comprising: A diffusion barrier layer on the copper structure; as well as Solder on the diffusion barrier layer above the copper structure.
31. A microelectronic device, comprising: Electronic components on or in a semiconductor substrate; The metallization structure above the semiconductor substrate includes conductive features along the side surface of the metallization structure; Contact structure, including: At least partially, a titanium barrier layer or a titanium-tungsten barrier layer is applied to the conductive feature. At least partially on the barrier layer, and A copper structure on the seed layer above the conductive features of the wafer or die. Bronze material between the barrier layer and the copper structure; as well as Bonding wires or flip-chip substrates attached to the contact structure.
32. The microelectronic device of claim 31, wherein the copper structure on the seed layer comprises: A resist layer on the seed layer, exposing a portion of the seed layer; as well as Copper material on the exposed portion of the seed layer.
33. The microelectronic device according to claim 31, further comprising: Solder on or above the copper structure.
34. The microelectronic device according to claim 31, further comprising: A diffusion barrier layer on the copper structure; as well as Solder on the diffusion barrier layer.