Display Devices

Abstract

The present application relates to a display device. The display device includes a display panel, a data driver, a power supply voltage generator, a drive controller and a timing compensator. The display panel displays an image based on input image data. The data driver outputs a data voltage to the display panel. The power supply voltage generator outputs a data power supply voltage to the data driver. The drive controller controls the driving timing of the data driver. When the feedback data power supply voltage is smaller than the reference data power supply voltage at the starting point of the effective period, the timing compensator changes the output timing of the data voltage of the data driver.

Description

Technical Field

[0001] Exemplary embodiments of the present invention relate to a power supply voltage generating circuit and a display device including the same. More specifically, exemplary embodiments of the present invention relate to a power supply voltage generating circuit for compensating for ripple of a data power supply voltage and a display device including the same. Background Art

[0002] A display device generally includes a display panel, a display panel driver driving the display panel, and a power supply voltage generator supplying a power supply voltage to the display panel driver.

[0003] The display panel generally includes a plurality of gate lines, a plurality of data lines and a plurality of pixels. The display panel driver generally includes a gate driver and a data driver, wherein the gate driver outputs gate signals to the plurality of gate lines and the data driver outputs data voltages to the plurality of data lines. Summary of the invention

[0004] According to a load of the data driver, a ripple may be generated at a data power voltage supplied to the data driver. The display quality of the display panel may be deteriorated due to the ripple of the data power voltage.

[0005] Exemplary embodiments of the present invention provide a power supply voltage generating circuit that compensates for a ripple of a data power supply voltage to improve display quality.

[0006] Exemplary embodiments of the present invention also provide a display device including the above-mentioned power supply voltage generating circuit.

[0007] In an exemplary embodiment of a display device according to the present invention, the display device includes a display panel, a data driver, a power supply voltage generator, a drive controller and a timing compensator. The display panel displays an image based on input image data. The data driver outputs a data voltage to the display panel. The power supply voltage generator outputs a data power supply voltage to the data driver. The drive controller controls the driving timing of the data driver. When the feedback data power supply voltage is smaller than the reference data power supply voltage at the starting point of the effective period, the timing compensator changes the output timing of the data voltage of the data driver.

[0008] In an exemplary embodiment, the reference data power supply voltage may be a data power supply voltage that is fed back after a first time from a rising edge of the vertical start signal.

[0009] In an exemplary embodiment, the timing compensator may adjust the output timing of the data voltage so that a starting point of the output data voltage is in a vertical blanking period before the effective period.

[0010] In an exemplary embodiment, the timing compensator may include an analog-to-digital converter and a data power supply voltage comparator, wherein the analog-to-digital converter converts the feedback data power supply voltage and the reference data power supply voltage, and the data power supply voltage comparator compares the converted feedback data power supply voltage and the converted reference data power supply voltage.

[0011] In an exemplary embodiment, the analog-to-digital converter and the data power supply voltage comparator may be provided in the power supply voltage generator.

[0012] In an exemplary embodiment, the analog-to-digital converter may be provided in the power supply voltage generator. The data power supply voltage comparator may be provided in the driving controller.

[0013] In an exemplary embodiment, the power supply voltage generator may include a capacitor, an inductor, a diode, a switch, a resistor, an error amplifier, a comparator, and a switch controller, wherein the capacitor includes a first electrode connected to an input node and a second electrode connected to ground, the inductor includes a first end connected to the input node and a second end connected to the first node, the diode includes an anode electrode connected to the first node and a cathode electrode connected to the output node, the switch includes a control electrode connected to the switch controller, an input electrode connected to the first node, and an output electrode connected to ground, the resistor includes a first end connected to the output node and a second end connected to the feedback node, the error amplifier includes a first input electrode connected to the feedback node, a second input electrode to which a reference voltage is applied, and an output electrode, the comparator includes a first input electrode connected to an output electrode of the error amplifier, a second input electrode to which a comparison voltage is applied, and an output electrode connected to the switch controller, and the switch controller is connected to the comparator and controls the switch. The timing compensator may be connected to the feedback node.

[0014] In an exemplary embodiment, the display device may further include a second timing compensator that applies a load to an output node of the data power supply voltage in a vertical blanking period prior to the active period.

[0015] In an exemplary embodiment, the second timing compensator may include a compensation resistor and a compensation switch connected in series.

[0016] In an exemplary embodiment, the second timing compensator may include a first compensation part and a second compensation part, the first compensation part including a first compensation resistor and a first compensation switch connected in series, and the second compensation part including a second compensation resistor and a second compensation switch connected in series. The second compensation part may be connected in parallel to the first compensation part.

[0017] In an exemplary embodiment, a turn-on period of the first compensation switch may be different from a turn-on period of the second compensation switch.

[0018] In an exemplary embodiment, the power supply voltage generator may include a capacitor, an inductor, a diode, a switch, a resistor, an error amplifier, a comparator, and a switch controller, wherein the capacitor includes a first electrode connected to an input node and a second electrode connected to ground, the inductor includes a first end connected to the input node and a second end connected to the first node, the diode includes an anode electrode connected to the first node and a cathode electrode connected to an output node, the switch includes a control electrode connected to the switch controller, an input electrode connected to the first node, and an output electrode connected to ground, the resistor includes a first end connected to the output node and a second end connected to a feedback node, the error amplifier includes a first input electrode connected to the feedback node, a second input electrode to which a reference voltage is applied, and an output electrode, the comparator includes a first input electrode connected to an output electrode of the error amplifier, a second input electrode to which a comparison voltage is applied, and an output electrode connected to the switch controller, and the switch controller is connected to the comparator and controls the switch. A second timing compensator may be connected to the feedback node.

[0019] In an exemplary embodiment, the display device may further include a second timing compensator which adjusts an output timing of a data voltage of the data driver according to input image data.

[0020] In an exemplary embodiment, the second timing compensator may be provided in the driving controller.

[0021] In an exemplary embodiment of a power supply voltage generating circuit according to the present invention, the power supply voltage generating circuit includes a capacitor, an inductor, a diode, a switch, a resistor, an error amplifier, a comparator, a switch controller and a timing compensator, wherein the capacitor includes a first electrode connected to an input node to which an input voltage is applied and a second electrode connected to ground, the inductor includes a first end connected to the input node and a second end connected to the first node, the diode includes an anode electrode connected to the first node and a cathode electrode connected to an output node to which an output voltage is output, the switch includes a control electrode connected to the switch controller, an input electrode connected to the first node and an output electrode connected to ground, the resistor includes a first end connected to the output node and a second end connected to a feedback node, the error amplifier includes a first input electrode connected to the feedback node, a second input electrode to which a reference voltage is applied, and an output electrode, the comparator includes a first input electrode connected to the output electrode of the error amplifier, a second input electrode to which a comparison voltage is applied, and an output electrode connected to the switch controller, the switch controller is connected to the comparator and controls the switch, the timing compensator is connected to the feedback node to receive a feedback output voltage, and the timing compensator outputs a timing compensation signal according to the level of the feedback output voltage.

[0022] In an exemplary embodiment, the timing compensator may include an analog-to-digital converter and a data power supply voltage comparator, wherein the analog-to-digital converter converts the feedback output voltage and the reference data power supply voltage, and the data power supply voltage comparator compares the converted feedback output voltage and the converted reference data power supply voltage.

[0023] In an exemplary embodiment, the timing compensator may include a compensation resistor and a compensation switch connected in series.

[0024] In an exemplary embodiment, the timing compensator may include a first compensation part and a second compensation part, wherein the first compensation part includes a first compensation resistor and a first compensation switch connected in series, and the second compensation part includes a second compensation resistor and a second compensation switch connected in series. The second compensation part may be connected in parallel to the first compensation part.

[0025] In an exemplary embodiment, a turn-on period of the first compensation switch may be different from a turn-on period of the second compensation switch.

[0026] According to the power supply voltage generating circuit and the display device including the power supply voltage generating circuit, the data power supply voltage is fed back and the waveform of the data power supply voltage is controlled so that the data power supply voltage may not drop during the effective period. Therefore, the display quality of the display panel can be prevented from being deteriorated due to the drop of the data power supply voltage. Therefore, the display quality of the display panel can be improved. In addition, the display panel driving signal is maintained at a uniform level during the vertical blanking period, thereby reducing the power consumption of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features and advantages of the present invention will become more apparent by describing specific exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0028] Figure 1 is a block diagram showing an exemplary embodiment of a display device according to the present invention;

[0029] Figure 2 It is shown Figure 1 A block diagram of a power supply voltage generator and a timing compensator;

[0030] Figure 3 It is shown Figure 2 Block diagram of the timing compensator;

[0031] Figure 4A is shown when the data supply voltage is not passed Figure 2 A timing diagram of a display panel driving signal when compensation is performed by a timing compensator;

[0032] Figure 4B is shown when the data supply voltage is Figure 2A timing diagram of a display panel driving signal when compensation is performed by a timing compensator;

[0033] Figure 5 is a block diagram showing an exemplary embodiment of a power supply voltage generator and a timing compensator according to the present invention;

[0034] Figure 6 It is shown Figure 5 Circuit diagram of timing compensator;

[0035] Fig. 7A is shown when the data supply voltage is not passed Figure 5 A timing diagram of a display panel driving signal when compensation is performed by a timing compensator;

[0036] Figure 7B is shown when the data supply voltage is Figure 5 A timing diagram of a display panel driving signal when compensation is performed by a timing compensator;

[0037] Figure 8 is a circuit diagram showing an exemplary embodiment of a timing compensator according to the present invention;

[0038] Fig. 9 is shown applied to Figure 8 A timing diagram of a control signal of a timing compensator;

[0039] Fig.10 is shown when the data supply voltage is Figure 8 A timing diagram of a display panel driving signal when compensation is performed by a timing compensator;

[0040] Fig.11 is a circuit diagram showing an exemplary embodiment of a drive controller according to the present invention;

[0041] Fig. 12A is a timing diagram showing a display panel driving signal according to first input image data; and

[0042] Fig. 12B is a timing diagram showing a display panel driving signal according to the second input image data. DETAILED DESCRIPTION

[0043] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

[0044] It should be understood that when an element is referred to as being "on" another element, the element may be directly on the other element, or there may be intervening elements between the element and the other element. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0045] It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first part" discussed below may be referred to as a second element, second component, second region, second layer or second part.

[0046] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms (including "at least one") unless the context clearly indicates otherwise. "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "comprises" and / or "comprising" or "includes" and / or "including" represent the presence of stated features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or combinations thereof.

[0047] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in one of the accompanying drawings is turned over, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, depending on the specific orientation of the accompanying drawings, the exemplary term "lower" may include both "lower" and "upper" orientations. Similarly, if the device in one of the accompanying drawings is turned over, the element described as being "below" or "beneath" of the other elements will then be oriented to be "above" the other elements. Therefore, the exemplary term "below" or "below" may include both upper and lower orientations.

[0048] For ease of description, spatially relative terms such as "below", "below", "down", "above", "upper", etc. may be used herein to describe the relationship between one element or feature and another (some) element or feature as shown in the drawings. It should be understood that, in addition to the orientation depicted in the drawings, spatially relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements described as being "below" or "below" other elements or features will then be oriented to be "above" other elements or features. Therefore, the exemplary term "below" may include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0049] As used herein, "about" or "approximately" includes the stated value and the mean within an acceptable deviation range of the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0050] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0051] Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. Therefore, deviations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp angles shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions, and are not intended to limit the scope of the claims.

[0052] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

[0053] Reference Figure 1The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a power supply voltage generator 600.

[0054] The display panel 100 includes a display area and a peripheral area adjacent to the display area.

[0055] The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels electrically connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D1, and the data lines DL extend in a second direction D2 crossing the first direction D1.

[0056] The driving controller 200 receives input image data IMG and an input control signal CONT from an external device (not shown). In an exemplary embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. In an exemplary embodiment, for example, the input image data IMG may include white image data. In an exemplary embodiment, for example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. In an exemplary embodiment, for example, the input control signal CONT may include a main clock signal and a data enable signal. In an exemplary embodiment, for example, the input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0057] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0058] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT and outputs the first control signal CONT1 to the gate driver 300. In an exemplary embodiment, for example, the first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0059] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. In an exemplary embodiment, for example, the second control signal CONT2 may include a horizontal start signal and a load signal.

[0060] The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0061] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0062] The gate driver 300 generates a gate signal driving the gate lines GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may sequentially output the gate signal to the gate lines GL.

[0063] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0064] In the illustrated exemplary embodiment, the gamma reference voltage generator 400 is physically separated from the driving controller 200 and the data driver 500. However, the present invention is not limited thereto. In another exemplary embodiment, for example, the gamma reference voltage generator 400 may be provided in the driving controller 200 or in the data driver 500.

[0065] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200 and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into an analog type data voltage VD using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage VD to the data line DL.

[0066] The power supply voltage generator 600 generates gate power supply voltages VON, VSS1, and VSS2 to operate the gate driver 300, and the power supply voltage generator 600 outputs the gate power supply voltages VON, VSS1, and VSS2 to the gate driver 300. The gate power supply voltages may include a gate-on voltage VON representing a high level of a gate signal, a first gate-off voltage VSS1 representing a low level of the gate signal, and a second gate-off voltage VSS2.

[0067] The power supply voltage generator 600 generates a data power supply voltage AVDD to operate the data driver 500, and the power supply voltage generator 600 outputs the data power supply voltage AVDD to the data driver 500. The data power supply voltage AVDD may be an analog power supply voltage provided to an amplifier in the data driver 500.

[0068] Figure 2 is a diagram showing the timing compensator 700 and Figure 1 600 is a block diagram of a supply voltage generator.

[0069] Figure 3 It is shown Figure 2 A block diagram of a timing compensator 700 is shown.

[0070] Reference Figures 1 to 3 , the power supply voltage generator 600 may include a DC to DC converter that generates the data power supply voltage AVDD.

[0071] The power supply voltage generator 600 includes a capacitor C1 , an inductor L1 , a diode DI, a switch S1 , a resistor R1 , an error amplifier EA, a comparator CP, and a switch controller 620 .

[0072] The capacitor C1 includes a first electrode and a second electrode, wherein the first electrode is connected to an input node to which an input voltage VIN is applied, and the second electrode is connected to the ground.

[0073] The inductor L1 includes a first end and a second end, wherein the first end is connected to the input node and the second end is connected to the first node N1.

[0074] The diode DI includes an anode electrode and a cathode electrode, wherein the anode electrode is connected to the first node N1 and the cathode electrode is connected to an output node outputting a data power supply voltage AVDD. The data power supply voltage AVDD is output to the data driver 500.

[0075] The switch S1 includes a control electrode, an input electrode, and an output electrode, wherein the control electrode is connected to the switch controller 620, the input electrode is connected to the first node N1, and the output electrode is connected to the ground.

[0076] The resistor R1 includes a first end and a second end, wherein the first end is connected to the output node and the second end is connected to the feedback node. The data power supply voltage AVDD is fed back through the feedback node. The power supply voltage generator 600 may also include a feedback resistor R2. The feedback resistor R2 includes a first end and a second end, wherein the first end is connected to the resistor R1 and the second end is connected to the ground. The data power supply voltage AVDD is divided by the resistor R1 and the feedback resistor R2, so that the feedback data power supply voltage AVDDF is applied to the feedback node.

[0077] The error amplifier EA includes a first input electrode and a second input electrode and an output electrode, wherein the first input electrode is connected to the feedback node and the second input electrode is applied with a reference voltage VREF. The difference between the feedback data power supply voltage AVDDF and the reference voltage VREF is amplified by the error amplifier EA, and the amplified difference is output to the comparator CP.

[0078] The comparator CP includes a first input electrode, a second input electrode, and an output electrode, wherein the first input electrode is connected to the output electrode of the error amplifier EA, the second input electrode is applied with a comparison voltage VRAMP, and the output electrode is connected to the switch controller 620. The comparison voltage VRAMP may be a sawtooth wave signal. The output voltage of the comparator CP is provided to the switch controller 620.

[0079] The switch controller 620 is connected to the comparator CP. The switch controller 620 controls the switch S1. In an exemplary embodiment, for example, the switch controller 620 may be a pulse width modulation controller that outputs a pulse width modulation signal. The on-time and off-time of the switch S1 are adjusted according to the switch control signal output by the switch controller 620. The level of the data power supply voltage AVDD may be adjusted according to the on-time and off-time of the switch S1.

[0080] The display device also includes a timing compensator 700 that controls an output timing of the data voltage VD.

[0081] When the feedback data power voltage AVDDF is smaller than the reference data power voltage at the starting point of the effective period, the timing compensator 700 adjusts the output timing of the data voltage VD of the data driver 500 .

[0082] The timing compensator 700 may include an analog-to-digital converter 720 that converts the feedback data power voltage AVDDF and the reference data power voltage and a data power voltage comparator 740 that compares the converted feedback data power voltage AVDDFD and the converted reference data power voltage.

[0083] In an exemplary embodiment, for example, the analog-to-digital converter 720 and the data power supply voltage comparator 740 may be provided in the power supply voltage generator 600. In this case, the data power supply voltage comparator 740 may output the comparison result CR to the driving controller 200.

[0084] In an alternative exemplary embodiment, the analog-to-digital converter 720 may be provided in the power supply voltage generator 600, and the data power supply voltage comparator 740 may be provided in the driving controller 200. In this case, the analog-to-digital converter 720 may output the converted feedback data power supply voltage AVDDFD and the converted reference data power supply voltage to the driving controller 200.

[0085] Figure 4A is shown when the data supply voltage AVDD is not Figure 2 7 is a timing diagram of a display panel driving signal when the timing compensator 700 performs compensation. Figure 4BIt shows that when the data power supply voltage AVDD is Figure 2 7 is a timing diagram of a display panel driving signal when the timing compensator 700 performs compensation.

[0086] Reference Figure 4A , the data power supply voltage AVDD may be maintained at a uniform level during the vertical blanking period VBLANK. When the data driver 500 starts to output the data voltage VD to the display panel 100 in the active period ACTIVE, the data power supply voltage AVDD may be significantly reduced due to a sudden increase in the load of the data driver 500 (period A1).

[0087] When a sufficient time has passed since the start of driving the data driver 500 , the data power supply voltage AVDD returns to a stable level (period A2 ).

[0088] During the period in which the level of the data power voltage AVDD decreases, the level of the data voltage VD applied to the display panel 100 may decrease in response to the target level, thereby reducing the brightness of the image displayed on the upper portion of the display panel 100 corresponding to the starting point of the active period ACTIVE.

[0089] Reference Figure 4B , the timing compensator 700 can adjust the output timing of the data voltage VD so that the starting point of the output data voltage VD is in the vertical blanking period VBLANK before the effective period ACTIVE. The output timing of the data voltage VD can be synchronized with the data clock signal CLK of the data driver 500. Therefore, when the output timing of the data voltage VD changes, the timing of the data clock signal CLK can change.

[0090] In an exemplary embodiment, when the feedback data power supply voltage AVDDF is smaller than the reference data power supply voltage at the starting point of the active period ACTIVE, the timing compensator 700 advances the output timing of the data voltage VD by, for example, a first compensation time. Herein, the reference data power supply voltage may be a data power supply voltage fed back after a first time from a rising edge of the vertical start signal STV. The data power supply voltage fed back after a first time from a rising edge of the vertical start signal STV may have a stable level. The first time may be set to be equal to or greater than a time for stabilizing the data power supply voltage AVDD (e.g., Figure 4A period A1).

[0091] exist Figure 4AIn the example, at the start point of the active period ACTIVE, the data power supply voltage AVDD may be significantly reduced due to a sudden increase in the load of the data driver 500. At the start point of the active period ACTIVE, the timing compensator 700 compares the feedback data power supply voltage AVDDF with the reference data power supply voltage having a stable level after a sufficient time. Figure 4A In the embodiment, the feedback data power voltage AVDDF is smaller than the reference data power voltage at the starting point of the active period ACTIVE, so that the timing compensator 700 advances the output timing of the data voltage VD by the first compensation time.

[0092] In the next frame, the output timing of the data voltage VD is advanced by the first compensation time, and the timing compensator 700 compares the feedback data power voltage AVDDF with the reference data power voltage at the starting point of the active period ACTIVE of the next frame.

[0093] If the feedback data power supply voltage AVDDF is smaller than the reference data power supply voltage at the starting point of the active period ACTIVE of the next frame, the timing compensator 700 advances the output timing of the data voltage VD again by the first compensation time. When the feedback data power supply voltage AVDDF is equal to or greater than (i.e., not less than) the reference data power supply voltage at the starting point of the active period ACTIVE of the next frame, the timing compensator 700 maintains the output timing of the data voltage VD.

[0094] As described above, until the feedback data power supply voltage AVDDF is equal to the reference data power supply voltage at the starting point of the active period ACTIVE, the output timing of the data voltage VD is not adjusted. As a result, the data power supply voltage AVDD drops in the vertical blanking period VBLANK ( Figure 4B The data voltage VD may be in the effective period ACTIVE ( Figure 4B The time period A2 in the embodiment has a target level from the first pulse.

[0095] According to the exemplary embodiment shown, the timing compensator 700 adjusts the data output timing of the data driver 500 based on the feedback data power supply voltage AVDDF, so that the waveform of the data power supply voltage AVDD can be controlled not to drop in the effective period ACTIVE. Therefore, the display quality of the display panel 100 can be prevented from being degraded due to the drop of the data power supply voltage AVDD. Therefore, the display quality of the display panel 100 can be improved. In addition, the display panel drive signal can be maintained at a uniform level during the vertical blanking period VBLANK, so that the power consumption of the display device can be reduced.

[0096] Figure 5is a block diagram illustrating a power supply voltage generator 600 and a timing compensator 800 according to an exemplary embodiment of the present invention. Figure 6 It is shown Figure 5 A circuit diagram of a timing compensator 800 is shown.

[0097] In addition to the timing compensator 800, the power supply voltage generating circuit and the display device according to the exemplary embodiment shown are similar to those of the reference Figures 1 to 4B The power supply voltage generating circuit and the display device of the previously described exemplary embodiment are substantially the same. Therefore, the same reference numerals will be used to represent the same as those in Figures 1 to 4B The same or similar parts as those described in the previous exemplary embodiments are described herein, and any repeated explanation regarding the above elements will be omitted.

[0098] Reference Figure 1 , Figure 5 and Figure 6 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a power supply voltage generator 600.

[0099] The display device further includes a timing compensator 800 that applies a load to an output node of the data power supply voltage AVDD in the vertical blanking period VBLANK.

[0100] In an exemplary embodiment, for example, the display device may include the timing compensator 800 of the illustrated exemplary embodiment instead of Figure 3 In an alternative exemplary embodiment, the display device may include both the timing compensator 700 of the previous exemplary embodiment and the timing compensator 800 of the illustrated exemplary embodiment.

[0101] The timing compensator 800 may include a compensation resistor RA and a compensation switch SA connected in series.

[0102] When the compensation switch SA is turned on, the load of the compensation resistor RA is applied to the output node of the data power voltage AVDD. The compensation switch SA is turned on in the vertical blanking period VBLANK before the active period ACTIVE.

[0103] Fig. 7A is shown when the data supply voltage AVDD is not Figure 5 A timing diagram of a display panel driving signal when the timing compensator 800 performs compensation. Figure 7B It shows that when the data power supply voltage AVDD is Figure 5 A timing diagram of a display panel driving signal when the timing compensator 800 performs compensation.

[0104] Reference Fig. 7A During the vertical blanking period VBLANK, the data power supply voltage AVDD may be maintained at a uniform level. When the data driver 500 starts to output the data voltage VD to the display panel 100 in the active period ACTIVE, the data power supply voltage AVDD may be significantly reduced due to a sudden increase in the load IAVDD of the data driver 500 (period A1).

[0105] When a sufficient time has passed since the start of driving the data driver 500 , the data power supply voltage AVDD returns to a stable level (period A2 ).

[0106] During the period in which the level of the data power voltage AVDD decreases, the level of the data voltage VD applied to the display panel 100 may decrease in response to the target level, thereby reducing the brightness of the image displayed on the upper portion of the display panel 100 corresponding to the starting point of the active period ACTIVE.

[0107] Reference Figure 7B Before the vertical start signal STV is applied, the compensation switch SA is turned on in response to the compensation switch control signal CSA applied to the compensation switch SA. When the compensation switch SA is turned on, a load IAVDD corresponding to the resistance of the compensation resistor RA is applied to the output node of the data power supply voltage AVDD in the vertical blanking period VBLANK.

[0108] As a result, the data power supply voltage AVDD drops in the vertical blanking period VBLANK ( Figure 7B The data voltage VD may be in the effective period ACTIVE ( Figure 7B The time period A2 in the embodiment has a target level from the first pulse.

[0109] According to the exemplary embodiment shown, the timing compensator 800 applies the load IAVDD to the output node of the data power supply voltage AVDD in the vertical blanking period VBLANK, so that the waveform of the data power supply voltage AVDD can be controlled not to drop in the effective period ACTIVE. Therefore, the display quality of the display panel 100 can be prevented from being degraded due to the drop of the data power supply voltage AVDD. Therefore, the display quality of the display panel 100 can be improved. In addition, the display panel driving signal can be maintained at a uniform level during the vertical blanking period VBLANK, so that the power consumption of the display device can be reduced.

[0110] Figure 8 is a circuit diagram showing a timing compensator 800A according to an exemplary embodiment of the present invention. Fig. 9 is shown applied to Figure 8800A is a timing diagram of the control signals of the timing compensator 800A.

[0111] In addition to the timing compensator 800A, the power supply voltage generating circuit and the display device according to the exemplary embodiment shown are similar to those of the reference Figures 1 to 4B The power supply voltage generating circuit and the display device of the previously described exemplary embodiment are substantially the same. Therefore, the same reference numerals will be used to represent the same as those in Figures 1 to 4B The same or similar parts as those described in the previous exemplary embodiments are described herein, and any repeated explanation regarding the above elements will be omitted.

[0112] Reference Figure 1 , Figure 8 and Fig. 9 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a power supply voltage generator 600.

[0113] The display device further includes a timing compensator 800A that applies a load to an output node of the data power supply voltage AVDD in the vertical blanking period VBLANK.

[0114] In an exemplary embodiment, for example, a display device may include the timing compensator 800A of the illustrated exemplary embodiment instead of Figure 3 In an alternative exemplary embodiment, the display device may include both the timing compensator 700 of the previous exemplary embodiment and the timing compensator 800A of the illustrated exemplary embodiment.

[0115] The timing compensator 800A may include a plurality of compensation parts, each of which may include a compensation resistor and a compensation switch connected in series.

[0116] Although the timing compensator 800A includes three compensation sections connected in parallel in the illustrated exemplary embodiment, the present invention is not limited to the number of compensation sections.

[0117] In an exemplary embodiment, for example, the timing compensator 800A includes a first compensation part, a second compensation part, and a third compensation part connected in parallel. The first compensation part may include a first compensation resistor RA and a first compensation switch SA connected in series. The second compensation part may include a second compensation resistor RB and a second compensation switch SB connected in series. The third compensation part may include a third compensation resistor RC and a third compensation switch SC connected in series.

[0118] The on-period of the first compensation switch SA may be different from the on-period of the second compensation switch SB. The on-period of the second compensation switch SB may be different from the on-period of the third compensation switch SC. The on-period of the third compensation switch SC may be different from the on-period of the first compensation switch SA.

[0119] In an exemplary embodiment, for example, the first compensation switch control signal CSA may be valid for a first duration. In an exemplary embodiment, for example, the second compensation switch control signal CSB may be valid for a first duration and a second duration. In an exemplary embodiment, for example, the third compensation switch control signal CSC may be valid for a first duration, a second duration, and a third duration.

[0120] In the first duration, the first compensation switch control signal CSA, the second compensation switch control signal CSB, and the third compensation switch control signal CSC have an active level, so that the first compensation switch SA, the second compensation switch SB, and the third compensation switch SC are turned on.

[0121] In the second duration, the second compensation switch control signal CSB and the third compensation switch control signal CSC have an active level, so that the second compensation switch SB and the third compensation switch SC are turned on.

[0122] In the third duration, the third compensation switch control signal CSC has an active level, so that the third compensation switch SC is turned on.

[0123] Fig.10 It shows that when the data power supply voltage AVDD is Figure 8 A timing diagram of a display panel driving signal when the timing compensator 800A performs compensation.

[0124] Reference Fig. 7A During the vertical blanking period VBLANK, the data power supply voltage AVDD may be maintained at a uniform level. When the data driver 500 starts to output the data voltage VD to the display panel 100 in the active period ACTIVE, the data power supply voltage AVDD may be significantly reduced due to a sudden increase in the load IAVDD of the data driver 500 (period A1).

[0125] When a sufficient time has passed since the start of driving the data driver 500 , the data power supply voltage AVDD returns to a stable level (period A2 ).

[0126] During the period in which the level of the data power voltage AVDD decreases, the level of the data voltage VD applied to the display panel 100 may decrease in response to the target level, thereby reducing the brightness of the image displayed on the upper portion of the display panel 100 corresponding to the starting point of the active period ACTIVE.

[0127] Reference Fig.10 Before the vertical start signal STV is applied, the first compensation switch SA, the second compensation switch SB, and the third compensation switch SC are turned on in response to the first compensation switch control signal CSA, the second compensation switch SB, and the third compensation switch SC applied to the first compensation switch SA, the second compensation switch SB, and the third compensation switch SC. When the first compensation switch SA, the second compensation switch SB, and the third compensation switch SC are turned on, a load IAVDD corresponding to a combined resistance of the first compensation resistor RA, the second compensation resistor RB, and the third compensation resistor RC is applied to the output node of the data power supply voltage AVDD in the vertical blanking period VBLANK.

[0128] In an exemplary embodiment, for example, the first compensation switch SA, the second compensation switch SB, and the third compensation switch SC are turned on in the first duration, so that a first load corresponding to the parallel resistance of the first compensation resistor RA, the second compensation resistor RB, and the third compensation resistor RC can be applied to the output node of the data power supply voltage AVDD. The second compensation switch SB and the third compensation switch SC are turned on in the second duration, so that a second load corresponding to the parallel resistance of the second compensation resistor RB and the third compensation resistor RC can be applied to the output node of the data power supply voltage AVDD. The second load may be greater than the first load. The third compensation switch SC is turned on in the third duration, so that a third load corresponding to the resistance of the third compensation resistor RC can be applied to the output node of the data power supply voltage AVDD. The third load may be greater than the second load. In the exemplary embodiment shown, the load IAVDD of the data power supply voltage AVDD may have a gradually increasing waveform through the first compensation part to the third compensation part. When the load IAVDD of the data power supply voltage AVDD gradually increases, the degree of decrease of the data power supply voltage AVDD can be reduced, so that the degradation of the display panel can be stably prevented.

[0129] As a result, the data power supply voltage AVDD drops in the vertical blanking period VBLANK ( Fig.10 The data voltage VD may be in the effective period ACTIVE ( Fig.10 The time period A2 in the embodiment has a target level from the first pulse.

[0130] According to the exemplary embodiment shown, the timing compensator 800A applies the load IAVDD to the output node of the data power supply voltage AVDD in the vertical blanking period VBLANK, so that the waveform of the data power supply voltage AVDD can be controlled not to drop in the effective period ACTIVE. Therefore, the display quality of the display panel 100 can be prevented from being degraded due to the drop of the data power supply voltage AVDD. Therefore, the display quality of the display panel 100 can be improved. In addition, the display panel drive signal can be maintained at a uniform level during the vertical blanking period VBLANK, so that the power consumption of the display device can be reduced.

[0131] Fig.11 is a circuit diagram illustrating a driving controller 200 according to an exemplary embodiment of the present invention. Fig. 12A is a timing diagram showing a display panel driving signal according to first input image data. Fig. 12B is a timing diagram showing a display panel driving signal according to the second input image data.

[0132] In addition to the timing compensator 210, the power supply voltage generating circuit and the display device according to the exemplary embodiment shown are similar to those of the reference Figures 1 to 4B The power supply voltage generating circuit and the display device of the previously described exemplary embodiment are substantially the same. Therefore, the same reference numerals will be used to represent the same as those in Figures 1 to 4B The same or similar parts as those described in the previous exemplary embodiments are described herein, and any repeated explanation regarding the above elements will be omitted.

[0133] Reference Figure 1 , Fig.11 , Fig. 12A and Fig. 12B The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a power supply voltage generator 600.

[0134] The display device further includes a timing compensator 210 that adjusts an output timing of a data voltage VD of the data driver 500 based on the input image data IMG.

[0135] In an exemplary embodiment, for example, the display device may include the timing compensator 210 of the illustrated exemplary embodiment instead of Figure 3 In an alternative exemplary embodiment, the display device may include both the timing compensator 700 of the previous exemplary embodiment and the timing compensator 210 of the illustrated exemplary embodiment.

[0136] In the illustrated exemplary embodiment, the timing compensator 210 may be provided in the driving controller 200 .

[0137] The driving controller 200 includes a timing compensator 210, a data compensator 220, and a control signal generator 230. The driving controller 200 is not physically divided into blocks 210, 220, and 230, but is logically divided into blocks 210, 220, and 230 for convenience of explanation.

[0138] The load of the data driver 500 at the starting point of the active period ACTIVE may vary according to the input image data IMG applied to the driving controller 200. When the load of the data driver 500 at the starting point of the active period ACTIVE is relatively large, the drop of the data power supply voltage AVDD may be large. On the contrary, when the load of the data driver 500 at the starting point of the active period ACTIVE is relatively small, the drop of the data power supply voltage AVDD may be small.

[0139] In an exemplary embodiment, for example, when the input image data IMG represents a monochrome image, the data driver 500 may output the data voltage VD maintained at the same level, so that the load of the data driver 500 may be small. When the input image data IMG represents a horizontal stripe image, the data voltage VD may swing between a high level and a low level, so that the load of the data driver 500 may be large. The load of the data driver 500 according to the input image data IMG may vary according to the panel structure of the display panel 100 and the buffer structure of the data driver 500.

[0140] The timing compensator 210 analyzes the input image data IMG and outputs a timing signal TIM indicating a driving timing of the data driver 500 to the data compensator 220 and the control signal generator 230 .

[0141] When the data power supply voltage AVDD drops slightly at the start point of the active period ACTIVE, the timing compensator 210 may advance the output timing of the data voltage VD of the data driver 500 by a small amount. When the data power supply voltage AVDD drops significantly at the start point of the active period ACTIVE, the timing compensator 210 may advance the output timing of the data voltage VD of the data driver 500 by a large amount.

[0142] Fig. 12A The first input image data in may cause a small drop in the data power supply voltage AVDD at the starting point of the active period ACTIVE. Fig. 12AIn the active period ACTIVE, the data power voltage AVDD drops very little at the start point, so that the data voltage VD can have the target level from the first pulse in the active period ACTIVE. Therefore, the timing compensator 210 does not advance the output timing of the data voltage VD of the data driver 500.

[0143] Fig. 12B The second input image data in may cause a large drop in the data power supply voltage AVDD at the starting point of the active period ACTIVE. Fig. 12B In the embodiment, the timing compensator 210 can adjust the output timing of the data voltage VD so that the starting point of the output data voltage VD is in the vertical blanking period VBLANK before the effective period ACTIVE. As a result, the data power supply voltage AVDD drops in the vertical blanking period VBLANK ( Fig. 12B The data voltage VD may be in the effective period ACTIVE ( Fig. 12B The time period A2 in the embodiment has a target level from the first pulse.

[0144] The data compensator 220 receives input image data IMG from an external device. The data compensator 220 compensates the input image data IMG to generate a data signal DATA. The data compensator 220 outputs the data signal DATA to the data driver 500. The data compensator 220 may output the data signal DATA to the data driver 500 in response to the timing signal TIM.

[0145] In an exemplary embodiment, for example, the data compensator 220 may include a color characteristic compensating part (not shown) and a dynamic capacitance compensating part (not shown).

[0146] The color characteristic compensation part receives input image data IMG and performs adaptive color correction ("ACC"). The color characteristic compensation part may compensate the input image data IMG using a gamma curve. The dynamic capacitance compensation part performs dynamic capacitance compensation ("DCC") using previous frame data and current frame data to compensate current frame data.

[0147] The control signal generator 230 receives an input control signal CONT from an external device. The control signal generator 230 receives a timing signal TIM from the timing compensator 210 .

[0148] The control signal generator 230 generates a first control signal CONT1 based on the input control signal CONT and the timing signal TIM. The control signal generator 230 outputs the first control signal CONT1 to the gate driver 300. The control signal generator 230 generates a second control signal CONT2 based on the input control signal CONT and the timing signal TIM. The control signal generator 230 outputs the second control signal CONT2 to the data driver 500. The control signal generator 230 generates a third control signal CONT3 based on the input control signal CONT and the timing signal TIM. The control signal generator 230 outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0149] According to the exemplary embodiment shown, the timing compensator 210 adjusts the output timing of the data driver 500 according to the input image data IMG, so that the waveform of the data power supply voltage AVDD can be controlled not to drop in the effective period ACTIVE. Therefore, the display quality of the display panel 100 can be prevented from being degraded due to the drop of the data power supply voltage AVDD. Therefore, the display quality of the display panel 100 can be improved. In addition, during the vertical blanking period VBLANK, the display panel drive signal can be maintained at a uniform level, so that the power consumption of the display device can be reduced.

[0150] According to the present invention as described above, the display quality of the display panel can be improved, and the power consumption of the display device can be reduced.

[0151] The foregoing is an explanation of the present invention and should not be construed as limiting the present invention. Although some exemplary embodiments of the present invention have been described, it will be readily understood by those skilled in the art that many modifications can be made in the exemplary embodiments without substantially departing from the novel teachings and beneficial effects of the present invention. Accordingly, all of these modifications are intended to be included within the scope of the present invention as defined in the claims. In the claims, the clauses of device plus function are intended to cover structures described herein as performing the functions listed, and not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is an explanation of the present invention and should not be construed as being limited to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims. The present invention is defined by the appended claims and the equivalents of the claims included in the claims.

Claims

1. Display equipment, including: a display panel that displays an image based on input image data; a data driver, the data driver outputting a data voltage to the display panel; a power supply voltage generator, the power supply voltage generator outputting a data power supply voltage to the data driver; A driving controller, wherein the driving controller controls a driving timing of the data driver; as well as a timing compensator that changes an output timing of the data voltage of the data driver when the feedback data power voltage is smaller than the reference data power voltage at a starting point of an effective period, The timing compensator adjusts the output timing of the data voltage so that a starting point of outputting the data voltage is in a vertical blanking period before the effective period, and the vertical blanking period and the effective period are in the same frame.

2. The display device according to claim 1, wherein: The reference data power supply voltage is the data power supply voltage that is fed back after a first time from a rising edge of a vertical start signal.

3. The display device according to claim 1, wherein: The timing compensator comprises: an analog-to-digital converter, the analog-to-digital converter converting the feedback data power supply voltage and the reference data power supply voltage; and A data power supply voltage comparator compares the converted feedback data power supply voltage with the converted reference data power supply voltage.

4. The display device according to claim 3, wherein: The analog-to-digital converter and the data power supply voltage comparator are disposed in the power supply voltage generator.

5. The display device according to claim 3, wherein: The analog-to-digital converter is arranged in the supply voltage generator, and Wherein, the data power supply voltage comparator is arranged in the driving controller.

6. The display device according to claim 1, wherein: The power supply voltage generator comprises: a capacitor including a first electrode connected to the input node and a second electrode connected to ground; an inductor including a first end connected to the input node and a second end connected to a first node; a diode including an anode electrode connected to the first node and a cathode electrode connected to an output node; a switch comprising a control electrode connected to a switch controller, an input electrode connected to the first node, and an output electrode connected to the ground; a resistor including a first end connected to the output node and a second end connected to a feedback node; an error amplifier including a first input electrode connected to the feedback node, a second input electrode to which a reference voltage is applied, and an output electrode; a comparator including a first input electrode connected to the output electrode of the error amplifier, a second input electrode to which a comparison voltage is applied, and an output electrode connected to the switch controller; and the switch controller, the switch controller being connected to the comparator and controlling the switch, Wherein, the timing compensator is connected to the feedback node. 7 . The display device of claim 1 , further comprising a second timing compensator that applies a load to an output node of the data power supply voltage in a vertical blanking period prior to the active period.

8. The display device according to claim 7, wherein: The second timing compensator includes a compensation resistor and a compensation switch connected in series.

9. The display device according to claim 7, wherein: The second timing compensator comprises: a first compensation part including a first compensation resistor and a first compensation switch connected in series; and a second compensation part, the second compensation part including a second compensation resistor and a second compensation switch connected in series, the second compensation part being connected in parallel to the first compensation part.

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