Method for forming a perforated structure, computer readable medium and computer system

Abstract

A structure and method for a through-hole structure of a three-dimensional integrated circuit (IC) package. The through-hole structure includes: a middle portion extending through a planar structure; and a first end and a second end, each connected to the middle portion and located on a different side of the planar structure. One or more of the first end and the second end include a plurality of through-holes and one or more of a metalloid layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for forming an extended TSV structure, a non-transitory computer-readable medium, and a computer system. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. In three-dimensional (3D) integrated circuit packaging, through-silicon vias (TSVs) can be used to connect integrated circuits / components on opposite sides of a silicon wafer substrate / die (or any suitable planar structure). A through-silicon via is an electrical connection that passes through / extends through a silicon wafer substrate / die and connects devices / structures (e.g., metal interconnects) on opposite sides of the silicon wafer substrate / die.

[0003] The 3D integrated circuit package may be modeled using an integrated circuit design tool (e.g., an Electronic Design Automation (EDA) tool). The design rules applied by the integrated circuit design tool may be used to determine whether a connection pattern between a through silicon via and another device / structure (e.g., a metal interconnect) is acceptable. For example, a design rule check (DRC) and / or a layout versus schematic (LVS) check may be performed on a circuit layout including the through silicon via to check whether any violation of the design rule has been detected. When no violation is detected, the circuit layout may be converted into a corresponding graphic database system (GDS) file for tape-out. Summary of the invention

[0004] According to an embodiment of the present invention, a through-hole structure includes a middle portion and a first end and a second end. The middle portion extends through a planar structure. The first end and the second end are each connected to the middle portion and are located on different sides of the planar structure, wherein one or more of the first end and the second end include a plurality of through-holes and one or more of the metalloid layers.

[0005] According to an embodiment of the present invention, a method for forming an extended through silicon via (TSV) structure includes: connecting a quasi-metal layer and one or more of a plurality of through holes to one end of the through silicon via to form the extended through silicon via structure; defining wiring properties of the quasi-metal layer and the one or more of the plurality of through holes, wherein the wiring properties of the quasi-metal layer include being incompatible with being connected to an internal connection, and the wiring properties of the plurality of through holes include being connectable to the quasi-metal layer, the through silicon via, and the internal connection; and in response to the connection pattern of the quasi-metal layer and the plurality of through holes being consistent with the corresponding wiring properties, connecting the end of the extended through silicon via structure to the internal connection.

[0006] According to an embodiment of the present invention, a non-transitory computer-readable medium containing a computer-executable program implements a method of forming an extended through silicon via (TSV) structure when the computer-executable program is executed by a processor, the method comprising: connecting a metalloid layer and one or more of a plurality of through-holes to one end of a through silicon via to form the extended through silicon via structure; defining wiring properties of the metalloid layer and the one or more of the plurality of through-holes, wherein the wiring properties of the metalloid layer include being inaccessible to an internal connection, and the wiring properties of the plurality of through-holes include being connectable to the metalloid layer, the through silicon via, and the internal connection; and in response to the connection pattern of the metalloid layer and the plurality of through-holes being consistent with the corresponding wiring properties, connecting the end of the extended through silicon via structure to the internal connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of illustration and discussion.

[0008] Figure 1 Illustration of the connection pattern of TSVs.

[0009] Figures 2A to 2D Each illustrates a connection pattern of an exemplary first extended TSV structure according to some embodiments of the present invention.

[0010] Figures 3A to 3C Each illustrates a connection pattern of an exemplary second extended TSV structure according to some embodiments of the present invention.

[0011] Figure 4A and Figure 4B Each illustrates a connection pattern of an exemplary third extended TSV structure according to some embodiments of the present invention.

[0012] FIG. 5A to FIG. 5CEach illustrates an exemplary method of forming an extended TSV structure in a circuit layout according to some embodiments of the present invention.

[0013] Figure 6 An exemplary computer system for implementing various embodiments of the present invention is described.

[0014] Figure 7 A process of forming a circuit layout of a 3D integrated circuit package based on a Graphic Database System (GDS) file according to some embodiments of the present invention is described.

[0015] [Explanation of Symbols]

[0016] 100, 300, 310, 320, 400, 410: connection pattern

[0017] 101, 201-1, 201-2, 201-3, 301-1, 301-2, 301-3, 401-1, 401-2: Through-silicon vias

[0018] 102-1: First metal interconnect

[0019] 102-2: Second metal interconnect

[0020] 103, 203, 303, 403: Wafer substrate / die

[0021] 200, 210, 220, 230: connection pattern

[0022] 202-1, 202-2, 206-1, 206-2, 302-1, 302-2, 402-1, 402-2: Metal interconnects

[0023] 204A, 204B, 204C, 204D, 204E, 204F, 404A, 404B: metalloid layer

[0024] 205-1A, 205-1B, 205-2A, 205-2B, 205-3A, 205-3B, 205-4A, 205-4B, 205-5A, 205-5B, 205-6A, 205-6B, 205-7A, 205-8A, 305-1A, 3 05-1B, 305-2A, 305-2B, 305-3A, 305-3B, 305-4A, 305-4B, 405-1A, 405-1B, 405-2A, 405-2B, 407-1A, 407-1B, 407-2A, 407-2B: Through hole

[0025] 240-1, 240-2, 240-3, 240-4: First extended TSV structure

[0026] 304A, 408A, 408B, 304B, 304C: Second extended TSV structure

[0027] 406A, 406B: The third extended silicon via structure

[0028] 500, 510, 520, 700: Method

[0029] 600: Computer Systems

[0030] 602: Input / output interface

[0031] 603: Input / output devices

[0032] 604: Processor

[0033] 606: Communications Infrastructure

[0034] 608: Main memory

[0035] 610: Secondary storage

[0036] 612: Hard Drive

[0037] 614: Removable storage drive

[0038] 618, 622: Removable storage unit

[0039] 620: Interface

[0040] 624: Communication interface

[0041] 626: Communication Path

[0042] 628: Remote Device / Network / Entity

[0043] 701, 702, 703, 5010, 5020, 5030, 5110, 5120, 5130, 5210, 5220: Operation DETAILED DESCRIPTION

[0044] The following disclosure provides many different embodiments or examples to implement the different features of the provided subject matter. Specific examples of components and arrangements are described below to make the present invention concise. These are only examples and are not intended to be limiting.

[0045] For ease of description, spatially relative terms, such as "below," "beneath," "beneath," "below," "lower," "above," "upper," etc., may be used to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0046] In some embodiments, the terms "about" and "substantially" may indicate that a value of a given quantity varies within 5% thereof (eg, ±1%, ±2%, ±3%, ±4%, ±5%).

[0047] In 3D integrated circuit packaging, silicon through vias may extend through the wafer substrate / die and may be used to connect metal interconnects on both sides of the wafer substrate / die. EDA tools for designing 3D integrated circuit packaging may include design rules that define connection patterns (e.g., connection patterns of silicon through vias). In the present invention, connection patterns describe connections formed between interconnect structures (e.g., silicon through vias) and other structures / devices. The connection pattern may describe the type of connection formed between the silicon through via and another device / structure. For example, the connection pattern between the silicon through via and the metal interconnect may be referred to as a "via-via" connection pattern. DRC and / or LVS checks may be performed after forming the connection pattern in the circuit layout to scan for design rule violations and / or perform circuit verification. The connection pattern may be compared with a model in the EDA tool (e.g., a model defined by the design rules) to check whether there is a design rule violation, and the connection pattern that violates the design rule may be marked for correction. The scan-check-correct process may be repeated (e.g., using a loop procedure) until all connection patterns pass the DRC and / or LVS check. The circuit layout can then be converted into a GDS file for final tape-out.

[0048] The design rules may allow a connection between a metal interconnect and a via, and both ends of the via may each be connected to a metal interconnect. The design rules may prohibit a via from being connected to (e.g., physically contacting) another via (e.g., providing a warning about such a connection). That is, the EDA tool includes design rules for a "metal-via-metal" connection pattern / model, and does not include a model for a "via-via" connection pattern. For example, both ends of a through-silicon via may be connected to a metal interconnect, respectively, and neither end of the through-silicon via may be connected to other through-vias. Therefore, the connection between the through-silicon via and the via violates the design rules. In the present invention, the term "directly connected to" refers to forming a direct contact without any structure in between.

[0049] Figure 1 A model of a connection pattern 100 defined by design rules is illustrated. The connection pattern 100 includes a through silicon via connected to two metal interconnects at each end. The connection pattern 100 includes a through silicon via 101, a wafer substrate / die 103, a first metal interconnect 102-1, and a second metal interconnect 102-2. The through silicon via 101 extends through the wafer substrate / die 103 and is connected to the first metal interconnect 102-1 and the second metal interconnect 102-2 at each end. The connection pattern 100 defines a "first metal interconnect-through silicon via-second metal interconnect" connection pattern consistent with the "metal-via-metal" model. Therefore, in the circuit layout, the connection pattern in which the through silicon via is connected to the metal interconnect at both ends can pass the DRC and / or LVS check.

[0050] However, in integrated circuit design, in some cases, it is desirable to insert one or more through-holes between the silicon via and the metal interconnection instead of directly connecting the silicon via and the metal interconnection. For example, the silicon via may be formed of a metal material (e.g., copper) having a specific hardness. Direct connection / contact between the silicon via and the metal interconnection may cause extremely high impact force on the metal interconnection, thereby damaging the metal interconnection. A solution to reduce damage to the metal interconnection is to form / insert one or more through-holes (e.g., smaller and / or softer than the silicon via) between the silicon via and the metal interconnection to buffer the impact force. That is, the solution includes inserting one or more through-holes between the silicon via 101 and the first metal interconnection 102-1 and / or between the silicon via 101 and the second metal interconnection 102-2. According to the design rules, such connection patterns are not allowed to be used due to lack of definition, so such connection patterns violate DRC and / or LVS checks.

[0051] The present invention provides a model for connecting silicon vias and through-holes, and provides a method for forming these models using EDA tools to realize 3D integrated circuit packaging. The model may include various extended silicon via structures (or through-hole structures), which allow the silicon vias to be connected to metal interconnects via through-holes. The model can be defined in a library / database of, for example, an EDA tool to expand or supplement current design rules. Therefore, in the design of 3D integrated circuit packaging, through-holes smaller than silicon vias can be formed / inserted between silicon vias and metal interconnects to (for example) reduce the impact force and damage to the metal interconnects caused by silicon vias. The model defined by the present invention can be consistent with current design rules and can allow the formation of "silicon via-through-hole" connection patterns in 3D integrated circuit packaging. By incorporating the disclosed model into the EDA tool, the circuit layout of the 3D integrated circuit package in which the silicon vias are connected to the metal interconnects via through-holes can be checked by DRC and / or LVS. Therefore, the metal interconnects are not susceptible to damage caused by direct contact with the silicon vias.

[0052] In addition, the placement and routing design rules of the connection patterns according to the disclosed model are consistent with the placement and routing design rules and can be flexibly incorporated into EDA tools. Therefore, DRC can be used to check the placement and routing of these connection patterns. In addition, the disclosed model and method can have a small dependence on device size and can be used for 3D integrated circuit packaging of devices of various technology nodes.

[0053] In the present invention, the term "via" or "vias" may refer to a via that is different from or smaller than a TSV; and the term "on..." may refer to the meaning of "above..." or "below...". For example, a via connected to one end of a TSV may indicate a via that is smaller than the TSV; and a pseudo-metal layer located "on" one end of the TSV may refer to a pseudo-metal layer located above the upper end of the TSV or below the lower end of the TSV. For illustrative purposes, an exemplary number of vias is shown to illustrate an embodiment. In various embodiments, the configuration (e.g., number, arrangement, and / or size) of the vias may vary.

[0054] FIG. 2A to FIG. 2D , FIG. 3A to FIG. 3C as well as FIG. 4A to FIG. 4B Each illustrates an exemplary connection pattern of an extended silicon through-hole structure according to some embodiments. Each of the extended silicon through-hole structures may extend through a wafer and / or a die located at a middle portion of the extended silicon through-hole structure. The middle portion may include a silicon through-hole. The two ends of the extended silicon through-hole structure may be connected to metal interconnects, respectively. The extended silicon through-hole structure and / or the connection pattern may be defined as a model that is consistent with the design rules and can be stored in an EDA tool to implement 3D integrated circuit packaging. In subsequent DRC and / or LVS checks, the connection pattern in the circuit layout (e.g., between the silicon through-hole and the metal interconnect) may be scanned and compared with these models stored in the EDA tool to determine whether the connection pattern is consistent with the design rules and / or the designed schematic diagram. The placement and routing of components in the circuit layout with the disclosed model is consistent with the placement and routing design rules.

[0055] Figures 2A to 2DEach illustrates an exemplary connection pattern of a first extended silicon via structure according to some embodiments. The first extended silicon via structure may include a silicon via and a quasi-metal layer (e.g., an auxiliary metal layer or a dummy metal layer) directly connected together. For simplicity, the end of the first extended silicon via structure may be referred to as a "connection end". The first extended silicon via structure may be connected to a metal inner connection via one or more through holes on the connection end so that the silicon via may be connected to the one or more through holes via the quasi-metal layer. The silicon via may be directly connected to one side of the quasi-metal layer, and the through hole may be directly connected to the other side of the quasi-metal layer. In other words, the quasi-metal layer may make the connection pattern 200 (for example, between the silicon via and the metal inner connection) to the connection pattern 240 satisfy the "metal-through hole-metal" model and pass the DRC and / or LVS inspection. In some embodiments, during the placement and routing process, the quasi-metal layer may be placed (for example, by an EDA tool) as a metal layer when the quasi-metal layer is connected to the through hole. In some embodiments, during the routing process, the metalloid layer can be configured to be non-connectable to other metal devices / structures (e.g., not electrically connected to / not conductively connected to other metal devices / structures). By using the disclosed TSV model in the circuit layout, the TSV can be connected to the metal interconnects via one or more through-holes.

[0056] Figure 2A The connection pattern 200 may include a first extended TSV structure 240-1 according to some embodiments. The first extended TSV structure 240-1 (indicated by a dotted line) may include a TSV 201-1 and a metalloid layer 204A, wherein the metalloid layer 204A is located on an upper end of the TSV 201-1. Figure 2AAs shown in , the first extended TSV structure 240-1 may extend through the wafer substrate / die 203 (or any suitable planar structure) and may be connected to the metal interconnect 202-1 and the metal interconnect 202-2, respectively. The metal interconnect 202-1 may be located above the wafer substrate / die 203, and the metal interconnect 202-2 may be located below the wafer substrate / die 203. The lower end of the first extended TSV structure 240-1 (e.g., at the bottom of the first extended TSV structure 240-1 along the y-axis) may be directly connected to the metal interconnect 202-2. The upper end of the first extended TSV structure 240-1 (e.g., at the top of the TSV along the y-axis) may be connected to the metal interconnect 202-1 via one or more through-holes. The through-holes may be connected to the first extended TSV structure 240-1 via the metalloid layer 204A. For illustration purposes, two vias (via 205-1A and via 205-1B) are shown. In some embodiments, TSV 201-1 may be modeled as a “via”. In some embodiments, each of via 205-1A and via 205-1B may be modeled as a “via”. In some embodiments, each of metal interconnect 202-1 and metal interconnect 202-2 may be modeled as “metal” and may be directly connected to TSV 201-1 and / or one or more vias (e.g., via 205-1A and via 205-1B).

[0057] The connection pattern 200 may satisfy the design rules. For example, the metalloid layer 204A may be modeled (e.g., defined) as "metal" and may be directly connected to the TSV 201-1 and the vias (e.g., via 205-1A and via 205-1B). In some embodiments, the metalloid layer 204A may be modeled as the same type (e.g., "metal") as the metal interconnect 202-1 and / or the metal interconnect 202-2. In some embodiments, the metalloid layer 204A may be modeled as a different type than the TSV 201-1. For example, the metalloid layer 204A may be defined as "metal" and the TSV 201-1 may be defined as a "via". In some embodiments, the metalloid layer 204A may be modeled as a different type than the via 205-1A and / or the via 205-1B. For example, the metalloid layer 204A may be defined as "metal", and the via 205-1A and / or the via 205-1B may be defined as "via". In the connection pattern 200, the connection of the metal interconnect 202-1, the via 205-1A and the via 205-1B, and the metalloid layer 204A may satisfy the "metal-via-metal" model, and the connection of the metalloid layer 204A, the TSV 201-1, and the metal interconnect 202-2 may satisfy the "metal-via-metal" model. Therefore, the connection pattern 200 may satisfy the design rules and allow the TSV 201-1 to be connected to the metal interconnect 202-1 via the via.

[0058] Figure 2B A connection pattern 210 is illustrated that may include another first extended TSV structure 240-2 according to some embodiments. The first extended TSV structure 240-2 (indicated by a dotted line) may include a TSV 201-2 and a metalloid layer 204B, the metalloid layer 204B being located above the lower end of the TSV 201-2. Unlike the connection pattern 200, in the connection pattern 210, the first extended TSV structure 240-2 may be connected to the metal interconnect 202-2 at the lower end of the first extended TSV structure 240-2 via one or more through-holes (e.g., through-hole 205-2A and through-hole 205-2B). In the first extended TSV structure 240-2, the metalloid layer 204B may be inserted above the lower end (e.g., along the y-axis) of the TSV 201-2. The lower end of the first extended TSV structure 240-2 may be connected to the through-hole via the metalloid layer 204B. An upper end of the first extended TSV structure 204 - 2 may be directly connected to the metal interconnect 202 - 1 .

[0059] The connection pattern 210 having the first extended TSV structure 240-2 may satisfy the design rules. For example, the metalloid layer 204B may be modeled as "metal" and may be directly connected to the TSV 201-2 and the vias (e.g., vias 205-2A and 205-2B). For example, in the connection pattern 210, the metal interconnect 202-1, the TSV 201-2, and the metalloid layer 204B may satisfy the "metal-via-metal" model, and the metalloid layer 204B, the vias 205-2A and 205-2B, and the metal interconnect 202-2 may satisfy the "metal-via-metal" model. Therefore, the connection pattern 210 may satisfy the design rules and allow the TSV 201-2 to be connected to the metal interconnect 202-2 via the vias.

[0060] Figure 2CThe connection pattern 220 according to some embodiments may include another first extended TSV structure 240-3. The first extended TSV 240-3 (indicated by a dotted line) may include the TSV 201-3 and the metalloid layer 204C and the metalloid layer 204D, which are located on both the upper end and the lower end of the TSV 201-3. Different from the connection pattern 200 and the connection pattern 210, in the connection pattern 220, the first extended TSV structure 240-3 may be connected to both the metal interconnect 202-1 and the metal interconnect 202-2 at the upper end and the lower end of the first extended TSV structure 240-3 via one or more vias (e.g., via 205-3A, via 205-3B, via 205-4A, and via 205-4B). The first extended TSV structure 240-3 may include: a metalloid layer 204C inserted on the upper end of the TSV 201-3; and a metalloid layer 204D inserted on the lower end of the TSV 201-3. The first extended TSV structure 240-3 may be connected to the vias 205-3A and 205-3B via the metalloid layer 204C and connected to the vias 205-4A and 205-4B via the metalloid layer 204D. The vias 205-3A and 205-3B may further be directly connected to the metal interconnect 202-1, and the vias 205-4A and 205-4B may further be directly connected to the metal interconnect 202-2.

[0061] The connection pattern 220 having the first extended TSV structure 240-3 may satisfy the design rules. For example, the metalloid layer 204C and the metalloid layer 204D may each be directly connected to the TSV 201-3 and the via (e.g., connected to the via 205-3A and the via 205-3B, the via 205-4A and the via 205-4B, respectively). In the connection pattern 220, the metal interconnect 202-1, the via 205-3A and the via 205-3B, and the metalloid layer 204C may satisfy the "metal-via-metal" model. In addition, the metalloid layer 204D, the via 205-4A and the via 205-4B, and the metal interconnect 202-2 may satisfy the "metal-via-metal" model. Therefore, the connection pattern 220 can satisfy the design rule and allow the TSV 201 - 3 to be connected to the metal interconnect 202 - 1 and the metal interconnect 202 - 2 through the through hole.

[0062] The metalloid layer may be different from the metal interconnect or metal layer. The metalloid layer may be defined (e.g., by an EDA tool) as being allowed to connect to TSVs and vias on each side of the metalloid layer during the routing process (e.g., according to design rules), but not to connect to other metal layers or metal interconnects. Figure 2DAccording to some embodiments, the connection pattern 230 may include a first extended TSV structure 240-4 and other metal layers / metal interconnects during placement and routing. Figure 2A to Figure 2C The first extended silicon via structure 240-4 may be the same as or similar to any of the extended silicon via structures 240-1 to 240-3 described in FIG. Figure 2C . The metalloid layer 204E and the metalloid layer 204F may be the same as the metalloid layer 204C and the metalloid layer 204D, respectively; and the vias 205-5A, 205-5B, 205-6A, and 205-6B may be the same as the vias 205-3A, 205-3B, 205-4A, and 205-4B, respectively. The connection pattern 230 may also include one or more other metal layers / metal interconnects (e.g., metal interconnects 206-1 and metal interconnects 206-2) at the same level (e.g., having the same height along the y-axis) as the metalloid layer 204E. In an example, metal interconnect 206-1 may be at the same level as metalloid layer 204E, and metal interconnect 206-2 may be at the same level as metalloid layer 204F. For example, each of metal interconnect 206-1 and metal interconnect 206-2 may have substantially the same thickness as each of metalloid layer 204E and metalloid layer 204F, respectively. Metal interconnect 206-1 may be connected to metal interconnect 202-1 via via 205-7A at the same level as via 205-5A and via 205-5B, and metal interconnect 206-2 may be connected to metal interconnect 202-2 via via 205-8A at the same level as via 205-6A and via 205-6B.

[0063] like Figure 2D As shown in , a metalloid layer (e.g., metalloid layer 204E or metalloid layer 204F) may be disconnected from a parallel metal interconnect / metal layer (e.g., a metal interconnect / metal layer at the same height as the metalloid layer along the y-axis). In some embodiments, it may be defined in the EDA tool that a metalloid layer (e.g., metalloid layer 204E or metalloid layer 204F) is not allowed to connect to any other metal interconnect / metal layer. For illustration purposes, two other metal interconnects / metal layers (e.g., metal interconnect 206-1 and metal interconnect 206-2) are shown at the same level as the metalloid layer. However, the number of metal interconnects / metal layers at the same level as the metalloid layer and the locations of these metal interconnects / metal layers may vary according to different design requirements and applications.

[0064] exist Figures 2A to 2D In the design shown (connection pattern 200 to connection pattern / 230), the configuration (e.g., number, arrangement, and size) of the through holes between the metal interconnect (e.g., metal interconnect 202-1 or metal interconnect 202-2) and the first extended through silicon via structure (e.g., first extended through silicon via structure 240-1, first extended through silicon via structure 240-2, first extended through silicon via structure 240-3, or first extended through silicon via structure 240-4) can be flexibly determined / defined in the library / database and / or in the circuit layout. For example, the through holes can be arranged in a one-dimensional pattern or array between the metal interconnect and the metalloid layer. One through hole can be separated from another through hole by a desired interval. In some embodiments, the number, arrangement, and / or size of these through holes in the library / database and / or circuit layout can be customized to meet different design requirements.

[0065] By using Figures 2A to 2D The design / first extended silicon via structure provided, the silicon via can be connected to the metal interconnection via a through hole, and the configuration (e.g., arrangement, number and / or size) of the through hole located between one end of the silicon via and the connected metal interconnection can be flexibly determined (e.g., adjustable) in the library / database and / or circuit layout to meet different design requirements. In the present invention, the term "adjustable" refers to the configuration of the through hole of the first extended silicon via that can be modified after the first extended silicon via is defined. For example, after the first extended silicon via is defined to include a 4×4 through hole array, the EDA tool may allow the arrangement of the through hole to be modified (e.g., automatically or manually) to a 3×3 array. Therefore, in various 3D integrated circuit packages, the connection between the silicon via and the metal interconnection can be improved / optimized by inserting a suitable number of through holes. Therefore, the metal interconnection may be less susceptible to impact force when in contact with the silicon via.

[0066] FIG. 3A to FIG. 3CEach illustrates an exemplary connection pattern of a second extended silicon via structure according to some embodiments. The second extended silicon via structure may be directly connected to a metal inner connection on each side. The second extended silicon via structure may include a silicon via and one or more through holes, and the silicon via is directly connected to the one or more through holes at at least one end of the silicon via. The second extended silicon via structure may also be referred to as a "through hole extended silicon via structure" or a "large silicon via". The second extended silicon via structure may be modeled as a single circuit structure using a resistance-inductance-capacitance (RLC) model. In some embodiments, the single circuit structure has a common electrical property (e.g., resistance, inductance and / or capacitance), rather than two connection structures each having its own electrical properties. For example, a single circuit structure may be modeled as an RLC subcircuit having its own electrical properties (e.g., resistance, inductance and / or capacitance). Modeling may determine the electrical properties of the second extended silicon via structure based on the structure / components of the second extended silicon via structure. Thus, the second extended TSV structure with a different through-hole arrangement can be stored (e.g., stored in a library / database of an EDA tool) and regarded (e.g., by the EDA tool) as a different second extended TSV structure. In some embodiments, after defining the second extended TSV structure, the arrangement (e.g., number, arrangement, and / or size) of the through-holes in the second extended TSV structure can be fixed / unchanged. In addition, unlike Figures 2A to 2D The first extended TSV structure described in Figures 3A to 3C The second extended TSV structure described in FIG. 1 does not require a metalloid layer. Instead, the second extended TSV structure (eg, Figures 3A to 3C Each of the second extended TSV structures (described in the drawings) can be placed and routed into a single circuit structure (e.g., a via). In some embodiments, the second extended TSV structure can be defined as having the same or similar electrical properties and / or placement and routing properties as the via, such as being connectable / connected to (e.g., physically contacting) a metal interconnect at both the upper and lower ends and conducting current between the connected structures. Figures 3A to 3C The metal interconnects 302-1 and 302-2, the through silicon vias 301 and the wafer substrate / die 303 can be connected to Figures 2A to 2D The metal interconnects 202-1 and 202-2, the TSV 201, and the wafer substrate / die 203 are the same or similar.

[0067] Figure 3AA connection pattern 300 that may include a second extended TSV structure according to some embodiments is illustrated. The second extended TSV structure 304A (indicated by a dotted line) may include a TSV 301-1 and one or more through-holes (e.g., through-hole 305-1A and through-hole 305-1B) that are directly connected to the upper end of the TSV 301-1. In some embodiments, the second extended TSV structure 304A may be defined as a "through-hole". In some embodiments, the TSV 301-1 and the one or more through-holes (e.g., through-hole 305-1A and through-hole 305-1B) connected to the TSV 301-1 may be modeled as a single "through-hole". The second extended TSV structure 304A may be directly connected to metal interconnects at both ends of the second extended TSV structure 304A. In some embodiments, the through holes (e.g., through hole 305-1A and through hole 305-1B) of the second extended TSV structure 304A may be directly connected to the upper ends (e.g., along the y-axis) of the metal interconnect 302-1 and the TSV 301-1, and the lower end (e.g., along the y-axis) of the second extended TSV structure 304A may be directly connected to the metal interconnect 302-2. The metal interconnect 302-1 (e.g., may be defined as "metal"), the second extended TSV structure 304A (e.g., may be defined as "via"), and the metal interconnect 302-2 (e.g., may be defined as "metal") may satisfy the "metal-via-metal" model accepted by the design rules.

[0068] Figure 3B A connection pattern 310 that may include another second extended TSV structure according to some embodiments is illustrated. The second extended TSV structure 304B (indicated by a dotted line) may include a TSV 301-2 and one or more through-holes (e.g., through-hole 305-2A and through-hole 305-2B), which are directly connected to the lower end of the TSV 301-2. In some embodiments, the second extended TSV structure 304B may be defined as a "through-hole". In some embodiments, the TSV 301-2 and the one or more through-holes (e.g., through-hole 305-2A and through-hole 305-2B) connecting the TSV 301-2 may be modeled as a single "through-hole". In some embodiments, the through holes (e.g., through hole 305-2A and through hole 305-2B) of the second extended TSV structure 304B may be directly connected to the lower ends (e.g., along the y-axis) of the metal interconnect 302-2 and the TSV 301-2, and the upper end of the second extended TSV structure 304B may be directly connected to the metal interconnect 302-1. The metal interconnect 302-1 (e.g., may be defined as "metal"), the second extended TSV structure 304B (e.g., may be defined as "via"), and the metal interconnect 302-2 (e.g., may be defined as "metal") may satisfy the "metal-via-metal" model accepted by the design rules.

[0069] Figure 3C A connection pattern 320 that may include another second extended TSV structure according to some embodiments is illustrated. A second extended TSV structure 304C (indicated by a dotted line) may include a TSV 301-3 and one or more through-holes (e.g., through-hole 305-3A, through-hole 305-3B, through-hole 305-4A, and through-hole 305-4B), which are directly connected at the upper and lower ends of the TSV 301-3. In some embodiments, the second extended TSV structure 304C may be defined as a "through-hole". In some embodiments, the TSV 301-3 and the one or more through-holes (e.g., through-hole 305-3A, through-hole 305-3B, through-hole 305-4A, and through-hole 305-4B) connected to the TSV 301-3 may be modeled as a single "through-hole". In some embodiments, the vias (e.g., vias 305-3A and 305-3B) of the second extended TSV structure 304C may be directly connected to the metal interconnect 302-1 and the upper end of the TSV 301-3, and the vias (e.g., vias 305-4A and 305-4B) may be directly connected to the lower end of the TSV 301-3 and the metal interconnect 302-2. The metal interconnect 302-1 (e.g., may be defined as “metal”), the second extended TSV structure 304C (e.g., may be defined as “via”), and the metal interconnect 302-2 (e.g., may be defined as “metal”) may satisfy the “metal-via-metal” model accepted by the design rules.

[0070] Different from Figures 2A to 2D The first extended TSV structure / design described in Figures 3A to 3CThe second extended silicon via structure / design described in the embodiment may have a static / fixed through-hole configuration: that is, when the second extended silicon via structure 304A to the second extended silicon via structure 304C are defined, the configuration of the through-hole connected at one end of the silicon via may be static / fixed. In the present invention, the term "static" refers to that after the second extended silicon via is defined, the through-hole configuration of the second extended silicon via cannot be modified. For example, after the second extended silicon via is defined to include a 4×4 through-hole array, the EDA tool does not allow the through-hole arrangement to be modified. To generate another extended silicon via with another arrangement, in addition to the second extended silicon via with a 4×4 arrangement, another second extended silicon via with a desired through-hole arrangement (e.g., a 3×3 arrangement) may also be defined. Since each extended TSV structure can be modeled using a corresponding (e.g., specific) resistance-inductance-capacitance (RLC) model, a second extended TSV structure having a different through-hole configuration may correspond to a different RLC model (e.g., having a different resistance, capacitance, and / or inductance). In some embodiments, different RLC models may be used to define second extended TSV structures each having a different through-hole configuration, and the second extended TSV structures may be added to a library / database (e.g., of an EDA tool). These second extended TSV structures may be selected to connect structures / devices (e.g., metal interconnects) located at both sides of the wafer / die based on the electrical properties of the wafer / die and design requirements. In an example, the library / database may include a plurality of different second extended TSV structures, each having a different through-hole arrangement (e.g., in a 2×2 array and in a 4×4 array) and corresponding to different electrical properties. The second extended TSV structure may be selected based on a design circuit layout and / or structure, where through-holes having different configurations are desired.

[0071] Figure 4A and Figure 4B Each of the exemplary connection patterns of the third extended TSV structure according to some embodiments is described. The third extended TSV structure may be composed of Figures 2A to 2D The first extended silicon via structure described in Figures 3A to 3C It is formed by combining the second extended silicon via structure described in . Figure 4A and Figure 4B The metal interconnects 402-1 and 402-2, the TSV 401, and the wafer substrate / die 403 may be respectively connected to Figures 2A to 2D / Figures 3A to 3C The metal interconnects 202-1 / 302-1 and 202-2 / 302-2, TSVs 201 / 301, and wafer substrate / die 203 / 303 are the same or similar.

[0072] exist Figure 4A In the connection pattern 400 described in , the third extended TSV structure 406A may include: a TSV 401-1; a quasi-metal layer 404A, directly connected to the upper end of the TSV 401-1 (e.g., along the y-axis); and one or more through-holes (e.g., through-hole 405-2A and through-hole 405-2B), directly connected to the lower end of the TSV 401-1 (along the y-axis). The third extended TSV structure 406A may also be connected to one or more through-holes (e.g., 405-1A and 405-1B) via the quasi-metal layer 404A. The third extended TSV structure 406A may be connected to the metal interconnect 402-1 via the through-holes (e.g., through-hole 405-1A and through-hole 405-1B), and directly connected to the metal interconnect 402-2. As Figure 4A As shown in , the third extended TSV structure 406A can also be regarded as a second extended TSV structure 408A (e.g., formed by TSV 401-1 and vias 405-2A and 405-2B) and a metalloid layer 404A located on the upper end of the second extended TSV structure 408A. In some embodiments, the second extended TSV structure 408A can be defined as a "via". In some embodiments, the TSV 401-1 and the one or more vias (e.g., 405-2A and 405-2B) connected to the TSV 401-1 can be modeled as a single "via". The metal interconnect 402-1 (e.g., can be defined as "metal"), the via 405-1A and the via 405-1B (e.g., each can be defined as a "via"), and the metalloid layer 404A (e.g., can be defined as "metal") can satisfy the "metal-via-metal" model. In addition, the metalloid layer 404A (eg, defined as “metal”), the second extended TSV structure 408A (eg, defined as “via”), and the metal interconnect 402 - 2 (eg, defined as “metal”) may satisfy the “metal-via-metal” model.

[0073] exist Figure 4B In the connection pattern 410 described in , the third extended TSV structure 406B may include: a TSV 401-2; a quasi-metal layer 404B, directly connected to the lower end of the TSV 401-2; and one or more through-holes (e.g., through-hole 407-1A and through-hole 407-1B), directly connected to the upper end of the TSV 401-2. The third extended TSV structure 406B may also be connected to one or more through-holes (e.g., through-hole 407-2A and through-hole 407-2B) via the quasi-metal layer 404B. The third extended TSV structure 406B may be directly connected to the metal interconnect 402-1, and connected to the metal interconnect 402-2 via through-holes (e.g., through-hole 407-2A and through-hole 407-2B). Figure 4BAs shown in , the third extended TSV structure 406B can be regarded as a second extended TSV structure 408B (e.g., formed by TSV 401-2 and vias 407-1A and 407-1B) and a metalloid layer 404B located on the lower end of the second extended TSV structure 408B. In some embodiments, the second extended TSV structure 408B can be defined as a "via". In some embodiments, the TSV 401-2 and the one or more vias connected to the TSV 401-2 (e.g., via 407-1A and via 407-1B) can be modeled as a single "via". The metal interconnect 402-2 (e.g., can be defined as "metal"), the via 407-2A and the via 407-2B (e.g., each can be defined as a "via"), and the metalloid layer 404B (e.g., can be defined as "metal") can satisfy the "metal-via-metal" model. In addition, the metalloid layer 404B (eg, defined as “metal”), the second extended TSV structure 408B (eg, defined as “via”), and the metal interconnect 402 - 1 (eg, defined as “metal”) may satisfy the “metal-via-metal” model.

[0074] In some embodiments, Figures 2A to 2D , Figures 3A to 3C as well as Figure 4A and Figure 4B The connection pattern and / or extended TSV structure described in the embodiment is defined in a library / database of, for example, an EDA tool to supplement the connection pattern of the TSV when a through-hole connection is desired between the TSV and the metal interconnect in a 3D integrated circuit package design (e.g., Figure 1 100).

[0075] In the library / database and / or circuit layout, after defining the second extended TSV structure and the third extended TSV structure, the via configurations in the second extended TSV structure and the third extended TSV structure can be fixed / unchanged, and the via configurations between the metal interconnect and the first extended TSV structure can be flexibly determined / customized to meet various design requirements. Figures 2A to 2D as well as Figures 3A to 3C The details of the through-hole configuration are described in.

[0076] In some embodiments, an extended TSV structure (e.g., a first extended TSV structure / a second extended TSV structure / a third extended TSV structure) may appear in a library / database as a single circuit structure (e.g., a symbol) without showing a specific configuration of vias, TSVs, and / or metalloid layers. For example, one extended TSV structure may be distinguished from other extended TSV structures in terms of their electrical properties (e.g., resistance, inductance, and / or capacitance). In 3D integrated circuit package design, an extended TSV structure may be selected based on its electrical properties and / or design requirements.

[0077] FIG. 5A to FIG. 5C A method of forming an extended TSV structure according to some embodiments is described. In some embodiments, when a circuit layout does not violate design rules, the circuit layout can be converted into a GDS file for tape-out. Figure 5A A method 500 for forming a first extended TSV structure according to some embodiments is described. In some embodiments, the operations / steps of method 500 may be performed in a different order. Variations of method 500 are within the scope of the present invention. Figures 2A to 2D Additional details of the first extended TSV structure can be found in the description of FIG.

[0078] At operation 5010, a quasi-metal layer is defined in an automatic place and route (APR) database. The properties of the quasi-metal layer may be defined to include, for example, material properties, dimensions, and electrical properties. In some embodiments, a quasi-metal layer may be defined as a layer placed at one end of a through-silicon via and connected to one or more through-holes. In some embodiments, a quasi-metal layer may be defined as a "non-wiring layer" and is not connected to other metal layers (e.g., or cannot be connected to metal interconnects) during the routing process. In some embodiments, the properties of the through-hole may be defined as being suitable for direct connection (e.g., connectable) to a quasi-metal layer and one or more metal interconnects. For example, a through-hole may be defined as being connectable to three layers during the routing process. In some embodiments, the one or more metal interconnects may include metal interconnects directly connected to the through-hole on both sides of the through-hole, for example, metal interconnects at adjacent horizontal heights.

[0079] At operation 5020, a metalloid layer is placed on one end of a TSV in the circuit layout to form a first extended TSV structure, and a via is placed between the metalloid layer and the metal interconnect in the circuit layout. In some embodiments, operation 5020 may be based on the metalloid layer being defined as a layer connected to the TSV and the via. The metalloid layer may be placed automatically or manually. In some embodiments, the circuit layout may be scanned to determine whether the TSV is suitable for direct connection to the metalloid layer. For example, an EDA tool may scan and select a TSV that is directly connected to one or more metal interconnects.

[0080] The EDA tool can check the connection pattern that may include a quasi-metal layer, silicon vias and / or a through hole. If the connection pattern with the quasi-metal layer, silicon vias and / or a through hole is consistent with the wiring properties of the quasi-metal layer and the through hole, the quasi-metal layer can be placed on one end of the selected silicon via, for example, between the metal inner connection and the selected silicon via. In some embodiments, the through hole can be placed to connect the quasi-metal layer and the metal inner connection. In some embodiments, the number of through holes placed between the quasi-metal layer and the metal inner connection can be flexibly determined based on the design requirements. In some embodiments, another through hole is placed to directly connect the metal inner connection with the metal inner connection at a lower level.

[0081] At operation 5030, the circuit layout is scanned for DRC, and connection patterns that violate the design rules are marked for correction. The EDA tool can accept connection patterns that are consistent with the DRC. In some embodiments, a routing process can be performed after operation 5020, and the circuit layout is scanned for DRC. In some embodiments, unacceptable connection patterns (e.g., connection patterns that violate the design rules) can be marked for correction. For example, connection patterns in which the quasi-metal layer is directly connected to other metal layers during the routing process are marked (e.g., connection patterns that do not conform to the DRC can be highlighted in the circuit layout by the EDA tool; the EDA tool can output an alarm voice to indicate that the connection pattern does not conform to the DRC). Correction of unacceptable connection patterns can be performed automatically or manually. For example, method 500 can loop back to operation 5010 to operation 5020 to manually or automatically correct the connection pattern. The corrected circuit layout can be scanned for DRC (e.g., using a loop process) until all connection patterns pass the DRC process.

[0082] Figure 5B A method 510 for forming a second extended TSV structure according to some embodiments is described. In some embodiments, the operations / steps of method 510 may be performed in a different order. Variations of method 510 are within the scope of the present invention. Figures 3A to 3C Additional details of the second extended TSV structure can be found in the description of FIG.

[0083] At operation 5110, one or more through-holes are connected to at least one end of the silicon through-hole to form a second extended silicon through-hole structure. The second extended silicon through-hole structure can be stored in the APR database, and the second extended silicon through-hole structure can be placed between metal interconnects in the circuit layout. The EDA tool can check the connection pattern of the through-hole, and if the connection pattern of the through-hole matches the wiring property of the through-hole, the through-hole is directly connected to the silicon through-hole and the metal interconnect. In some embodiments, the appropriate number of through-holes can be automatically or manually determined based on the electrical properties and design requirements of the formed second extended silicon through-hole structure. In some embodiments, after defining the second extended silicon through-hole structure, the number of through-holes can be fixed. In some embodiments, the second extended silicon through-hole can be defined as having the same or similar electrical properties as the through-hole, such as wiring properties. In some embodiments, the second extended silicon through-hole structure can be defined as being connected (e.g., directly connected) to the metal interconnect at both ends and being wired as a through-hole.

[0084] At operation 5120, in the APR flow, for example, an EDA tool considers the second extended TSV structure as a via. In some embodiments, the second extended TSV structure may be connected (eg, directly connected) to metal interconnects at both ends and routed as a via.

[0085] At operation 5130, the circuit layout is scanned for DRC / LVS checking, and connection patterns that violate the design rules / circuit layout verification are marked for correction. The EDA tool can accept connection patterns that comply with the DRC / LVS check. In some embodiments, unacceptable connection patterns (e.g., connection patterns that violate the design rules) can be marked for correction. For example, connection patterns where a quasi-metal layer connects to other metal layers during the routing process can be marked. Correction of unacceptable connection patterns can be performed automatically or manually. The corrected circuit layout can be scanned for DRC / LVS checking (e.g., using a loop process) until all connection patterns pass the DRC / LVS checking process.

[0086] Figure 5C Method 520 for forming a third extended TSV structure according to some embodiments is described. In some embodiments, the operations / steps of method 520 may be performed in a different order. Variations of method 520 are within the scope of the present invention. Figure 4A and Figure 4B Details of the third extended TSV structure can be found in the description of FIG.

[0087] At operation 5210, operations 5010, 5020, 5110, and 5120 are performed in any suitable order to form a third extended through silicon via structure. For example, the third extended through silicon via structure may be formed by first forming a first extended through silicon via structure, and then attaching / connecting a plurality of through holes to one end of the through silicon via that is not connected to the quasi-metal layer. Therefore, operations 5010 and 5020 may be performed before operations 5110 and 5120. In another example, the third extended through silicon via structure may be formed by first forming a second extended through silicon via structure, and then attaching / connecting a quasi-metal layer to one end of the through silicon via that is not connected to the through hole forming the second extended through silicon via structure. Therefore, operations 5110 and 5120 may be performed before operations 5010 and 5020. In some embodiments, the through hole and the quasi-metal layer are directly connected to the same through silicon via to form the third extended through silicon via structure. At operation 5220 , the circuit layout is scanned for DRC, and connection patterns violating the design rules are marked for correction, which is similar to operations 5030 and 5130 .

[0088] Figure 6 An exemplary computer system 600 is described in which various embodiments of the present invention may be implemented according to some embodiments. The computer system 600 may be any well-known computer capable of performing the functions and operations described herein. For example and without limitation, the computer system 600 may be capable of selecting a standard cell to be optimized and placing a metal cutout at a desired location in the standard cell, such as an EDA tool. The computer system 600 may be used, for example, to perform one or more operations in methods 500 to 520, which describe exemplary methods of forming an extended through silicon via structure.

[0089] Computer system 600 includes one or more processors (also referred to as central processing units or CPUs), such as processor 604. Processor 604 is connected to a communication infrastructure (or bus) 606. Computer system 600 also includes input / output devices 603, such as a monitor, keyboard, pointing device, etc., that communicate with communication infrastructure (or bus) 606 via input / output interface 602. EDA tools can receive instructions via input / output devices 603 to implement the functions and operations described herein, such as FIG. 5A to FIG. 5CThe computer system 600 also includes a main memory (or primary memory) 608, such as a random access memory (RAM). The main memory 608 may include one or more levels of cache memory. The main memory 608 stores control logic (e.g., computer software) and / or data. In some embodiments, the control logic (e.g., computer software) and / or data may include the above-mentioned FIG. 5A to FIG. 5C One or more of the operations described in methods 500 to 520 are shown.

[0090] The computer system 600 may also include one or more secondary storage devices or secondary memory 610. The secondary memory 610 may include, for example, a hard disk drive 612 and / or a removable storage device or removable storage drive 614. The removable storage drive 614 may be a floppy disk drive, a tape drive, a magnetic disk drive, an optical storage device, a tape backup device, and / or any other storage device / drive.

[0091] The removable storage drive 614 can interact with a removable storage unit 618. The removable storage unit 618 includes a computer usable or readable storage device that stores computer software (control logic) and / or data. The removable storage unit 618 can be a floppy disk, a magnetic tape, a magnetic disk, a digital video disk (DVD), an optical storage disk, and / or any other computer data storage device. The removable storage drive 614 can read from and / or write to the removable storage unit 618 in a well-known manner.

[0092] According to some embodiments, secondary memory 610 may include other components, means, or other methods that allow computer system 600 to access computer programs and / or other instructions and / or data. These components, means, or other methods may include, for example, a removable storage unit 622 and an interface 620. Examples of removable storage unit 622 and interface 620 may include a program cartridge and a cartridge interface (e.g., as found in a video game device), a removable memory chip (e.g., an erasable programmable read only memory (EPROM) or a programmable read only memory (PROM)) and an associated socket, a memory stick and a universal serial bus (USB) port, a memory card and an associated memory card slot, and / or any other removable storage unit and associated interface. In some embodiments, secondary memory 610, removable storage unit 618, and / or removable storage unit 622 may include the components described above with respect to FIG. 5A to FIG. 5C One or more of the operations described in methods 500 to 520 are shown.

[0093] The computer system 600 may also include a communication interface (or network interface) 624. The communication interface 624 enables the computer system 600 to interact and communicate with any combination of remote devices, remote networks, remote entities, etc. (individually or collectively labeled by reference number 628). For example, the communication interface 624 may allow the computer system 600 to communicate with the remote device 628 via a communication path 626, which may be wired and / or wireless and may include any combination of a local area network (LAN), a wide area network (WAN), the Internet, etc. Control logic and / or data may be transmitted to and from the computer system 600 via the communication path 626.

[0094] The operations in the foregoing embodiments may be implemented in a variety of configurations and architectures. Thus, the operations in the foregoing embodiments may be implemented in hardware, software, or both (e.g., FIG. 5A to FIG. 5C Methods 500 to 520 and Figure 7700 (described below)). In some embodiments, a tangible device or article of manufacture including a tangible computer-usable or readable medium having control logic (software) stored thereon is also referred to herein as a computer program product or program storage device. This includes, but is not limited to, computer system 600, primary memory 608, secondary memory 610, and removable storage unit 618 and removable storage unit 622, and tangible articles of manufacture embodied in any combination of the foregoing. This control logic, when executed by one or more data processing devices (e.g., computer system 600), causes such data processing devices to operate as described herein. In some embodiments, computer system 600 is installed with software to perform operations in the manufacture of photomasks and circuits, such as Figure 7 In some embodiments, the computer system 600 includes hardware / equipment for photomask manufacturing and circuit fabrication. For example, the hardware / equipment may be connected to a remote device, a network, an entity 628 of the computer system 600 or may be a part thereof.

[0095] Figure 7 An exemplary method 700 for performing circuit fabrication according to some embodiments is described. In some embodiments, the operations / steps of method 700 may be performed in a different order. Variations of method 700 are within the scope of the present invention.

[0096] In operation 701, a GDS file is provided. The GDS file may be generated by an EDA tool and includes an extended TSV structure according to the present invention. The operations illustrated in 701 may be implemented, for example, by an EDA tool that runs on a computer system (eg, the computer system 600 described above).

[0097] In operation 702, a photomask is formed based on the GDS file. In some embodiments, the GDS file provided in operation 701 can be used in a offline operation to generate a photomask to make one or more integrated circuits. In some embodiments, the circuit layout contained in the GDS file can be read and transferred to a quartz substrate or a glass substrate to form an opaque pattern corresponding to the circuit layout. The opaque pattern can be made of, for example, chrome or other suitable metals. Operation 702 can be performed by a photomask manufacturer, where a suitable software tool (e.g., an EDA tool) is used to read the circuit layout, and a suitable printing / deposition tool is used to transfer the circuit layout to a substrate. The photomask reflects the circuit layout / features contained in the GDS file.

[0098] In operation 703, one or more circuits are formed based on the photomask generated in operation 702. In some embodiments, the photomask can be used to form a pattern / structure of a circuit contained in a GDS file. In some embodiments, various fabrication tools (e.g., photolithography equipment, deposition equipment, and etching equipment) are used to form features of the one or more circuits on a semiconductor wafer.

[0099] In some embodiments, a through-hole structure includes: a middle portion extending through a planar structure; and a first end and a second end, each connected to the middle portion and located on different sides of the planar structure. One or more of the first end and the second end include a plurality of through-holes and one or more of the metalloid layers. In an embodiment, the metalloid layer cannot be connected to other metal layers during the automatic placement and routing process. In an embodiment, the metalloid layer is connected to the middle portion, and the metalloid layer can be connected to an internal connection via another plurality of through-holes on the first end. In an embodiment, the configuration of the other plurality of through-holes is adjustable. In an embodiment, the other plurality of through-holes are arranged in a two-dimensional array, and the size of the other plurality of through-holes, the arrangement of the other plurality of through-holes, the number of the other plurality of through-holes, or a combination thereof is adjustable. In an embodiment, the middle portion can be connected to other internal connections on the second end. In an embodiment, the middle portion is connected to another metalloid layer on the second end; the metalloid layer may be connected to the interconnection via a first portion of the other plurality of through-holes; and the other metalloid layer may be connected to the other interconnection via a second portion of the other plurality of through-holes. In an embodiment, the middle portion may be connected to the other interconnection via the plurality of through-holes. In an embodiment, the configuration of the plurality of through-holes is constant. In an embodiment, the plurality of through-holes are arranged in a two-dimensional array, and wherein the size of the plurality of through-holes, the arrangement of the plurality of through-holes, the number of the plurality of through-holes, or a combination thereof is adjustable. In an embodiment, the middle portion may be connected to at least one interconnection via the plurality of through-holes on at least one of the first end and the second end. In an embodiment, the configuration of the plurality of through-holes is constant. In an embodiment, the plurality of through-holes are arranged in a two-dimensional array, and wherein the size of the plurality of through-holes, the arrangement of the plurality of through-holes, the number of the plurality of through-holes, or a combination thereof is adjustable.

[0100] In some embodiments, a method for forming an extended through silicon via structure includes: connecting a metalloid layer and one or more of a plurality of through holes to one end of a through silicon via to form the extended through silicon via structure; and defining the wiring properties of the metalloid layer and the one or more of the plurality of through holes. The wiring properties of the metalloid layer may include being not connectable to an internal connection, and the wiring properties of the plurality of through holes may include being connectable to the metalloid layer, the through silicon via, and the internal connection. The method may also include: connecting the end of the extended through silicon via structure to the internal connection in response to the connection pattern of the metalloid layer and the plurality of through holes being consistent with the corresponding wiring properties. In an embodiment, connecting the end of the extended through silicon via structure to the internal connection includes: connecting the metalloid layer to the internal connection via one or more of another plurality of through holes; and defining the wiring properties of the metalloid layer includes: defining the metalloid layer as not connectable to other metal layers. In an embodiment, connecting the end of the extended TSV structure to the internal connection includes connecting the plurality of through-holes to the internal connection; and defining the wiring property includes defining the extended TSV structure as being connectable to the internal connection. In an embodiment, the method further includes inserting the one or more of the additional plurality of through-holes between the metalloid layer and the internal connection, wherein the one or more of the additional plurality of through-holes form a connection with the metal layer and the internal connection. In an embodiment, the method further includes performing a design rule check to detect whether there is a design rule violation, and correcting the detected design rule violation, wherein the design rule violation includes a direct connection between the metalloid layer and the internal connection and a connection between the metalloid layer and the other metal layer.

[0101] In some embodiments, a non-transitory computer-readable medium contains a computer executable program, which, when executed by a processor, implements a method for forming an extended through silicon via structure in a 3D integrated circuit package. The method may include: connecting a metalloid layer and one or more of a plurality of through-holes to one end of a through silicon via to form the extended through silicon via structure; and defining the wiring properties of the metalloid layer and the one or more of the plurality of through-holes. The wiring properties of the metalloid layer may include being not connectable to an internal connection, and the wiring properties of the plurality of through-holes may include being connectable to the metalloid layer, the through silicon via, and the internal connection. The method may also include: in response to the connection pattern of the metalloid layer and the plurality of through-holes being consistent with the corresponding wiring properties, connecting the end of the extended through silicon via structure to the internal connection. In an embodiment, the processor is further configured to: perform a design rule check to detect whether there is a design rule violation, and correct the detected design rule violation, wherein the design rule violation includes a direct connection between the metalloid layer and the internal connection and a connection between the metalloid layer and other metal layers.

[0102] It should be understood that the detailed description of the present invention (and not the abstract) is intended to be used to interpret the claims. The abstract of the present invention may set forth one or more but not all exemplary embodiments covered, and thus is not intended to be limited to the appended claims.

[0103] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for forming an extended through silicon via structure, comprising: Connecting the metalloid layer and one or more of the plurality of through holes to one end of the TSV to form the extended TSV structure; defining a wiring property of the metalloid layer and the one or more of the plurality of vias, wherein the wiring property of the metalloid layer includes being incapable of being connected to an internal connection, and the wiring property of the plurality of vias includes being connectable to the metalloid layer, the TSV, and the internal connection; as well as In response to the connection patterns of the metalloid layer and the plurality of through holes being consistent with corresponding wiring properties, the end of the extended TSV structure is connected to the internal connection.

2. The method according to claim 1, wherein: Connecting the end of the extended TSV structure to the internal connection includes: connecting the metalloid layer to the internal connection via one or more of the additional plurality of through holes; and Defining the wiring properties of the metalloid layer includes defining the metalloid layer as not connectable to another metal layer.

3. The method according to claim 1, wherein: Connecting the end of the extended TSV structure to the internal connection includes connecting the plurality of vias to the internal connection; and Defining the wiring property includes defining the extended TSV structure to be connectable to the internal connection.

4. The method of claim 2, further comprising inserting the one or more of the additional plurality of vias between the metalloid layer and the interconnect, wherein the one or more of the additional plurality of vias form a connection with the metal layer and the interconnect.

5. The method according to claim 2 further includes performing a design rule check to detect whether there is a design rule violation and correcting the detected design rule violation, wherein the design rule violation includes a direct connection between the metalloid layer and the internal connection and a connection between the metalloid layer and the other metal layer.

6. A non-transitory computer readable medium containing a computer executable program, wherein the computer executable program, when executed by a processor, implements a method of forming an extended through silicon via structure, the method comprising: Connecting the metalloid layer and one or more of the plurality of through holes to one end of the TSV to form the extended TSV structure; defining a wiring property of the metalloid layer and the one or more of the plurality of vias, wherein the wiring property of the metalloid layer includes being incapable of being connected to an internal connection, and the wiring property of the plurality of vias includes being connectable to the metalloid layer, the TSV, and the internal connection; as well as In response to the connection patterns of the metalloid layer and the plurality of through holes being consistent with corresponding wiring properties, the end of the extended TSV structure is connected to the internal connection.

7. The non-transitory computer-readable medium of claim 6, wherein the processor is further configured to: A design rule check is performed to detect whether there is a design rule violation and to correct the detected design rule violation, wherein the design rule violation includes a direct connection between the metalloid layer and the interconnection line and a connection between the metalloid layer and another metal layer.

8. The non-transitory computer-readable medium of claim 6, wherein: Connecting the end of the extended TSV structure to the internal connection includes connecting the metalloid layer to the internal connection through one or more of a plurality of additional vias; as well as Defining the wiring properties of the metalloid layer includes defining that the metalloid layer cannot be connected to other metal layers.

9. The non-transitory computer-readable medium of claim 6, wherein: Connecting the end of the extended TSV structure to the internal connection includes connecting the plurality of vias to the internal connection; as well as Defining the wiring property includes defining that the extended TSV structure can be connected to the internal connection.

10. The non-transitory computer-readable medium of claim 6, wherein the processor is further configured to insert the one or more of an additional plurality of vias between the metalloid layer and the interconnect, wherein the one or more of the additional plurality of vias form a connection with the metal layer and the interconnect.

11. A computer system comprising: a memory configured to store instructions; as well as A processor, when executing the instructions, is configured to perform a plurality of operations, the plurality of operations comprising: Connecting the metalloid layer and one or more of the plurality of through holes to one end of the TSV to form an extended TSV structure; defining a wiring property of the metalloid layer and the one or more of the plurality of vias, wherein the wiring property of the metalloid layer includes being inaccessible to an internal connection, and the wiring property of the plurality of vias includes being connectable to the metalloid layer, the TSV, and the internal connection; and In response to the connection patterns of the metalloid layer and the plurality of through holes being consistent with corresponding wiring properties, the end of the extended TSV structure is connected to the internal connection.

12. The computer system of claim 11, wherein: Connecting the end of the extended TSV structure to the internal connection includes connecting the metalloid layer to the internal connection through one or more of a plurality of additional vias; as well as Defining the wiring properties of the metalloid layer includes defining that the metalloid layer cannot be connected to other metal layers.

13. The computer system of claim 11, wherein: Connecting the end of the extended TSV structure to the internal connection includes connecting the plurality of vias to the internal connection; as well as Defining the wiring property includes defining that the extended TSV structure can be connected to the internal connection.

14. The computer system of claim 11, wherein each of the plurality of through-vias is smaller than the extended TSV structure.

15. The computer system of claim 11, wherein connecting the end of the extended TSV structure to the internal connection comprises: In response to the connection pattern complying with a corresponding design rule check or circuit layout verification check, the end of the extended TSV structure is connected to the internal connection.

16. The computer system of claim 11, wherein the processor is further configured to insert the one or more of another plurality of vias between the metalloid layer and the interconnect, wherein the one or more of the another plurality of vias form a connection with the metal layer and the interconnect.

17. The computer system of claim 11, wherein the processor is further configured to perform a design rule check to detect whether a design rule violation exists and to correct the detected design rule violation, wherein the design rule violation includes a direct connection between the metalloid layer and the interconnect and a connection between the metalloid layer and another metal layer.

18. The computer system of claim 11, wherein the processor is further configured to connect a plurality of additional vias to another end of the TSV.

19. The computer system of claim 11, wherein the processor is further configured to connect another end of the TSV to another internal connection.

20. The computer system of claim 11, wherein the processor is further configured to connect another end of the extended TSV structure to another internal connection.

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