Display device and method of manufacturing the same

Abstract

Disclosed are a display device and a method for manufacturing the same, the display device comprising: a pixel circuit; an insulating layer covering the pixel circuit; a first partition portion disposed on the insulating layer and extending in a first direction; a second partition portion separated from the first partition portion in a second direction intersecting the first direction and extending in the first direction; a plurality of connection partition portions disposed between the first partition portion and the second partition portion, wherein each of the plurality of connection partition portions extends in the second direction; a first electrode disposed on the first partition portion and electrically connected to the pixel circuit; a second electrode disposed on the second partition portion; and a light-emitting element disposed between the plurality of connection partition portions and electrically connected to the first electrode and the second electrode.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2018-0097411, filed on August 21, 2018, and all rights arising therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The disclosure herein relates to a display device capable of improving reliability and manufacturing yield and a method of manufacturing the same. Background Art

[0003] The display device may include a light emitting element. The light emitting element may be electrically connected to the electrode and may emit light by a voltage applied to the electrode. The light emitting element may be directly formed on the electrode, or a light emitting element formed separately from the electrode may be connected to the electrode. Summary of the invention

[0004] In a display device, when a light emitting element is separately formed and then connected to an electrode, it may be desirable to align the light emitting element with the electrode. If the light emitting element is not regularly aligned with the electrode, the light emitting element may not emit light.

[0005] The disclosure may provide a display device having improved reliability and manufacturing yield and a method of manufacturing the display device.

[0006] In an embodiment of the invention, a display device may include: a pixel circuit; an insulating layer covering the pixel circuit; a first partition portion arranged on the insulating layer and extending in a first direction; a second partition portion separated from the first partition portion in a second direction intersecting the first direction and extending in the first direction; a plurality of connection partition portions arranged between the first partition portion and the second partition portion, wherein each of the plurality of connection partition portions extends in the second direction; a first electrode arranged on the first partition portion and electrically connected to the pixel circuit; a second electrode arranged on the second partition portion; and a light-emitting element arranged between the plurality of connection partition portions and electrically connected to the first electrode and the second electrode.

[0007] In an embodiment, when viewed in a plan view, the light emitting element may be surrounded by the first partition part, the second partition part, and the plurality of connection partition parts.

[0008] In an embodiment, the first separation portion, the second separation portion, and the plurality of connection separation portions may include the same material as one another.

[0009] In an embodiment, the first electrode may extend in the first direction and may cover the first partition portion, and the second electrode may extend in the first direction and may cover the second partition portion. In such an embodiment, when viewed in a plan view, a first distance in the second direction between the first electrode and the second electrode in a region adjacent to the plurality of connected partition portions may be equal to a second distance in the second direction between the first electrode and the second electrode in a region overlapping the plurality of connected partition portions.

[0010] In an embodiment, the first electrode may include a first extended electrode portion extending in the first direction, and a first protruding electrode portion protruding from the first extended electrode portion in a direction toward the second electrode. In such an embodiment, the second electrode may include a second extended electrode portion extending in the first direction, and a second protruding electrode portion protruding from the second extended electrode portion in a direction toward the first electrode.

[0011] In an embodiment, the first protruding electrode portion may be disposed between the plurality of connecting and separating portions when viewed in a plan view, and the second protruding electrode portion may be disposed between the plurality of connecting and separating portions when viewed in a plan view.

[0012] In an embodiment, when viewed in a plan view, a first distance in the second direction between the first protruding electrode portion and the second protruding electrode portion may be smaller than a second distance in the second direction between the first extension electrode portion and the second extension electrode portion.

[0013] In an embodiment, each of the first and second separation portions may have a first thickness, each of the plurality of connected separation portions may have a second thickness, and the first thickness may be equal to the second thickness.

[0014] In an embodiment, each of the first and second separation portions may have a first thickness, each of the plurality of connected separation portions may have a second thickness, and the first thickness may be greater than the second thickness.

[0015] In an embodiment, each of the plurality of connection partitioning parts may have a trapezoidal shape when viewed in a cross-sectional view parallel to the first direction.

[0016] In an embodiment, an outermost surface of each of the plurality of connection partitioning parts may have a curvature when viewed in a cross-sectional view parallel to the first direction.

[0017] In an embodiment, the plurality of connection partitioning parts may be spaced apart from each other in the first direction. In such an embodiment, the first partitioning part, the second partitioning part, and the plurality of connection partitioning parts may be connected to each other to constitute a single unit.

[0018] In an embodiment of the invention, a method for manufacturing a display device may include the following steps: setting a pixel circuit on a substrate layer; setting an insulating layer covering the pixel circuit; setting an initial insulating layer on the insulating layer; patterning the initial insulating layer to form a first partition portion, a second partition portion and a plurality of connected partition portions; setting a first electrode covering the first partition portion; setting a second electrode covering the second partition portion; setting a light-emitting element between the first electrode and the second electrode and between the plurality of connected partition portions; and aligning the light-emitting element.

[0019] In an embodiment, patterning the preliminary insulating layer may include disposing a mask over the preliminary insulating layer, and exposing and developing the preliminary insulating layer using the mask to form the first separation part, the second separation part, and the plurality of connection separation parts.

[0020] In an embodiment, the mask may include a light blocking portion and a light transmitting portion. In such an embodiment, the step of disposing the mask above the initial insulating layer may include disposing the mask in such a manner that the light blocking portion may be disposed to overlap with an area where the first partition, the second partition, and the plurality of connected partitions are to be formed.

[0021] In an embodiment, the mask may include a light blocking portion, a light transmitting portion, and a light semi-transmitting portion. In such an embodiment, the step of disposing the mask above the initial insulating layer may include disposing the mask in such a manner that the light blocking portion may be disposed to overlap with a region where the first partition portion and the second partition portion are to be formed, and the light semi-transmitting portion may be disposed to overlap with a region where the plurality of connected partition portions are to be formed.

[0022] In an embodiment of the invention, a display device may include: a first partition portion extending in a first direction; a second partition portion separated from the first partition portion in a second direction intersecting the first direction and extending in the first direction; a first electrode arranged on the first partition portion; a second electrode arranged on the second partition portion; a first connecting partition portion arranged between the first partition portion and the second partition portion; a second connecting partition portion arranged between the first partition portion and the second partition portion and separated from the first connecting partition portion in the first direction; and a light-emitting element arranged in a space defined by the first partition portion and the second partition portion and the first connecting partition portion and the second connecting partition portion, and electrically connected to the first electrode and the second electrode.

[0023] In an embodiment, the first electrode and the second electrode may extend in the first direction and may be spaced apart from each other in the second direction. In such an embodiment, a separation distance between the first electrode and the second electrode in the second direction may be different depending on the position.

[0024] In an embodiment, when viewed in a plan view, a separation distance in a region overlapping the first connection separation portion or the second connection separation portion may be greater than a separation distance in a region between the first connection separation portion and the second connection separation portion.

[0025] In an embodiment, the first electrode may include a first extended electrode portion extending in the first direction, and a first protruding electrode portion protruding from the first extended electrode portion in a direction toward the second electrode. In such an embodiment, the second electrode may include a second extended electrode portion extending in the first direction, and a second protruding electrode portion protruding from the second extended electrode portion in a direction toward the first electrode. In such an embodiment, the first protruding electrode portion and the second protruding electrode portion may be disposed in a region between the first connection separation portion and the second connection separation portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] These and / or other features of the invention will become apparent and more readily understood through the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a perspective view showing a display device according to an embodiment of the invention;

[0028] Figure 2 is a block diagram showing a display device according to an embodiment of the invention;

[0029] Figure 3 is an equivalent circuit diagram of a pixel according to an embodiment of the invention;

[0030] Figure 4A is a cross-sectional view showing a light emitting element according to an embodiment of the invention;

[0031] Figure 4B is a cross-sectional view showing a light emitting element according to an alternative embodiment of the invention;

[0032] Figure 4C is a cross-sectional view showing a light emitting element according to another alternative embodiment of the invention;

[0033] Figure 4D is a cross-sectional view showing a light emitting element according to another alternative embodiment of the invention;

[0034] Figure 5 is a cross-sectional view showing a display panel according to an embodiment of the invention;

[0035] Figure 6 is a plan view showing some components of a display panel according to an embodiment of the invention;

[0036] Fig. 7A is along Figure 6 A cross-sectional view taken along line II';

[0037] Figure 7B is along Figure 6 A cross-sectional view taken along line II-II';

[0038] Figure 8 is a plan view showing some components of a display panel according to an alternative embodiment of the invention;

[0039] Fig.9A is along Figure 8 A cross-sectional view taken along line III-III';

[0040] Fig. 9B is along Figure 8 A cross-sectional view taken along line IV-IV';

[0041] Fig.10 It is shown Figure 7B A cross-sectional view of an alternative embodiment of the portion shown in FIG.

[0042] Fig.11A is along Figure 8 A cross-sectional view taken along line V-V';

[0043] Fig. 11B It is shown Fig.11A A cross-sectional view of an alternative embodiment of the portion shown in FIG.

[0044] Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D is a schematic diagram showing an embodiment of a process of forming a first partition portion, a second partition portion, and a plurality of connected partition portions;

[0045] Fig.13A , Fig. 13B and Fig. 13C is a schematic diagram showing an alternative embodiment of a process of forming a first partition portion, a second partition portion, and a plurality of connected partition portions; and

[0046] Fig.14 is a cross-sectional view illustrating a process of aligning a light emitting element according to an embodiment of the invention. DETAILED DESCRIPTION

[0047] The invention will now be described more fully below with reference to the accompanying drawings showing various embodiments. However, the invention can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0048] It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present. In contrast, the term “directly” means that there are no intervening elements present.

[0049] The terms used herein are only for the purpose of describing specific embodiments and are not intended to be restrictive. Unless the context clearly indicates otherwise, as used herein, the singular forms "one", "a kind of" and "the" are intended to include plural forms including "at least one". "Or" means "and / or". "At least A and B" means "A and / or B". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when the term "comprising" or "including" is used in this specification, the features, regions, wholes, steps, operations, elements and / or components stated are listed, but the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups are not excluded.

[0050] For ease of description, spatially relative terms such as "under," "below," "below," "above," and "above" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, then the elements described as "below" or "beneath" other elements or features will subsequently be positioned as "above" the other elements or features. Therefore, the exemplary term "below" may include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0051] It will be understood that, although the terms first, second, etc. can be used here to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings here, the first element, first component, first region, first layer or first part discussed below can be referred to as the second element, second component, second region, second layer or second part.

[0052] To take into account measurement issues and errors associated with measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art.

[0053] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary illustrations. In the accompanying drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shapes of the illustrations, for example due to manufacturing techniques and / or manufacturing tolerances, are expected. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown here, but include deviations in shapes, for example, caused by manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. In addition, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and unless the terms are interpreted in an ideal or overly formal sense, they are explicitly defined herein.

[0055] Hereinafter, exemplary embodiments of the invention will be described in detail with reference to the accompanying drawings.

[0056] Figure 1 is a perspective view showing a display device according to an embodiment of the invention.

[0057] Reference Figure 1 , an embodiment of the display device DD can display an image through a display area DA defined therein. In an embodiment, as Figure 1 As shown in FIG. 1 , the display area DA is disposed in a plane defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1. However, embodiments of the invention are not limited thereto. In an alternative embodiment, the display area of ​​the display device DD may be disposed in a curved surface.

[0058] The thickness direction of the display device DD may be indicated by a third direction DR3. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be relative concepts and may be changed to other directions. The clause "when viewed in a plan view" used herein may mean the clause "when viewed from a plan view on the third direction DR3". In addition, the term "thickness direction" may mean the third direction DR3.

[0059] exist Figure 1 In the embodiment, the display device DD is a television. In other embodiments, the display device DD may be a large electronic device (e.g., a monitor and an external billboard) or a small and medium-sized electronic device (e.g., a personal computer, a laptop, a personal digital assistant (“PDA”), a car navigation unit, a game console, a smart phone, a tablet computer, and a camera). However, these are merely exemplary, and the display device may also be applied to other electronic devices without departing from the spirit and scope of the invention.

[0060] Figure 2 is a block diagram showing a display device according to an embodiment of the invention.

[0061] Reference Figure 2 , an embodiment of a display device DD may include a display panel DP, a signal controller (or a timing controller) TC, a data driver DDV, and a scan driver GDV. Each of the signal controller TC, the data driver DDV, and the scan driver GDV may include a circuit.

[0062] The display panel DP may be a micro light emitting element display panel including micro light emitting elements. In one embodiment, for example, the display panel DP may be a micro light emitting diode (micro LED) display panel.

[0063] The display panel DP may include a plurality of data lines DL1 to DLm, a plurality of scan lines SL1 to SLn, and a plurality of pixels PX.

[0064] The plurality of data lines DL1 to DLm may extend in a first direction DR1 and may be arranged in a second direction DR2 crossing the first direction DR1. The plurality of scan lines SL1 to SLn may extend in a second direction DR2 and may be arranged in the first direction DR1.

[0065] Each of the pixels PX may include a light emitting element and a pixel circuit electrically connected to the light emitting element. The pixel circuit may include a plurality of transistors. A first power supply voltage ELVDD and a second power supply voltage ELVSS may be provided to each of the pixels PX.

[0066] When viewed in a plan view, the pixels PX may be regularly arranged on the display panel DP. Each of the pixels PX may display one of the primary colors or one of the mixed colors. The primary colors may include red, green, and blue, and the mixed colors may include various colors such as yellow, cyan, magenta, and white. However, the colors displayed by the pixels PX are not limited thereto.

[0067] In an embodiment, the signal controller TC may receive image data RGB from an external system. The signal controller TC may convert the image data RGB into converted image data R'G'B' suitable for operation of the display panel DP and may output or provide the converted image data R'G'B' to the data driver DDV.

[0068] In such an embodiment, the signal controller TC may receive a control signal CS from an external system. The control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a master clock signal, and a data enable signal. The signal controller TC may provide a first control signal CONT1 to the data driver DDV, and may provide a second control signal CONT2 to the scan driver GDV. The first control signal CONT1 may be a signal for controlling the data driver DDV, and the second control signal CONT2 may be a signal for controlling the scan driver GDV.

[0069] The data driver DDV may provide an electrical signal or voltage to a plurality of data lines DL1 to DLm in response to a first control signal CONT1 received from the signal controller TC. The data driver DDV may be implemented as an independent integrated circuit to be electrically connected to one side of the display panel DP or directly mounted on the display panel DP. In some embodiments, the data driver DDV may be implemented as a separate chip or may include a plurality of chips.

[0070] The scan driver GDV may provide an electrical signal to the scan lines SL1 to SLn in response to a second control signal CONT2 received from the signal controller TC. The scan driver GDV may be integrated in a predetermined area of ​​the display panel DP. In one embodiment, for example, the scan driver GDV may include a plurality of thin film transistors formed by the same process as the pixel circuit of the pixel PX (e.g., a low temperature polycrystalline silicon ("LTPS") process or a low temperature polycrystalline oxide ("LTPO") process). Alternatively, the scan driver GDV may be implemented as an independent integrated circuit chip to be electrically connected to one side of the display panel DP.

[0071] When a gate-on voltage is applied to one of the plurality of scan lines SL1 to SLn, a switching transistor of a row of pixels connected to the scan line may be turned on. When a data driver DDV supplies a data drive signal to the data lines DL1 to DLm, the data drive signal supplied to the data lines DL1 to DLm may be applied to the pixels through the turned-on switching transistor. The data drive signal may be an analog voltage corresponding to a grayscale value of image data.

[0072] Figure 3 is an equivalent circuit diagram of a pixel according to an embodiment of the invention. Figure 3 Shows Figure 2 An equivalent circuit diagram of one of the multiple pixels PX.

[0073] Reference Figure 3 , an embodiment of the pixel PX can be electrically connected to a plurality of signal lines. In an embodiment, the scan line SL, the data line DL, the first power line PL1 and the second power line PL2 collectively define a signal line. However, embodiments of the invention are not limited thereto. In an optional embodiment, the pixel PX can be additionally connected to at least one of the other various signal lines.

[0074] The pixel PX may include a light emitting element ED, a first electrode E1, a second electrode E2, and a pixel circuit PXC. The pixel circuit PXC may include a first thin film transistor TR1, a capacitor CAP, and a second thin film transistor TR2. However, the number of thin film transistors and capacitors included in the pixel circuit PXC is not limited to Figure 3 In an alternative embodiment, the pixel circuit PXC may include seven thin film transistors and one capacitor.

[0075] The first thin film transistor TR1 may be a switching transistor configured to control on / off of the pixel PX. The thin film transistor TR1 may transmit or block a data signal provided through the data line DL in response to a scan signal provided through the scan line SL.

[0076] The capacitor CAP may be connected to the first thin film transistor TR1 and the first power line PL1. The capacitor CAP may be charged with a charge or voltage corresponding to a difference between a data signal transmitted from the first thin film transistor TR1 and a first power voltage ELVDD provided through the first power line PL1.

[0077] The second thin film transistor TR2 may be connected to the first thin film transistor TR1, the capacitor CAP, and the light emitting element ED. The second thin film transistor TR2 may control the driving current flowing through the light emitting element ED in response to the amount of charge stored in the capacitor CAP. The on time of the second thin film transistor TR2 may be determined according to the amount of charge stored in the capacitor CAP.

[0078] In the embodiment, all the first thin film transistors TR1 and the second thin film transistors TR2 may be N-type thin film transistors or P-type thin film transistors, but are not limited thereto. Alternatively, one of the first thin film transistor TR1 and the second thin film transistor TR2 may be an N-type thin film transistor, and the other of the first thin film transistor TR1 and the second thin film transistor TR2 may be a P-type thin film transistor.

[0079] The light emitting element ED may be connected to the second thin film transistor TR2 and the second power line PL2. For example, in one embodiment, the light emitting element ED may be connected to the first electrode E1 and the second electrode E2, the first electrode E1 is electrically connected to the second thin film transistor TR2, and the second electrode E2 is electrically connected to the second power line PL2. The first electrode E1 may be electrically connected to the pixel circuit PXC, and the second electrode E2 may receive a power supply voltage (e.g., a second power supply voltage ELVSS) through the second power line PL2.

[0080] The light emitting element ED may emit light by a voltage corresponding to a difference between a signal transmitted through the second thin film transistor TR2 and a second power voltage ELVSS received through the second power line PL2 .

[0081] The light emitting element ED may be a micro LED element. The micro LED element may be an LED element having a length of several nanometers to several hundred micrometers. However, the length of the micro LED element is not limited to this numerical range.

[0082] In an embodiment, Figure 3 As shown in FIG. 1 , one light emitting element ED may be connected between the second thin film transistor TR2 and the second power line PL2 , but is not limited thereto. In an alternative embodiment, a plurality of light emitting elements ED may be provided. The plurality of light emitting elements ED may be connected in parallel to each other.

[0083] Figure 4A is a cross-sectional view showing a light emitting element according to an embodiment of the invention.

[0084] The light emitting element ED may have one of various shapes such as a cylindrical shape and a polygonal column shape. Figure 4A A cross section of the light emitting element ED is shown.

[0085] Reference Figure 4A , an embodiment of the light emitting element ED may include an N-type semiconductor layer SCN, a P-type semiconductor layer SCP, and an active layer AL. The active layer AL may be disposed between the N-type semiconductor layer SCN and the P-type semiconductor layer SCP.

[0086] The N-type semiconductor layer SCN can be provided by doping the semiconductor layer with an N-type dopant, and the P-type semiconductor layer SCP can be provided by doping the semiconductor layer with a P-type dopant. The semiconductor layer may include a semiconductor material. In one embodiment, for example, the semiconductor material may include but is not limited to GaN, AlN, AlGaN, InGaN, InN, InAlGaN or AlInN. In one embodiment, for example, the N-type dopant may include but is not limited to silicon (Si), germanium (Ge), tin (Sn), selenium (Se), tellurium (Te) or any combination thereof. In one embodiment, for example, the P-type dopant may include but is not limited to magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) or any combination thereof.

[0087] The active layer AL may have at least one of a single quantum well structure, a multi-quantum well structure, a quantum wire structure, and a quantum dot structure. In the active layer AL, electrons injected through the N-type semiconductor layer SCN may be recombined with holes injected through the P-type semiconductor layer SCP. The active layer AL may be a layer configured to emit light having energy determined by an intrinsic energy band of a material. The position of the active layer AL may be changed differently depending on the type of the diode.

[0088] The N-type semiconductor layer SCN may be connected to the first electrode E1 and the second electrode E2 (see Figure 3 ), the P-type semiconductor layer SCP may be connected to the other of the first electrode E1 and the second electrode E2.

[0089] The length LT of the light emitting element ED may be in the range from several nanometers to hundreds of micrometers. In one embodiment, for example, the length LT of the light emitting element ED may be in the range from 1 micrometer to 100 micrometers.

[0090] Figure 4B is a cross-sectional view showing a light emitting element according to an alternative embodiment of the invention.

[0091] Reference Figure 4B In addition to the light emitting element EDa further comprising a first electrode layer ECL1 and a second electrode layer ECL2, such an embodiment of the light emitting element EDa may be Figure 4A The embodiments of the light emitting element ED shown in FIG. 1 are basically the same. Figure 4B The same or identical elements shown in FIG. 1 have been used to describe the Figure 4A The embodiments of the light emitting element ED shown in the drawings are denoted by the same reference numerals, and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0092] The first electrode layer ECL1 may be adjacent to the N-type semiconductor layer SCN, and the second electrode layer ECL2 may be adjacent to the P-type semiconductor layer SCP. In one embodiment, for example, the first electrode layer ECL1, the N-type semiconductor layer SCN, the active layer AL, the P-type semiconductor layer SCP, and the second electrode layer ECL2 may be arranged sequentially or stacked one on top of another.

[0093] Each of the first electrode layer ECL1 and the second electrode layer ECL2 may include or be formed of a metal or an alloy of the metal. In one embodiment, for example, each of the first electrode layer ECL1 and the second electrode layer ECL2 may include or be formed of molybdenum (Mo), chromium (Cr), nickel (Ni), gold (Au), aluminum (Al), titanium (Ti), platinum (Pt), vanadium (V), tungsten (W), lead (Pb), palladium (Pd), copper (Cu), rhodium (Rh), iridium (Ir), or any alloy thereof. The first electrode layer ECL1 and the second electrode layer ECL2 may include the same material as each other or different materials from each other.

[0094] Figure 4C is a cross-sectional view showing a light emitting element according to another alternative embodiment of the invention.

[0095] Reference Figure 4C , except that the light emitting element EDb further includes the insulating layer IL, such an embodiment of the light emitting element EDb may be the same as Figure 4A In one embodiment, for example, the light emitting element EDb may have a core-shell structure. Figure 4C The same or identical elements shown in FIG. 1 have been used to describe the Figure 4A The embodiments of the light emitting element ED shown in the drawings are denoted by the same reference numerals, and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0096] The insulating layer IL may cover the N-type semiconductor layer SCN, the P-type semiconductor layer SCP, and the active layer AL, and may protect outer surfaces of the N-type semiconductor layer SCN, the P-type semiconductor layer SCP, and the active layer AL. In an alternative embodiment, the insulating layer IL may only cover the active layer AL.

[0097] Figure 4D is a cross-sectional view showing a light emitting element according to another alternative embodiment of the invention.

[0098] Reference Figure 4D, except that the light emitting element EDc further includes the insulating layer ILa, such an embodiment of the light emitting element EDc may be Figure 4B The embodiments of the light emitting element EDa shown in FIG. 1 are basically the same. Figure 4D The same or identical elements shown in FIG. 1 have been used to describe the Figure 4B The embodiments of the light emitting element EDa shown in the drawings are denoted by the same reference numerals, and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0099] In such an embodiment, the insulating layer ILa may cover the N-type semiconductor layer SCN, the P-type semiconductor layer SCP and the active layer AL, but may not cover the first electrode layer ECL1 and the second electrode layer ECL2. In an optional embodiment, the insulating layer ILa may cover at least a portion of the first electrode layer ECL1 and the second electrode layer ECL2, or may completely cover the first electrode layer ECL1 and the second electrode layer ECL2.

[0100] Figure 5 is a cross-sectional view showing a display panel according to an embodiment of the invention, Figure 6 1 is a plan view showing some components of a display panel according to an embodiment of the invention. For the purpose of making description and explanation easy and convenient, Figure 5 and Figure 6 shows the area corresponding to one pixel, and Figure 5 and Figure 6 Some components are omitted.

[0101] Reference Figure 5 and Figure 6 In an embodiment of the display panel, the first base layer BL1 and the second base layer BL2 may be disposed opposite to or facing each other. Each of the first base layer BL1 and the second base layer BL2 may be a silicon substrate, a plastic substrate, a glass substrate, or an insulating film, or may have a stacked structure including a plurality of insulating layers.

[0102] The buffer layer BFL may be disposed on the first base layer BL1. The first thin film transistor TR1 and the second thin film transistor TR2 may be disposed on the buffer layer BFL.

[0103] The first thin film transistor TR1 may include a first control electrode CE1, a first input electrode IE1, a first output electrode OE1, and a first semiconductor pattern SP1. The second thin film transistor TR2 may include a second control electrode CE2, a second input electrode IE2, a second output electrode OE2, and a second semiconductor pattern SP2.

[0104] The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be disposed on the buffer layer BFL. In an embodiment, the buffer layer BFL may provide a reformed or modified surface to the first semiconductor pattern SP1 and the second semiconductor pattern SP2. In such an embodiment, the adhesive strength between the buffer layer BFL and the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be improved compared to a case where the first semiconductor pattern SP1 and the second semiconductor pattern SP2 are directly formed on the first base layer BL1. Alternatively, the buffer layer BFL may be a barrier layer for protecting the bottom surfaces of the first semiconductor pattern SP1 and the second semiconductor pattern SP2. In such an embodiment, the buffer layer BFL may prohibit or prevent contaminants or moisture from penetrating from the inside of the first base layer BL1 or through the first base layer BL1 to the first semiconductor pattern SP1 and the second semiconductor pattern SP2.

[0105] The first insulating layer L1 may be disposed on the buffer layer BFL and may cover the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The first insulating layer L1 may include an inorganic material. In one embodiment, for example, the inorganic material may include but is not limited to silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide.

[0106] The first and second control electrodes CE1 and CE2 may be disposed on the first insulating layer L1. The second insulating layer L2 may be disposed on the first insulating layer L1 and may cover the first and second control electrodes CE1 and CE2. The second insulating layer L2 may include an inorganic material.

[0107] Capacitor CAP (see Figure 3 ) may include a first capacitor electrode (not shown) and a second capacitor electrode CPa. In one embodiment, for example, the first capacitor electrode may be defined by a portion branched from the second control electrode CE2, and the second capacitor electrode CPa may be disposed on the second insulating layer L2.

[0108] The third insulating layer L3 may be disposed on the second insulating layer L2 and may cover the second capacitor electrode CPa. The first input electrode IE1, the first output electrode OE1, the second input electrode IE2, and the second output electrode OE2 may be disposed on the third insulating layer L3. The first input electrode IE1 and the first output electrode OE1 may be connected to the first semiconductor pattern SP1 by passing through a through hole defined by the first insulating layer to the third insulating layer L1, L2, and L3. The second input electrode IE2 and the second output electrode OE2 may be connected to the second semiconductor pattern SP2 by passing through a through hole defined by the first insulating layer to the third insulating layer L1, L2, and L3. At least a portion of each of the signal lines (e.g., scan lines or data lines) may be disposed on the third insulating layer L3, as may the first input electrode IE1 and the first output electrode OE1, and the second input electrode IE2 and the second output electrode OE2.

[0109] The fourth insulating layer L4 may be disposed on the third insulating layer L3 and may cover the first input electrode IE1, the first output electrode OE1, the second input electrode IE2, and the second output electrode OE2. The fourth insulating layer L4 may have a single-layer structure or a multi-layer structure including a plurality of layers. The fourth insulating layer L4 may include an organic material and / or an inorganic material.

[0110] The connection electrode CNE may be disposed on the fourth insulating layer L4. At least another portion of each of the signal lines (eg, scan lines or data lines) may be disposed on the fourth insulating layer L4 in addition to the connection electrode CNE. The connection electrode CNE may be connected to the second output electrode OE2.

[0111] The fifth insulating layer L5 may be disposed on the fourth insulating layer L4 and may cover the connection electrode CNE. The fifth insulating layer L5 may include an organic material. The fifth insulating layer L5 may cover the pixel circuit PXC disposed thereunder (see Figure 3 ), and may have a flat top surface.

[0112] The first partition BR1, the second partition BR2, and a plurality of connection partitions CBR may be disposed on the fifth insulating layer L5. Each of the first partition BR1 and the second partition BR2 may extend in the first direction DR1. The second partition BR2 may be separated from the first partition BR1 in the second direction DR2. The connection partition CBR may be disposed between the first partition BR1 and the second partition BR2. Each of the connection partitions CBR may extend in the second direction DR2. The connection partitions CBR may be separated from each other in the first direction DR1 and may be arranged in the first direction DR1. The first partition BR1, the second partition BR2, and the connection partition CBR may include the same material as each other. In one embodiment, for example, each of the first partition BR1, the second partition BR2, and the connection partition CBR may include an organic material. The first partition BR1, the second partition BR2, and the plurality of connection partitions CBR may be connected to each other to form a single unit.

[0113] The first electrode E1 may be disposed on the first partitioning portion BR1, and the second electrode E2 may be disposed on the second partitioning portion BR2. The first electrode E1 may extend in the first direction DR1 and may cover the first partitioning portion BR1. The second electrode E2 may extend in the first direction DR1 and may cover the second partitioning portion BR2. In such an embodiment, the first partitioning portion BR1 may be disposed between the first electrode E1 and the fifth insulating layer L5, and the second partitioning portion BR2 may be disposed between the second electrode E2 and the fifth insulating layer L5.

[0114] A through hole may be defined in the fifth insulating layer L5, and a portion of the connection electrode CNE may be exposed through the through hole. The first electrode E1 may be electrically connected to the exposed portion of the connection electrode CNE. Even though not shown in the drawings, the second electrode E2 may also be electrically connected to the second power line PL2 (see FIG. 1 ). Figure 3 In such an embodiment, the second power supply voltage ELVSS (see Figure 3 ) may be provided to the second electrode E2.

[0115] The first electrode E1 may include a first reflective electrode RFE1 and a first cover electrode CPE1, and the second electrode E2 may include a second reflective electrode RFE2 and a second cover electrode CPE2.

[0116] Each of the first reflective electrode RFE1 and the second reflective electrode RFE2 may include a reflective material. Each of the first reflective electrode RFE1 and the second reflective electrode RFE2 may have a single-layer structure or a multi-layer structure. In one embodiment, for example, each of the first reflective electrode RFE1 and the second reflective electrode RFE2 may have a structure in which an indium tin oxide ("ITO") layer, a silver ("Ag") layer, and an indium tin oxide ("ITO") layer are sequentially stacked one on top of the other.

[0117] The first cover electrode CPE1 may cover or cover the first reflective electrode RFE1, and the second cover electrode CPE2 may cover or cover the second reflective electrode RFE2. In one embodiment, for example, each of the first cover electrode CPE1 and the second cover electrode CPE2 may include at least one of IZO, ITO, indium gallium oxide ("IGO"), indium zinc gallium oxide ("IGZO"), and any mixture / compound thereof.

[0118] The light emitting element ED may be disposed on the fifth insulating layer L5. The light emitting element ED may be provided in plurality, and the plurality of light emitting elements ED may be connected in parallel to each other. Even if not shown in the drawings, an insulating pattern (not shown) may be disposed between the fifth insulating layer L5 and the light emitting element ED. The light emitting element ED may be electrically connected to the first electrode E1 and the second electrode E2. The light emitting element ED may be disposed between a plurality of connection partitions CBR. In one embodiment, for example, when viewed in a plan view, the light emitting element ED may be surrounded by a first partition BR1, a second partition BR2, and a plurality of connection partitions CBR.

[0119] In an embodiment, Figure 5 As shown in , a portion of the light emitting element ED is disposed on the first electrode E1, and another portion of the light emitting element ED is disposed on the second electrode E2. However, the embodiments of the invention are not limited thereto. In an optional embodiment, the light emitting element ED may be disposed between the first electrode E1 and the second electrode E2. In one embodiment, for example, the length of the light emitting element ED may be less than the distance between the first electrode E1 and the second electrode E2. In an embodiment, when viewed in a plan view, the light emitting element ED may not overlap with the first electrode E1 and the second electrode E2.

[0120] A sixth insulating layer (or insulating pattern) L6 may be disposed on the light emitting element ED. The sixth insulating layer L6 may cover at least a portion of a top surface of the light emitting element ED.

[0121] The light emitting element ED may be electrically connected to the first electrode E1 through the first connection electrode CNE1 , and may be electrically connected to the second electrode E2 through the second connection electrode CNE2 .

[0122] The second connection electrode CNE2 may be disposed on the light emitting element ED and the second electrode E2. The seventh insulating layer L7 may be disposed on the second connection electrode CNE2. The first connection electrode CNE1 may be disposed on the light emitting element ED and the first electrode E1. Even if the length of the light emitting element ED is several hundred micrometers or less, the second connection electrode CNE2 and the first connection electrode CNE1 may not be in direct contact with each other due to the seventh insulating layer L7. However, the embodiments of the invention are not limited thereto. In an optional embodiment, the first connection electrode CNE1 and the second connection electrode CNE2 may be formed simultaneously by the same process. In such an embodiment, the seventh insulating layer L7 may be omitted.

[0123] The first connection electrode CNE1 and the second connection electrode CNE2 may include a conductive material. In one embodiment, for example, the conductive material may include at least one of IZO, ITO, IGO, IGZO, or any mixture / compound thereof. However, the embodiments of the invention are not limited thereto. In an optional embodiment, for example, the conductive material may be a metal material, and the metal material may include, for example, molybdenum, silver, titanium, copper, aluminum, or any alloy thereof.

[0124] An eighth insulating layer L8 may be disposed on the first connection electrode CNE1 and the seventh insulating layer L7. The eighth insulating layer L8 may be an encapsulation layer.

[0125] The light blocking layer BM may be disposed on one surface of the second base layer BL2, the surface of the second base layer BL2 facing the first base layer BL1. An opening may be defined in the light blocking layer BM, and a wavelength conversion portion CL may be disposed to cover the opening. An area exposed by the opening may correspond to the pixel light emitting area PXA.

[0126] The wavelength conversion portion CL may include a luminophore or a photoluminescent material. In one embodiment, for example, the luminophore may absorb the first light provided from the light emitting element ED, and may convert the wavelength of the first light into the wavelength of a second light having a color different from the color of the first light. In such an embodiment, the luminophore may convert the first light into the second light, and may emit the second light. For example, the luminophore may be a quantum dot. The first light may be blue light, and the second light may be green light or red light. However, embodiments of the invention are not limited thereto. In an optional embodiment, the wavelength conversion portion CL may be replaced by a color filter. The color filter may absorb light of a specific wavelength to achieve a specific color. In another optional embodiment, the wavelength conversion portion CL may be omitted. In such an embodiment, the light emitting element ED may emit blue light, green light, or red light.

[0127] The ninth insulating layer L9 may be disposed between the wavelength conversion portion CL and the eighth insulating layer L8. In one embodiment, for example, the pixel circuit PXC (see FIG. 1 ) is disposed thereon through the ninth insulating layer L9. Figure 3 ) and the first base layer BL1 of the light emitting element ED may be bonded to the second base layer BL2 on which the wavelength conversion portion CL and the light blocking layer BM are disposed. In one embodiment, for example, the ninth insulating layer L9 may include an optically transparent adhesive film, an optically transparent resin, or a pressure-sensitive adhesive film. However, embodiments of the invention are not limited thereto. In another embodiment, the ninth insulating layer L9 may be omitted.

[0128] Fig. 7A is along Figure 6 A cross-sectional view taken along line II' of Figure 7B is along Figure 6 A cross-sectional view taken along line II-II'.

[0129] Fig. 7A It can be a cross-sectional view of a region adjacent to the connection partition portion CBR. In other words, Fig. 7A It may be a cross-sectional view of a region in which the connecting spacer portion CBR is not provided in a plan view (eg, a region not overlapped with the connecting spacer portion CBR in a plan view). Figure 7B It can be a cross-sectional view of the region overlapping with the connection partition portion CBR. In other words, Figure 7B It may be a cross-sectional view of a region in which the connection partition portion CBR is provided in a plan view.

[0130] Fig. 7A , a first distance LT1 between the first electrode E1 and the second electrode E2 is shown in FIG. Figure 7B , a second distance LT2 between the first electrode E1 and the second electrode E2 is shown in FIG. Each of the first distance LT1 and the second distance LT2 may be a distance measured between the first electrode E1 and the second electrode E2 when viewed in a plan view (e.g., when viewed in a third direction DR3). In one embodiment, for example, each of the first distance LT1 and the second distance LT2 may be a distance in the second direction DR2. In an embodiment, the first distance LT1 and the second distance LT2 may be equal to each other.

[0131] Each of the first partition BR1 and the second partition BR2 may have a first thickness TK1, and each of the connecting partitions CBR may have a second thickness TK2. The first thickness TK1 may be the maximum thickness of each of the first partition BR1 and the second partition BR2, and the second thickness TK2 may be the maximum thickness of each of the connecting partitions CBR. In an embodiment, the first thickness TK1 and the second thickness TK2 may be equal to each other.

[0132] A space SPA surrounded by the first and second partitioning parts BR1 and BR2 and the first and second connection partitioning parts CBR1 and CBR2 adjacent to each other among the plurality of connection partitioning parts CBR may be defined. When viewed in a plan view, the light emitting element ED may be disposed in the space SPA. According to an embodiment of the invention, the arrangement position of the light emitting element ED may be determined by the space SPA.

[0133] Figure 8 is a plan view showing some components of a display panel according to an alternative embodiment of the invention. Fig.9A is along Figure 8 A cross-sectional view taken along line III-III'. Fig. 9B is along Figure 8 A cross-sectional view taken along line IV-IV'.

[0134] Reference Figure 8 , Fig.9A and Fig. 9B In an embodiment of the display panel, the first electrode E1a may include a first extended electrode portion E1e extending in the first direction DR1 and a first protruding electrode portion E1p protruding from the first extended electrode portion E1e. The second electrode E2a may include a second extended electrode portion E2e extending in the first direction DR1 and a second protruding electrode portion E2p protruding from the second extended electrode portion E2e. The first protruding electrode portion E1p may protrude from the first extended electrode portion E1e in a direction toward the second electrode E2a, and the second protruding electrode portion E2p may protrude from the second extended electrode portion E2e in a direction toward the first electrode E1a.

[0135] In an embodiment, when viewed in a plan view, the first protruding electrode portion E1p and the second protruding electrode portion E2p may be disposed between the connecting partition portions CBR adjacent to each other. In such an embodiment, when viewed in a plan view, the first protruding electrode portion E1p and the second protruding electrode portion E2p may overlap with a space SPA surrounded by the first connecting partition portions CBR1 and CBR2 and the first partition portions BR1 and BR2.

[0136] Fig.9A , a first distance LT1a between the first electrode E1a and the second electrode E2a is shown in FIG. Fig. 9B, a second distance LT2a between the first electrode E1a and the second electrode E2a is shown in FIG. Each of the first distance LT1a and the second distance LT2a may be a distance measured between the first electrode E1a and the second electrode E2a when viewed in a plan view (e.g., when viewed in the third direction DR3). In one embodiment, for example, each of the first distance LT1a and the second distance LT2a may be a distance in the second direction DR2.

[0137] The first distance LT1a may correspond to a minimum distance between the first protruding electrode portion E1p and the second protruding electrode E2p, and the second distance LT2a may correspond to a minimum distance between the first extended electrode portion E1e and the second extended electrode portion E2e. In an embodiment, the first distance LT1a may be smaller than the second distance LT2a.

[0138] According to an embodiment of the invention, as described above, the first distance LT1a between the first electrode E1a and the second electrode E2a in the region where the light emitting element ED is disposed may be smaller than the second distance LT2a between the first electrode E1a and the second electrode E2a in the region where the light emitting element ED is not disposed.

[0139] Fig.10 It is shown Figure 7B A cross-sectional view of an alternative portion shown in FIG.

[0140] Reference Fig.10 , each of the first partitioning portion BR1 and the second partitioning portion BR2 may have a first thickness TK1a, and each of the connecting partitioning portions CBRa may have a second thickness TK2a. The first thickness TK1a may be the maximum thickness of each of the first partitioning portion BR1 and the second partitioning portion BR2, and the second thickness TK2a may be the maximum thickness of each of the connecting partitioning portions CBRa. In an embodiment, the first thickness TK1a may be greater than the second thickness TK2a.

[0141] Fig.11A is along Figure 8 A cross-sectional view taken along line V-V'.

[0142] Reference Figure 8 and Fig.11A , a cross section CBS1 of each of the connection partition portions CBR may have a trapezoidal shape. The cross section CBS1 may be a plane parallel to the first direction DR1 and the third direction DR3.

[0143] Fig. 11B It is shown Fig.11A A cross-sectional view of an alternative embodiment of a portion is shown in FIG.

[0144] Reference Figure 8 and Fig. 11B , when viewed in a cross-sectional view parallel to the first direction DR1 and the third direction DR3, the outermost surface of each of the connecting partitions CBR may have a curvature. In one embodiment, for example, a cross section CBS2 of each of the connecting partitions CBR may have a convex lens shape. In such an embodiment where the connecting partition CBR has a circular shape, in the process of aligning the light emitting element ED, the light emitting element ED disposed on the connecting partition CBR may be effectively introduced into the space between the connecting partitions CBR.

[0145] FIG. 12A to FIG. 12D is a schematic diagram illustrating an embodiment of a process of forming a first partition portion, a second partition portion, and a plurality of connection partition portions.

[0146] Reference Fig. 12A , a first base layer BL1 may be prepared. Even though not shown in the drawings, the first base layer BL1 may be disposed on a working substrate (not shown) in a manufacturing process. After the display panel is manufactured, the working substrate may be removed.

[0147] A pixel circuit PXC including a first thin film transistor TR1 and a second thin film transistor TR2 may be disposed or formed on the first base layer BL1 (see FIG. Figure 3 ). A fifth insulating layer L5 may be provided or formed to cover the pixel circuit PXC. The fifth insulating layer L5 may include an organic material. The fifth insulating layer L5 may provide a flat top surface.

[0148] A preliminary insulating layer BBR may be disposed or formed on the fifth insulating layer L5. The preliminary insulating layer BBR may include an organic material.

[0149] Reference Fig. 12A and Fig. 12B After forming the preliminary insulating layer BBR, a mask MK may be disposed over the preliminary insulating layer BBR. The mask MK may be a binary mask including a light transmitting portion TP and a light blocking portion BP.

[0150] The preliminary insulating layer BBR may be a positive photoresist layer or a negative photoresist layer. Hereinafter, for the convenience of description, an embodiment in which the preliminary insulating layer BBR is a positive photoresist layer will be described in detail.

[0151] In such an embodiment, the light blocking portion BP may be disposed in a region where the first and second partitioning portions BR1 and BR2 are to be formed (see FIG. Fig. 12C and Fig.12D ) and the connecting partition CBR (see Fig.12D) region. The light transmission portion TP may overlap with the remaining region except for the region. After the mask MK is disposed over the preliminary insulating layer BBR, light may be radiated.

[0152] Reference Fig. 12C and Fig.12D , the initial insulating layer BBR (see Fig. 12A ) is patterned to form a first partition BR1, a second partition BR2 and a connecting partition CBR. The patterning process may include an exposure process and a development process. The first partition BR1, the second partition BR2 and the connecting partition CBR may be formed simultaneously by the same process.

[0153] FIG. 13A to FIG. 13C is a schematic diagram showing an alternative embodiment of a process of forming a first partition portion, a second partition portion, and a plurality of connected partition portions.

[0154] Reference FIG. 13A to FIG. 13C After forming the preliminary insulating layer BBR, a mask MKa may be disposed over the preliminary insulating layer BBR. The mask MKa may be a half-tone mask including a light transmitting portion TP, a light semi-transmitting portion HTP, and a light blocking portion BP.

[0155] The light blocking portion BP may be disposed to overlap with the first region where the first and second partition portions BR1 and BR2 are to be formed, and the light semi-transmitting portion HTP may be disposed to overlap with the second region where the connecting partition portion CBRa is to be formed. The light transmitting portion TP may overlap with the remaining region except the first and second regions.

[0156] The initial insulating layer BBR may be patterned to form a first partition BR1, a second partition BR2, and a connecting partition CBRa. A portion of the connecting partition CBRa in the thickness direction may be removed, so that the thickness of the connecting partition CBRa may be smaller than that of the first partition BR1 and the second partition BR2. As a result, in the process of arranging the light emitting element ED, the light emitting element ED may be arranged between the first partition BR1 and the second partition BR2 (see FIG. 1 ). Figure 5 ) possibility.

[0157] Fig.14 is a cross-sectional view illustrating a process of aligning a light emitting element according to an embodiment of the invention.

[0158] Reference Figure 8 and Fig.14 , a first electrode E1a covering the first separating portion BR1 and a second electrode E2a covering the second separating portion BR2 may be formed.

[0159] A solution and a solvent including a light emitting element ED may be provided on the first electrode E1a and the second electrode E2a. The solvent may be a material that can evaporate at room temperature or by heating. The solution may be an ink or a paste that may include the light emitting element ED. The light emitting element ED may be disposed in a space defined among the first partition BR1, the second partition BR2, and the connecting partition CBR. According to an embodiment of the invention, the arrangement position of the light emitting element ED may be controlled by the connecting partition CBR.

[0160] Electric power may be applied to the first electrode E1a and the second electrode E2a to form an electric field between the first electrode E1a and the second electrode E2a. Bipolarity may be induced in the light emitting element ED by the electric field, and the light emitting element ED may be aligned on the first electrode E1a and the second electrode E2a by the electrophoretic force. According to an embodiment of the invention, the distance between the first electrode E1a and the second electrode E2a in the region in which the light emitting element ED is disposed may be smaller than the distance between the first electrode E1a and the second electrode E2a in the region in which the light emitting element ED is not disposed. As a result, the electrophoretic force occurring at the light emitting element ED may be increased, and thus the light emitting element ED may be effectively aligned.

[0161] According to the embodiment of the invention, the arrangement position of the light emitting element ED can be controlled by the connection partition portion CBR, and the light emitting element ED can be effectively aligned by the first protruding electrode portion E1p and the second protruding electrode portion E2p. Therefore, the effective alignment probability of the light emitting element ED can be increased. As a result, the yield of the product and the reliability of the product can be improved.

[0162] According to an embodiment of the invention, a display device may include a plurality of connection partitions connecting a first partition and a second partition, and a light-emitting element may be arranged in a space defined by the plurality of connection partitions, the first partition, and the second partition. In addition, the first electrode may include a first extended electrode portion and a first protruding electrode portion, and the second electrode may include a second extended electrode portion and a second protruding electrode portion. The first protruding electrode portion and the second protruding electrode portion may be arranged in a space between the plurality of connection partitions. The arrangement direction and arrangement position of the light-emitting element may be controlled by the plurality of connection partitions and the first protruding electrode portion and the second protruding electrode portion. Therefore, the manufacturing yield and reliability of the display device may be improved.

[0163] Although the invention has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, it should be understood that the above embodiments are not restrictive but illustrative. Therefore, the scope of the invention is determined by the broadest permissible interpretation of the claims and their equivalents, and should not be restricted or limited by the foregoing description.

Claims

1. A display device, comprising: Pixel circuit; an insulating layer, covering the pixel circuit; A first separation portion, disposed on the insulating layer and extending in a first direction; a second partition portion, spaced apart from the first partition portion in a second direction intersecting the first direction and extending in the first direction; a plurality of connecting partitions disposed between the first partition and the second partition, wherein each of the plurality of connecting partitions extends in the second direction; a first electrode disposed on the first partition portion and electrically connected to the pixel circuit; a second electrode disposed on the second partition portion; and a light emitting element having a first side surface facing the first partition portion, a second side surface opposite to the first side surface and facing the second partition portion, a third side surface connecting the first side surface and the second side surface, and a fourth side surface opposite to the third side surface and connecting the first side surface and the second side surface, The third side surface faces a first connecting and separating portion among the plurality of connecting and separating portions, and the fourth side surface faces a second connecting and separating portion among the plurality of connecting and separating portions.

2. The display device according to claim 1, wherein: When viewed in a plan view, the light emitting element is surrounded by the first partitioning portion, the second partitioning portion, and the plurality of connecting partitioning portions.

3. The display device according to claim 2, wherein: The first partition portion, the second partition portion, and the plurality of connection partition portions include the same material as one another.

4. The display device according to claim 2, wherein: The first electrode extends in the first direction and covers the first partition portion, The second electrode extends in the first direction and covers the second partition portion, and When viewed in the plan view, a first distance in the second direction between the first electrode and the second electrode in a region adjacent to the multiple connected separation portions is equal to a second distance in the second direction between the first electrode and the second electrode in a region overlapping the multiple connected separation portions.

5. The display device according to claim 2, wherein: The first electrode includes: a first extended electrode portion extending in the first direction; and a first protruding electrode portion protruding from the first extended electrode portion in a direction toward the second electrode, and The second electrode includes: a second extended electrode portion extending in the first direction; and a second protruding electrode portion protruding from the second extended electrode portion in a direction toward the first electrode.

6. The display device according to claim 5, wherein: When viewed in the plan view, the first protruding electrode portion is disposed between the plurality of connecting and separating portions, and The second protruding electrode portion is disposed between the plurality of connecting partition portions when viewed in the plan view.

7. The display device according to claim 5, wherein: A first distance between the first protruding electrode portion and the second protruding electrode portion in the second direction is smaller than a second distance between the first extension electrode portion and the second extension electrode portion in the second direction when viewed in the plan view.

8. The display device according to claim 1, wherein: Each of the first partition portion and the second partition portion has a first thickness, Each of the plurality of connection partitioning portions has a second thickness, and The first thickness is equal to the second thickness.

9. The display device according to claim 1, wherein: Each of the first partition portion and the second partition portion has a first thickness, Each of the plurality of connection partitioning portions has a second thickness, and The first thickness is greater than the second thickness.

10. The display device according to claim 1, wherein: Each of the plurality of connection partitioning parts has a trapezoidal shape when viewed in a cross-sectional view parallel to the first direction.

11. The display device according to claim 1, wherein: When viewed in a cross-sectional view parallel to the first direction, an outermost surface of each of the plurality of connecting and separating parts has a curvature.

12. The display device according to claim 1, wherein: The plurality of connection and separation portions are spaced apart from each other in the first direction, and The first partition part, the second partition part, and the plurality of connection partition parts are connected to each other to constitute a single unit.

13. A method for manufacturing a display device, the method comprising the following steps: Disposing a pixel circuit on the substrate layer; Disposing an insulating layer covering the pixel circuit; providing an initial insulating layer on the insulating layer; patterning the initial insulating layer to form a first separation portion, a second separation portion, and a plurality of connection separation portions; Disposing a first electrode covering the first partition portion; Disposing a second electrode covering the second partition portion; Disposing a light emitting element between the first electrode and the second electrode and between the plurality of connecting and separating parts, so that the light emitting element has a first side surface facing the first separating part, a second side surface opposite to the first side surface and facing the second separating part, a third side surface connecting the first side surface and the second side surface, and a fourth side surface opposite to the third side surface and connecting the first side surface and the second side surface; as well as The light emitting element is aligned so that the third side faces a first connecting partition portion among the plurality of connecting partition portions, and the fourth side faces a second connecting partition portion among the plurality of connecting partition portions.

14. The method according to claim 13, wherein: The step of patterning the initial insulating layer comprises: disposing a mask over the initial insulating layer; and The preliminary insulating layer is exposed and developed using the mask to form the first partition part, the second partition part, and the plurality of connection partition parts.

15. The method according to claim 14, wherein: The mask includes a light blocking portion and a light transmitting portion, and The step of disposing the mask over the preliminary insulating layer includes disposing the mask in such a manner that the light blocking portion is disposed to overlap a region in which the first and second partitions and the plurality of connection partitions are to be formed.

16. The method according to claim 14, wherein: The mask includes a light blocking portion, a light transmitting portion, and a light semi-transmitting portion, and The step of setting the mask above the initial insulating layer includes setting the mask in such a manner that the light blocking portion is set to overlap with a region where the first partition portion and the second partition portion will be formed, and the light semi-transmitting portion is set to overlap with a region where the multiple connected partition portions will be formed.

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