Electronic devices

Abstract

An electronic device is provided. The electronic device includes: a base substrate including a front surface and a rear surface facing each other, and a module hole penetrating the front surface and the rear surface is defined in the base substrate; a thin film transistor is disposed on the base substrate; a light emitting device including a first electrode connected to the thin film transistor, a second electrode disposed on the first electrode, and a light emitting pattern disposed between the first electrode and the second electrode; an encapsulation layer covering the light emitting device; an input sensing unit disposed on the base substrate and including a plurality of first conductive patterns and a plurality of second conductive patterns disposed on the plurality of first conductive patterns; and an insulating layer disposed between the plurality of first conductive patterns and the plurality of second conductive patterns. The encapsulation layer is disposed between the plurality of first conductive patterns and the plurality of second conductive patterns.

Description

[0001] This patent application claims the benefit of Korean Patent Application No. 10-2018-0104569, filed on September 3, 2018, which is hereby incorporated by reference in its entirety. Technical Field

[0002] The present disclosure herein relates to an electronic device and a method for manufacturing the electronic device, and more particularly, to an electronic device with a simplified manufacturing process and a method for manufacturing the electronic device. Background Art

[0003] The electronic device is activated according to the electrical signal. Such an electronic device may include a device composed of various electronic components, such as a display unit that displays an image and an input sensing unit that senses an external input. The electronic components may be electrically connected to each other through differently arranged signal lines.

[0004] The display unit includes a light emitting element that generates an image. The input sensing unit may include a sensing electrode for sensing an external input. The thickness of the electronic device in which the display unit and the input sensing unit are provided in one panel may increase, and thus the process cost may increase. Summary of the invention

[0005] The present disclosure provides an electronic device and a method for manufacturing the electronic device, in which integration of a display unit and an input sensing unit is improved and a manufacturing process is simplified.

[0006] An embodiment of the inventive concept provides an electronic device, comprising: a base substrate, comprising a front surface and a rear surface facing each other, and a module hole penetrating the front surface and the rear surface is defined in the base substrate; a thin film transistor, disposed on the base substrate; a light emitting device, comprising a first electrode connected to the thin film transistor, a second electrode disposed on the first electrode, and a light emitting pattern disposed between the first electrode and the second electrode; an encapsulation layer, configured to cover the light emitting device; an input sensing unit, disposed on the base substrate, and comprising a plurality of first conductive patterns and a plurality of second conductive patterns disposed on the plurality of first conductive patterns; and an insulating layer, disposed between the plurality of first conductive patterns and the plurality of second conductive patterns, wherein the encapsulation layer is disposed between the plurality of first conductive patterns and the plurality of second conductive patterns.

[0007] In an embodiment, the plurality of second conductive patterns may include: a first sensing electrode extending in a first direction; and a second sensing electrode extending in a direction crossing the first direction to generate capacitance together with the first sensing electrode.

[0008] In an embodiment, at least a portion of the plurality of first conductive patterns may be connected to at least a portion of the plurality of second conductive patterns through a contact hole penetrating the encapsulation layer.

[0009] In an embodiment, the plurality of first conductive patterns may overlap the second electrode on a plane, and the contact hole may penetrate the second electrode.

[0010] In an embodiment, the electronic device may further include an inner insulating layer configured to cover side surfaces of the contact hole, wherein the second electrode and the plurality of second conductive patterns may be electrically disconnected from each other by the inner insulating layer.

[0011] In an embodiment, each of the first electrode, the light emitting pattern, and the second electrode may be provided in plural, and the plural second electrodes may be provided to overlap the plural light emitting patterns, respectively.

[0012] In an embodiment, the plurality of first conductive patterns may be spaced apart from the plurality of second electrodes on a plane.

[0013] In an embodiment, the electronic device may further include an auxiliary electrode adjacent to the first electrode, wherein the plurality of second electrodes may be connected to the auxiliary electrode.

[0014] In an embodiment, the plurality of first conductive patterns and the plurality of second conductive patterns may be spaced apart from each other on a plane.

[0015] In an embodiment, the insulating layer may include an organic layer disposed between the first electrode and the second electrode, and the organic layer may completely cover the plurality of first conductive patterns.

[0016] In an embodiment, the insulating layer may further include a plurality of insulating patterns respectively covering the plurality of first conductive patterns, and the organic layer may cover the plurality of insulating patterns.

[0017] In an embodiment, a plurality of insulation patterns may cover the top surface and the side surfaces of each first conductive pattern, respectively.

[0018] In an embodiment, the encapsulation layer may include a first inorganic layer, a second inorganic layer disposed on the first inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer, and the module hole may penetrate the first inorganic layer and the second inorganic layer.

[0019] In an embodiment, the electronic device may further include a groove portion defined along an edge of the module hole and recessed from a front surface of the base substrate, wherein the first inorganic layer and the second inorganic layer may cover a side surface of the groove portion.

[0020] In an embodiment, the electronic device may further include an organic pattern disposed in the groove portion, wherein the organic pattern may be covered by the first inorganic layer and the second inorganic layer.

[0021] In an embodiment, the organic pattern may include the same material as that of at least one of the insulating layer and the second electrode.

[0022] In an embodiment of the inventive concept, a method for manufacturing an electronic device includes: forming a thin film transistor on a base substrate, the base substrate including a hole area and an effective area adjacent to the hole area; forming a first electrode connected to the thin film transistor in the effective area; forming an insulating layer having an opening defined therein to expose at least a portion of the first electrode; forming a first mask layer, the first mask layer including an opening to expose at least a portion of the hole area of ​​the base substrate; forming a recess in the base substrate through the opening of the first mask layer; patterning the first mask layer to form a plurality of first conductive patterns separated from the opening; forming a light emitting pattern in the opening; forming an organic layer overlapping the light emitting pattern and the plurality of first conductive patterns on a plane; forming a second electrode on the organic layer; forming an encapsulation layer on the second electrode; and forming a plurality of second conductive patterns on the encapsulation layer.

[0023] In an embodiment, the method may further include: forming a plurality of contact holes penetrating the encapsulation layer and the second electrode; and forming an inner insulating layer, the inner insulating layer covering inner surfaces of the plurality of contact holes and exposing top surfaces of at least a portion of the plurality of first conductive patterns, wherein at least a portion of the plurality of second conductive patterns may contact top surfaces of the plurality of first conductive patterns exposed through the plurality of contact holes.

[0024] In an embodiment, the light emitting pattern may be provided in plurality, and the step of forming the second electrode may further include forming a plurality of patterns respectively overlapping the plurality of light emitting patterns.

[0025] In an embodiment, the base substrate may include a base layer and an auxiliary layer covering a front surface of the base layer, and the recessed portion may penetrate the auxiliary layer and be recessed from the front surface of the base layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept. In the drawings:

[0027] Figure 1 is a perspective view of an electronic device according to an embodiment of the inventive concept;

[0028] Figure 2A yes Figure 1 An exploded perspective view of an electronic device;

[0029] Figure 2B yes Figure 1 A block diagram of an electronic device;

[0030] Figure 3A is along Figure 2A A cross-sectional view taken along line II';

[0031] Figure 3B It is shown Figure 3A A schematic equivalent circuit diagram of a portion of a component;

[0032] Figure 4A is along Figure 2A A cross-sectional view taken along line II-II';

[0033] Figure 4B and Figure 4C It is shown Figure 2A The plan of area XX';

[0034] Figure 5A is a plan view showing a portion of an area of ​​an electronic panel according to an embodiment of the inventive concept;

[0035] Figure 5B is a cross-sectional view showing a portion of a region of an electronic panel according to an embodiment of the inventive concept;

[0036] Fig. 6A is a plan view showing a portion of an area of ​​an electronic panel according to an embodiment of the inventive concept;

[0037] Figure 6B is a cross-sectional view showing a portion of a region of an electronic panel according to an embodiment of the inventive concept;

[0038] Fig. 7A and Figure 7B is a cross-sectional view of an electronic panel according to an embodiment of the inventive concept;

[0039] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E , Fig.8F , Figure 8G , Figure 8H , Figure 8I , Figure 8J , Figure 8K , Figure 8L and Figure 8M is a cross-sectional view illustrating a process of manufacturing an electronic panel according to an embodiment of the inventive concept; and

[0040] Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D and Fig.9E is a cross-sectional view illustrating a process of manufacturing an electronic panel according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0041] In this specification, it will be understood that when a component (or region, layer, portion) is referred to as being "on," "connected to," or "coupled to" another component, the component may be directly disposed on, directly connected / coupled to, the other component, or intermediate components may also be present.

[0042] The same reference numerals always represent the same elements. In addition, in the drawings, the thickness, proportion and size of components are exaggerated for clarity of explanation.

[0043] The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] It will be understood that although terms such as "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from other components. For example, a first element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims. Unless otherwise indicated, terms in the singular may include plural forms.

[0045] In addition, “under”, “below”, “above”, “on”, etc. are used to explain the relationship association of components shown in the drawings. These terms may be relative concepts and are described based on the directions shown in the drawings.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, unless interpreted in an idealized or overly formal sense, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are clearly defined here.

[0047] The meaning of “include” or “comprising” indicates the existence of properties, fixed numbers, steps, operations, elements, components or combinations thereof, but does not exclude other properties, fixed numbers, steps, operations, elements, components or combinations thereof.

[0048] Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0049] Figure 1 is a perspective view of an electronic device according to an embodiment of the inventive concept. Figure 2A yes Figure 1 An exploded perspective view of an electronic device. Figure 2B yes Figure 1 In the following, reference will be made to Figures 1 to 2B An electronic device according to an embodiment of the inventive concept is described.

[0050] The electronic device EA may be a device activated according to an electrical signal. The electronic device EA may include various examples. For example, the electronic device EA may include a tablet computer, a laptop computer, a computer, a smart TV, etc. In this embodiment, an electronic device EA including a smart phone will be described as an example.

[0051] like Figure 1 As shown in , the electronic device EA may display an image IM on its front surface. The front surface may be defined to be parallel to a surface defined by the first direction DR1 and the second direction DR2. The front surface may include a transmission area TA and a bezel area BZA adjacent to the transmission area TA.

[0052] The image IM is displayed in the transmission area TA of the electronic device EA. Figure 1 An Internet search window is shown as an example of the image IM. The transmissive area TA may have a rectangular shape parallel to the first direction DR1 and the second direction DR2. However, this is only an example. For example, the electronic device EA may have various shapes and is not limited to the shape shown.

[0053] The frame area BZA is adjacent to the transmission area TA. The frame area BZA may surround the transmission area TA. However, this is only an example. For example, the frame area BZA may be disposed adjacent to only one side of the transmission area TA, or may be omitted. The electronic device EA according to the inventive concept may include various configurations and is not limited to the configuration shown.

[0054] The normal direction of the front surface may correspond to the thickness direction of the electronic device EA (hereinafter, referred to as the third direction DR3). In this embodiment, the front surface (or top surface) or the rear surface (or bottom surface) of each member may be defined relative to the direction in which the image IM is displayed. The front surface and the rear surface may face each other in the third direction DR3.

[0055] The directions indicated as the first direction DR1, the second direction DR2, and the third direction DR3 may be relative concepts and, therefore, may be optionally changed to different directions. Hereinafter, the first direction, the second direction, and the third direction may be directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3, respectively, and are represented by the same reference numerals, respectively.

[0056] The electronic device EA according to the inventive concept can sense a user input TC applied from the outside (hereinafter, also referred to as "external input TC"). The user input TC includes various types of external inputs such as a part of the user's body, light, heat, pressure, etc. In the present embodiment, the user input TC is shown as a user's hand applied to the front surface. However, this is only an example. For example, as described above, the user input TC can be provided in various forms. The electronic device EA can sense the user input TC applied to the side surface or the rear surface of the electronic device EA according to the structure of the electronic device EA, but is not limited to a specific embodiment.

[0057] like Figure 1 and Figure 2A As shown in FIG. 1 , the electronic device EA includes an electronic panel PN, a window member WM, an electronic module EM and a receiving member BM. Figure 2B As shown in FIG. 1 , in addition to the electronic panel PN, the electronic device EA may further include a first electronic module EM1, a second electronic module EM2 and a power module PM. Figure 2A In, omitted Figure 2B In the following, reference will be made to Figures 1 to 2B To describe the electronic device EA.

[0058] The electronic panel PN may display an image IM and sense an external input TC. For example, the electronic panel PN may include a display unit DPU that displays an image IM and an input sensing unit ISU that senses an external input TC. In this embodiment, the input sensing unit ISU may sense an external input TC applied to the window member WM.

[0059] The electronic panel PN may include an active area AA, a peripheral area NAA, and a hole area HA divided on a plane. The active area AA may be an area activated according to an electrical signal.

[0060] In the present embodiment, the active area AA may be an area in which the image IM is displayed and the external input TC is also sensed. However, this is only an example. For example, the area of ​​the active area AA in which the image IM is displayed and the area of ​​the active area AA in which the external input TC is sensed may be separated from each other, and the present disclosure is not limited to a specific embodiment.

[0061] The peripheral area NAA may be an area covered by the frame area BZA. The peripheral area NAA is adjacent to the active area AA. The peripheral area NAA may surround the active area AA. A driving circuit or a driving line for driving the active area AA may be provided in the peripheral area NAA.

[0062] In the present embodiment, the electronic panel PN can be assembled in a state where the active area AA and the peripheral area NAA are flat to face the window member WM. However, this is merely an example. For example, a portion of the peripheral area NAA of the electronic panel PN may be curved. Here, a portion of the peripheral area NAA may be set to face the rear surface of the electronic device EA to reduce the area of ​​the border area BZA on the front surface of the electronic device EA. Alternatively, the electronic panel PN may be assembled in a state where a portion of the active area AA is curved. Alternatively, in the electronic panel PN according to an embodiment of the inventive concept, the peripheral area NAA may be omitted.

[0063] The edge of the hole area HA may be surrounded by the active area AA. The hole area HA may be spaced apart from the peripheral area NAA on a plane, and the active area AA is located between the hole area HA and the peripheral area NAA.

[0064] The hole area HA may be an area in which the module hole MH is defined. Therefore, the module hole MH may be surrounded on a plane by the active area AA in which the image IM is displayed.

[0065] At least one module hole MH penetrating the electronic panel PN in the third direction DR3 may be defined in the electronic panel PN according to an embodiment of the inventive concept. The module hole MH may be a through hole connected from the front surface of the electronic panel PN to the rear surface. Components disposed on the rear surface of the electronic panel PN to overlap with the module hole MH may be visible through the module hole MH at the front surface of the electronic panel PN. In the present embodiment, although the module hole MH has a cylindrical shape having a certain height in the third direction DR3, the inventive concept is not limited thereto. For example, the module hole MH may have a polygonal column shape, an elliptical column shape, a cone shape, etc., and is not limited to a specific embodiment.

[0066] The module hole MH overlaps with the electronic module EM on a plane. The electronic module EM can receive a signal input through the module hole MH to provide the signal to the electronic panel PN. The electronic module EM can receive an external input TC through the module hole MH. The electronic module EM can be a module having a size that can be accommodated in the module hole MH and / or a module having a size similar to that of the module hole MH. The electronic module EM will be described in more detail below.

[0067] The window member WM is arranged on the front surface of the electronic device EA. The window member WM can be arranged on the front surface of the electronic panel PN to protect the electronic panel PN. For example, the window member WM may include a glass substrate, a sapphire substrate or a plastic film. The window member WM may have a single-layer or multi-layer structure. For example, the window member WM may have a laminated structure of a plurality of plastic films bonded to each other by using an adhesive, or may have a laminated structure of a glass substrate and a plastic film bonded to each other by using an adhesive.

[0068] The window member WM may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area through which incident light is transmitted. The transmission area TA may have a shape corresponding to the shape of the active area AA. For example, the transmission area TA overlaps the entire surface of at least a portion of the active area AA. The image IM displayed in the active area AA of the electronic panel PN may be visible from the outside through the transmission area TA.

[0069] The bezel area BZA may be an area having a light transmittance relatively smaller than that of the transmission area TA. The bezel area BZA defines the shape of the transmission area TA. The bezel area BZA may be disposed adjacent to the transmission area TA to surround the transmission area TA.

[0070] The frame area BZA may have a predetermined color. The frame area BZA may cover the peripheral area NAA of the electronic panel PN to prevent the peripheral area NAA from being visible from the outside. However, this is only an example. For example, in the window member WM according to an embodiment of the inventive concept, the frame area BZA may be omitted.

[0071] The receiving member BM may be coupled to the window member WM. The receiving member BM may be disposed on the rear surface of the electronic device EA. The receiving member BM may be coupled to the window member WM to define an internal space.

[0072] The receiving member BM may include a material having relatively high rigidity. For example, the receiving member BM may include a plurality of frames and / or plates made of glass, plastic, and metal. The receiving member BM may stably protect the components of the electronic device EA received in the internal space from external impacts. Figure 2B The electronic panel PN and various components may be accommodated in the internal space provided by the accommodation member BM.

[0073] Reference Figure 2B , the electronic device EA may include a power module PM, a first electronic module EM1 and a second electronic module EM2. The power module PM supplies power required for all operations of the electronic device EA. The power module PM may include a general battery module.

[0074] The first electronic module EM1 and the second electronic module EM2 may include various functional modules for driving the electronic device EA. The first electronic module EM1 may be directly mounted on a motherboard electrically connected to the electronic panel PN, or may be mounted on a separate board and electrically connected to the motherboard through a connector (not shown).

[0075] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM and an external interface IF. A portion of the module may not be mounted on the motherboard but may be electrically connected to the motherboard through a flexible circuit board.

[0076] The control module CM controls the overall operation of the electronic device EA. The control module CM may be a microprocessor. For example, the control module CM may activate or deactivate the electronic panel PN. The control module CM may control other modules such as the image input module IIM or the audio input module AIM based on a touch signal received from the electronic panel PN.

[0077] The wireless communication module TM can send / receive wireless signals to / from other terminals by using Bluetooth or Wi-Fi lines. The wireless communication module TM can send / receive audio signals by using universal communication lines. The wireless communication module TM includes a transmitter TM1 that modulates and sends the signal to be sent and a receiver TM2 that demodulates the received signal.

[0078] The image input module IIM processes the image signal to convert the processed image signal into image data that can be displayed on the electronic panel PN. The audio input module AIM receives an external audio signal by using a microphone during a recording mode or a voice recognition mode to convert the received audio signal into electrical sound data.

[0079] The external interface IF serves as an interface connected to an external charger, a wired / wireless data port, and a card (eg, a memory card and a SIM / UIM card) slot.

[0080] The second electronic module EM2 may include an audio output module AOM, a light emitting module LM, a light receiving module LRM and a camera module CMM. The above components may be mounted directly on the motherboard, may be mounted on a separate board and electrically connected to the electronic panel PN through a connector (not shown), or may be electrically connected to the first electronic module EM1.

[0081] The audio output module AOM converts audio data received from the wireless communication module TM or audio data stored in the memory MM to output the converted audio data to the outside.

[0082] The light emitting module LM generates and outputs light. The light emitting module LM may output infrared rays. The light emitting module LM may include an LED. The light receiving module LRM may sense infrared rays. When infrared rays having a predetermined level or higher are sensed, the light receiving module LRM may be activated. The light receiving module LRM may include a CMOS sensor. The infrared rays generated in the light emitting module LM may be output and then reflected by an external object (e.g., a user's finger or face), and the reflected infrared rays may be incident into the light receiving module LRM. The camera module CMM captures external images.

[0083] Figure 2A The electronic module EM can receive an external input TC transmitted through the module hole MH, or provide an output through the module hole MH. The electronic module EM can be one of the modules constituting the first electronic module EM1 and the second electronic module EM2. For example, the electronic module EM can be a camera, a speaker, or a sensor that senses light or heat. The electronic module EM can sense the external input TC through the module hole MH, or can provide a sound signal such as voice to the outside through the module hole MH. Here, the remaining components of the first electronic module EM1 and the second electronic module EM2 can be arranged at different positions, so they may not be shown. However, this is only an example. The electronic module EM may include a plurality of modules constituting the first electronic module EM1 and the second electronic module EM2, but is not limited to a specific embodiment. Although not shown, the electronic device EA according to the embodiment of the inventive concept may also include a transparent member disposed between the electronic module EM and the electronic panel PN. The transparent member may be an optically transparent film so that the external input TC transmitted through the module hole MH penetrates the transparent member and is transmitted to the electronic module EM. The transparent member may be attached to the rear surface of the electronic panel PN or disposed between the electronic panel PN and the electronic module EM, and there is no adhesive layer. The electronic device EA according to the inventive concept may have various shapes, but is not limited to a specific embodiment.

[0084] In the inventive concept, the electronic panel PN may include a module hole MH. Therefore, a separate space outside the peripheral area NAA in which the electronic module EM is disposed may be omitted. In addition, the module hole MH may be defined in a hole area HA surrounded by the active area AA, so that the electronic module EM is disposed to overlap with the transmission area TA but not with the border area BZA. Therefore, the area of ​​the border area BZA may be reduced to realize an electronic device EA with a narrow border. In addition, when the electronic module EM is accommodated in the module hole MH, a compact electronic device EA may be realized.

[0085] Figure 3A is along Figure 2A A cross-sectional view taken along line II'. Figure 3B It is shown Figure 3ASchematic equivalent circuit diagram of a part of the components. In the following, reference will be made to Figure 3A and Figure 3B To describe the present disclosure.

[0086] The electronic panel PN may include a base substrate BSS, a circuit layer DP-C, a display device layer DP-D, an encapsulation layer DP-E, and an input sensing unit ISU. The circuit layer DP-C and the display device layer DP-D may include components of the pixel PX.

[0087] The pixel PX may be provided in the active area AA. The pixel PX may generate light to realize the above-mentioned image IM. The pixel PX may be provided in plurality and arranged in the active area AA.

[0088] Reference Figure 3B , the pixel PX can be connected to a plurality of signal lines. In the present embodiment, the gate line GL, the data line DL and the power line VDD in the signal line are shown as examples. However, this is only an example. For example, the pixel PX according to the embodiment of the inventive concept can be additionally connected to various signal lines, but the inventive concept is not limited to a specific embodiment.

[0089] The pixel PX may include a first thin film transistor TR1, a capacitor CAP, a second thin film transistor TR2, and a light emitting device OD. The first thin film transistor TR1 may be a switching device that controls on / off of the pixel PX. The first thin film transistor TR1 may transmit or block a data signal transmitted through the data line DL in response to a gate signal transmitted through the gate line GL.

[0090] The capacitor CAP is connected to the first thin film transistor TR1 and the power line VDD. The capacitor CAP charges an amount of electric charge corresponding to a difference between a data signal received from the first thin film transistor TR1 and a first power supply voltage applied to the power line VDD.

[0091] The second thin film transistor TR2 is connected to the first thin film transistor TR1, the capacitor CAP and the light emitting device OD. The second thin film transistor TR2 controls the driving current flowing through the light emitting device OD to correspond to the amount of charge stored in the capacitor CAP. The on-time of the second thin film transistor TR2 can be determined according to the amount of charge charged in the capacitor CAP. The second thin film transistor TR2 provides the first power supply voltage transmitted through the power line VDD to the light emitting device OD during the on-time.

[0092] The light emitting device OD connects the second thin film transistor TR2 to the power terminal VSS. The light emitting device OD emits light corresponding to the voltage difference between the signal transmitted through the second thin film transistor TR2 and the second power supply voltage received through the power terminal VSS. The light emitting device OD may emit light during the on time of the second thin film transistor TR2.

[0093] The light emitting device OD includes a light emitting material. The light emitting device OD may generate light having a color corresponding to the light emitting material. The color of the light generated in the light emitting device OD may have one of red, green, blue, and white.

[0094] Figure 3A FIG. 2 shows an example of a thin film transistor TR-P (hereinafter, referred to as a pixel transistor) and a light emitting device OD in components of a pixel PX. The pixel transistor TR-P may be connected to Figure 3B corresponds to the second thin film transistor TR2.

[0095] The pixel transistor TR-P and the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30 among the plurality of insulating layers may constitute a circuit layer DP-C. Each of the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30 may include an organic material and / or an inorganic material and have a single-layer or multi-layer structure. The circuit layer DP-C is disposed on the base substrate BSS.

[0096] The base substrate BSS includes a base layer BS and an auxiliary layer BL. The base layer BS may be an insulating base. The base layer BS may be provided in a flexible state. For example, the base layer BS may include polyimide (PI). Alternatively, the base layer BS may be provided in a rigid state. For example, the base layer BS may be made of various materials such as glass, plastic, etc., but is not limited to a specific embodiment.

[0097] The auxiliary layer BL is disposed on the base layer BS. The auxiliary layer BL may be directly disposed on the base layer BS to cover the front surface of the base layer BS. Therefore, the front surface of the auxiliary layer BL may be disposed as the front surface of the base substrate BSS, and the rear surface of the base layer BS may be disposed as the rear surface of the base substrate BSS.

[0098] The auxiliary layer BL includes an inorganic material. The auxiliary layer BL may include a barrier layer and / or a buffer layer. Therefore, the auxiliary layer BL may prevent oxygen or moisture introduced through the base layer BS from penetrating into the circuit layer DP-C or the display device layer DP-D, or may reduce the surface energy of the base substrate BSS, so that the circuit layer DP-C is stably formed on the base substrate BSS.

[0099] In the base substrate BSS, at least one of the base layer BS and the auxiliary layer BL may be provided in plural and alternately stacked. Alternatively, at least one of the barrier layer and the buffer layer constituting the auxiliary layer BL may be provided in plural or may be omitted. However, this is only an example. For example, the base substrate BSS according to an embodiment of the inventive concept may be implemented according to various configurations, but the inventive concept is not limited to a specific embodiment.

[0100] The pixel transistor TR-P includes a semiconductor pattern SP, a control electrode CE, an input electrode IE, and an output electrode OE. The semiconductor pattern SP is disposed on a base substrate BSS. The semiconductor pattern SP may include a semiconductor material. The control electrode CE is separated from the semiconductor pattern SP, and a first insulating layer 10 is located between the control electrode CE and the semiconductor pattern SP. The control electrode CE may be connected to one electrode of each of the above-mentioned first thin film transistor TR1 and the capacitor CAP.

[0101] The input electrode IE and the output electrode OE may be separated from the control electrode CE, and the second insulating layer 20 is located between the input electrode IE and the output electrode OE and the control electrode CE. The input electrode IE and the output electrode OE of the pixel transistor TR-P may be connected to one side and the other side of the semiconductor pattern SP by penetrating the first insulating layer 10 and the second insulating layer 20, respectively.

[0102] The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the input electrode IE and the output electrode OE. In the pixel transistor TR-P, the semiconductor pattern SP may be disposed on the control electrode CE. Alternatively, the semiconductor pattern SP may be disposed on the input electrode IE and the output electrode OE. Alternatively, the input electrode IE and the output electrode OE may be disposed on the same layer and directly connected to the semiconductor pattern SP. The pixel transistor TR-P according to an embodiment of the inventive concept may have various structures, but the inventive concept is not limited to a specific embodiment.

[0103] The light emitting device OD is disposed on the circuit layer DP-C. The light emitting device OD may constitute the display device layer DP-D together with the fourth insulating layer 40 among the plurality of insulating layers. The light emitting device OD includes a first electrode E1, a light emitting pattern EP, a control layer EL, and a second electrode E2. The fourth insulating layer 40 may include an organic material and / or an inorganic material and have a single-layer or multi-layer structure.

[0104] The first electrode E1 may be connected to the pixel transistor TR-P by penetrating the third insulating layer 30. Although not shown, the electronic panel PN may further include a separate connection electrode disposed between the first electrode E1 and the pixel transistor TR-P. Here, the first electrode E1 may be electrically connected to the pixel transistor TR-P through the connection electrode.

[0105] The fourth insulating layer 40 is disposed on the third insulating layer 30. An opening may be defined in the fourth insulating layer 40. The opening may expose at least a portion of the first electrode E1. The fourth insulating layer 40 may be a pixel defining layer.

[0106] The light emitting pattern EP may be disposed in the opening and on the first electrode E1 exposed by the opening. The light emitting pattern EP may include a light emitting material. For example, the light emitting pattern EP may be made of at least one of materials emitting red, green, and blue light, and include a fluorescent material or a phosphorescent material. The light emitting pattern EP may include an organic light emitting material and an inorganic light emitting material. The light emitting pattern EP may emit light in response to a potential difference between the first electrode E1 and the second electrode E2.

[0107] The control layer EL is disposed between the first electrode E1 and the second electrode E2. The control layer EL is disposed adjacent to the light emitting pattern EP. The control layer EL controls the movement of charges to improve the light emitting efficiency and life of the light emitting device OD. The control layer EL may include at least one of a hole transport material, a hole injection material, an electron transport material, and an electron injection material.

[0108] In the present embodiment, the control layer EL may be disposed between the light emitting pattern EP and the second electrode E2. However, this is only an example. For example, the control layer EL may be disposed between the light emitting pattern EP and the first electrode E1, or may be disposed as a plurality of layers stacked in the third direction DR3 with the light emitting pattern EP located between the plurality of layers.

[0109] The control layer EL may have an integral shape extending from the active area AA to the peripheral area NAA. The control layer EL may be provided in common for a plurality of pixels PX.

[0110] The second electrode E2 is disposed on the light emitting pattern EP. The second electrode E2 may face the first electrode E1. The second electrode E2 may have an integral shape extending from the active area AA to the peripheral area NAA. The second electrode E2 may be commonly disposed for a plurality of pixels PX. The light emitting device OD disposed for each pixel PX may receive a common power supply voltage (hereinafter, referred to as a second power supply voltage) through the second electrode E2.

[0111] The second electrode E2 may include a transmissive conductive material or a transflective conductive material. Therefore, the light generated in the light emitting pattern EP may be easily emitted in the third direction DR3 through the second electrode E2. However, this is only an example. For example, the light emitting device OD including a transmissive or semi-transmissive material according to an embodiment of the inventive concept may be driven in a bottom emission mode, or may be driven in a double-side emission mode in which light is emitted from all front and rear surfaces, but the inventive concept is not limited to a specific embodiment.

[0112] The encapsulation layer DP-E may be disposed on the light emitting device OD to encapsulate the light emitting device OD. The encapsulation layer DP-E may have an integral shape extending from the active area AA to the peripheral area NAA. The encapsulation layer DP-E may be provided in common for a plurality of pixels PX. Although not shown, a cap layer covering the second electrode E2 may be further provided between the second electrode E2 and the encapsulation layer DP-E.

[0113] The encapsulation layer DP-E may include a first inorganic layer IOL1, an organic layer OL, and a second inorganic layer IOL2 sequentially stacked in the third direction DR3. However, the inventive concept is not limited thereto. For example, the encapsulation layer DP-E may also include a plurality of inorganic layers and organic layers.

[0114] The first inorganic layer IOL1 may cover the second electrode E2. The first inorganic layer IOL1 may prevent external moisture or oxygen from penetrating into the light emitting device OD. For example, the first inorganic layer IOL1 may include silicon nitride, silicon oxide, or a combination thereof. The first inorganic layer IOL1 may be formed by a deposition process.

[0115] The organic layer OL may be disposed on the first inorganic layer IOL1 to contact the first inorganic layer IOL1. The organic layer OL may provide a flat surface on the first inorganic layer IOL1. The organic layer OL may cover a curvature formed on the top surface of the first inorganic layer IOL1 or particles existing on the first inorganic layer IOL1 to prevent the surface state of the top surface of the first inorganic layer IOL1 from affecting the components disposed on the organic layer OL. In addition, the organic layer OL may reduce stress between layers contacting each other. The organic layer OL may include an organic material and may be formed by a solution process such as spin coating, slit coating, an inkjet process, and the like.

[0116] The second inorganic layer IOL2 may be disposed on the organic layer OL to cover the organic layer OL. When compared with the second inorganic layer IOL2 disposed on the first inorganic layer IOL1, the second inorganic layer IOL2 may be relatively stably formed on a flat surface. The second inorganic layer IOL2 may encapsulate moisture discharged from the organic layer OL to prevent moisture from being introduced. The second inorganic layer IOL2 may include silicon nitride, silicon oxide, or a combination thereof. The second inorganic layer IOL2 may be formed by a deposition process.

[0117] The input sensing unit ISU may include a first conductive layer MTL1 and a second conductive layer MTL2. The first conductive layer MTL1 may be disposed under the encapsulation layer DP-E. Specifically, the first conductive layer MTL1 is disposed between the fourth insulating layer 40 and the control layer EL.

[0118] The first conductive layer MTL1 may include a conductive material. For example, the first conductive layer MTL1 may include at least one of a metal, a transparent conductive oxide, and a conductive polymer.

[0119] The first conductive layer MTL1 includes a plurality of first conductive patterns MP1. The first conductive patterns MP1 may be disposed to be separated from the light emitting patterns EP. The first conductive patterns MP1 may not overlap with the light emitting patterns EP on a plane. The first conductive patterns MP1 may be disposed on the fourth insulating layer 40 and may be covered by the control layer EL.

[0120] The second conductive layer MTL2 is disposed on the encapsulation layer DP-E. In the present embodiment, the second conductive layer MTL2 may be directly disposed on the top surface of the second inorganic layer IOL2. However, this is only an example. For example, a separate insulating layer such as a buffer layer may be further disposed between the second conductive layer MTL2 and the second inorganic layer IOL2.

[0121] The second conductive layer MTL2 may include a conductive material. For example, the second conductive layer MTL2 may include at least one of a metal, a transparent conductive oxide, and a conductive polymer.

[0122] The second conductive layer MTL2 includes a plurality of second conductive patterns MP2. The second conductive patterns MP2 may be disposed to be spaced apart from the light emitting patterns EP on a plane. The second conductive patterns MP2 may not overlap with the light emitting patterns EP on a plane.

[0123] In the present embodiment, a portion of the second conductive pattern MP2 may be electrically connected to the first conductive pattern MP1 through a contact hole CH penetrating the encapsulation layer DP-E. Specifically, the contact hole CH may penetrate the encapsulation layer DP-E, the second electrode E2, and the control layer EL to extend to the top surface of each first conductive pattern MP1. At least a portion of the second conductive pattern MP2 may be connected to each first conductive pattern MP1 corresponding to the second conductive pattern MP2 through the contact hole CH.

[0124] Each first conductive pattern MP1 may be used as a bridge electrode. Here, the parts of the second conductive patterns MP2 separated from each other may be electrically connected to each other through the first conductive patterns MP1. Alternatively, each first conductive pattern MP1 may be used as a sensor electrode. Here, the second conductive patterns MP2 and the first conductive patterns MP1 may be connected to each other to increase the area of ​​the sensor electrode, thereby improving the external input sensing sensitivity.

[0125] This is only an example. For example, the first conductive pattern MP1 and the second conductive pattern MP2 may be electrically insulated from each other. Here, the first conductive pattern MP1 and the second conductive pattern MP2 may be used as sensor electrodes that receive different electrical signals from each other. The input sensing unit ISU may sense the external input TC through a change in capacitance generated between the first conductive pattern MP1 and the second conductive pattern MP2. In the input sensing unit ISU according to the inventive concept, the connection between the first conductive pattern MP1 and the second conductive pattern MP2 may be implemented differently depending on the functions of the first conductive pattern MP1 and the second conductive pattern MP2. This will be described in more detail below.

[0126] An inner insulating layer IP covering the side surface of the contact hole CH may be disposed in the contact hole CH. The inner insulating layer IP may prevent the second inorganic layer IOL2, the organic layer OL, the first inorganic layer IOL1, the second electrode E2, and the control layer EL exposed to the side surface of the contact hole CH from contacting the second conductive pattern MP2. Therefore, electrical connection between other conductive materials (e.g., between the second electrode E2 and the second conductive pattern MP2) other than the electrical connection between the second conductive pattern MP2 and the first conductive pattern MP1 may be prevented from occurring.

[0127] In the present disclosure, the input sensing unit ISU may include a first conductive layer MTL1 and a second conductive layer MTL2, the first conductive layer MTL1 and the second conductive layer MTL2 are separated from each other and the encapsulation layer DP-E is located between the first conductive layer MTL1 and the second conductive layer MTL2. In addition, the first conductive layer MTL1 and the second conductive layer MTL2 may be provided to be separated from each other, and the second electrode E2 of the light emitting device OD as a component of the display unit DPU is located between the first conductive layer MTL1 and the second conductive layer MTL2.

[0128] That is, according to the inventive concept, a component of the input sensing unit ISU can be set between components of the display unit DPU. Therefore, in the electronic panel PN including the input sensing unit ISU and the display unit DPU, the process can be simplified and the process cost can be reduced. This will be described in detail later.

[0129] The electronic panel PN according to an embodiment of the inventive concept may further include a thin film transistor (hereinafter, referred to as a driving transistor) TR-D disposed in the peripheral area NAA, a plurality of signal patterns E-VSS, E-CNT, VIN, and CL, and a plurality of dam portions DM1 and DM2. The driving transistor TR-D and the signal patterns E-VSS, VIN, and CL may constitute a circuit layer DP-C.

[0130] A driving transistor TR-D having a structure corresponding to the pixel transistor TR-P is shown as an example. For example, the driving transistor TR-D may include a semiconductor pattern SP disposed on a base substrate BSS, a control electrode CE disposed on a first insulating layer 10, an input electrode IE disposed on a second insulating layer 20, and an output electrode OE. Therefore, the pixel transistor TR-P and the driving transistor TR-D can be formed simultaneously by the same process, so the process can be simplified and the process cost can be reduced. However, this is only an example. For example, the driving transistor TR-D according to an embodiment of the inventive concept may have a structure different from that of the pixel transistor TR-P, but is not limited to a specific embodiment.

[0131] The signal patterns E-VSS, E-CNT, VIN, and CL may include a power line E-VSS, a connection electrode E-CNT, an initialization voltage line VIN, and a drive signal line CL. The power line E-VSS may correspond to the power terminal VSS of the pixel PX. Therefore, the power line E-VSS supplies the second power supply voltage to the light emitting device OD. In the present embodiment, the second power supply voltage supplied to the pixel PX may be a common voltage with respect to all pixels PX.

[0132] The power line E-VSS may be disposed on the second insulating layer 20 to constitute the circuit layer DP-C. The power line E-VSS may be formed by the same process as the input electrode IE or the output electrode OE of the driving transistor TR-D. However, this is only an example. For example, the power line E-VSS may be disposed on a layer different from the layer of the input electrode IE and the output electrode OE of the driving transistor TR-D, and thus may be formed by a separate process, but the inventive concept is not limited to a specific embodiment.

[0133] The connection electrode E-CNT may be disposed on the third insulating layer 30 to constitute the display device layer DP-D. The connection electrode E-CNT is electrically connected to the power supply line E-VSS. The connection electrode E-CNT may extend from the top surface of the third insulating layer 30 to cover the top surface of the power supply line E-VSS exposed from the third insulating layer 30.

[0134] The second electrode E2 of the light emitting device OD extends from the active area AA and is connected to the connection electrode E-CNT. The connection electrode E-CNT can receive a second power supply voltage from the power supply line E-VSS. Therefore, the second power supply voltage can be transmitted to the second electrode E2 through the connection electrode E-CNT and provided to each pixel PX.

[0135] The connection electrode E-CNT may be disposed on the same layer as the first electrode E1 of the light emitting device OD, and thus may be formed simultaneously with the first electrode E1. However, this is only an example. For example, the connection electrode E-CNT and the first electrode E1 may be disposed on different layers from each other.

[0136] The driving signal line CL may be provided in a plurality and disposed on the second insulating layer 20. The driving signal line CL may be provided in the peripheral area NAA. The driving signal line CL may be a routing line connected to a pad (also referred to as a "pad" or "pad") (not shown) or a line constituting an integrated circuit (IC). The driving signal lines CL may be provided to be separated from each other in the second direction DR2 to independently transmit electrical signals.

[0137] An initialization voltage line VIN may be provided in the active area AA to supply an initialization voltage to the pixel PX. Although not shown, the initialization voltage line VIN may be provided in plurality to supply an initialization voltage to each pixel PX.

[0138] The drive signal line CL and the initialization voltage line VIN may be disposed on the same layer and formed simultaneously by the same process. However, this is only an example. For example, the drive signal line CL and the initialization voltage line VIN may be independently formed by separate processes, but are not limited to a specific embodiment.

[0139] The dams DM1 and DM2 are disposed in the peripheral area NAA. When the organic layer OL of the encapsulation layer DP-E is formed, the dams DM1 and DM2 may prevent the organic layer OL (eg, Figure 3A The dams DM1 and DM2 may be provided so as to overflow from the active area AA to the outside of the dams DM1 and DM2 in the second direction DR2. The dams DM1 and DM2 may be provided adjacent to at least one side of the active area AA. The dams DM1 and DM2 may surround the active area AA on a plane. The dams DM1 and DM2 may be provided in plurality and include a first dam DM1 and a second dam DM2.

[0140] The first dam DM1 may be disposed relatively closer to the active area AA than the second dam DM2. The first dam DM1 may be disposed to overlap the power line E-VSS in a plane. In this embodiment, the connection electrode E-CNT may pass between the first dam DM1 and the power line E-VSS in a cross section.

[0141] In this embodiment, the first dam DM1 may be made of the same material as the fourth insulating layer 40, and the first dam DM1 and the fourth insulating layer 40 may be formed simultaneously through one mask. Therefore, a separate process for forming the first dam DM1 may not be required, thereby reducing process cost and simplifying the process.

[0142] The second dam portion DM2 may be disposed at an outer portion relative to the first dam portion DM1. The second dam portion DM2 may be disposed at a position where a portion of the power line E-VSS is covered. In the present embodiment, the second dam portion DM2 may have a multilayer structure including a first layer DM2-L1 and a second layer DM2-L2. For example, the first layer DM2-L1 and the third insulating layer 30 may be formed simultaneously, and the second layer DM2-L2 and the fourth insulating layer 40 may be formed simultaneously. Therefore, the second dam portion DM2 may be easily formed even without performing a separate process.

[0143] In the present embodiment, the connection electrode E-CNT may be disposed to partially overlap the first layer DM2-L1 of the second dam portion DM2. The connection electrode E-CNT may have an end portion interposed between the first layer DM2-L1 and the second layer DM2-L2. However, this is only an example. For example, the connection electrode E-CNT may not extend to the second dam portion DM2, but the inventive concept is not limited to a specific embodiment.

[0144] The first inorganic layer IOL1 and the second inorganic layer IOL2 may extend from the active area AA to the outside of the second dam DM2. The first inorganic layer IOL1 and the second inorganic layer IOL2 may cover the first dam DM1 and the second dam DM2. The organic layer OL may be disposed within the first dam DM1. However, this is only an example. For example, a portion of the organic layer OL may extend to a region overlapping the first dam DM1, but the inventive concept is not limited to a specific embodiment.

[0145] Figure 4A is along Figure 2A A cross-sectional view taken along line II-II'. Figure 4B and Figure 4C It is shown Figure 2A Floor plan of area XX'. Figure 4A It can basically correspond to the cross-sectional view of region XX'. Figure 4B and Figure 4C In FIG. 1 , a part of the components of the electronic panel PN is briefly shown. Specifically, Figure 4A shows a pixel PX, Figure 4B and Figure 4C The input sensing unit ISU (see Figure 3A ). In the following, reference will be made to FIG. 4A to FIG. 4C To describe the present disclosure.

[0146] The hole area HA may be surrounded by the active area AA in a plane. Figure 4B and Figure 4C , for ease of description, the hole area HA is indicated by a dotted line. The pixel PX may be disposed to be spaced apart from the module hole MH, and a portion of the pixel PX disposed adjacent to the hole area HA may be disposed along an edge of the hole area HA.

[0147] Reference Figure 4A , the module hole MH is defined in the hole area HA. ​​The module hole MH may be defined in the center of the hole area HA. ​​The module hole MH may be a through hole to penetrate the electronic panel PN. The module hole MH penetrates the front surface and the rear surface of the base substrate BSS. Specifically, the module hole MH penetrates the component disposed in the hole area HA on the layer disposed on the front surface of the base substrate BSS. Therefore, the first insulating layer 10, the second insulating layer 20, the control layer EL, the second electrode E2, the first inorganic layer IOL1, and the second inorganic layer IOL2 extending to the hole area HA may be penetrated to define the side surface BS-H of the module hole MH.

[0148] The electronic panel PN according to the present embodiment may further include a recessed pattern GV defined in the hole area HA. ​​The recessed pattern GV may be defined along the edge of the module hole MH. In the present embodiment, the recessed pattern GV is shown as a closed line surrounding the module hole MH and has a circular shape similar to the shape of the module hole MH. However, this is only an example. For example, the recessed pattern GV may have a shape different from the shape of the module hole MH, may have a closed line shape including a polygonal shape, an elliptical shape, or at least a partially circular shape, or may be set to a shape including a plurality of partially cut patterns, but the inventive concept is not limited to a specific embodiment.

[0149] The recessed pattern GV may be a pattern recessed from the front surface of the electronic panel PN. A portion of the components of the electronic panel PN may be removed to form the recessed pattern GV. Unlike the module hole MH, the recessed pattern GV may not penetrate the electronic panel PN. Therefore, the rear surface of the substrate BSS overlapped with the recessed pattern GV may not be opened by the recessed pattern GV.

[0150] The recessed pattern GV may be defined to penetrate the remaining components except a portion of the base layer BS. In the present embodiment, the recessed pattern GV may be formed by connecting a penetration portion defined in the auxiliary layer BL to a recessed portion defined in the base layer BS. The inner surface of the recessed pattern GV may be covered by the first inorganic layer IOL1 and the second inorganic layer IOL2.

[0151] The recessed pattern GV may have an undercut shape including a tip portion TP protruding inwardly. The tip portion TP according to the present embodiment may be formed so that a portion of the auxiliary layer BL protrudes further into the inside of the recessed pattern GV than the base layer BS. The electronic panel PN according to an embodiment of the inventive concept may have various layer structures as long as the tip portion TP is disposed on the recessed pattern GV, but the inventive concept is not limited to a specific embodiment.

[0152] The electronic panel PN may further include a predetermined organic pattern EL-P disposed in the recessed pattern GV. The organic pattern EL-P may be made of the same material as that of the control layer EL. Alternatively, the organic pattern EL-P may also include the same material as that of the second electrode E2. The organic pattern EL-P may have a single-layer or multi-layer structure.

[0153] The organic pattern EL-P may be disposed in the recessed pattern GV by being spaced apart from the control layer EL and the second electrode E2. The organic pattern EL-P may be covered by the first inorganic layer IOL1, and thus may not be exposed to the outside.

[0154] According to the inventive concept, the recessed pattern GV cuts off the continuity of the control layer EL connected to the active area AA from the side surface BS-H of the module hole MH. The control layer EL may be disconnected at the area overlapping with the recessed pattern GV. The control layer EL may serve as a moving path for external contaminants such as moisture or air. The layer exposed through the module hole MH (e.g., a path for moisture or air introduced from the control layer EL via the hole area HA to be introduced into the active area AA) may be covered by the recessed pattern GV. Therefore, the reliability of the electronic panel PN in which the module hole MH is defined may be improved.

[0155] In the electronic panel PN according to the embodiment of the inventive concept, the recessed pattern GV may be provided in plurality spaced apart from each other in the second direction DR2, and a portion of the organic layer OL may extend to fill a portion of the recessed pattern GV. In the electronic panel PN according to the embodiment of the inventive concept, the recessed pattern GV may be omitted, but the inventive concept is not limited to a specific embodiment.

[0156] As described above, the pixel PX and the input sensing unit ISU are disposed to be separated from the module hole MH on a plane. Figure 4B and Figure 4C , the module hole MH and the pixel PX and the input sensing unit ISU adjacent to the module hole MH will be described.

[0157] Reference Figure 4B , the pixels PX may be arranged to surround the hole area HA. ​​Parts of the pixels PX may be arranged along the edge of the hole area HA. ​​The pixels PX may be spaced apart from the module hole MH on a plane.

[0158] A plurality of signal lines SL1 and SL2 connected to the pixel PX may be disposed in the hole area HA. ​​The signal lines SL1 and SL2 may be connected to the pixel PX via the hole area HA. Figure 4B , for convenience of description, an example is shown in which a first signal line SL1 and a second signal line SL2 among a plurality of signal lines connected to the pixel PX.

[0159] The first signal line SL1 extends in the first direction DR1. The first signal line SL1 is connected to the pixels PX arranged in the same row in the first direction DR1 among the pixels PX. The first signal line SL1 may be connected to the data line DL (see FIG. Figure 3B )correspond.

[0160] A portion of the pixel PX connected to the first signal line SL1 may be disposed above the module hole MH, and the other portion of the pixel PX may be disposed below the module hole MH. Therefore, even if a portion of the pixel PX relative to the module hole MH is omitted, the pixels PX in the same row connected to the first signal line SL1 may receive a data signal through the same line.

[0161] The second signal line SL2 extends in the second direction DR2. The second signal line SL2 is connected to the pixels PX arranged in the same row in the second direction DR2 among the pixels PX. The second signal line SL2 may be connected to the gate line GL (see FIG. Figure 3B )correspond.

[0162] A portion of the pixel PX connected to the second signal line SL2 may be disposed at the left side of the module hole MH, and the other portion of the pixel PX may be disposed at the right side of the module hole MH. Therefore, even if a portion of the pixel PX relative to the module hole MH is omitted, the pixels PX in the same row connected to the second signal line SL2 may be turned on / off by substantially the same gate signal.

[0163] The electronic panel PN according to an embodiment of the inventive concept may further include a connection pattern disposed in the hole area HA. ​​Here, the first signal line SL1 may be disconnected at an area overlapping the hole area HA. ​​The connection portion of the first signal line SL may be connected by the connection pattern. Similarly, the second signal line SL2 may be disconnected at an area overlapping the hole area HA, and a connection pattern connecting the disconnected portion of the second signal line SL2 may also be provided.

[0164] Reference Figure 4C , the input sensing unit ISU may include a first sensing electrode extending in a first direction DR1 and a second sensing electrode extending in a second direction DR2. The input sensing unit ISU receives position or intensity information of the external input TC through a capacitance change between the first sensing electrode and the second sensing electrode. In this embodiment, the first sensing electrode may include a first sensing pattern S1 and a first bridge pattern B1, and the second sensing electrode may include a second sensing pattern S2 and a second bridge pattern B2.

[0165] The first sensing pattern S1 may be provided in plurality and arranged to be spaced apart from each other. The first sensing pattern S1 may include a plurality of grid lines MSL crossing the first direction DR1 and the second direction DR2. The grid lines MSL may include a first grid line MSL1 extending in one direction and a second grid line MSL2 extending in a direction crossing the first grid line MSL1. The first grid line MSL1 and the second grid line MSL2 may be connected to each other to form the first sensing pattern S1 having a mesh shape.

[0166] The first bridge pattern B1 extends in the first direction DR1. The first bridge pattern B1 may be provided in plurality and arranged to connect two first sensing patterns S1 arranged adjacent to each other in the first direction DR1. The first sensing patterns S1 may be connected to each other by the first bridge pattern B1 as first sensing electrodes extending in the first direction DR1.

[0167] The second sensing pattern S2 is separated from the first sensing pattern S1. The second sensing pattern S2 may be provided in plurality and arranged to be separated from each other. The second sensing pattern S2 may have the same shape as that of the first sensing pattern S1. Specifically, the second sensing pattern S2 may include a plurality of grid lines MSL including a first grid line MSL1 and a second grid line MSL2. The input sensing unit ISU according to an embodiment of the inventive concept may include a first sensing pattern S1 and a second sensing pattern S2 to improve flexibility. However, this is merely an example. For example, the second sensing pattern S2 may have a shape different from that of the first sensing pattern S1, but the inventive concept is not limited to a specific embodiment.

[0168] The second bridge pattern B2 extends in the second direction DR2. The second bridge pattern B2 may be provided in plurality and arranged to connect two second sensing patterns S2 arranged adjacent to each other in the second direction DR2. The second sensing patterns S2 may be connected to each other through the second bridge pattern B2 as second sensing electrodes extending in the second direction DR2.

[0169] In the present embodiment, the first sensing pattern S1, the second sensing pattern S2, and the second bridge pattern B2 may be arranged on the same layer, and the first bridge pattern B1 may be arranged on a different layer. Therefore, the first sensing pattern S1, the second sensing pattern S2, and the second bridge pattern B2 may be formed simultaneously by using the same mask. The first bridge pattern B1 and the second bridge pattern B2 may be arranged on different layers from each other. Therefore, even if the first bridge pattern B1 and the second bridge pattern B2 are arranged to cross each other on a plane, the first bridge pattern B1 and the second bridge pattern B2 may be electrically insulated from each other. The first sensing pattern S1 may be connected to the first bridge pattern B1 through a predetermined contact hole CH-B, and the second sensing pattern S2 may be directly connected to the second bridge pattern B2.

[0170] In the present embodiment, a portion of the first sensing electrode and the second sensing electrode may be disconnected relative to the module hole MH. For example, a portion of the first sensing electrode may be divided into an upper portion and a lower portion relative to the module hole MH. A portion of the first sensing pattern S1 may have a shape in which a portion overlapping the hole area HA is removed. Alternatively, for example, a portion of the second sensing electrode may be divided into a left portion and a right portion relative to the module hole MH. A portion of the second sensing pattern S2 may have a shape in which a portion overlapping the hole area HA is removed.

[0171] In the electronic panel PN according to the embodiment of the inventive concept, the input sensing unit ISU may further include a first bridge wire BL1 and a second bridge wire BL2. The first bridge wire BL1 and the second bridge wire BL2 may electrically connect the sensing electrodes disconnected via the hole area HA to each other. Specifically, the first bridge wire BL1 connects the first sensing electrodes divided into the upper part and the lower part to each other, and the second bridge wire BL2 connects the second sensing electrodes divided into the left part and the right part to each other.

[0172] The first bridge line BL1 and the second bridge line BL2 may be disposed on different layers from each other. In the present embodiment, the first bridge line BL1 may be disposed on the same layer as the first bridge pattern B1, and the second bridge line BL2 may be disposed on the same layer as the second bridge pattern B2. Therefore, the first bridge line BL1 may be connected to the first sensing pattern S1 through a predetermined contact hole CH-B, and the second bridge line BL2 may be directly connected to the second sensing pattern S2. However, this is only an example. For example, the input sensing unit ISU according to an embodiment of the inventive concept may have various structures, but is not limited to a specific embodiment.

[0173] In the present embodiment, the grid line MSL, the first bridge pattern B1, the second bridge pattern B2, the first bridge line BL1, and the second bridge line BL2 may correspond to the conductive patterns MP1 and MP2, respectively. Specifically, each of the first conductive pattern MP1 and the second conductive pattern MP2 may be the first grid line MSL1 or the second grid line MSL2. Alternatively, each of the first conductive pattern MP1 and the second conductive pattern MP2 may be the first bridge line BL1 or the second bridge line BL2.

[0174] In the electronic panel PN according to the inventive concept, the pixels PX or the sensing patterns S1 and S2 separated from each other with respect to the module hole MH can be connected to each other through the signal lines SL1 and SL2 or the bridge lines BL1 and BL2 to maintain the organic combination between the pixels PX separated from each other with respect to the module hole MH or between the sensing patterns S1 and S2, thereby facilitating the electrical control of the pixels PX. Therefore, even if the module hole MH is defined in the area surrounded by the active area AA, the electronic panel PN in which the active area AA is stably driven can be provided.

[0175] Figure 5A is a plan view illustrating a portion of an area of ​​an electronic panel according to an embodiment of the inventive concept. Figure 5B is a cross-sectional view illustrating a portion of a region of an electronic panel according to an embodiment of the inventive concept. Figure 5A 1 shows a plan view of the electronic panel PN when viewed from the front side. In addition, for ease of description, the Figure 5A and Figure 5B part of the component.

[0176] like Figure 5A and Figure 5B As shown in FIG. 1 , a second conductive layer MTL2 disposed on the uppermost layer on the front surface of the electronic panel PN is shown. The first sensing patterns S1 and the second sensing patterns S2 separated from each other include the second conductive layer MTL2 and the first conductive layer MTL1. Each of the first sensing patterns S1 and the second sensing patterns S2 may include a first mesh pattern MS1 ​​and a second mesh pattern MS2. The first mesh pattern MS1 ​​and the second mesh pattern MS2 may correspond to the second conductive pattern MP2.

[0177] The first and second mesh patterns MS1 and MS2 may be spaced apart from the light emitting patterns EP1 , EP2 , and EP3 on a plane. Figure 5B The light emitting pattern EP may be one of the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3. That is, the second conductive pattern MP2 may not overlap with the light emitting patterns EP1, EP2, and EP3 on a plane.

[0178] According to the inventive concept, even if the second conductive layer MTL2 is optically opaque, the second conductive layer MTL2 can be prevented from affecting the display characteristics of the light emitting patterns EP1, EP2, and EP3. However, this is only an example. For example, the second conductive layer MTL2 may overlap a portion of the light emitting patterns EP1, EP2, and EP3, and may be configured to be optically opaque and to overlap the light emitting patterns EP1, EP2, and EP3, but is not limited to a specific embodiment.

[0179] The input sensing unit ISU according to an embodiment of the inventive concept may further include a dummy pattern DP. The dummy pattern DP may be disposed in a separate space between the first sensing pattern S1 and the second sensing pattern S2. The dummy pattern DP may prevent a boundary between the first sensing pattern S1 and the second sensing pattern S2 from being easily visible and deteriorating visibility of the input sensing unit ISU.

[0180] exist Figure 5A , a plurality of light emitting patterns EP1, EP2, and EP3 are shown by dotted lines. The light emitting patterns EP1, EP2, and EP3 include a first light emitting pattern EP1, a second light emitting pattern EP2, and a third light emitting pattern EP3. The lights emitted from the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 may have different colors from each other. The first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 may have different shapes from each other on a plane. However, this is merely an example. For example, the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 may have the same shape, and the lights emitted from the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 may have the same color, but the inventive concept is not limited to a specific embodiment.

[0181] Reference Figure 5A and Figure 5B , each of the first sensing pattern S1 and the second sensing pattern S2 may have a basic double-layer structure including a first conductive layer MTL1 and a second conductive layer MTL2. Therefore, the first conductive layer MTL1 and the second conductive layer MTL2 constituting the first sensing pattern S1 and the first conductive layer MTL1 and the second conductive layer MTL2 constituting the second sensing pattern S2 may have the same shape.

[0182] The first conductive pattern MP1 may be disposed to be spaced apart from the opening OP in which the light emitting pattern EP is disposed of the fourth insulating layer 40. The first and second conductive layers MTL1 and MTL2 constituting the first sensing pattern S1 and the first and second conductive layers MTL1 and MTL2 constituting the second sensing pattern S2 may be electrically connected to each other through the contact hole CH penetrating the encapsulation layer DP-E.

[0183] In this embodiment, the second electrode E2 may overlap the first sensing pattern S1, the second sensing pattern S2, and the light emitting pattern EP on a plane. Therefore, the contact hole CH may also penetrate the second electrode E2. The inner insulating layer IP may cover the side surface of the contact hole CH to block the electrical connection between the second electrode E2 and the input sensing unit ISU.

[0184] According to the inventive concept, the input sensing unit ISU may include first and second sensing patterns S1 and S2 each including first and second conductive layers MTL1 and MTL2. Therefore, the first and second conductive patterns MP1 and MP2 may be connected to each other through contact holes CH penetrating the encapsulation layer DP-E and the second electrode E2.

[0185] The input sensing unit ISU according to an embodiment of the inventive concept may include a display unit DPU (see Figure 2B ) and a first conductive layer MTL1 and a second conductive layer MTL2 separated from each other and with the encapsulation layer DP-E located therebetween. According to the inventive concept, a portion of the components of the input sensing unit ISU may be disposed between the components of the display unit DPU to reduce the thickness of the electronic panel PN and improve the integration of the electronic panel PN in a cross-section.

[0186] Fig. 6A is a plan view illustrating a portion of an area of ​​an electronic panel according to an embodiment of the inventive concept. Figure 6B is a cross-sectional view illustrating a portion of a region of an electronic panel according to an embodiment of the inventive concept. Fig. 6A Shown with Figure 5A The corresponding area, Figure 6B Shown with Figure 5B In the following, reference will be made to Fig. 6A and Figure 6B To describe the present disclosure. Figures 1 to 5B The same components are given the same reference numerals, and their detailed description will be omitted.

[0187] In the electronic panel PN according to an embodiment of the inventive concept, the first sensing pattern S11 and the second sensing pattern S21 may be disposed on different layers from each other. For ease of description, Fig. 6A A state in which shadows of the first sensing pattern S11 and the second sensing pattern S21 disposed on different layers are differently displayed is shown.

[0188] like Figure 6B As shown in , the first sensing pattern S11 may include a first conductive layer MTL11. The first conductive layer MTL11 includes a plurality of first conductive patterns MP11. The first conductive pattern MP11 is disposed between the fourth insulating layer 40 and the control layer EL. The second sensing pattern S21 may include a second conductive layer MTL21. The second conductive layer MTL21 includes a plurality of second conductive patterns MP21. The second conductive pattern MP21 is disposed on the encapsulation layer DP-E.

[0189] In the input sensing unit ISU according to the present embodiment, the first sensing pattern S11 and the second sensing pattern S21 may be respectively provided as conductive layers MTL11 and MTL21 separated from each other with the encapsulation layer DP-E therebetween. Therefore, the contact hole CH penetrating the encapsulation layer DP-E may be omitted (see FIG. Figure 5B ).

[0190] In this embodiment, a second electrode may be provided for each light emitting pattern, and the second electrode includes a plurality of patterns separated from each other. For ease of description, a first pattern E21, a second pattern E22, and a third pattern E23 are shown. The first pattern E21, the second pattern E22, and the third pattern E23 may be provided to overlap with the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3, respectively.

[0191] Figure 6B A light emitting device OD1 including a first pattern E21 is shown. The first pattern E21 may be connected to the penetration control layer EL and the fourth insulating layer 40 and is disposed to be separated from the first electrode E1 by an auxiliary electrode AE. The first pattern E21 may receive an electrical signal opposite to that of the first electrode E1 through the auxiliary electrode AE. The auxiliary electrode AE ​​may extend between the light emitting patterns EP1, EP2, and EP3, and may also be connected to the second pattern E22 and the third pattern E23. Therefore, the first pattern E21, the second pattern E22, and the third pattern E23 separated from each other may be connected to one auxiliary electrode AE ​​to receive substantially the same electrical signal.

[0192] According to the inventive concept, a first conductive layer MTL11 and a second conductive layer MTL21 disposed on different layers and having an encapsulation layer DP-E therebetween can be provided respectively by a first sensing pattern S11 and a second sensing pattern S21 to reduce the thickness of the electronic panel PN and improve the integration of the electronic panel PN. In addition, a second electrode can be provided by a plurality of patterns E21, E22, and E23 to reduce the influence of the second electrode on the capacitance between the first sensing pattern S11 and the second sensing pattern S21. Therefore, an electronic panel PN having sufficient sensing sensitivity with respect to an external input TC can be provided.

[0193] Fig. 7A and Figure 7B is a cross-sectional view of an electronic panel according to an embodiment of the inventive concept. For ease of description, Fig. 7A and Figure 7B Shown with Figure 6B In the following, reference will be made to Fig. 7A and Figure 7B To describe the present disclosure. Figures 1 to 6B The same components are given the same reference numerals, and their detailed description will be omitted.

[0194] like Fig. 7A As shown in FIG. 1 , the first sensing pattern S12 includes a first conductive layer MTL12, and the second sensing pattern S22 includes a second conductive layer MTL22. The second conductive layer MTL22 includes a plurality of second conductive patterns MP22 disposed on the encapsulation layer DP-E. Figure 6B The second conductive patterns MP21 correspond to those of FIG. 1 , and thus their repeated description will be omitted.

[0195] The first conductive layer MTL12 may include a plurality of first conductive patterns MP12 and a plurality of insulating patterns IL. The insulating patterns IL may be disposed on the first conductive patterns MP12. The insulating patterns IL may contact the first conductive patterns MP12, and the insulating patterns IL may cover the top surfaces of the first conductive patterns MP12, respectively. The insulating patterns IL may improve electrical insulation between components adjacent to the first conductive patterns MP12 (e.g., the second electrodes E2).

[0196] Alternatively, if Figure 7B As shown in FIG. 1 , the first sensing pattern S13 includes a first conductive layer MTL13, and the second sensing pattern S23 includes a second conductive layer MTL23. The second conductive layer MTL23 includes a plurality of second conductive patterns MP23 disposed on the encapsulation layer DP-E. Figure 6B The second conductive patterns MP21 correspond to those of FIG. 1 , and thus their repeated description will be omitted.

[0197] The first conductive layer MTL13 may include a plurality of first conductive patterns MP13 and a plurality of insulating patterns IL1. The insulating patterns IL1 may be disposed on the first conductive patterns MP13. The insulating patterns IL1 may contact the first conductive patterns MP13, and the insulating patterns IL1 may cover top surfaces and side surfaces of the first conductive patterns MP13, respectively.

[0198] According to the inventive concept, the electronic panel PN may further include insulating patterns IL and IL1 covering the first conductive patterns MP12 and MP13 respectively to prevent short circuits between the second electrode E2 and the first conductive layers MTL12 and MTL13 and defects of parasitic capacitance. Therefore, the electrical characteristics and reliability of the electronic panel PN may be improved.

[0199] FIG. 8A to FIG. 8M is a cross-sectional view illustrating a process of manufacturing an electronic panel according to an embodiment of the inventive concept. FIG. 9A to FIG. 9E is a cross-sectional view illustrating a process of manufacturing an electronic panel according to an embodiment of the inventive concept. FIG. 8A to FIG. 8M The diagram shows the manufacturing Figure 4A A cross-sectional view of the process in the area of FIG. 9A to FIG. 9E Shown with Figure 8MA cross-sectional view of the region corresponding to region YY'. FIG. 8A to FIG. 9E To describe the present disclosure. Figures 1 to 7B The same components are given the same reference numerals, and their detailed description will be omitted.

[0200] like Fig. 8A As shown in , a pixel transistor TR-P, a plurality of insulating layers 10, 20, 30 and 40, and a first electrode E1 are formed on a base substrate BSS. An auxiliary layer BL may be formed by depositing or applying an inorganic material on the base layer BS to provide the base substrate BSS. The pixel transistor TR-P may be formed by a general thin film transistor manufacturing process including a deposition or patterning process, but is not limited to a specific embodiment. The first electrode E1 may be formed after forming a through hole in the third insulating layer 30 to expose the output electrode OE. Here, the area corresponding to the hole area HA may be removed. Thereafter, an insulating material may be deposited or applied to form a fourth insulating layer 40. Here, the fourth insulating layer 40 may overlap the entire hole area HA and the active area AA.

[0201] Afterwards, if Figure 8B As shown in , the fourth insulating layer 40 may be patterned to form an opening OP that exposes a portion of the first electrode E1. A light emitting pattern to be formed later may be formed in the opening OP. Therefore, the opening OP may correspond to the light emitting region. Here, the region corresponding to the hole region HA may also be removed. Here, a portion of each of the first insulating layer 10 and the second insulating layer 20 may be removed to form a predetermined opening. The opening may have a circular shape in the hole region HA on a plane. In addition, a recessed pattern GV may be formed in the opening later.

[0202] Afterwards, if Figure 8C As shown in , a first mask layer M1 is formed on the fourth insulating layer 40. The first mask layer M1 may be formed by depositing or applying a conductive material. The first mask layer M1 may completely cover the active area AA and the hole area HA, and may also be formed in the opening in which the insulating layer is formed. The conductive material may include various materials having conductivity. For example, the first mask layer M1 may be formed of at least one of a metal, a transparent conductive oxide, and a conductive polymer.

[0203] Afterwards, if Fig.8D and Fig. 8E As shown in FIG. 1 , a photoresist pattern PRP is formed on the first mask layer M1, and then the photoresist pattern PRP is patterned to form a second mask layer M2 (see FIG. 1 ). Fig.8F The second mask layer M2 may be formed by forming an opening OP-M defined in the hole area HA in the first mask layer M1 (see Fig.8F). The region of the first mask layer M1 exposed from the photoresist pattern PRP may be removed through an etching process ET1 to form an opening OP-M. The opening OP-M may correspond to a region in which the recess pattern GV is formed.

[0204] Afterwards, if FIG. 8F to FIG. 8H As shown in FIG, a recessed portion (hereinafter, also referred to as a "groove portion") HM is formed in the base substrate BSS. The recessed portion HM may be formed in the hole area HA. ​​The recessed portion HM is formed in a region corresponding to the opening OP-M of the second mask layer M2.

[0205] Specifically, Fig.8F and Figure 8G As shown in , after removing the photoresist pattern PRP, an opening OP-B may be formed in the auxiliary layer BL by using the second mask layer M2 as a mask. The region of the auxiliary layer BL exposed from the second mask layer M2 (i.e., the region of the auxiliary layer BL exposed by the opening OP-M of the second mask layer M2) may be removed by an etching process ET2 to form the opening OP-B.

[0206] Afterwards, if Figure 8G and Figure 8H As shown in , a portion of the base layer BS can be removed by using the second mask layer M2 as a mask to form a recessed portion HM. At least a portion of the area of ​​the base layer BS exposed from the auxiliary layer BL (i.e., at least a portion of the area of ​​the auxiliary layer BL exposed by the opening OP-B) can be removed by an etching process ET3. Here, the intensity and time of the etching process ET3 can be controlled to remove only a portion of the base layer BS that has a thickness that is not enough to penetrate the base layer BS. Therefore, the recessed portion HM can penetrate the auxiliary layer BL and then have a depth recessed from the base layer BS.

[0207] The recessed portion HM may have a side surface including an undercut shape. The auxiliary layer BL may have an end portion further protruding than the inner surface of the base layer BS. This may be caused by the difference in etching rate between the auxiliary layer BL and the base layer BS. Therefore, the recessed portion HM may include a predetermined tip portion.

[0208] Afterwards, if Figure 8I As shown in FIG, a first conductive layer MTL1 is formed on the fourth insulating layer 40. The first conductive layer MTL1 may be formed by patterning the second mask layer M2 to form a plurality of conductive patterns MP1. According to the inventive concept, the second mask layer M2 may not be removed but may be retained as the first conductive layer MTL1. Therefore, the process of removing the second mask layer M2 may be omitted, and a portion of forming the input sensing unit ISU may be performed during the process of forming the display unit DPU.

[0209] Afterwards, if Figure 8J As shown in , a light emitting device OD is formed. The light emitting device OD may be formed by sequentially forming a light emitting pattern EP, a control layer EL, and a second electrode E2 on a first electrode E1. The light emitting pattern EP may be formed by printing or injecting a light emitting material in the opening OP.

[0210] The control layer EL may be formed by depositing an organic material. The control layer EL may be formed by thermal deposition (i.e., evaporation). Here, a portion of the organic material may be deposited in the recessed portion HM to form an organic pattern EL-P. The second electrode E2 may be formed by depositing a conductive material. The deposition of the second electrode E2 may include a physical deposition process including thermal deposition and sputtering. Therefore, although not shown, a portion of the conductive material may be formed in the recessed portion HM during the deposition process of the second electrode E2 to form a pattern.

[0211] Afterwards, if Figure 8K As shown in FIG. 1 , an encapsulation layer DP-E is formed on the display device layer DP-D. The encapsulation layer DP-E may be formed by sequentially stacking a first inorganic layer IOL1, an organic layer OL, and a second inorganic layer IOL2.

[0212] Specifically, the first inorganic layer IOL1 may be formed in the active area AA and the hole area HA. ​​The first inorganic layer IOL1 may be formed by depositing an insulating material. For example, the first inorganic layer IOL1 may be formed by depositing an inorganic material or by chemical vapor deposition. Here, the first inorganic layer IOL1 may be formed along the inner surface of the groove portion HM.

[0213] The organic layer OL may be formed by applying a liquid organic material to the first inorganic layer IOL1 through a solution process such as a screen printing process or an inkjet process. The liquid organic material covers the curved top surface of the first inorganic layer IOL1 to provide a flat surface. In the present embodiment, although the organic layer OL is formed in the active area AA, embodiments of the inventive concept are not limited thereto. For example, a portion of the organic layer OL may extend according to the amount of the applied or diffused liquid organic material to fill a portion of the groove portion HM.

[0214] The second inorganic layer IOL2 may be formed by depositing an insulating material on the organic layer OL. For example, the second inorganic layer IOL2 may be formed by depositing an inorganic material or by chemical vapor deposition. The second inorganic layer IOL2 covers the top surface of the organic layer OL and the portion of the first inorganic layer IOL1 not covered by the organic layer OL. The second inorganic layer IOL2 may be formed to contact the first inorganic layer IOL1, and the first inorganic layer IOL1 and the second inorganic layer IOL2 may seal the organic layer OL. Here, the second inorganic layer IOL2 may be formed along the inner surface of the groove portion HM, and thus a recessed pattern GV may be formed.

[0215] Afterwards, if Figure 8L As shown in FIG. 1 , a module hole MH is formed in the hole area HA. ​​The module hole MH may be formed to penetrate the electronic panel PN. The base substrate BSS, the first insulating layer 10, the second insulating layer 20, the control layer EL, the second electrode E2, the first inorganic layer IOL1, and the second inorganic layer IOL2 disposed in the hole area HA may be penetrated by laser or drilling.

[0216] Afterwards, if Figure 8M As shown in FIG. 1 , a plurality of second conductive patterns MP2 may be formed on the encapsulation layer DP-E to form an input sensing unit ISU. This will be referred to as FIG. 9A to FIG. 9E to describe.

[0217] like Fig. 9A As shown in FIG. 1 , a first conductive pattern MP1 is formed on the fourth insulating layer 40 , and a control layer EL, a second electrode E2 , a first inorganic layer IOL1 , an organic layer OL, and a second inorganic layer IOL2 are sequentially stacked on the first conductive pattern MP1 . Fig. 9A Can be used with Figure 8I Process corresponding.

[0218] Afterwards, if Fig. 9B As shown in , a contact hole CH exposing the first conductive pattern MP1 is formed. The contact hole CH may be formed by removing portions of the control layer EL, the second electrode E2, the first inorganic layer 101, the organic layer OL, and the second inorganic layer 102 through a predetermined etching process. The etching process for forming the contact hole CH may be performed as a single process or a plurality of processes. For each of the control layer EL, the second electrode E2, the first inorganic layer 101, the organic layer OL, and the second inorganic layer 102, the etching process may be performed under different environments, but is not limited to a specific embodiment.

[0219] Afterwards, if Fig. 9C As shown in , an insulating layer ILL is formed. The insulating layer ILL may be formed by depositing or applying an insulating material. Here, the insulating layer ILL may cover the top surface of the second inorganic layer IOL2, the inner surface of the contact hole CH, and the portion of the first conductive pattern MP1 exposed by the contact hole CH.

[0220] Afterwards, if Fig.9DAs shown in , the insulating layer ILL may be patterned to form an inner insulating layer IP. The inner insulating layer IP may be formed by leaving only a portion of the insulating layer ILL covering the inner surface of the contact hole CH and removing the remaining portion. Specifically, the inner insulating layer IP may be formed by removing a portion of the insulating layer ILL covering the top surface of the second inorganic layer IOL2 and a portion of the insulating layer ILL covering the top surface of the first conductive pattern MP1. Therefore, a portion of the first conductive pattern MP1 may be exposed from the inner insulating layer IP, and the second electrode E2 may be covered by the inner insulating layer IP. Although not shown, a portion of the insulating layer ILL covering the top surface of the second inorganic layer IOL2 may not be removed to remain on the second inorganic layer IOL2, but the inventive concept is not limited to a specific embodiment.

[0221] Afterwards, if Fig.9E As shown in , the second conductive pattern MP2 is formed. The second conductive pattern MP2 may be formed by depositing or applying a conductive material on the second inorganic layer IOL2 and then patterning the deposited or applied conductive material. The second conductive pattern MP2 may contact the top surface of the first conductive pattern MP1 exposed from the inner insulating layer IP.

[0222] Therefore, even if the first conductive pattern MP1 and the second conductive pattern MP2 are separated from each other and the encapsulation layer DP-E is located therebetween, the first conductive pattern MP1 and the second conductive pattern MP2 can be easily connected to each other. In addition, even if the second electrode E2 is disposed between the first conductive pattern MP1 and the second conductive pattern MP2, since the second electrode E2 is covered by the inner insulating layer IP, the electrical connection between the second electrode E2 and the second conductive pattern MP2 can be stably blocked.

[0223] According to the inventive concept, a portion of the components of the input sensing unit can be disposed between the components of the display unit, and electrical interference between the components can be prevented. Therefore, the thickness of the electronic device can be reduced, and the integration of multiple units on a cross section can be improved.

[0224] In addition, according to the inventive concept, a part of the components of the input sensing unit can be formed in the process of manufacturing the display unit. Therefore, the number of processes can be reduced to reduce the manufacturing cost.

[0225] It will be apparent to those skilled in the art that various modifications and variations may be made in the inventive concept. Thus, it is intended that the present disclosure covers modifications and variations of the invention that come within the scope of the appended claims and their equivalents.

[0226] Therefore, the true protection scope of the inventive concept should be determined by the technical scope of the appended claims.

Claims

1. An electronic device, comprising: a base substrate including a front surface and a rear surface facing each other, and a module hole penetrating the front surface and the rear surface is defined in the base substrate; A thin film transistor is disposed on the base substrate; a light emitting device comprising a first electrode connected to the thin film transistor, a second electrode disposed on the first electrode, and a light emitting pattern disposed between the first electrode and the second electrode; An encapsulation layer, covering the light-emitting device; an input sensing unit disposed on the base substrate and comprising a plurality of first conductive patterns and a plurality of second conductive patterns disposed on the plurality of first conductive patterns; as well as an insulating layer, disposed between the plurality of first conductive patterns and the plurality of second conductive patterns, Wherein, the encapsulation layer is disposed between the plurality of first conductive patterns and the plurality of second conductive patterns, Wherein, the plurality of first conductive patterns are arranged below the second electrode.

2. The electronic device according to claim 1, wherein: The plurality of second conductive patterns include: A first sensing electrode extending in a first direction; and The second sensing electrode extends in a direction crossing the first direction to generate capacitance together with the first sensing electrode.

3. The electronic device according to claim 2, wherein: At least a portion of the plurality of first conductive patterns is connected to at least a portion of the plurality of second conductive patterns through a contact hole penetrating the encapsulation layer.

4. The electronic device according to claim 3, wherein: The plurality of first conductive patterns overlap with the second electrode on a plane, and The contact hole penetrates the second electrode.

5. The electronic device according to claim 3, further comprising an inner insulating layer covering a side surface of the contact hole, in, The second electrode and the plurality of second conductive patterns are electrically disconnected from each other by the inner insulating layer.

6. The electronic device according to claim 1, wherein: Each of the first electrode, the light emitting pattern and the second electrode is provided in plural numbers, wherein the plurality of second electrodes are arranged to overlap the plurality of light emitting patterns respectively, and The plurality of first conductive patterns are separated from the plurality of second electrodes on a plane.

7. The electronic device according to claim 1, further comprising an auxiliary electrode adjacent to the first electrode, in, Each of the first electrode, the light emitting pattern and the second electrode is provided in plural numbers, wherein the plurality of second electrodes are arranged to overlap the plurality of light emitting patterns respectively, and Wherein, the plurality of second electrodes are connected to the auxiliary electrode.

8. The electronic device according to claim 1, wherein: Each of the first electrode, the light emitting pattern and the second electrode is provided in plural numbers, wherein the plurality of second electrodes are arranged to overlap the plurality of light emitting patterns respectively, and The plurality of first conductive patterns and the plurality of second conductive patterns are separated from each other on a plane.

9. The electronic device according to claim 1, wherein: The insulating layer includes an organic layer disposed between the first electrode and the second electrode, and The organic layer completely covers the plurality of first conductive patterns.

10. The electronic device according to claim 1, wherein: The insulating layer includes an organic layer disposed between the first electrode and the second electrode, wherein the organic layer completely covers the plurality of first conductive patterns, Wherein, the insulating layer further includes a plurality of insulating patterns respectively covering the plurality of first conductive patterns, and Wherein, the organic layer covers the plurality of insulating patterns.

11. The electronic device according to claim 1, wherein: The encapsulation layer includes a first inorganic layer, a second inorganic layer disposed on the first inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer, and The module holes penetrate the first inorganic layer and the second inorganic layer.

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