A high-speed VPX storage device with multiple interfaces

Abstract

The technical problem to be solved by the present invention is to provide a high-speed storage board that supports multiple mainstream VPX data bus forms and can be directly used without changing the VPX architecture chassis structure. The technical solution of the present invention includes a VPX connector, an interface expansion chip, a storage control chip, a high-speed DDR cache, and an SSD hard disk group. The external system data is connected to the storage control chip and the interface expansion chip through the VPX connector, and the external data enters the interface expansion chip through the SRIO interface and the Ethernet interface on the VPX connector, and accesses the storage control chip through the 1G Ethernet interface on the VPX connector. The interface expansion chip is connected to the VPX connector, and is connected to the storage control chip through the LVDS data interface. The storage control chip is connected to the high-speed DDR cache and the SSD hard disk group.

Description

Technical Field

[0001] The present invention relates to a storage device, in particular to a high-speed VPX storage device with multiple interfaces. Background Art

[0002] The multi-interface high-speed VPX storage board is designed for VPX chassis with high-speed data storage requirements. Currently, the VPX chassis architecture is increasingly used due to its ease of use, high interface speed, and good structural stability. In a VPX chassis system, especially a single chassis system, a storage device is often required that can be directly integrated into the VPX chassis system to save data without occupying other space resources. The multi-interface high-speed VPX storage board can meet this type of demand. Summary of the invention

[0003] 1. Purpose of the invention

[0004] The technical problem to be solved by the present invention is to provide a high-speed storage board that supports multiple mainstream VPX data bus forms and can be directly used without changing the VPX architecture chassis structure.

[0005] 2. Technical solution

[0006] The multi-interface high-speed VPX storage board of the present invention comprises a VPX connector, an interface expansion chip, a storage control chip, a high-speed DDR cache, and an SSD hard disk group. The external system data interacts with the storage control chip and the interface expansion chip through the VPX connector to control the working state of the board. The external data enters the interface expansion chip through the SRIO interface and the Ethernet interface on the VPX connector, and accesses the storage control chip through the 1G Ethernet interface on the VPX connector. The interface expansion chip selects two data channels from the four data signals through the parameters transmitted by the storage control chip (usually there is only one of the two data interfaces, SRIO and 10G Ethernet, in the VPX chassis, so only one of the data is sent to the next stage here), and then sends the data to the storage control chip through the LVDS data interface. The storage control chip is connected to the high-speed DDR cache and the SSD hard disk group, controls the data to be cached to the DDR cache or written to the SSD hard disk group, and completes the data storage operation.

[0007] In order to improve the data processing efficiency of the storage control chip, the storage control chip includes a microblaze controller, a data buffer queue, a high-speed DMA channel, a hard disk driver, a control IO, an LVDS data interface (a custom data interface implemented by the IO of the FPGA) and a SATA data interface. After receiving the data, the microblaze controller in the storage control chip first places the data in the high-speed DDR cache through a DMA operation, and then sends the data to the hard disk driver through a DMA operation after the cached data reaches a threshold. The hard disk driver writes the data to the SSD hard disk group to complete the data storage operation.

[0008] Preferably, the cache data threshold is 64MB.

[0009] Preferably, the data storage controller chip is implemented using a Xilinx xc7k325t chip.

[0010] In order to implement the above method, the microblaze controller builds a large data cache between the LVDS data interface and the hard disk driver. When the data of the LVDS data interface enters the data cache, the microblaze controller does not directly read and write the data, but writes the data to the hard disk. The microblaze controller builds a DMA (direct memory access) channel between the LVDS data interface and the DDR memory, so that the data received by the LVDS data interface is directly stored in the DDR memory; at the same time, the microblaze controller also builds a DMA (direct memory access) channel between the DDR memory and the hard disk driver, so that the data can be directly written from the DDR memory to the hard disk; here, the microblaze controller sets the DMA (direct memory access) receiving address of the LVDS data interface on the DDR memory and the DMA (direct memory access) sending address of the hard disk driver to the same address, eliminating the data moving process, so that after the LVDS data interface receives the data, the microblaze controller can immediately control the data to be written to the hard disk, thereby achieving the effect of high-speed storage.

[0011] Preferably, the interface expansion chip is implemented using a Xilinx xc7k325t chip, which has two SRIO (Serial Rapid IO) interfaces and two 10G Ethernet interfaces and VPX connectors externally, and an LVDS data interface and control IO connected to the hard disk controller internally. The interface expansion chip includes a control program, an SRIO interface program, a 10G Ethernet interface program, a buffer FIFO, a data path switching program, a control IO, a LVDS data interface, an SRIO data interface, and a 10G Ethernet data interface.

[0012] The interface expansion chip receives the control signal from the storage control chip through the control IO, thereby controlling the working state and working parameters of the SRIO interface program and the 10G Ethernet interface, and at the same time controlling the data path switching program to control the data finally sent to the storage control chip. The interface expansion chip sends the data from the external SRIO interface and the 10G Ethernet interface to the buffer FIFO after being processed by the SRIO interface program and the 10G Ethernet interface program. The buffer FIFO sends the data to the data path switching program. At this time, the data path switching program determines which data needs to be sent to the storage control chip through the control parameters of the control program, and then sends the required data to the storage control chip through the LVDS data interface.

[0013] Preferably, the SSD hard disk group is constructed using a 2.5-inch SSD hard disk with a standard 2T capacity, and the capacity can be expanded as needed.

[0014] 3. Technical Effect

[0015] In the technical solution of the present invention, the multi-interface high-speed VPX storage board provided has the characteristics of fast storage speed, strong data interface compatibility and easy use; the data storage main control module of the multi-interface high-speed VPX storage board uses FPGA as the control core, with more stable performance, and can be applied to harsh environments. The FPGA directly controls and manages the SATA hard disk, effectively avoiding the problems of low hard disk operation efficiency and slow reading and writing speed when using a general-purpose processor; the high-speed data interface of the multi-interface high-speed VPX storage board uses a VPX connector to directly connect to the chassis backplane, which is stable and reliable, with unified standards, and can be applied to most VPX standard chassis, with a wide range of applications and convenient access. In addition, the structure of using a storage controller and an interface expansion function separately is more conducive to modular design, making product updates and upgrades more convenient; at the same time, functional separation can reduce the demand for single-chip FPGA chip resources and effectively reduce production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic structural diagram of an implementation scheme of the present invention.

[0017] In the figure, 1. VPX connector; 2. Interface expansion chip; 3. Storage control chip; 4. High-speed DDR cache; 5. SSD hard disk group.

[0018] Figure 2 It is a block diagram of the internal data flow of the interface expansion chip.

[0019] Figure 3 It is a block diagram of the data flow of the storage control chip. DETAILED DESCRIPTION

[0020] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] like Figure 1 As shown, the multi-interface high-speed VPX storage board of the present invention comprises a VPX connector 1; an interface expansion chip 2; a storage control chip 3; a high-speed DDR cache 4; and an SSD hard disk group 5. The system interacts with the storage control chip 3 on the multi-interface high-speed VPX storage board through 1G Ethernet to control the working state of the board. Data enters the interface expansion chip 2 through the SRIO interface and the 10G Ethernet interface on the VPX connector 1. The interface expansion chip 2 selects two data channels from the four data signals through the parameters passed by the storage control chip 3 (usually there is only one of the two data interfaces, SRIO and 10G Ethernet, in the VPX chassis, so only one of the data is sent to the next stage here), and then sends the data to the storage control chip 3 through the LVDS data interface. After receiving the data, the microblaze controller in the storage control chip 3 first places the data in the high-speed DDR cache 4 through DMA operation, and then sends the data to the hard disk driver through DMA operation after the cached data reaches the threshold. The hard disk driver writes the data to the SSD hard disk group 5 to complete the data storage operation.

[0022] Specifically, the storage control chip 3 includes a microblaze controller, a data buffer queue, a high-speed DMA channel, a hard disk driver, a control IO, an LVDS data interface (a custom data interface implemented by the IO of the FPGA) and a SATA data interface. The microblaze controller uses a high-speed DDR cache to build a large data cache area between the LVDS data interface and the hard disk driver. When the data of the LVDS data interface enters the data cache, the microblaze controller does not directly read and write the data, but writes the data to the hard disk in the following method: the microblaze controller builds a DMA (direct memory access) channel between the LVDS data interface and the DDR memory, so that the data received by the LVDS data interface is directly stored in the DDR memory; at the same time, the microblaze controller also builds a DMA (direct memory access) channel between the DDR memory and the hard disk driver, so that the data can be directly written from the DDR memory to the hard disk; here, the microblaze controller sets the DMA (direct memory access) receiving address of the LVDS data interface on the DDR memory and the DMA (direct memory access) sending address of the hard disk driver to the same address, so that after the LVDS data interface receives the data, the microblaze controller can immediately control the data to be written to the hard disk.

[0023] Preferably, the data storage controller chip is implemented using a Xilinx xc7k325t chip, which includes a microblaze controller, a data buffer FIFO, a high-speed DMA channel, a hard disk driver, a control IO, an LVDS data interface (a custom data interface implemented by the IO of the FPGA) and a SATA data interface.

[0024] Preferably, the interface expansion chip is also implemented using a Xilinx xc7k325t chip, with two SRIO (Serial Rapid IO) interfaces and two 10G Ethernet interfaces and VPX connectors externally, and an LVDS data interface and control IO connected to the hard disk controller internally. The interface expansion chip includes a control program, an SRIO interface program, a 10G Ethernet interface program, a buffer FIFO, a data path switching program, a control IO, a LVDS data interface, an SRIO data interface, and a 10G Ethernet data interface.

[0025] The interface expansion chip receives control signals from the storage control chip through the control IO to control the working status and working parameters of the SRIO interface program and the 10G Ethernet interface, and at the same time controls the data path switching program to control the data that is finally sent to the storage control chip. The interface expansion chip sends the data from the external SRIO interface and the 10G Ethernet interface to the buffer FIFO after being processed by the SRIO interface program and the 10G Ethernet interface program. The buffer FIFO sends the data to the data path switching program. The data path switching program determines which data needs to be sent to the storage control chip through the control parameters of the control program, and then sends the required data to the storage control chip through the LVDS data interface.

[0026] The SSD hard disk group is built with 2.5-inch SSD hard disks, with a standard 2T capacity, and the capacity can be expanded as needed.

[0027] A specific embodiment of the present invention: the storage controller chip in the multi-interface high-speed VPX storage board is constructed using a Xilinx FPGA chip, a microblaze core runs on the FPGA, and the SATA hard disk, data interface, hard disk drive, and DDR cache are managed and controlled by the microblaze core; the LVDS data interface is implemented using the IO of the FPGA, using a custom communication protocol, and the communication bandwidth reaches 800MB / s, which can meet most application requirements; the SRIO data interface uses the GTX high-speed transceiver of the Xilinx FPGA to achieve high-speed data transmission and reception; 10G Ethernet is similar to SRIO, and also uses the GTX high-speed transceiver of the Xilinx FPGA to achieve high-speed data transmission and reception. The hard disk driver implements the SATA controller function by FPGA logic, without the need for an external SATA control chip. The controller driver implements support for the exFAT standard file system. The control IO uses a 16-bit single-ended IO signal, with 8 bits as address lines and 8 bits as data lines. It can implement read and write operations of 255 8-bit control registers, which is sufficient to meet control requirements. The data buffer FIFO is implemented using Xilinx's internal Block Ram resources, making expansion and modification very convenient. The high-speed DMA channel is implemented using the DMA controller provided by Xilinx.

Claims

1. A multi-interface high-speed VPX storage device, comprising a VPX connector, an interface expansion chip, a storage control chip, a high-speed DDR cache, and an SSD hard disk group; The interface expansion chip is a Xilinx XC7K325T FPGA chip, and the interface expansion chip includes 2 SRIO interfaces and 2 10G Ethernet interfaces connected to the VPX connector, an LVDS data interface connected to the storage control chip, and a control IO and cache FIFO; The storage control chip is a Xilinx XC7K325T FPGA chip, which includes a Microblaze controller, a data buffer queue, a high-speed DMA channel, a hard disk driver, a control IO, an LVDS data interface, and a SATA data interface; the SSD hard disk group, the hard disk driver, and the high-speed DDR cache are managed by the Microblaze controller; the LVDS data interface is implemented by the IO of the FPGA; External data enters the interface expansion chip through the two SRIO interfaces and two 10G Ethernet interfaces on the VPX connector; the interface expansion chip is connected to the VPX connector; The interface expansion chip sends the data from the two SRIO interfaces and the two 10G Ethernet interfaces to the buffer FIFO; the interface expansion chip selects two data from the four data signals including the two SRIO interfaces and the two 10G Ethernet interfaces through the parameters transmitted by the storage control chip through the control IO, and then sends the selected data to the storage control chip through the LVDS data interface; The storage control chip is connected to the high-speed DDR cache and the SSD hard disk group; The Microblaze controller of the storage control chip constructs a DMA channel between the LVDS data interface of the storage control chip and the high-speed DDR cache, so that the data received by the LVDS data interface is directly stored in the high-speed DDR cache; the Microblaze controller also constructs a DMA channel between the high-speed DDR cache and the hard disk driver, so that the data is directly written from the high-speed DDR cache to the SSD hard disk group; The Microblaze controller sets the DMA receiving address of the LVDS data interface of the storage control chip on the high-speed DDR cache and the DMA sending address of the hard disk driver to the same address; The specific method for the Microblaze controller in the storage control chip to process data is as follows: the Microblaze controller does not directly read and write data, but builds a DMA channel between the LVDS data interface and the high-speed DDR cache, so that the data received by the LVDS data interface is directly stored in the high-speed DDR cache; at the same time, the Microblaze controller also builds a DMA channel between the high-speed DDR cache and the hard disk driver, so that data can be directly written from the high-speed DDR cache to the hard disk; here, the Microblaze controller sets the DMA receiving address of the LVDS data interface on the high-speed DDR cache and the DMA sending address of the hard disk driver to the same address, so that after the LVDS data interface receives the data, the Microblaze controller can immediately control the data to be written to the hard disk; The storage control chip is accessed through the 1G Ethernet interface on the VPX connector, and commands are exchanged with the storage control chip to control the working state of the multi-interface high-speed VPX storage device.

2. A multi-interface high-speed VPX storage device as claimed in claim 1, characterized in that: The LVDS data interface is connected to the high-speed DDR cache through a high-speed DMA channel constructed by the Microblaze controller, and the high-speed DDR cache is connected to the hard disk driver through a high-speed DMA channel constructed by the Microblaze controller. After receiving the data, the Microblaze controller in the storage control chip first places the data in the high-speed DDR cache through a DMA operation, and then sends the data to the hard disk driver through a DMA operation after the cached data reaches a threshold. The hard disk driver writes the data to the SSD hard disk group to complete the data storage operation.

3. A multi-interface high-speed VPX storage device as claimed in claim 2, characterized in that: The high-speed DDR cache data threshold is 64MB.

4. A multi-interface high-speed VPX storage device as claimed in claim 3, characterized in that: The SSD hard disk group is built using a 2.5-inch SSD hard disk with a standard 2T capacity.

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