Semiconductor interconnect structure and method for manufacturing the same

Abstract

The present invention provides a semiconductor interconnect structure and a preparation method thereof, comprising the following steps: 1) providing a substrate, a dielectric layer formed on the substrate, and forming a contact hole in the dielectric layer; 2) forming a first metal layer at least at the bottom and sidewall of the contact hole by low-temperature chemical vapor deposition, the first metal layer including a nucleation layer; 3) forming a second metal layer on the first metal layer by electroplating including low current density electroplating, the second metal layer including a seed layer, and the resistivity of the second metal layer is less than the resistivity of the first metal layer. The present invention can avoid the formation of holes inside the metal layer filled in the contact hole by first forming the first metal layer at low temperature in the contact hole and then forming the second metal layer, thereby effectively reducing the resistance value of the entire filled metal layer; the resistivity of the second metal layer is less than the resistivity of the first metal layer, which can further reduce the resistance value of the entire filled metal layer.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a semiconductor interconnection structure and a preparation method thereof. Background Art

[0002] In existing semiconductor companies, tungsten film deposition using chemical vapor deposition (CVD) is a common process in many semiconductor manufacturing processes. In existing processes, such as Figure 1 As shown, generally, a dielectric layer 10 located on a substrate 10' and having a contact hole 11 formed therein is placed in a vacuum chamber and heated to a process temperature, and then an adhesion barrier layer 12 and a nucleation seed layer 13 are sequentially formed in the contact hole 11, and then a tungsten metal layer 14 is deposited in the contact hole 11.

[0003] However, with the continuous deepening of device miniaturization, the size of semiconductor interconnection structures is getting smaller and smaller. When the existing chemical vapor deposition process is used to fill the contact hole 11 with a high aspect ratio in one step to form the tungsten metal layer 14, it is easy to form a hole 15 in the tungsten metal layer 14 in the contact hole 11. The existence of the hole 15 will cause electromigration problems in the subsequent copper process and make the resistance value of the metal layer filled in the contact hole larger, thereby reducing the reliability of the semiconductor device. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a semiconductor interconnect structure and a preparation method thereof, which is used to solve the problem that when the tungsten metal layer is formed in the contact hole in one step using the existing chemical vapor deposition process in the prior art, holes are formed in the filled tungsten metal layer, which leads to electromigration problems in the subsequent copper process and makes the resistance value of the contact hole larger, thereby reducing the reliability of the semiconductor device.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor interconnect structure, the method for preparing a semiconductor interconnect structure comprising the following steps:

[0006] 1) providing a substrate, wherein a dielectric layer is formed on the substrate, and a contact hole is formed in the dielectric layer;

[0007] 2) forming a first metal layer at least on the bottom and sidewalls of the contact hole by low temperature chemical vapor deposition, wherein the first metal layer includes a nucleation layer; and

[0008] 3) forming a second metal layer on the first metal layer by electroplating including low current density electroplating, wherein the second metal layer includes a seed layer, and the resistivity of the second metal layer is lower than the resistivity of the first metal layer.

[0009] As a preferred solution of the present invention, the aspect ratio of the contact hole formed in step 1) is greater than 5.

[0010] As a preferred solution of the present invention, the material of the first metal layer deposited in step 2) includes tungsten; and the material of the second metal layer deposited in step 3) includes copper.

[0011] As a preferred solution of the present invention, in step 2), the reaction gas used to form the first metal layer includes tungsten hexafluoride and monosilane.

[0012] As a preferred solution of the present invention, in step 2), the temperature for forming the first metal layer is no higher than 300° C., and the thickness of the formed first metal layer is between 500 angstroms and 700 angstroms.

[0013] As a preferred embodiment of the present invention, step 2) comprises the following steps:

[0014] 2-1) forming the nucleation layer at least on the bottom and sidewall of the contact hole; and

[0015] 2-2) forming a main body layer of the first metal layer on the surface of the nucleation layer, wherein the material of the nucleation layer is the same as that of the main body layer of the first metal layer.

[0016] As a preferred embodiment of the present invention, the deposition period of the nucleation layer is between 8 and 10.

[0017] As a preferred embodiment of the present invention, diborane and tungsten hexafluoride are used as reaction gases for one deposition cycle at a temperature not higher than 300° C.; and monosilane and tungsten hexafluoride are used as reaction gases for 7 to 9 deposition cycles at a temperature not higher than 300° C.

[0018] As a preferred embodiment of the present invention, step 3) comprises the following steps:

[0019] 3-1) forming the seed layer in the contact hole, wherein the seed layer is located on the upper surface of the first metal layer;

[0020] 3-2) electroplating a first electroplating layer of a first thickness gradually from the upper surface of the seed layer upward in the contact hole under a first current density condition; and

[0021] 3-3) continuing to electroplate a second electroplating layer of a second thickness on the upper surface of the first electroplating layer and the upper surface of the dielectric layer under a second current density condition, wherein the first current density is less than the second current density; wherein:

[0022] The first electroplating layer and the second electroplating layer together constitute a main body layer of the second metal layer, and a material of the seed layer is the same as a material of the main body layer of the second metal layer.

[0023] As a preferred embodiment of the present invention, in step 3-2), the first current density is between 1.5A and 3A, and the first thickness is between 900A and 1100A; in step 3-3), the second current density is between 20A and 40A, and the second thickness is between 3500A and 4500A.

[0024] As a preferred solution of the present invention, the thickness of the seed layer is between 150 angstroms and 200 angstroms.

[0025] As a preferred embodiment of the present invention, the following steps are also included between step 1) and step 2): a step of forming an adhesion barrier layer at the bottom, sidewalls and upper surface of the contact hole and the dielectric layer; in step 2), the first metal layer is formed on the surface of the adhesion barrier layer.

[0026] As a preferred solution of the present invention, in step 2), the first metal layer is also formed on the upper surface of the dielectric layer; and after step 3), the method further includes removing the first metal layer and the second metal layer located on the dielectric layer.

[0027] As a preferred solution of the present invention, in step 2), the ratio of the thickness of the first metal layer formed at the bottom of the contact hole to the depth of the contact hole is proportional to the aspect ratio of the contact hole.

[0028] As a preferred solution of the present invention, in step 2), the thickness of the first metal layer formed in the contact hole accounts for 10% to 70% of the depth of the contact hole.

[0029] The present invention also provides a semiconductor interconnect structure, comprising:

[0030] substrate;

[0031] A dielectric layer is located on the upper surface of the substrate, and a contact hole is formed in the dielectric layer;

[0032] A first metal layer is formed on the bottom and sidewalls of the contact hole by low-temperature chemical vapor deposition, wherein the first metal layer includes a nucleation layer; and

[0033] The second metal layer is formed on the first metal layer by electroplating including low current density electroplating to fill the contact hole. The second metal layer includes a seed layer. The resistivity of the second metal layer is less than the resistivity of the first metal layer.

[0034] As a preferred solution of the present invention, the aspect ratio of the contact hole is greater than 5.

[0035] As a preferred solution of the present invention, the first metal layer also includes a main layer located on the surface of the nucleation layer, and the main layer of the first metal layer includes a tungsten metal layer; the second metal layer also includes a main layer located on the surface of the seed layer, and the main layer of the second metal layer includes a copper metal layer.

[0036] As a preferred solution of the present invention, the deposition temperature of the first metal layer is not higher than 300° C., and the thickness of the first metal layer is between 500 angstroms and 700 angstroms.

[0037] As a preferred solution of the present invention, the main layer of the second metal layer includes a first electroplating layer and a second electroplating layer, the first electroplating layer is located on the upper surface of the first metal layer, and the second electroplating layer is at least located on the upper surface of the first electroplating layer.

[0038] As a preferred embodiment of the present invention, the first electroplating layer is formed by electroplating at a current density between 1.5A and 3A, and the thickness of the first electroplating layer is between 900 angstroms and 1100 angstroms; the second electroplating layer is formed by electroplating at a current density between 20A and 40A, and the thickness of the second electroplating layer is between 3500 angstroms and 4500 angstroms.

[0039] As a preferred solution of the present invention, the nucleation layer is located between the dielectric layer and the main body layer of the first metal layer; the material of the nucleation layer is the same as the material of the main body layer of the first metal layer; and

[0040] The seed layer is located between the main body layer of the first metal layer and the main body layer of the second metal layer; the material of the seed layer is the same as the material of the main body layer of the second metal layer.

[0041] As a preferred solution of the present invention, the thickness of the seed layer is between 150 angstroms and 200 angstroms.

[0042] As a preferred solution of the present invention, the semiconductor interconnect structure further includes an adhesion barrier layer, which is formed at least on the bottom edge and sidewall of the contact hole and is located between the dielectric layer and the first metal layer.

[0043] As a preferred embodiment of the present invention, the thickness of the adhesion barrier layer is between 100 angstroms and 200 angstroms.

[0044] As a preferred solution of the present invention, the first metal layer directly covers the bottom and sidewalls of the second metal layer, and the height-to-width ratio of the second metal layer is smaller than the depth-to-width ratio of the contact hole.

[0045] As described above, the semiconductor interconnect structure and the method for manufacturing the same of the present invention have the following beneficial effects:

[0046] The present invention forms the second metal layer before forming the first metal layer at a low temperature in the contact hole, thereby avoiding the formation of holes in the metal layer filled in the contact hole, thereby effectively reducing the resistance value of the entire filled metal layer;

[0047] The resistivity of the second metal layer is lower than that of the first metal layer, which can further reduce the resistance value of the entire filled metal layer;

[0048] The first metal layer may include tungsten, and the second metal layer may include copper. A tungsten layer is formed in the contact hole, and then a copper layer is formed in the contact hole. Tungsten and copper will not merge. Tungsten can act as a barrier layer to prevent copper from diffusing into the dielectric layer below the tungsten. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic diagram of the cross-sectional structure of a structure obtained after a tungsten metal layer is filled in a contact hole using a chemical vapor deposition process in the prior art.

[0050] Figure 2 Shown is a flow chart of a method for preparing a semiconductor interconnect structure provided in Embodiment 1 of the present invention.

[0051] Figures 3 to 10 It shows a schematic diagram of the cross-sectional structure in each step of the method for preparing the semiconductor interconnect structure provided in the first embodiment of the present invention; wherein, Fig.10 It is a schematic diagram of the cross-sectional structure of the semiconductor interconnection structure in the second embodiment of the present invention.

[0052] Component number description

[0053] 10' Base

[0054] 10 Dielectric layer

[0055] 11 Contact hole

[0056] 12 Adhesion barrier layer

[0057] 13 Nucleation layer

[0058] 14 Tungsten metal layer

[0059] 15 Holes

[0060] 20' Base

[0061] 20 Dielectric layer

[0062] 21 Contact hole

[0063] 22 First metal layer

[0064] 221 Main layer of the first metal layer

[0065] 23 Second Metal Layer

[0066] 231 First electroplating layer

[0067] 232 Second electroplating layer

[0068] 233 Main layer of the second metal layer

[0069] 24 Nucleation layer

[0070] 25 Seed Layer

[0071] 26 Adhesion barrier layer DETAILED DESCRIPTION

[0072] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0073] See also Figures 2 to 10 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0074] Embodiment 1

[0075] like Figure 2 As shown, the present invention provides a method for preparing a semiconductor interconnect structure, and the method for preparing a semiconductor interconnect structure comprises the following steps:

[0076] 1) providing a substrate, wherein a dielectric layer is formed on the substrate, and a contact hole is formed in the dielectric layer;

[0077] 2) forming a first metal layer at least on the bottom and sidewalls of the contact hole by low temperature chemical vapor deposition, wherein the first metal layer includes a nucleation layer; and

[0078] 3) forming a second metal layer on the first metal layer by electroplating including low current density electroplating, wherein the second metal layer includes a seed layer, and the resistivity of the second metal layer is lower than the resistivity of the first metal layer.

[0079] In step 1), refer to Figure 2The S1 step and Figure 3 , a substrate 20 ′ is provided, a dielectric layer 20 is formed on the substrate 20 ′, and a contact hole 21 is formed in the dielectric layer 20 .

[0080] As an example, the substrate 20 ′ may be any existing substrate, and the material of the substrate 20 ′ may include but is not limited to silicon dioxide, gallium nitride or sapphire, etc.

[0081] As an example, the dielectric layer 20 can be any semiconductor interconnect structure that can form the contact hole 21 and the contact hole 21 needs to be filled, such as an interlayer dielectric layer of a semiconductor device, which can form the contact hole 21, and after filling, an electrical connection structure (e.g., a conductive plug) is formed to serve as an interconnection structure between upper and lower device layers. The material of the dielectric layer 20 can include but is not limited to silicon oxide or silicon nitride, etc.

[0082] As an example, the number of the contact holes 21 formed in the dielectric layer 20 may be multiple, and the multiple contact holes 21 are arranged at intervals in the dielectric layer 20. The multiple contact holes 21 may be arranged at equal intervals in the dielectric layer 20, or may be arranged at unequal intervals. Figure 3 It is only taken as an example that one contact hole 21 is formed in the dielectric layer 20 , and the actual number of the contact holes 21 is not limited thereto.

[0083] As an example, the cross-sectional shape of the contact hole 21 can be set according to actual needs. Preferably, in this embodiment, the cross-sectional shape of the contact hole 21 can include any shape that can be filled, such as a rectangle, a trapezoid or a U shape.

[0084] As an example, the contact hole 21 is preferably a contact hole with a high aspect ratio. Preferably, in this embodiment, the aspect ratio of the contact hole 21 may be greater than 5.

[0085] As an example, Figure 4 As shown, after step 1), the following step is also included: forming an adhesion barrier layer 26 on the bottom and sidewall of the contact hole 21 and the upper surface of the dielectric layer 20. The adhesion barrier layer 26 may include a Ti layer, a TiN layer, or a Ti layer and a TiN layer; the thickness of the adhesion barrier layer 26 should not be too thick, and generally the thickness of the adhesion barrier layer 26 is between 100 angstroms and 200 angstroms.

[0086] It should be noted that the “between” mentioned above and subsequently refers to a numerical range including two endpoints. For example, the “between 100 angstroms and 200 angstroms” mentioned above refers to a numerical range including the two endpoints of 100 and 200.

[0087] In step 2), refer to Figure 2 The S2 step in Figures 5 and 6 A first metal layer 22 is formed at least on the bottom and sidewall of the contact hole 21 by low-temperature chemical vapor deposition, wherein the first metal layer 22 includes a nucleation layer 24 .

[0088] As an example, Figure 5 As shown, step 2) includes the following steps:

[0089] 2-1) forming the nucleation layer 24 at the bottom and sidewall of the contact hole 21; and

[0090] 2-2) forming the main body layer 221 of the first metal layer 22 on the surface of the nucleation layer 24 , wherein the material of the nucleation layer 24 is the same as that of the main body layer 221 of the first metal layer 22 .

[0091] As an example, the nucleation layer 24 is usually deposited in multiple cycles, for example, each deposition cycle is 10s (of course, in other examples, the time of each deposition cycle can also be set to other values ​​according to actual needs, which is not limited here), and the reaction gas is sequentially introduced in a pulsed supply mode for deposition in each deposition cycle, and the waste and reaction by-products are discharged after each deposition cycle. Preferably, in this embodiment, the deposition cycle of the nucleation layer 24 is between 8 and 10; specifically, diborane (B2H6) and tungsten hexafluoride (WF6) are first introduced at a temperature not higher than 300°C for deposition as a wetting layer for one deposition cycle, and then monosilane (SiH4) and tungsten hexafluoride (WF6) are introduced at a temperature not higher than 300°C for deposition for 7 to 9 deposition cycles, and the reaction formula at this time is: 2WF6(g) + 3SiH4(g) = 2W (s) + 3SiF4(g) + 6H2(g). In the existing process, the process of chemical vapor deposition is generally between 400°C and 1200°C. In the present invention, the temperature required for low-temperature chemical vapor deposition to form the first metal layer 22 is less than 300 degrees Celsius. The nucleation layer 24 deposited in the above manner has relatively good uniformity and good crystal orientation, which can lay a good foundation for the post-filling of the contact hole 21.

[0092] As an example, the first metal layer 22 is also formed on the upper surface of the dielectric layer 20 .

[0093] As an example, in step 2), the ratio of the thickness of the first metal layer 22 formed in the contact hole 21 to the depth of the contact hole 21 is proportional to the aspect ratio of the contact hole 21, that is, the larger the aspect ratio of the contact hole 21, the smaller the ratio of the thickness of the first metal layer 22 to the depth of the contact hole 21. Preferably, the thickness of the first metal layer 22 formed in the contact hole 21 accounts for 10% to 70% of the depth of the contact hole 21. For example, when the aspect ratio of the contact hole 21 is 5, the thickness of the first metal layer 22 formed in the contact hole 21 accounts for about 65% of the depth of the contact hole 21, and when the aspect ratio of the contact hole 21 is 12, the thickness of the first metal layer 22 formed in the contact hole 21 accounts for about 50% of the depth of the contact hole 21.

[0094] As an example, the material of the first metal layer 22 may include tungsten; specifically, in step 2), the first metal layer 22 may be formed by chemical vapor deposition at a temperature not higher than 300°C, and the reaction gas used to form the first metal layer 22 may include tungsten hexafluoride and hydrogen (H2); the thickness of the formed first metal layer 22 may be between 500 angstroms and 700 angstroms. The present invention first deposits the first metal layer 22 in the contact hole 21 under low temperature conditions. Since the deposition rate of the first metal layer 22 is relatively slow under low temperature conditions, no holes will be generated in the first metal layer 22 deposited in the contact hole 21; at the same time, when a certain thickness of the first metal layer 22 is first deposited in the contact hole 21 and then the second metal layer 23 is deposited in the contact hole 21, the actual depth-to-width ratio of the unfilled portion of the contact hole 21 corresponding to the second metal layer 23 will be significantly reduced, thereby avoiding the generation of holes in the second metal layer 23 when the second metal layer 23 is subsequently deposited.

[0095] In step 3), refer to Figure 2 The S3 steps in Figures 7 to 9 A second metal layer 23 is formed on the first metal layer 22 by electroplating including low current density electroplating, wherein the second metal layer 23 includes a seed layer 25 , and the resistivity of the second metal layer 23 is less than the resistivity of the first metal layer 22 .

[0096] As an example, step 3) includes the following steps:

[0097] 3-1) forming the seed layer 25 in the contact hole 21, wherein the seed layer 25 is located on the upper surface of the first metal layer 22, such as Figure 7 As shown;

[0098] 3-2) electroplating a first electroplating layer 231 of a first thickness gradually from the upper surface of the seed layer 25 upward in the contact hole 21 under a first current density condition; and

[0099] 3-3) continuing to electroplate a second electroplating layer 232 of a second thickness on the upper surface of the first electroplating layer 231 and the upper surface of the dielectric layer 20 under a second current density condition, wherein the first current density is less than the second current density; wherein,

[0100] The first electroplating layer 231 and the second electroplating layer 232 together constitute the main body layer 233 of the second metal layer 23 , and the material of the seed layer 25 is the same as that of the main body layer 233 of the second metal layer 23 .

[0101] As an example, the seed layer 25 can be formed by an electroplating process; the thickness of the seed layer 25 located in the contact hole 21 can account for about 2%~3% of the sum of the thicknesses of the second metal layer 23 and the seed layer 25. Preferably, in this embodiment, the thickness of the seed layer 25 can be between 150 angstroms and 200 angstroms.

[0102] As an example, the material of the second metal layer 23 may include copper.

[0103] As an example, in step 3-2), the first current density is between 1.5A and 3A, and the first thickness is between 900 angstroms and 1100 angstroms; in step 3-3), the second current density is between 20A and 40A, and the second thickness is between 3500 angstroms and 4500 angstroms.

[0104] It should be noted that the first electroplating layer 231 may completely fill the contact hole 21 , or may partially fill the contact hole 21 .

[0105] It should be further explained that, in one example, the first electroplating layer 231 may be located on the bottom, sidewalls of the contact hole 21 and the upper surface of the dielectric layer 20. In this case, the thickness of the first electroplating layer 231 located at the bottom of the contact hole 21 is much greater than the thickness of the first electroplating layer 231 located on the sidewalls of the contact hole 231 and the upper surface of the dielectric layer 20. Figure 8 As shown; in another example, the first electroplating layer 231 may also be filled only from the bottom of the contact hole 21 from bottom to top at the bottom of the contact hole 21, and is not formed on the sidewalls of the contact hole 21 and the upper surface of the dielectric layer 20.

[0106] A portion of the second metal layer 23 is first formed by electroplating at a lower current density. At a low current density, the deposition rate of the second metal layer 23 is slow, which can effectively avoid the formation of holes in the formed second metal layer 23.

[0107] Since the resistivity of copper is significantly lower than that of tungsten, the contact hole 21 is filled with the first metal layer 22 including tungsten and the second metal layer 23 including copper. Compared with the solution of directly filling the contact hole with a tungsten metal layer in the prior art, the present invention can significantly reduce the resistance value of the entire metal layer filled in the contact hole 21; at the same time, tungsten and copper will not fuse, and tungsten can act as a barrier layer to prevent copper from diffusing into the dielectric layer below the tungsten, thereby reducing the use of barrier layers.

[0108] As an example, Fig.10 As shown, after step 3), the first metal layer 22 and the second metal layer 23 located on the dielectric layer 20 (i.e., above the upper surface of the dielectric layer 20) are further removed. Specifically, the first metal layer 22 and the second metal layer 23 located on the upper surface of the dielectric layer 20 can be removed by, but not limited to, a chemical mechanical polishing process (CMP).

[0109] It should be noted that, when the nucleation layer 24 and the seed layer 25 are formed on the dielectric layer 20 , the nucleation layer 24 on the dielectric layer 20 and the seed layer 25 on the dielectric layer 20 are also removed at the same time.

[0110] It needs to be further explained that Fig.10 The second metal layer 23 is shown as a whole, and the first electroplating layer 231 and the second electroplating layer 232 are not specifically shown.

[0111] Embodiment 2

[0112] Please combine Figures 2 to 8 Continue reading Figures 9 and 10 The present invention also provides a semiconductor interconnect structure, the semiconductor interconnect structure comprising:

[0113] Base 20';

[0114] A dielectric layer 20, the dielectric layer 20 is located on the upper surface of the substrate 20', and a contact hole 21 is formed in the dielectric layer 20;

[0115] A first metal layer 22, wherein the first metal layer 22 is formed on the bottom and sidewalls of the contact hole 21 by low-temperature chemical vapor deposition, and the first metal layer 22 includes a nucleation layer 24; and

[0116] The second metal layer 23 is formed on the first metal layer 22 by electroplating including low current density electroplating to fill the contact hole 21 . The second metal layer 23 includes a seed layer 25 . The resistivity of the second metal layer 23 is less than the resistivity of the first metal layer 22 .

[0117] As an example, the substrate 20 ′ may be any existing substrate, and the material of the substrate 20 ′ may include but is not limited to silicon dioxide, gallium nitride or sapphire, etc.

[0118] As an example, the dielectric layer 20 can be any semiconductor interconnect structure that can form the contact hole 21 and the contact hole 21 needs to be filled, such as an interlayer dielectric layer of a semiconductor device, which can form the contact hole 21, and after filling, an electrical connection structure (e.g., a conductive plug) is formed to serve as an interconnection structure between upper and lower device layers. The material of the dielectric layer 20 can include but is not limited to silicon oxide or silicon nitride, etc.

[0119] As an example, the number of the contact holes 21 formed in the dielectric layer 20 may be multiple, and the multiple contact holes 21 are arranged at intervals in the dielectric layer 20. The multiple contact holes 21 may be arranged at equal intervals in the dielectric layer 20, or may be arranged at unequal intervals. Figure 3 It is only taken as an example that one contact hole 21 is formed in the dielectric layer 20 , and the actual number of the contact holes 21 is not limited thereto.

[0120] As an example, the cross-sectional shape of the contact hole 21 can be set according to actual needs. Preferably, in this embodiment, the cross-sectional shape of the contact hole 21 can include any shape that can be filled, such as a rectangle, a trapezoid or a U shape.

[0121] As an example, the contact hole 21 is preferably a contact hole with a high aspect ratio. Preferably, in this embodiment, the aspect ratio of the contact hole 21 may be greater than 5.

[0122] As an example, the ratio of the thickness of the first metal layer 22 in the contact hole 21 to the depth of the contact hole 21 is proportional to the aspect ratio of the contact hole 21, that is, the larger the aspect ratio of the contact hole 21, the smaller the ratio of the thickness of the first metal layer 22 to the depth of the contact hole 21. Preferably, the thickness of the first metal layer 22 in the contact hole 21 accounts for 45% to 70% of the depth of the contact hole 21. For example, when the aspect ratio of the contact hole 21 is 5, the thickness of the first metal layer 22 in the contact hole 21 accounts for about 65% of the depth of the contact hole 21, and when the aspect ratio of the contact hole 21 is 12, the thickness of the first metal layer 22 in the contact hole 21 accounts for about 50% of the depth of the contact hole 21.

[0123] As an example, the first metal layer 22 also includes a main layer 221, the main layer 221 of the first metal layer 22 is located on the surface of the nucleation layer 24, and the main layer 221 of the first metal layer 22 may include a tungsten metal layer. Specifically, the first metal layer 22 may be formed by a chemical vapor deposition process at a temperature not higher than 300°C; the thickness of the first metal layer 22 may be between 500 angstroms and 700 angstroms. The first metal layer 22 of the present invention is formed under low temperature conditions. Since the deposition rate of the first metal layer 22 is relatively slow under low temperature conditions, no holes will be generated in the first metal layer 22 deposited in the contact hole 21; at the same time, when the first metal layer 22 of a certain thickness is formed in the contact hole 21 first, and then the second metal layer 23 is formed in the contact hole 21, the actual depth-to-width ratio of the unfilled portion of the contact hole 21 corresponding to the second metal layer 23 will be significantly reduced, thereby avoiding the generation of holes in the second metal layer 23 when the second metal layer 23 is subsequently deposited.

[0124] As an example, the second metal layer 23 also includes a main layer 233, the main layer 233 of the second metal layer 23 is located on the surface of the seed layer 25, and the main layer 233 of the second metal layer 23 includes a copper metal layer; the main layer 233 of the second metal layer 23 includes a first electroplating layer 231 and a second electroplating layer 232, the first electroplating layer 231 is located on the upper surface of the first metal layer 22, and the second electroplating layer 232 is at least located on the upper surface of the first electroplating layer 231.

[0125] As an example, the first electroplating layer 231 is formed by electroplating at a current density between 1.5A and 3A, and the thickness of the first electroplating layer 231 is between 900 angstroms and 1100 angstroms; the second electroplating layer 232 is formed by electroplating at a current density between 20A and 40A, and the thickness of the second electroplating layer 232 is between 3500 angstroms and 4500 angstroms.

[0126] It should be noted that the first electroplating layer 231 may fill the contact hole 21 completely or partially. It should be further noted that, in one example, the first electroplating layer 231 may be located at the bottom, sidewalls of the contact hole 21 and the upper surface of the dielectric layer 20. In this case, the thickness of the first electroplating layer 231 located at the bottom of the contact hole 21 is much greater than the thickness of the first electroplating layer 231 located at the sidewalls of the contact hole 231 and the upper surface of the dielectric layer 20. Figure 8 As shown; in another example, the first electroplating layer 231 may also be filled only from the bottom of the contact hole 21 from bottom to top at the bottom of the contact hole 21, and is not formed on the sidewalls of the contact hole 21 and the upper surface of the dielectric layer 20.

[0127] A portion of the second metal layer 23 is first formed by electroplating at a lower current density. At a low current density, the deposition rate of the second metal layer 23 is slow, which can effectively avoid the formation of holes in the formed second metal layer 23.

[0128] Since the resistivity of copper is significantly lower than that of tungsten, the contact hole 21 is filled with the first metal layer 22 including tungsten and the second metal layer 23 including copper. Compared with the solution of directly filling the contact hole with a tungsten metal layer in the prior art, the present invention can significantly reduce the resistance value of the entire metal layer filled in the contact hole 21; at the same time, tungsten and copper will not fuse, and tungsten can act as a barrier layer to prevent copper from diffusing into the dielectric layer below the tungsten, thereby reducing the use of barrier layers.

[0129] As an example, the nucleation layer 24 is located between the dielectric layer 20 and the main layer 221 of the first metal layer 22; the material of the nucleation layer 24 is the same as the material of the main layer 221 of the first metal layer 22;

[0130] The seed layer 25 is located between the main layer 221 of the first metal layer 22 and the main layer 233 of the second metal layer 23 ; the material of the seed layer 25 is the same as that of the main layer 233 of the second metal layer 23 .

[0131] As an example, the seed layer 25 can be formed by an electroplating process; the thickness of the seed layer 25 located in the contact hole 21 can account for about 2%~3% of the sum of the thicknesses of the second metal layer 23 and the seed layer 25. Preferably, in this embodiment, the thickness of the seed layer 25 can be between 150 angstroms and 200 angstroms.

[0132] As an example, the semiconductor interconnect structure further includes an adhesion barrier layer 26 , which is formed at least on the bottom edge and sidewalls of the contact hole 21 and is located between the dielectric layer 20 and the first metal layer 22 .

[0133] As an example, the adhesion barrier layer 26 may include a Ti layer, a TiN layer, or a Ti layer and a TiN layer; the thickness of the adhesion barrier layer 26 should not be too thick, and generally the thickness of the adhesion barrier layer 26 is between 100 angstroms and 200 angstroms.

[0134] It should be noted that the “between” mentioned above and subsequently refers to a numerical range including two endpoints. For example, the “between 100 angstroms and 200 angstroms” mentioned above refers to a numerical range including the two endpoints of 100 and 200.

[0135] In one example, if Fig. 9 As shown, the first metal layer 22 , the second metal layer 23 , the nucleation layer 24 , the seed layer 25 and the adhesion barrier layer 26 are not only located in the contact hole 21 , but also located on the upper surface of the dielectric layer 20 .

[0136] In another example, if Fig.10 As shown, the first metal layer 22, the second metal layer 23, the nucleation layer 24, the seed layer 25 and the adhesion barrier layer 26 are only located in the contact hole 21, that is, the upper surfaces of the first metal layer 22, the second metal layer 23, the nucleation layer 24, the seed layer 25 and the adhesion barrier layer 26 are all flush with the upper surface of the dielectric layer 20.

[0137] It should be noted that Fig.10 The second metal layer 23 is shown as a whole, and the first electroplating layer 231 and the second electroplating layer 232 are not specifically shown.

[0138] As an example, the first metal layer 22 directly covers the bottom and sidewalls of the second metal layer 23 , and the height-to-width ratio of the second metal layer 23 is smaller than the depth-to-width ratio of the contact hole 21 .

[0139] In summary, the present invention provides a semiconductor interconnect structure and a method for preparing the same, the method for preparing the semiconductor interconnect structure comprising the following steps: 1) providing a substrate having a dielectric layer formed on the substrate, and forming a contact hole in the dielectric layer; 2) forming a first metal layer at least on the bottom and sidewall of the contact hole by low-temperature chemical vapor deposition, the first metal layer comprising a nucleation layer; and 3) forming a second metal layer on the first metal layer by an electroplating method including low current density electroplating, the second metal layer comprising a seed layer, the resistivity of the second metal layer being less than the resistivity of the first metal layer. The present invention forms a first metal layer at a low temperature in the contact hole before forming a second metal layer, thereby avoiding the formation of holes in the metal layer filled in the contact hole, thereby effectively reducing the resistance value of the entire filled metal layer; the resistivity of the second metal layer is less than that of the first metal layer, which can further reduce the resistance value of the entire filled metal layer; the first metal layer can include tungsten, and the second metal layer can include copper. Now a tungsten layer is formed in the contact hole, and then a copper layer is formed in the contact hole. Tungsten and copper will not merge, and tungsten can act as a barrier layer to avoid copper from diffusing into the dielectric layer below the tungsten.

[0140] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor interconnect structure, characterized in that: include: 1) providing a substrate, wherein a dielectric layer is formed on the substrate, and a contact hole is formed in the dielectric layer; 2) forming a first metal layer at least on the bottom and sidewall of the contact hole by low temperature chemical vapor deposition, wherein the first metal layer includes a nucleation layer, and the material of the first metal layer includes tungsten; and 3) forming a second metal layer on the first metal layer by electroplating including low current density electroplating, wherein the second metal layer includes a seed layer, the resistivity of the second metal layer is less than the resistivity of the first metal layer, and the material of the second metal layer includes copper; The following steps are also included between step 1) and step 2): a step of forming an adhesion barrier layer at the bottom, sidewall and upper surface of the contact hole; in step 2), the first metal layer is formed on the surface of the adhesion barrier layer, and the first metal layer completely separates the second metal layer from the adhesion barrier layer.

2. The method for preparing a semiconductor interconnect structure according to claim 1, characterized in that: The contact hole formed in step 1) has a depth-to-width ratio greater than 5.

3. The method for preparing a semiconductor interconnect structure according to claim 1, characterized in that: In step 2), the reaction gas used to form the first metal layer includes tungsten hexafluoride and monosilane.

4. The method for preparing a semiconductor interconnect structure according to claim 1, characterized in that: In step 2), the temperature for forming the first metal layer is not higher than 300° C., and the thickness of the formed first metal layer is between 500 angstroms and 700 angstroms.

5. The method for preparing a semiconductor interconnect structure according to claim 1, wherein: Step 2) includes the following steps: 2-1) forming the nucleation layer at least on the bottom and sidewall of the contact hole; and 2-2) forming a main body layer of the first metal layer on the surface of the nucleation layer, wherein the material of the nucleation layer is the same as that of the main body layer of the first metal layer.

6. The method for preparing a semiconductor interconnect structure according to claim 5, characterized in that: The deposition period of the nucleation layer is between 8 and 10.

7. The method for preparing a semiconductor interconnect structure according to claim 6, characterized in that: The deposition was performed using diborane and tungsten hexafluoride as reaction gases for one deposition cycle at a temperature not higher than 300° C.; and the deposition was performed using monosilane and tungsten hexafluoride as reaction gases for 7 to 9 deposition cycles at a temperature not higher than 300° C.

8. The method for preparing a semiconductor interconnect structure according to claim 1, characterized in that: Step 3) includes the following steps: 3-1) forming the seed layer in the contact hole, wherein the seed layer is located on the upper surface of the first metal layer; 3-2) electroplating a first electroplating layer of a first thickness gradually from the upper surface of the seed layer upward in the contact hole under a first current density condition; and 3-3) continuing to electroplate a second electroplating layer of a second thickness on the upper surface of the first electroplating layer and the upper surface of the dielectric layer under a second current density condition, wherein the first current density is less than the second current density; wherein: The first electroplating layer and the second electroplating layer together constitute a main body layer of the second metal layer, and a material of the seed layer is the same as a material of the main body layer of the second metal layer.

9. The method for preparing a semiconductor interconnect structure according to claim 8, characterized in that: In step 3-2), the first current density is between 1.5A and 3A, and the first thickness is between 900 angstroms and 1100 angstroms; in step 3-3), the second current density is between 20A and 40A, and the second thickness is between 3500 angstroms and 4500 angstroms.

10. The method for preparing a semiconductor interconnect structure according to claim 8, characterized in that: The thickness of the seed layer is between 150 angstroms and 200 angstroms.

11. The method for preparing a semiconductor interconnect structure according to claim 1, characterized in that: In step 2), the first metal layer is also formed on the upper surface of the dielectric layer; after step 3), the step of removing the first metal layer and the second metal layer on the dielectric layer is also included.

12. The method for preparing a semiconductor interconnect structure according to any one of claims 1 to 11, characterized in that: In step 2), the ratio of the thickness of the first metal layer formed at the bottom of the contact hole to the depth of the contact hole is proportional to the aspect ratio of the contact hole.

13. The method for preparing a semiconductor interconnect structure according to any one of claims 1 to 11, characterized in that: In step 2), the thickness of the first metal layer formed in the contact hole accounts for 10% to 70% of the depth of the contact hole.

14. A semiconductor interconnect structure, characterized in that: The semiconductor interconnect structure comprises: substrate; A dielectric layer is located on the upper surface of the substrate, and a contact hole is formed in the dielectric layer; A first metal layer is formed on the bottom and sidewall of the contact hole by low-temperature chemical vapor deposition, wherein the first metal layer includes a nucleation layer, and the material of the first metal layer includes tungsten; and a second metal layer formed on the first metal layer by electroplating including low current density electroplating to fill the contact hole, the second metal layer including a seed layer, the resistivity of the second metal layer being less than the resistivity of the first metal layer, and the material of the second metal layer including copper; The adhesion barrier layer is formed at least on the bottom and sidewall of the contact hole and is located between the dielectric layer and the first metal layer. The first metal layer completely separates the second metal layer from the adhesion barrier layer.

15. The semiconductor interconnect structure according to claim 14, characterized in that: The aspect ratio of the contact hole is greater than 5.

16. The semiconductor interconnect structure according to claim 14, characterized in that The first metal layer also includes a main layer located on the surface of the nucleation layer, and the main layer of the first metal layer includes a tungsten metal layer; the second metal layer also includes a main layer located on the surface of the seed layer, and the main layer of the second metal layer includes a copper metal layer.

17. The semiconductor interconnect structure according to claim 14, wherein: The deposition temperature of the first metal layer is not higher than 300° C., and the thickness of the first metal layer is between 500 angstroms and 700 angstroms.

18. The semiconductor interconnect structure according to claim 16, wherein: The main body layer of the second metal layer includes a first electroplating layer and a second electroplating layer, the first electroplating layer is located on the upper surface of the first metal layer, and the second electroplating layer is at least located on the upper surface of the first electroplating layer.

19. The semiconductor interconnect structure according to claim 18, characterized in that: The first electroplating layer is formed by electroplating at a current density between 1.5A and 3A, and the thickness of the first electroplating layer is between 900A and 1100A; the second electroplating layer is formed by electroplating at a current density between 20A and 40A, and the thickness of the second electroplating layer is between 3500A and 4500A.

20. The semiconductor interconnect structure according to claim 14, wherein: The nucleation layer is located between the dielectric layer and the main body layer of the first metal layer; the material of the nucleation layer is the same as the material of the main body layer of the first metal layer; and The seed layer is located between the main body layer of the first metal layer and the main body layer of the second metal layer; the material of the seed layer is the same as the material of the main body layer of the second metal layer.

21. The semiconductor interconnect structure according to claim 20, characterized in that The thickness of the seed layer is between 150 angstroms and 200 angstroms.

22. The semiconductor interconnect structure according to claim 14, wherein: The thickness of the adhesion barrier layer is between 100 angstroms and 200 angstroms.

23. The semiconductor interconnect structure according to any one of claims 14 to 22, characterized in that: The first metal layer directly covers the bottom and sidewalls of the second metal layer, and the height-to-width ratio of the second metal layer is smaller than the depth-to-width ratio of the contact hole.

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