Display device

Abstract

A display device is provided. The display device includes: a substrate; a display area located above the substrate and including a plurality of pixels; a non-display area arranged outside the display area; a first power supply voltage line corresponding to one side of the display area in the non-display area and including a first conductive layer and a second conductive layer arranged above the first conductive layer; a second power supply voltage line spaced apart from the first power supply voltage line in the non-display area; a first dam unit surrounding the display area and overlapping the second power supply voltage line in a plan view; a second dam unit arranged outside the first dam unit; and a third dam unit arranged between the display area and the first dam unit and overlapping the first conductive layer and the second conductive layer of the first power supply voltage line in a plan view.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2018-0106749, filed on September 6, 2018, which is hereby incorporated by reference in its entirety. Technical Field

[0002] One or more exemplary embodiments relate to a display device, and more particularly, to a display device that achieves high quality while reducing an area of ​​an invalid space of the display device. Background Art

[0003] A display device is a device that visually displays data. In recent years, the purpose of display devices has become more diverse. In addition, since display devices are thin and lightweight, the scope of use of display devices has gradually been expanded.

[0004] The display device includes a substrate that is divided into a display area and a non-display area outside the display area. The non-display area, in which non-display elements such as a pad unit, a plurality of wirings, and a driving circuit unit are arranged, is an ineffective space where no image is realized. In recent years, the demand for reducing the ineffective space of the display device has increased. Summary of the invention

[0005] One or more exemplary embodiments include a display device that reduces dead space and provides high-quality images. However, it should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for limiting the disclosure.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented exemplary embodiments.

[0007] According to one or more exemplary embodiments, a display device includes: a substrate; a display area located above the substrate and including a plurality of pixels; a non-display area arranged outside the display area; a first power supply voltage line corresponding to one side of the display area in the non-display area and including a first conductive layer and a second conductive layer arranged above the first conductive layer; a second power supply voltage line spaced apart from the first power supply voltage line in the non-display area; a first dam unit surrounding the display area and overlapping the second power supply voltage line in a plan view; a second dam unit arranged outside the first dam unit; and a third dam unit arranged between the display area and the first dam unit and overlapping the first conductive layer and the second conductive layer of the first power supply voltage line in a plan view.

[0008] In an exemplary embodiment, the display device may further include: a first planarization layer arranged in the display area and the non-display area; a second planarization layer arranged above the first planarization layer; and a pixel defining layer arranged above the second planarization layer, wherein the third dam unit may include at least one of the pixel defining layer and the second planarization layer.

[0009] In an exemplary embodiment, a step difference may be provided in a top surface of an upper layer among the pixel defining layer and the second planarization layer.

[0010] In an exemplary embodiment, a bottom layer among the pixel defining layer and the second planarization layer may cover an end portion of the second conductive layer.

[0011] In an exemplary embodiment, the upper layer among the pixel defining layer and the second planarization layer may cover an end portion of the bottom layer.

[0012] In an exemplary embodiment, each of the plurality of pixels may include a first electrode, an emission layer arranged on the first electrode, and a second electrode arranged on the emission layer, and the second electrode may be commonly arranged in the plurality of pixels and may extend to the non-display area to cover a portion of the third dam unit.

[0013] In an exemplary embodiment, the display device may further include a thin film encapsulation layer including a first inorganic encapsulation layer covering the display area, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer, and the thin film encapsulation layer may cover the third dam unit.

[0014] In exemplary embodiments, the first inorganic encapsulating layer may directly contact the second inorganic encapsulating layer at the outside of the second dam unit.

[0015] In exemplary embodiments, a width of the second conductive layer may be smaller than a width of the first conductive layer.

[0016] In an exemplary embodiment, the second conductive layer may be provided in plurality and spaced apart from each other over the first conductive layer, and the third dam unit may wrap each of the plurality of spaced apart second conductive layers with an insulating layer to constitute a plurality of sub-dam units.

[0017] In exemplary embodiments, the insulating layer may be disposed between the first conductive layer and the second conductive layer, and the first conductive layer may be electrically connected to the second conductive layer through a contact hole defined by the insulating layer.

[0018] In an exemplary embodiment, the second power supply voltage line may include a third conductive layer and a fourth conductive layer disposed on the third conductive layer.

[0019] In exemplary embodiments, the insulating layer may be disposed between the third conductive layer and the fourth conductive layer, and the third conductive layer may be electrically connected to the fourth conductive layer through a contact hole defined by the insulating layer.

[0020] In exemplary embodiments, the first dam unit or the second dam unit may cover an end portion of the fourth conductive layer.

[0021] In an exemplary embodiment, the third conductive layer may include the same material as that of the first conductive layer, and the fourth conductive layer may include the same material as that of the second conductive layer.

[0022] In exemplary embodiments, a width of the fourth conductive layer may be greater than a width of the second conductive layer.

[0023] In an exemplary embodiment, a plurality of wirings spaced apart from each other may be disposed between the substrate and the first conductive layer and between the substrate and the third conductive layer in a direction crossing the first conductive layer and the third conductive layer.

[0024] In an exemplary embodiment, the display device may further include: a first planarization layer arranged in the display area and the non-display area; a second planarization layer arranged above the first planarization layer; and a pixel defining layer arranged above the second planarization layer, wherein the first dam unit and the second dam unit may include at least one of the pixel defining layer and the second planarization layer.

[0025] In exemplary embodiments, a height of the second dam unit may be greater than a height of the first dam unit.

[0026] According to one or more exemplary embodiments, a display device includes: a display area including a plurality of display elements; a non-display area arranged outside the display area; a terminal unit arranged at one end of the non-display area; a first power supply voltage line arranged between the display area and the terminal unit and including a first conductive layer and a second conductive layer arranged on the first conductive layer; a second power supply voltage line spaced apart from the first power supply voltage line and including a third conductive layer and a fourth conductive layer arranged on the third conductive layer; a first dam unit overlapping the second power supply voltage line in a plan view; a second dam unit arranged outside the first dam unit; a third dam unit arranged between the display area and the first dam unit and overlapping the first conductive layer and the second conductive layer of the first power supply voltage line in a plan view; and a thin film encapsulation layer including a first inorganic encapsulation layer covering the display area and the third dam unit, an organic encapsulation layer located on the first inorganic encapsulation layer, and a second inorganic encapsulation layer located on the organic encapsulation layer.

[0027] In an exemplary embodiment, the display device may further include: a first planarization layer arranged in the display area and the non-display area; a second planarization layer arranged above the first planarization layer; and a pixel defining layer arranged above the second planarization layer, wherein the third dam unit may include at least one of the pixel defining layer and the second planarization layer.

[0028] In an exemplary embodiment, a plurality of wirings spaced apart from each other may be disposed between the substrate and the first conductive layer and between the substrate and the third conductive layer in a direction facing the terminal unit.

[0029] In an exemplary embodiment, the third conductive layer may include the same material as that of the first conductive layer, and the fourth conductive layer may include the same material as that of the second conductive layer.

[0030] In an exemplary embodiment, the display device may further include a thin film transistor, and the first to third dam units may include an insulating layer pattern including the same material as that of an insulating layer disposed between the thin film transistor and the display element. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] These and / or other aspects will become apparent and more readily understood through the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a plan view of a display device according to an exemplary embodiment;

[0033] Figure 2A and Figure 2B is an equivalent circuit diagram of one pixel included in a display device according to an exemplary embodiment;

[0034] Figure 3 is along Figure 1 A cross-sectional view of a pixel included in a display device according to an exemplary embodiment is taken along line IIIA-IIIB;

[0035] Figure 4 is along Figure 1 A cross-sectional view taken along line IIIA-IIIB and line IVA-IVB;

[0036] Figure 5 is a cross-sectional view of a display device according to another exemplary embodiment;

[0037] Figure 6 is a cross-sectional view of a display device according to still another exemplary embodiment; and

[0038] Figure 7 and Figure 8 is a cross-sectional view of an exemplary embodiment in which a step difference is provided in a top surface of a third dam unit. DETAILED DESCRIPTION

[0039] Since the disclosure allows for various changes and many exemplary embodiments, the exemplary embodiments will be shown in the drawings and described in detail in the written description. When referring to the exemplary embodiments described with reference to the drawings, the disclosed effects and characteristics and methods for achieving the effects and characteristics will be apparent. However, the disclosure can be implemented in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein.

[0040] Hereinafter, the disclosure will be described more fully with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. When describing with reference to the accompanying drawings, like reference numerals in the drawings represent like or corresponding elements, and repeated description thereof will be omitted.

[0041] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements in the list.

[0043] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component.

[0044] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0045] It will also be understood that the terms “comprises / includes” and / or variations thereof used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0046] It will be understood that when a layer, region or component is referred to as being "on" or "over" another layer, region or component, the layer, region or component may be directly or indirectly disposed on or over the other layer, region or component. That is, for example, intervening layers, regions or components may be present.

[0047] For the convenience of explanation, the sizes of components in the drawings may be exaggerated. In other words, since the sizes and thicknesses of components in the drawings are arbitrarily shown for the convenience of explanation, the following exemplary embodiments are not limited thereto.

[0048] When a specific exemplary embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described order.

[0049] It will be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, the layer, region, or component may be "directly connected" to the other layer, region, or component, or may be "indirectly connected" to the other layer, region, or component with other layers, regions, or components located between them. For example, it will be understood that when a layer, region, or component is referred to as being "connected or electrically connected" to another layer, region, or component, the layer, region, or component may be "directly connected or directly electrically connected" to the other layer, region, or component, or may be "indirectly connected or indirectly electrically connected" to the other layer, region, or component with other layers, regions, or components located between them.

[0050] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0051] The display device is a device that displays an image and may be a liquid crystal display, an electrophoretic display, an organic light emitting display, an inorganic light emitting display, a field emission display, a surface conduction electron emission display, a plasma display, a cathode ray display, or the like.

[0052] Hereinafter, although an organic light emitting display device is exemplarily described as a display device according to an exemplary embodiment, the display device is not limited thereto, and the display device may be various other display devices.

[0053] Figure 1 is a plan view of a display device 1 according to an exemplary embodiment, Figure 2A and Figure 2B is an equivalent circuit diagram of one pixel included in the display device 1 according to an exemplary embodiment, Figure 3 is along Figure 1 A cross-sectional view of one pixel included in the display device 1 according to an exemplary embodiment is taken along line IIIA-IIIB, Figure 4 is along Figure 1 Cross-sectional views taken along line IIIA-IIIB and line IVA-IVB.

[0054] Reference Figure 1The display device 1 includes a display unit 1DA disposed on a substrate 100. The display unit 1DA includes pixels P connected to data lines DL extending in a first direction and scan lines SL extending in a second direction crossing the first direction. Each pixel P may be connected to a driving voltage line PL extending in the first direction.

[0055] One pixel P may emit, for example, red light, green light, blue light, or white light, and may include, for example, an organic light emitting diode ("OLED"). In addition, each pixel P may further include elements such as a thin film transistor and a capacitor.

[0056] The display unit 1DA provides a predetermined image by using light emitted from the pixels P, and defines a display area DA. The non-display area NDA is arranged outside the display area DA. For example, the non-display area NDA may surround the display area DA.

[0057] The non-display area NDA is an area where no pixels P are arranged, and thus does not provide an image. The first power supply voltage line 10 and the second power supply voltage line 20 having different voltages may be arranged in the non-display area NDA. The first power supply voltage line 10 may be arranged between the display area DA and the terminal unit 30.

[0058] The first power supply voltage line 10 may include a first main voltage line 11 and a first connection line 12. Each of the first main voltage line 11 and the first connection line 12 is arranged on one side of the display area DA. For example, in the case where the display area DA has a rectangular shape, the first main voltage line 11 may be arranged to correspond to one side of the display area DA. The first connection line 12 extends from the first main voltage line 11 in a first direction. Here, the first direction may be understood as a direction from the display area DA to the terminal unit 30 located near the edge of the substrate 100. The first connection line 12 may be connected to the first terminal 32 of the terminal unit 30.

[0059] The second power supply voltage line 20 may include a second main voltage line 21 and a second connection line 22, the second main voltage line 21 surrounds two opposite ends of the first main voltage line 11 and a portion of the display area DA, and the second connection line 22 extends from the second main voltage line 21 in the first direction. For example, in the case where the display area DA has a rectangular shape, the second main voltage line 21 may extend along two opposite ends of the first main voltage line 11 and the remaining sides of the display area DA except for one side adjacent to the first main voltage line 11. The second connection line 22 may extend in the first direction in parallel with the first connection line 12, and may be connected to the second terminal 33 of the terminal unit 30. The second power supply voltage line 20 may be bent to surround the opposite ends of the first main voltage line 11.

[0060] The terminal unit 30 is disposed at one end of the substrate 100 and includes a plurality of terminals 31, 32, and 33. The terminal unit 30 is not covered by the insulating layer and is exposed, and thus, can be electrically connected to a flexible printed circuit board or a controller (not shown) such as a driver IC chip.

[0061] The controller converts a plurality of image signals transmitted from the outside into a plurality of image data signals, and transmits the image data signals to the display area DA through the third terminal 31. In addition, the controller may receive a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, generate a control signal for controlling driving of a first gate driver and a second gate driver (not shown), and transmit the control signal to the first gate driver and the second gate driver, respectively, through terminals (not shown).

[0062] The controller may transmit different voltages to the first power voltage line 10 and the second power voltage line 20 through the first terminal 32 and the second terminal 33 , respectively.

[0063] The first power supply voltage line 10 can provide a first power supply voltage ELVDD (see FIG. Figure 2A and Figure 2B ), the second power supply voltage line 20 can provide the second power supply voltage ELVSS to each pixel P (see Figure 2A and Figure 2B ).

[0064] For example, the first power supply voltage ELVDD (see Figure 2A and Figure 2B ) can be supplied to each pixel P through the driving voltage line PL connected to the first power voltage line 10. The second power voltage ELVSS (see Figure 2A and Figure 2B ) is provided to the organic light emitting diode OLED of each pixel P (see Figure 2A and Figure 2B ) cathode. In this case, the second main voltage line 21 of the second power voltage line 20 may be connected to the cathode of the organic light emitting diode OLED in the non-display area NDA (see Figure 2A and Figure 2B )connect.

[0065] Although not shown, a scan driver configured to supply a scan signal to the scan line SL of each pixel P, a data driver configured to supply a data signal to the data line DL, etc. may be disposed in the non-display area NDA.

[0066] The first dam unit 110 and the second dam unit 120 may be spaced apart from each other in the non-display area NDA. Each of the first dam unit 110 and the second dam unit 120 surrounds the display area DA.

[0067] The first dam unit 110 and the second dam unit 120 serve as a dam portion configured to form a thin film encapsulation layer 400 (see FIG. Figure 3 and Figure 4 ) of the organic encapsulation layer 420 (see Figure 3 and Figure 4 ), while blocking the organic material from flowing into the edge of the substrate 100, thereby preventing the edge tail of the organic encapsulation layer 420 from being formed at the edge of the substrate 100.

[0068] In a plan view, the first dam unit 110 and the second dam unit 120 may overlap the second power supply voltage line 20. Therefore, the height of the first dam unit 110 and the second dam unit 120 may be raised by the third conductive layer 20a constituting the second power supply voltage line 20 (see FIG. Figure 4 ) and the fourth conductive layer 20b (see Figure 4 ) height. Figure 4 As shown in , the height of the second dam unit 120 may be greater than that of the first dam unit 110 .

[0069] It may happen that the organic encapsulation layer 420 flows over the first dam unit 110 and the second dam unit 120 to the edge of the substrate 100 despite the arrangement of the first dam unit 110 and the second dam unit 120. For example, in the case where the second dam unit 120 is arranged closer to the first dam unit 110 from the edge of the substrate 100 to reduce the area recognized as an invalid space (i.e., an area where an image is not implemented) by an external viewer, or in the case where the first dam unit 110 is arranged closer to the second dam unit 120 to increase the display area DA of the display unit 1DA, the interval between the first dam unit 110 and the second dam unit 120 may be reduced, and thus the organic encapsulation layer 420 may flow over the second dam unit 120 to the edge of the substrate 100. The edge tail formed by the overflow of the organic material may serve as a transmission path for external impurities, thereby causing defects in the organic light emitting diode OLED.

[0070] In the present exemplary embodiment, since the third dam unit 130 is arranged between the display unit 1DA and the first dam unit 110 so that the third dam unit 130 overlaps the first power supply voltage line 10 in a plan view, the reflow speed of the organic material can be reduced. Therefore, the edge tail of the organic material can be effectively prevented from being formed.

[0071] The third dam unit 130 may overlap the first power supply voltage line 10. Therefore, the height of the third dam unit 130 may be increased by the first conductive layer 10a constituting the first power supply voltage line 10 (see FIG. Figure 4 ) and the second conductive layer 10b (see Figure 4 )’s height.

[0072] Reference Figure 2AIn an exemplary embodiment, each pixel P includes a pixel circuit PC connected to a scan line SL and a data line DL and an organic light emitting diode OLED connected to the pixel circuit PC.

[0073] The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2 and a storage capacitor Cst. The switching thin film transistor T2 is connected to the scan line SL and the data line DL, and transmits a data signal Dm input through the data line DL to the driving thin film transistor T1 in response to a scan signal Sn input through the scan line SL.

[0074] The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between a voltage transmitted from the switching thin film transistor T2 and a first power source voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0075] The driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL through the organic light emitting diode OLED in response to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a predetermined brightness by using the driving current.

[0076] although Figure 2A A case where the pixel circuit PC includes two thin film transistors and one storage capacitor is shown, but the invention is not limited thereto.

[0077] Reference Figure 2B In another exemplary embodiment, the pixel circuit PC may include a driving thin film transistor T1 and a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, a first emission control thin film transistor T5, a second emission control thin film transistor T6, a second initialization thin film transistor T7 and a storage capacitor Cst.

[0078] Figure 2B It is shown that each pixel P includes signal lines SLn, SLn-1, EL and DL, initialization voltage line VL and driving voltage line PL, but the invention is not limited thereto. In another exemplary embodiment, at least one of the signal lines SLn, SLn-1, EL and DL and / or the initialization voltage line VL may be shared by adjacent pixels.

[0079] The drain electrode of the driving thin film transistor T1 may be electrically connected to the organic light emitting diode OLED via the second emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm in response to the switching operation of the switching thin film transistor T2 and transmits a driving current to the organic light emitting diode OLED.

[0080] The gate electrode of the switching thin film transistor T2 is connected to the first scan line SLn, and the source electrode of the switching thin film transistor T2 is connected to the data line DL. The drain electrode of the switching thin film transistor T2 may be connected to the source electrode of the driving thin film transistor T1 and connected to the driving voltage line PL via the first emission control thin film transistor T5.

[0081] The switching thin film transistor T2 is turned on in response to the first scan signal Sn transmitted through the first scan line SLn, and performs a switching operation of transmitting the data signal Dm transmitted through the data line DL to the source electrode of the driving thin film transistor T1.

[0082] The gate electrode of the compensation thin film transistor T3 may be connected to the first scan line SLn. The source electrode of the compensation thin film transistor T3 may be connected to the drain electrode of the driving thin film transistor T1, and connected to the pixel electrode of the organic light emitting diode OLED via the second emission control thin film transistor T6. The drain electrode of the compensation thin film transistor T3 may be connected to one electrode of the storage capacitor Cst, the source electrode of the first initialization thin film transistor T4, and the gate electrode of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the first scan signal Sn transmitted through the first scan line SLn, and the driving thin film transistor T1 is diode-connected by connecting the gate electrode of the driving thin film transistor T1 to the drain electrode of the driving thin film transistor T1.

[0083] The gate electrode of the first initialization thin film transistor T4 may be connected to the second scan line SLn-1 (also referred to as the previous scan line). The drain electrode of the first initialization thin film transistor T4 may be connected to the initialization voltage line VL. The source electrode of the first initialization thin film transistor T4 may be connected to one electrode of the storage capacitor Cst, the drain electrode of the compensation thin film transistor T3, and the gate electrode of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to the second scan signal Sn-1 transmitted through the second scan line SLn-1, and may perform an initialization operation of initializing the voltage of the gate electrode of the driving thin film transistor T1 by transmitting the initialization voltage VINT to the gate electrode of the driving thin film transistor T1.

[0084] The gate electrode of the first emission control thin film transistor T5 may be connected to the emission control line EL. The source electrode of the first emission control thin film transistor T5 may be connected to the driving voltage line PL. The drain electrode of the first emission control thin film transistor T5 is connected to the source electrode of the driving thin film transistor T1 and the drain electrode of the switching thin film transistor T2.

[0085] The gate electrode of the second emission control thin film transistor T6 may be connected to the emission control line EL. The source electrode of the second emission control thin film transistor T6 may be connected to the drain electrode of the driving thin film transistor T1 and the source electrode of the compensation thin film transistor T3. The drain electrode of the second emission control thin film transistor T6 may be electrically connected to the pixel electrode of the organic light emitting diode OLED. The first emission control thin film transistor T5 and the second emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal En transmitted through the emission control line EL, and the first power supply voltage ELVDD is transmitted to the organic light emitting diode OLED, so that the driving current flows through the organic light emitting diode OLED.

[0086] The gate electrode of the second initialization thin film transistor T7 may be connected to the second scan line SLn-1. The source electrode of the second initialization thin film transistor T7 may be connected to the pixel electrode of the organic light emitting diode OLED. The drain electrode of the second initialization thin film transistor T7 may be connected to the initialization voltage line VL. The second initialization thin film transistor T7 may be turned on in response to the second scan signal Sn-1 transmitted through the second scan line SLn-1 to initialize the pixel electrode of the organic light emitting diode OLED.

[0087] although Figure 2B The case where the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the second scan line SLn-1 is shown, but the present invention is not limited thereto. In another exemplary embodiment, the first initialization thin film transistor T4 may be connected to the second scan line SLn-1 (e.g., the previous scan line) and driven in response to the second scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to a separate signal line (e.g., the next scan line) and driven in response to a signal transmitted through the relevant scan line.

[0088] The other electrode of the storage capacitor Cst may be connected to the driving voltage line PL. One electrode of the storage capacitor Cst may be connected to the gate electrode of the driving thin film transistor T1, the drain electrode of the compensation thin film transistor T3, and the source electrode of the first initialization thin film transistor T4.

[0089] The counter electrode (eg, cathode) of the organic light emitting diode OLED receives the second power voltage ELVSS (or the common power voltage). The organic light emitting diode OLED receives the driving current from the driving thin film transistor T1 and emits light.

[0090] The pixel circuit PC according to the invention is not limited to the reference Figure 2A and Figure 2B The number of thin film transistors and storage capacitors and the circuit design described above can be variously changed.

[0091] Reference Figure 3 Describe the reference in more detail Figure 2A and Figure 2B The first and second thin film transistors T1 and T2 and the storage capacitor Cst of the pixel circuit PC of each pixel P are described.

[0092] Reference Figure 3 , a buffer layer 101 is disposed on the substrate 100 , and a driving thin film transistor T1 , a switching thin film transistor T2 , and a storage capacitor Cst are disposed above the buffer layer 101 .

[0093] The substrate 100 may include various materials, such as glass, metal, or plastic. In an exemplary embodiment, for example, the substrate 100 may include a flexible substrate including a polymer resin, such as polyethersulfone ("PES"), polyacrylate ("PAR"), polyetherimide ("PEI"), polyethylene naphthalate ("PEN"), polyethylene terephthalate ("PET"), polyphenylene sulfide ("PPS"), polyarylate, polyimide ("PI"), polycarbonate ("PC"), or cellulose acetate propionate ("CAP").

[0094] In an exemplary embodiment, the substrate configured to prevent the penetration of impurities includes SiO x and / or SiN x The buffer layer 101 may be disposed on the substrate 100 .

[0095] The driving thin film transistor T1 includes a driving semiconductor layer A1 and a driving gate electrode G1, and the switching thin film transistor T2 includes a switching semiconductor layer A2 and a switching gate electrode G2. The first gate insulating layer 103 is arranged between the driving semiconductor layer A1 and the driving gate electrode G1 and between the switching semiconductor layer A2 and the switching gate electrode G2. In an exemplary embodiment, the first gate insulating layer 103 may include a silicon-based material such as SiO x 、SiN x And SiON inorganic insulating materials.

[0096] In an exemplary embodiment, the driving semiconductor layer A1 or the switching semiconductor layer A2 may include amorphous silicon or polycrystalline silicon. In another exemplary embodiment, the driving semiconductor layer A1 or the switching semiconductor layer A2 may include an oxide containing at least one of In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, and Zn.

[0097] The driving semiconductor layer A1 includes a driving channel region overlapped with the driving gate electrode G1 and not doped with impurities, and a driving source region and a driving drain region respectively located in two opposite sides of the driving channel region and doped with impurities. The driving source electrode S1 and the driving drain electrode D1 may be connected to the driving source region and the driving drain region of the driving semiconductor layer A1, respectively.

[0098] The switching semiconductor layer A2 may include a switching channel region overlapped with the switching gate electrode G2 and not doped with impurities, and a switching source region and a switching drain region respectively located in two opposite sides of the switching channel region and doped with impurities. The switching source electrode S2 and the switching drain electrode D2 may be connected to the switching source region and the switching drain region of the switching semiconductor layer A2, respectively.

[0099] In an exemplary embodiment, the driving gate electrode G1 or the switching gate electrode G2 may include one of Mo, Al, Cu, and Ti, and include a single layer or a multi-layer.

[0100] In an exemplary embodiment, in a plan view, the storage capacitor Cst may be overlapped with the driving thin film transistor T1. In this case, the area of ​​the storage capacitor Cst and the driving thin film transistor T1 may be increased, and a high-quality image may be provided. For example, the driving gate electrode G1 may be used as a first storage capacitor plate CE1 of the storage capacitor Cst. The second storage capacitor plate CE2 may be overlapped with the first storage capacitor plate CE1, and the second gate insulating layer 105 may be disposed between the first storage capacitor plate CE1 and the second storage capacitor plate CE2. In an exemplary embodiment, the second gate insulating layer 105 may include a material such as SiO x 、SiN x And SiON inorganic insulating materials.

[0101] The driving thin film transistor T1 , the switching thin film transistor T2 , and the storage capacitor Cst may be covered by the interlayer insulating layer 107 .

[0102] In an exemplary embodiment, the interlayer insulating layer 107 may include SiON, SiO x and / or SiN x Inorganic material layer.

[0103] The data line DL may be disposed on the interlayer insulating layer 107, and may be connected to the switching semiconductor layer A2 of the switching thin film transistor T2 through a contact hole passing through the interlayer insulating layer 107. The data line DL may function as a switching source electrode S2.

[0104] The driving source electrode S1, the driving drain electrode D1, the switching source electrode S2, and the switching drain electrode D2 may be disposed on the interlayer insulating layer 107. Each of the switching source electrode S2 and the switching drain electrode D2 may be connected to the switching semiconductor layer A2 through a contact hole passing through the interlayer insulating layer 107. Each of the driving source electrode S1 and the driving drain electrode D1 may be connected to the driving semiconductor layer A1 through a contact hole passing through the interlayer insulating layer 107.

[0105] Meanwhile, the data line DL, the driving source electrode S1 , the driving drain electrode D1 , the switching source electrode S2 , and the switching drain electrode D2 may be covered by an inorganic protective layer (not shown).

[0106] In an exemplary embodiment, the inorganic protective layer (not shown) may include SiN x and SiO x The inorganic protective layer (not shown) may prevent some wirings exposed in the non-display area NDA (eg, wirings simultaneously formed during the same process as the manufacturing process of the data lines DL) from being damaged by an etchant used to pattern the pixel electrode 310.

[0107] The driving voltage line PL may be arranged on a layer different from that of the data line DL. In this specification, “A and B are said to be arranged on different layers” means that at least one insulating layer is arranged between A and B, and one of A and B is arranged below the at least one insulating layer, and the other of A and B is arranged on the at least one insulating layer. The first planarization layer 109 may be arranged between the driving voltage line PL and the data line DL, and the driving voltage line PL may be covered by the second planarization layer 111.

[0108] In an exemplary embodiment, the driving voltage line PL may be a single layer or multiple layers including at least one of Al, Cu, Ti, and alloys thereof. In an exemplary embodiment, the driving voltage line PL may include a triple layer structure of Ti / Al / Ti.

[0109] although Figure 3 A configuration in which the driving voltage line PL is arranged on the first planarization layer 109 is shown, but the present invention is not limited thereto. In another exemplary embodiment, the driving voltage line PL may be connected to an additional voltage line (not shown) disposed on the same layer as the data line DL through a through hole (not shown) defined in the second planarization layer 111, and resistance may be reduced.

[0110] The first planarization layer 109 and the second planarization layer 111 may include a single layer or a plurality of layers.

[0111] The first planarization layer 109 and the second planarization layer 111 may include an organic insulating material. In an exemplary embodiment, for example, the organic insulating material may include an imide-based polymer, a general polymer such as polymethyl methacrylate ("PMMA") or polystyrene ("PS"), a polymer derivative having a phenolic group, an acrylic polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, or a vinyl alcohol polymer.

[0112] In an exemplary embodiment, the first planarization layer 109 and the second planarization layer 111 may include an inorganic insulating material. For example, the inorganic insulating material may include SiON, SiO x and SiN x .

[0113] An organic light emitting diode OLED including a pixel electrode 310, an opposing electrode 330, and an intermediate layer 320 between the pixel electrode 310 and the opposing electrode 330 may be located on the second planarization layer 111. The intermediate layer 320 may include an emission layer.

[0114] The pixel electrode 310 is connected to a connection wiring CL provided on the first planarization layer 109 , and the connection wiring CL is connected to the driving drain electrode D1 of the driving thin film transistor T1 .

[0115] The pixel electrode 310 may include a transparent electrode or a reflective electrode.

[0116] In the case where the pixel electrode 310 includes a transparent electrode, the pixel electrode 310 may include a transparent conductive layer. In an exemplary embodiment, the transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In this case, in addition to the transparent conductive layer, the pixel electrode 310 may further include a semi-transmissive layer configured to improve light efficiency. In an exemplary embodiment, the semi-transmissive layer may include a thin layer ranging from several nanometers (nm) to tens of nm and containing at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, and Yb.

[0117] In the case where the pixel electrode 310 includes a reflective electrode, the pixel electrode 310 may include a reflective layer including at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and a mixture thereof, and a transparent conductive layer disposed on and / or below the reflective layer. In an exemplary embodiment, the transparent conductive layer may include ITO, IZO, ZnO, In 2 O 3, IGO and AZO.

[0118] The invention is not limited thereto, and the pixel electrode 310 may include various materials and have a single-layer structure or a multi-layer structure. Various modifications may be made.

[0119] The pixel defining layer 113 may be disposed on the pixel electrode 310 .

[0120] The pixel defining layer 113 defines a pixel by defining an opening exposing the pixel electrode 310. In addition, the pixel defining layer 113 may prevent arcing from occurring at an end of the pixel electrode 310 by increasing a distance between an edge of the pixel electrode 310 and the counter electrode 330. In an exemplary embodiment, the pixel defining layer 113 may include an organic material such as polyimide or hexamethyldisiloxane ("HMDSO").

[0121] The intermediate layer 320 may include a low molecular weight material or a polymer material.

[0122] In the case where the intermediate layer 320 includes a low molecular weight material, the intermediate layer 320 may have a structure in which a hole injection layer ("HIL"), a hole transport layer ("HTL"), an emission layer ("EML"), an electron transport layer ("ETL"), an electron injection layer ("EIL"), etc. are stacked in a single structure or a composite structure. In an exemplary embodiment, the intermediate layer 320 may include various organic materials such as copper phthalocyanine (CuPc), N,N'-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (NPB), and tris-8-hydroxyquinoline aluminum (Alq 3 ). The intermediate layer 320 may be formed by various methods such as vacuum deposition.

[0123] In the case where the intermediate layer 320 includes a polymer material, the intermediate layer 320 may generally have a structure including an HTL and an EML. In this case, the HTL may include poly(3,4-ethylenedioxythiophene) ("PEDOT"), and the EML may include a polymer material such as a polyphenylene vinylene (PPV)-based material and a polyfluorene-based material. The intermediate layer 320 may be formed by various methods such as screen printing, inkjet printing, and laser induced thermal imaging.

[0124] The intermediate layer 320 may be provided as a whole across the plurality of pixel electrodes 310 , or provided as a pattern layer corresponding to each of the plurality of pixel electrodes 310 .

[0125] The counter electrode 330 is disposed throughout the display area DA and may cover the display area DA. That is, the counter electrode 330 may be integrally provided throughout the plurality of organic light emitting diodes OLED and may correspond to the plurality of pixel electrodes 310 .

[0126] The counter electrode 330 is electrically connected to the second power supply voltage line 20 .

[0127] The counter electrode 330 may include a transparent electrode or a reflective electrode.

[0128] In the case where the counter electrode 330 includes a transparent electrode, for example, the counter electrode 330 may include at least one of Ag, Al, Mg, Li, Ca, Cu, LiF / Ca, LiF / Al, MgAg, and CaAg, and may include a thin layer having a thickness ranging from several nm to tens of nm.

[0129] In the case where the counter electrode 330 includes a reflective electrode, for example, the counter electrode 330 may include at least one of Ag, Al, Mg, Li, Ca, Cu, LiF / Ca, LiF / Al, MgAg, and CaAg. The configuration and material of the counter electrode 330 according to the invention are not limited thereto and may be variously modified.

[0130] Since the organic light emitting diode OLED may be easily damaged by external moisture or oxygen, the organic light emitting diode OLED may be protected by being covered by the thin film encapsulation layer 400 .

[0131] The thin film encapsulation layer 400 may cover the display area DA and extend throughout the display area DA. The thin film encapsulation layer 400 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. In an exemplary embodiment, the thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

[0132] In an exemplary embodiment, the first inorganic encapsulating layer 410 may cover the counter electrode 330 and include SiO x 、SiN x and / or SiON.

[0133] When necessary, other layers such as a capping layer (not shown) may be disposed between the first inorganic encapsulating layer 410 and the opposing electrode 330 .

[0134] For example, the capping layer (not shown) may include SiO 2 、SiN x 、ZnO 2 、TiO 2 、ZrO 2 、ITO、IZO、Alq 3 , CuPc, CBP, a-NPB and ZiO 2 At least one organic material or inorganic material in the organic light emitting diode OLED may be included to improve light efficiency. In another exemplary embodiment, the cap layer (not shown) may allow plasma resonance to occur in response to light emitted from the organic light emitting diode OLED. For example, the cap layer (not shown) may include nanoparticles.

[0135] Meanwhile, the capping layer (not shown) may prevent the organic light emitting diode OLED from being damaged by heat, plasma, etc. generated during a chemical vapor deposition (“CVD”) process or a sputtering process for forming the thin film encapsulation layer 400. In an exemplary embodiment, for example, the capping layer (not shown) may include an epoxy-based material including at least one of a bisphenol-type epoxy resin, an epoxy-type butadiene resin, a fluorine-type epoxy resin, and a novolac epoxy resin.

[0136] In addition, when necessary, a layer (not shown) including LiF may be disposed between the first inorganic encapsulation layer 410 and the capping layer (not shown).

[0137] Since the first inorganic encapsulation layer 410 is disposed along the structure therebelow, the top surface of the first inorganic encapsulation layer 410 is uneven. The organic encapsulation layer 420 flattens the top surface thereof by covering the first inorganic encapsulation layer 410. The top surface of the organic encapsulation layer 420 may be substantially flat at a portion of the top surface corresponding to the display area DA.

[0138] In an exemplary embodiment, the organic encapsulation layer 420 may include at least one of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and HMDSO.

[0139] In an exemplary embodiment, the second inorganic encapsulating layer 430 may cover the organic encapsulating layer 420 and include SiO x 、SiN x Because the second inorganic encapsulation layer 430 is in direct contact with the first inorganic encapsulation layer 410 in an edge region of the display device 1 (e.g., the second dam unit 120), the second inorganic encapsulation layer 430 may allow the organic encapsulation layer 420 not to be exposed to the outside of the display device 1 (more specifically, the outside of the second dam unit 120).

[0140] Reference Figure 4 In the region IVA-IVB, the buffer layer 101, the first gate insulating layer 103 and the second gate insulating layer 105 are arranged above the substrate 100 and extend from the driving circuit unit (not shown) to the terminal unit 30 (see Figure 1 A plurality of wirings SPL ) and spaced apart from each other are provided on the second gate insulating layer 105.

[0141] In exemplary embodiments, the plurality of wirings SPL may include the same material as that of the second storage capacitor plate CE2 of the storage capacitor Cst.

[0142] The interlayer insulating layer 107 covers the plurality of wirings SPL, and the first power supply voltage line 10 and the second power supply voltage line 20 are arranged on the interlayer insulating layer 107 .

[0143] The first power supply voltage line 10 has a structure in which a first conductive layer 10a and a second conductive layer 10b are stacked. The first conductive layer 10a is connected to the second conductive layer 10b through a contact hole defined by a first planarization layer 109, which is connected from the display unit 1DA (see Figure 1 ) extends and is disposed between the first conductive layer 10a and the second conductive layer 10b.

[0144] The plurality of second conductive layers 10 b are disposed above the first conductive layer 10 a , and a width W2 of the second conductive layer 10 b is smaller than a width W1 of the first conductive layer 10 a .

[0145] The first conductive layer 10 a may include the same material as that of the data line DL or the driving source electrode S1 and the driving drain electrode D1 of the driving thin film transistor T1 or the switching source electrode S2 and the switching drain electrode D2 of the switching thin film transistor T2 .

[0146] The second conductive layer 10b may include the same material as that of the driving voltage line PL or the connection wiring CL. In an exemplary embodiment, the second conductive layer 10b may have a stack structure of Ti / Al / Ti.

[0147] The second power supply voltage line 20 may have a structure in which a third conductive layer 20a and a fourth conductive layer 20b are stacked. The third conductive layer 20a is connected to the fourth conductive layer 20b through a contact hole defined by the first planarization layer 109, which is connected from the display unit 1DA (see Figure 1 ) extends and is disposed between the third conductive layer 20a and the fourth conductive layer 20b. The width of the fourth conductive layer 20b is greater than the width W2 of the second conductive layer 10b.

[0148] The third conductive layer 20a may include the same material as the first conductive layer 10a, and the fourth conductive layer 20b may include the same material as the second conductive layer 10b. In an exemplary embodiment, the fourth conductive layer 20b may have a stack structure of Ti / Al / Ti.

[0149] The third dam unit 130 is disposed at a position where the first conductive layer 10a overlaps the second conductive layer 10b in a plan view. The third dam unit 130 may include a first layer 111c including the same material as the second planarization layer 111 and a second layer 113c including the same material as the pixel defining layer 113.

[0150] The first layer 111 c of the third dam unit 130 covers all top and side surfaces of the second conductive layer 10 b to prevent the second conductive layer 10 b from contacting the opposite electrode 330 .

[0151] The second layer 113c of the third dam unit 130 is provided to cover the top and side surfaces of the first layer 111c. While patterning the second layer 113c during the photolithography process, a process margin is ensured and the height of the second layer 113c is stably ensured, and the second conductive layer 10b can be prevented from contacting the opposite electrode 330.

[0152] although Figure 4 A structure in which the third dam unit 130 includes both the first layer 111c and the second layer 113c is shown, but the invention is not limited thereto. The third dam unit 130 may include one of the first layer 111c and the second layer 113c. In this case, during a patterning process using a halftone mask, a selected layer may be set higher than the height of the second planarization layer 111 disposed in the display area DA.

[0153] From the display unit 1DA (see Figure 1 ) The extending counter electrode 330 covers a portion of the second layer 113c of the third dam unit 130. In the case where the area covered by the counter electrode 330 is large, it is beneficial to prevent the degradation of the organic light emitting diode OLED.

[0154] The first and second dam units 110 and 120 spaced apart from each other are spaced apart from the third dam unit 130 in a direction facing the end of the substrate 100. At least a portion of the first and second dam units 110 and 120 is disposed at a position where the third conductive layer 20a and the fourth conductive layer 20b overlap in a plan view.

[0155] The first dam unit 110 may include a first layer 111 a including the same material as that of the second planarization layer 111 and a second layer 113 a including the same material as that of the pixel defining layer 113 .

[0156] although Figure 4 The first layer 111a of the first dam unit 110 is shown to cover both the top and side surfaces of the fourth conductive layer 20b, but the invention is not limited thereto. The first layer 111c of the third dam unit 130 may cover one end of the second conductive layer 10b to prevent degradation of the second conductive layer 10b.

[0157] The second dam unit 120 may include a first layer 111b including the same material as the second planarization layer 111, a second layer 113b including the same material as the pixel defining layer 113, and a third layer 115b including the same material as the spacer (not shown).

[0158] The spacer (not shown) may protrude from the pixel defining layer 113 in the thickness direction of the thin film encapsulation layer 400, and is configured to prevent defects due to mask chopping, etc. during a manufacturing process. The spacer (not shown) may include the same material as that of the pixel defining layer 113, and may be provided to have a height different from that of the pixel defining layer 113 when the pixel defining layer 113 is formed by using a halftone mask.

[0159] The organic encapsulation layer 420 may be prevented from flowing over the second dam unit 120 , and mask chopping may be prevented by providing the second dam unit 120 higher than the first dam unit 110 .

[0160] The first dam unit 110 and the second dam unit 120 serve as dams for blocking the organic material from flowing into the edge of the substrate 100 when forming the organic encapsulation layer 420 including the organic material and constituting the thin film encapsulation layer 400. Therefore, the first dam unit 110 and the second dam unit 120 can prevent the edge tail of the organic encapsulation layer 420 from being formed at the edge of the substrate 100.

[0161] However, a situation may occur where the organic encapsulation layer 420 flows over the first dam unit 110 and the second dam unit 120 to the edge of the substrate 100 despite the arrangement of the first dam unit 110 and the second dam unit 120. For example, in a case where the second dam unit 120 is arranged closer to the first dam unit 110 from the edge of the substrate 100 to reduce an area recognized as an invalid space (i.e., a region where an image is not realized) by an external viewer, or in a case where the first dam unit 110 is arranged closer to the second dam unit 120 to increase the display unit 1DA, the interval between the first dam unit 110 and the second dam unit 120 may be reduced, and thus the organic encapsulation layer 420 may flow over the second dam unit 120 to the edge of the substrate 100.

[0162] In the present exemplary embodiment, since the third dam unit 130 is arranged between the display unit 1DA and the first dam unit 110 so that the third dam unit 130 overlaps the first power supply voltage line 10 in a plan view, the reflow speed of the organic material can be reduced. Therefore, the edge tail of the organic material can be effectively prevented from being formed.

[0163] Meanwhile, in order to reduce the area of ​​the invalid space, an alternative solution may be provided to reduce the width of the first power supply voltage line 10 and the second power supply voltage line 20. However, if the width of the first power supply voltage line 10 and the second power supply voltage line 20 is reduced, the resistance value of the first power supply voltage line 10 and the second power supply voltage line 20 will increase.

[0164] In this exemplary embodiment, since the first power supply voltage line 10 has a two-layer structure in which the first conductive layer 10a and the second conductive layer 10b are stacked, and the second power supply voltage line 20 has a two-layer structure in which the third conductive layer 20a and the fourth conductive layer 20b are stacked, the resistance value thereof can be reduced, effectively preventing the voltage drop inside the first power supply voltage line 10 or the second power supply voltage line 20, thereby providing a high-quality image.

[0165] Figure 5 is a cross-sectional view of a display device 2 according to another exemplary embodiment. Figure 5 In, due to Figure 4 The same reference numerals as in the accompanying drawings denote the same components, and thus a repeated description thereof will be omitted, and differences will be mainly described.

[0166] Reference Figure 5 , a buffer layer 101 and a first gate insulating layer 103 are arranged on the substrate 100. From the driving circuit unit (not shown) toward the terminal unit 30 (see Figure 1 ) and are spaced apart from each other are arranged on the first gate insulating layer 103.

[0167] The plurality of wirings SPL are covered by the second gate insulating layer 105 and the interlayer insulating layer 107 , and the first power supply voltage line 10 and the second power supply voltage line 20 are arranged on the interlayer insulating layer 107 .

[0168] The present exemplary embodiment is different from the above-described exemplary embodiments in that a plurality of wirings SPL are arranged on the first gate insulating layer 103 instead of on the second gate insulating layer 105 .

[0169] The driving circuit unit (not shown) may include a gate driving circuit unit configured to transmit a driving gate signal to a pixel and a data driving circuit unit configured to transmit a data signal to a pixel. The driving circuit unit (not shown) may be arranged in the display unit 1DA (see Figure 1 ) and the first dam unit 110. A wiring extending from a driving circuit unit (not shown) may be connected to the terminal unit 30 through a wiring SPL.

[0170] In the present exemplary embodiment, the wiring SPL may include the same material as that of the first storage capacitor plate CE1 of the storage capacitor Cst serving as the driving gate electrode G1 of the driving thin film transistor T1 or the switching gate electrode G2 of the switching thin film transistor T2 .

[0171] and Figure 4 Compared to the above exemplary embodiment shown in , in the present exemplary embodiment, mutual interference of electrical signals between conductive layers can be reduced by adding the second gate insulating layer 105 to the insulating space between the wiring SPL and the first conductive layer 10a of the first power supply voltage line 10 and between the wiring SPL and the third conductive layer 20a of the second power supply voltage line 20. In the exemplary embodiment, the wiring SPL can be arranged in a direction crossing the first conductive layer 10a and the third conductive layer 20a.

[0172] Figure 6 is a cross-sectional view of a display device 3 according to yet another exemplary embodiment. Figure 6 In, due to Figure 4 The same reference numerals as in the accompanying drawings denote the same components, and thus a repeated description thereof will be omitted, and differences will be mainly described.

[0173] Reference Figure 6 , a buffer layer 101, a first gate insulating layer 103 and a second gate insulating layer 105 are arranged on the substrate 100. From the driving circuit unit (not shown) toward the terminal unit 30 (see Figure 1 ) and are spaced apart from each other are arranged on the second gate insulating layer 105.

[0174] The plurality of wirings SPL are covered with the interlayer insulating layer 107 , and the first power supply voltage line 10 and the second power supply voltage line 20 are arranged on the interlayer insulating layer 107 .

[0175] The first power supply voltage line 10 has a structure in which a first conductive layer 10a and a second conductive layer 10b are stacked. Although the configuration in which a plurality of second conductive layers 10b are provided over the first conductive layer 10a is similar to Figure 4 The present exemplary embodiment is the same as the above exemplary embodiment shown in , but the present exemplary embodiment is different from the above exemplary embodiment in the number of second conductive layers 10b arranged in the region serving as the third dam unit 130. Figure 4 In the above exemplary embodiment shown in , one second conductive layer 10b is arranged in the region used as the third dam unit 130. In contrast, two second conductive layers 10b are arranged in the present exemplary embodiment. That is, in the present exemplary embodiment, the third dam unit 130 includes a first sub-dam unit 130-1 and a second sub-dam unit 130-2.

[0176] The widths W21 and W22 of the second conductive layer 10 b are respectively smaller than the width W1 of the first conductive layer 10 a .

[0177] The first layer 111 c - 1 of the first sub-dam unit 130 - 1 may prevent the second conductive layer 10 b from contacting the opposite electrode 330 by covering all top and side surfaces of the second conductive layer 10 b .

[0178] The second layer 113c-1 of the first sub-dam unit 130-1 is configured to cover the top surface and the side surface of the first layer 111c-1. While patterning the second layer 113c-1 during the photolithography process, a process margin is ensured and the height of the second layer 113c-1 is stably ensured, so that the second conductive layer 10b can be effectively prevented from contacting the counter electrode 330.

[0179] The first layer 111 c - 2 of the second sub-dam unit 130 - 2 may prevent the second conductive layer 10 b from contacting the opposite electrode 330 by covering all top and side surfaces of the second conductive layer 10 b .

[0180] The second layer 113c-2 of the second sub-dam unit 130-2 is configured to cover the top surface and the side surface of the first layer 111c-2. While patterning the second layer 113c-2 during the photolithography process, a process margin is ensured and the height of the second layer 113c-2 is stably ensured, so that the second conductive layer 10b can be effectively prevented from contacting the counter electrode 330.

[0181] The present exemplary embodiment may prevent an increase in the area of ​​the invalid space by dividing the second conductive layer 10 b and configuring the third dam unit 130 to have a plurality of sub-dam units, thereby further reducing the reflow speed of the organic material.

[0182] although Figure 6 It is shown that two sub-dam units constituting the third dam unit 130 are provided, but the invention is not limited thereto, and in another exemplary embodiment, the third dam unit 130 may include three or more sub-dam units.

[0183] Figure 7 and Figure 8 is a cross-sectional view of an exemplary embodiment in which a step difference is provided in a top surface of a third dam unit.

[0184] Reference Figure 7 , a step difference is provided in the second layer 113c-3 disposed on the first layer 111c-3 of the third sub-dam unit 130-3, and thus the second layer 113c-3 is divided into two parts.

[0185] The first layer 111c-3 may include the second planarization layer 111 (see Figure 4 , Figure 5 and Figure 6 ) of the same material, although not in Figure 7 However, the first layer 111c-3 covers the first power supply voltage line 10 (see Figure 4 , Figure 5 and Figure 6 ) of the second conductive layer 10b (see Figure 4 , Figure 5 and Figure 6 )'s top and side surfaces.

[0186] As described above, the second layer 113c-3 includes the pixel defining layer 113 (see Figure 4 , Figure 5 and Figure 6 ), and the second layer 113c-3 is divided into two parts by providing the second layer 113c-3 on one first layer 111c-3, so that the second layer 113c-3 has a step difference. The step difference can be provided by using, for example, a photolithography process.

[0187] although Figure 7 The case where the step difference of the second layer 113c-3 divided into two parts is the same is shown, but the present invention is not limited thereto. The shape of the step difference may be variously changed.

[0188] In addition, despite Figure 7 A structure in which a step difference is provided so that a portion of the top surface of the first layer 111c-3 is exposed is shown, but the invention is not limited thereto. In another exemplary embodiment, a step difference may be provided so that the top surface of the first layer 111c-3 is not exposed, and a portion of the second layer 113c-3 remains on the top surface of the first layer 111c-3.

[0189] The counter electrode 330 covers a portion of the second layer 113 c - 3 , and the first inorganic encapsulating layer 410 is disposed on the counter electrode 330 .

[0190] Similar to the above exemplary embodiment, the first inorganic encapsulation layer 410 may completely cover the third sub-dam unit 130-3 and extend to the second dam unit 120 (see FIG. 1 ). Figure 4 , Figure 5 and Figure 6 ) end.

[0191] When the organic encapsulation layer 420 including an organic material is formed after the first inorganic encapsulation layer 410 is formed (see Figure 4 , Figure 5 and Figure 6 ), the reflow speed of the organic material can be reduced due to the step difference set in the second layer 113c-3. Therefore, the edge tail of the organic material can be effectively prevented from being formed. Therefore, the area of ​​the invalid space can be effectively prevented from being increased.

[0192] Reference Figure 8 , a step difference is provided in the second layer 113c-4 disposed on the first layer 111c-4 of the fourth sub-dam unit 130-4, and thus the second layer 113c-4 is divided into four parts.

[0193] and Figure 7 compared to, Figure 8 An exemplary embodiment of Figure 7 The difference lies in the number of divided parts of the second layer 113c-4, while the rest of the structure is the same.

[0194] By forming a greater number of step differences in the second layer 113c-4, the reflow speed of the organic material can be further reduced. Therefore, the edge tail of the organic material can be effectively prevented from being formed. Therefore, the area of ​​the invalid space can be prevented from increasing.

[0195] although Figure 7 and Figure 8 1 shows an exemplary embodiment in which a step difference is provided in the third dam units 130-3 and 130-4, but this exemplary embodiment may be applied to the first dam unit 110 (see Figure 4 , Figure 5 and Figure 6 ) and the second dam unit 120 (see Figure 4 , Figure 5 and Figure 6 ). For example, in another exemplary embodiment, by also in the second layer 113a (see Figure 4 , Figure 5 and Figure 6 ) and in the third layer 115b (see Figure 4 , Figure 5 and Figure 6 ) is provided with a step difference, which can further reduce the reflux speed of the organic material. The second layer 113a is the first dam unit 110 (see Figure 4 , Figure 5 and Figure 6 ) is the top layer, and the third layer 115b is the second dam unit 120 (see Figure 4 , Figure 5 and Figure 6 ) on the top layer.

[0196] According to an exemplary embodiment, the dead space can be reduced by arranging the third dam unit between the display unit and the first dam unit so that the third dam unit overlaps the first power supply voltage line and thus reduces the reflow speed of the organic material. In addition, a display device that provides a high-quality image through a power supply voltage line with a reduced voltage drop can be implemented. However, the scope of the invention is not limited by this effect.

[0197] Although the disclosure has been described with reference to the exemplary embodiments shown in the drawings, this is provided by way of example only, and those skilled in the art will understand that various changes in form and details and their equivalents may be made therein without departing from the spirit and scope of the present disclosure as defined by the claims.

Claims

1. A display device, the display device include: substrate; A display area, located above the substrate and comprising a plurality of pixels; a non-display area, arranged outside the display area; a first power supply voltage line corresponding to one side of the display area in the non-display area and comprising a first conductive layer and a second conductive layer arranged above the first conductive layer; a second power supply voltage line spaced apart from the first power supply voltage line in the non-display area; a first dam unit surrounding the display area and overlapping the second power supply voltage line in a plan view; a second dam unit disposed outside the first dam unit and overlapping the second power supply voltage line in a plan view; as well as A third dam unit is disposed between the display area and the first dam unit and overlaps the first conductive layer and the second conductive layer of the first power supply voltage line in a plan view.

2. The display device according to claim 1, wherein the display device further comprises: include: A first planarization layer is arranged in the display area and the non-display area; a second planarization layer, arranged above the first planarization layer; as well as A pixel defining layer is arranged above the second planarization layer, Wherein, the third dam unit includes at least one of the pixel defining layer and the second planarization layer.

3. The display device according to claim 2, in, A step difference is provided in a top surface of an upper layer among the pixel defining layer and the second planarization layer.

4. The display device according to claim 2, in, The bottom layer among the pixel defining layer and the second planarization layer covers the end of the second conductive layer.

5. The display device according to claim 4, in, An upper layer among the pixel defining layer and the second planarization layer covers an end portion of the bottom layer.

6. The display device according to claim 1, in, Each of the plurality of pixels includes a first electrode, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer, and The second electrode is commonly disposed in the plurality of pixels, and extends to the non-display area to cover a portion of the third dam unit.

7. The display device according to claim 1, further comprising a thin film encapsulation layer, wherein the thin film encapsulation layer comprises a first inorganic encapsulation layer covering the display area, an organic encapsulation layer located on the first inorganic encapsulation layer, and a second inorganic encapsulation layer located on the organic encapsulation layer, in, The thin film encapsulation layer covers the third dam unit.

8. The display device according to claim 7, in, The first inorganic encapsulating layer directly contacts the second inorganic encapsulating layer outside the second dam unit.

9. The display device according to claim 1, in, The width of the second conductive layer is smaller than the width of the first conductive layer.

10. The display device according to claim 9, in, The second conductive layer is provided in plurality, and the second conductive layers are spaced apart from each other above the first conductive layer, and The third dam unit covers each of the plurality of second conductive layers spaced apart from each other with an insulating layer to constitute a plurality of sub-dam units.

11. The display device according to claim 1, in, An insulating layer is disposed between the first conductive layer and the second conductive layer, and The first conductive layer is electrically connected to the second conductive layer through a contact hole defined by the insulating layer.

12. The display device according to claim 1, in, The second power supply voltage line includes a third conductive layer and a fourth conductive layer disposed on the third conductive layer.

13. The display device according to claim 12, in, An insulating layer is arranged between the third conductive layer and the fourth conductive layer, and The third conductive layer is electrically connected to the fourth conductive layer through a contact hole defined by the insulating layer.

14. The display device according to claim 12, in, The first dam unit or the second dam unit covers an end portion of the fourth conductive layer.

15. The display device according to claim 12, in, The third conductive layer includes the same material as that of the first conductive layer, and the fourth conductive layer includes the same material as that of the second conductive layer.

16. The display device according to claim 12, in, The width of the fourth conductive layer is greater than the width of the second conductive layer.

17. The display device according to claim 12, in, A plurality of wirings spaced apart from each other are provided between the substrate and the first conductive layer and between the substrate and the third conductive layer in a direction crossing the first conductive layer and the third conductive layer.

18. The display device according to claim 1, further comprising: include: A first planarization layer is arranged in the display area and the non-display area; a second planarization layer, arranged above the first planarization layer; as well as A pixel defining layer is arranged above the second planarization layer, The first dam unit and the second dam unit include at least one of the pixel defining layer and the second planarization layer.

19. The display device according to claim 1, in, The second dam unit has a height greater than that of the first dam unit.

20. A display device, the display device include: A display area including a plurality of display elements; a non-display area, arranged outside the display area; a terminal unit, arranged at one end of the non-display area; a first power supply voltage line, arranged between the display area and the terminal unit, and comprising a first conductive layer and a second conductive layer arranged on the first conductive layer; a second power supply voltage line spaced apart from the first power supply voltage line and comprising a third conductive layer and a fourth conductive layer disposed on the third conductive layer; a first dam unit overlapping the second power supply voltage line in a plan view; a second dam unit disposed outside the first dam unit and overlapping the second power supply voltage line in a plan view; a third dam unit disposed between the display area and the first dam unit and overlapping the first conductive layer and the second conductive layer of the first power supply voltage line in a plan view; as well as The thin film encapsulation layer includes a first inorganic encapsulation layer covering the display area and the third dam unit, an organic encapsulation layer located on the first inorganic encapsulation layer, and a second inorganic encapsulation layer located on the organic encapsulation layer.

21. The display device according to claim 20, wherein the display device further comprises: include: A first planarization layer is arranged in the display area and the non-display area; a second planarization layer, arranged above the first planarization layer; as well as A pixel defining layer is arranged above the second planarization layer, Wherein, the third dam unit includes at least one of the pixel defining layer and the second planarization layer.

22. The display device according to claim 20, in, A plurality of wirings spaced apart from each other are provided between a substrate and the first conductive layer and between the substrate and the third conductive layer in a direction facing the terminal unit.

23. The display device according to claim 20, in, The third conductive layer includes the same material as that of the first conductive layer, and the fourth conductive layer includes the same material as that of the second conductive layer.

24. The display device according to claim 20, further comprising a thin film transistor, in, The first to third dam units include an insulating layer pattern including a material that is the same as a material of an insulating layer disposed between the thin film transistor and the display element.

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