Display device

Abstract

This application relates to a display device. The display device includes a substrate, pixels, scan lines, data lines, and power lines. Among them, each pixel includes at least one transistor, a storage capacitor connected to the at least one transistor, and a light-emitting element connected to the at least one transistor. The scan lines are connected to each pixel among the pixels, the data lines are connected to each pixel among the pixels, and the power lines supply a first power supply voltage to the light-emitting elements. The power lines include a first conductive pattern, a second conductive pattern, and a third conductive pattern, where: the first conductive pattern extends in a first direction and is disposed on a first insulating intermediate layer; the second conductive pattern extends in the first direction, is disposed on a second insulating intermediate layer, and is connected to the first conductive pattern via a first contact hole; the third conductive pattern extends in a second direction, is disposed on a third insulating intermediate layer, and is connected to the second conductive pattern via a second contact hole.

Description

[0001] Cross - reference to Related Applications

[0002] This application claims priority and all benefits arising therefrom to Korean Patent Application No. 10 - 2018 - 0116601, filed on September 28, 2018, the content of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to a display device, and more particularly, to an organic light - emitting display device. Background Art

[0004] Among display devices, an organic light - emitting display device generally includes two electrodes and an organic light - emitting layer disposed between the two electrodes. In an organic light - emitting display device, electrons injected from one of the two electrodes and holes injected from the other of the two electrodes recombine in the organic light - emitting layer to form excitons, and the excitons emit light through energy emission.

[0005] When the size, resolution, and desired driving frequency of a display device increase, the resistance - capacitance (“RC”) delay increases. When the size and desired brightness of a display device increase, the voltage (“IR”) drop increases. Recently, research has been conducted on display panel structures for preventing RC delay and IR drop. Summary of the Invention

[0006] Exemplary embodiments provide a display device having improved line resistance of power lines.

[0007] Exemplary embodiments also provide a display device having improved resistance - capacitance (“RC”) delay of scan signals.

[0008] In an exemplary embodiment of the present invention, a display device is provided. The display device includes a substrate, a plurality of pixels, a plurality of scan lines, data lines, and power lines, wherein: the substrate includes a display area and a non-display area; the plurality of pixels are located in the display area, and each of the plurality of pixels includes at least one transistor, a storage capacitor connected to the at least one transistor, and a light-emitting element connected to the at least one transistor; the plurality of scan lines are connected to each of the plurality of pixels, and the plurality of scan lines extend in a first direction; the data lines are connected to each of the plurality of pixels, and the data lines extend in a second direction; the power lines supply a first power voltage to the light-emitting elements. Wherein, the at least one transistor includes an active pattern disposed on the substrate, a source electrode and a drain electrode respectively connected to the active pattern, a gate electrode disposed on the active pattern, an insulating intermediate layer, and a protective layer disposed on the insulating intermediate layer. A gate insulating layer overlapping the active pattern is interposed between the gate electrode and the active pattern. The insulating intermediate layer includes a first insulating intermediate layer, a second insulating intermediate layer, and a third insulating intermediate layer that cover the gate electrode and are sequentially stacked. Wherein, the power lines include a first conductive pattern extending in the first direction, a second conductive pattern extending in the first direction, and a third conductive pattern extending in the second direction. The first conductive pattern is disposed on the first insulating intermediate layer, the second conductive pattern is disposed on the second insulating intermediate layer, the second conductive pattern is connected to the first conductive pattern via a first contact hole, the third conductive pattern is disposed on the third insulating intermediate layer, and the third conductive pattern is connected to the second conductive pattern via a second contact hole.

[0009] In an exemplary embodiment, the storage capacitor may include a lower electrode disposed in the same layer as the gate electrode and an upper electrode overlapping the lower electrode. The upper electrode is disposed on the first insulating intermediate layer.

[0010] In an exemplary embodiment, the first conductive pattern and the second conductive pattern may overlap at least a part of the lower electrode of the storage capacitor.

[0011] In an exemplary embodiment, the area of the first conductive pattern overlapping the lower electrode may be larger than the area of the second conductive pattern overlapping the lower electrode.

[0012] In an exemplary embodiment, in a plan view, no opening may be defined in the upper electrode.

[0013] In an exemplary embodiment, through the connection of the first conductive pattern to the third conductive pattern, the power lines may have a mesh structure.

[0014] In an exemplary embodiment, at least one of the scan lines may be disposed in the same layer as the second conductive pattern and connected to the gate electrode.

[0015] In an exemplary embodiment, the gate electrode may be a conductive pattern having an island shape.

[0016] In an exemplary embodiment, at least one of the scan lines may include an aluminum alloy.

[0017] In an exemplary embodiment, the display device may further include an emission control line connected to each of the pixels, and the emission control line extends in a first direction.

[0018] In an exemplary embodiment, the emission control line may be disposed in the same layer as the gate electrode.

[0019] In an exemplary embodiment, the emission control line may be disposed in the same layer as the second conductive pattern.

[0020] In an exemplary embodiment, the display device may further include an initialization line that supplies an initialization voltage to the pixels. The initialization line may include a first initialization conductive pattern disposed in the same layer as the second conductive pattern, and the first initialization conductive pattern extends in a first direction.

[0021] In an exemplary embodiment, the initialization line may further include a second initialization conductive pattern disposed in the same layer as the third conductive pattern, and the second initialization conductive pattern extends in a second direction.

[0022] In an exemplary embodiment, the display device may further include a shielding pattern disposed in the same layer as the first conductive pattern, and the shielding pattern is connected to the first initialization conductive pattern.

[0023] In an exemplary embodiment, at least one transistor may include a driving transistor that controls a driving current flowing through the light-emitting element. In a plan view, the shielding pattern may include a portion located between the data line and the gate node of the driving transistor.

[0024] In another exemplary embodiment of the present invention, a display device is provided. The display device includes a substrate, a plurality of pixels, a plurality of scan lines, data lines, and power lines, wherein: the substrate includes a display area and a non-display area; the plurality of pixels are located in the display area, and each of the plurality of pixels includes at least one transistor, a storage capacitor connected to the at least one transistor, and a light-emitting element connected to the at least one transistor; the plurality of scan lines are connected to each of the pixels, and the plurality of scan lines extend in a first direction; the data lines are connected to each of the pixels, and the data lines extend in a second direction; the power lines supply a first power supply voltage to the light-emitting elements, wherein at least one transistor includes an active pattern disposed on the substrate, a source electrode and a drain electrode each connected to the active pattern, a gate electrode disposed on the active pattern, an insulating intermediate layer, and a protective layer disposed on the insulating intermediate layer. A gate insulating layer overlapping the active pattern is interposed between the gate electrode and the active pattern. The insulating intermediate layer includes a first insulating intermediate layer, a second insulating intermediate layer, and a third insulating intermediate layer that cover the gate electrode and are sequentially stacked. Among them, at least one of the scan lines is disposed on the second insulating intermediate layer and is connected to the gate electrode via a contact hole.

[0025] In an exemplary embodiment, the gate electrode connected to the at least one of the scan lines may be a conductive pattern having an island shape.

[0026] In an exemplary embodiment, the power line may include a first conductive pattern extending in the first direction, a second conductive pattern extending in the first direction, and a third conductive pattern extending in the second direction. Among them, the first conductive pattern is disposed on the first insulating intermediate layer, the second conductive pattern is disposed on the second insulating intermediate layer, the second conductive pattern is connected to the first conductive pattern, the third conductive pattern is disposed on the third insulating intermediate layer, and the third conductive pattern is connected to the second conductive pattern.

[0027] In an exemplary embodiment, the area of the first conductive pattern may be larger than the area of the second conductive pattern.

[0028] The resistance of the second conductive pattern and the third conductive pattern may be smaller than the resistance of the first conductive pattern.

[0029] In an exemplary embodiment, the display device may further include an emission control line connected to each of the pixels, and the emission control line extends in the first direction.

[0030] In an exemplary embodiment, the emission control line may be disposed in the same layer as the gate electrode.

[0031] In an exemplary embodiment, the storage capacitor may include a lower electrode disposed in the same layer as the gate electrode and an upper electrode overlapping the lower electrode. The upper electrode is disposed on the first insulating intermediate layer. In a plan view, no opening is defined in the upper electrode.

[0032] In an exemplary embodiment, the display device may further include an initialization line that supplies an initialization voltage to the pixels. The initialization line may include a first initialization conductive pattern disposed on the second insulating intermediate layer and a second initialization conductive pattern disposed on the third insulating intermediate layer. The first initialization conductive pattern extends in a first direction, and the second initialization conductive pattern extends in a second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings.

[0034] Figure 1 is a block diagram showing an exemplary embodiment of a display device according to the present invention.

[0035] Figure 2 is a circuit diagram showing an example of a pixel included in the Figure 1 display device.

[0036] Figure 3 is a plan view showing an example of the Figure 2 pixel.

[0037] Figure 4 is a Figure 3 cross-sectional view taken along line I-I' of the pixel.

[0038] Figure 5 is a Figure 3 cross-sectional view taken along line II-II' of the pixel.

[0039] Figure 6 is a Figure 3 cross-sectional view taken along line III-III' of the pixel.

[0040] Figure 7 is a plan view showing an Figures 3 to 6 active pattern, source electrode, and drain electrode shown in

[0041] Figure 8 is a plan view showing a Figures 3 to 6 gate electrode and emission control line shown in

[0042] Figure 9 is a plan view showing a Figures 3 to 6 first conductive pattern of a power line shown in

[0043] Figure 10 is a plan view showing a Figures 3 to 6 first scan line to third scan line, second conductive pattern of a power line, and first initialization line shown in

[0044] Figure 11 is a plan view showing aFigures 3 to 6 A plan view of a third conductive pattern of a data line, a second initialization line, and a power line shown in

[0045] Figure 12 is a plan view showing Figure 2 another example of a pixel.

[0046] Figure 13 is a cross-sectional view taken along line IV-IV' of Figure 12

[0047] Figure 14 is a plan view showing Figure 1 an example of a power line included in a display device of

[0048] Figure 15 is a plan view showing Figure 1 an example of a scan line included in a display device of

[0049] Figure 16 is a plan view showing Figure 1 another example of a scan line included in a display device of

[0050] Figure 17 is a plan view showing Figure 2 an example of a pixel.

[0051] Figure 18 is a plan view showing Figure 1 an example of a power line included in a display device of

[0052] Figure 19 is a plan view showing Figure 1 an example of an initialization line included in a display device of DETAILED DESCRIPTION

[0053] Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In all the drawings, the same reference numerals are given to the same elements, and their repeated description will be omitted.

[0054] For clarity of illustration, dimensions may be exaggerated in the drawings. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the text, the same reference numerals denote the same elements.

[0055] It will be understood that when an element is referred to as being "on" another element, it may be directly on the other element, or intermediate elements may be present between them. Conversely, when an element is referred to as being "directly on" another element, no intermediate element is present.

[0056] ​It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another. Thus, without departing from the teachings herein, the "first element", "first component", "first region", "first layer", or "first section" discussed below may be referred to as a second element, second component, second region, second layer, or second section.

[0057] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms "comprises" and / or "comprising", or "includes" and / or "including" are used in this specification, it is meant that the stated features, regions, wholes, steps, operations, elements, and / or components are present, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or their combinations.

[0058] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another as shown in the figures. It will be understood that the relative terms are intended to include different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures in the drawings is flipped, the element described as on the "lower" side of another element will then be oriented on the "upper" side of that other element. Thus, the exemplary term "lower" may include both the "lower" and "upper" orientations depending on the specific orientation of the drawing. Similarly, if the device in one of the figures in the drawings is flipped, the element described as "below" or "beneath" another element will then be oriented "above" that other element. Thus, the exemplary terms "below" or "beneath" may include both above and below orientations.

[0059] For ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is flipped, an element described as "below" or "beneath" another element or feature will then be oriented "above" that other element or feature. Thus, the exemplary term "below" can include both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0060] As used herein, "about" or "approximately" includes the stated value and the average within an acceptable deviation range of the specific value as determined by one of ordinary skill in the art in view of the measurements discussed and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or this disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0062] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, variations in the shapes of the figures due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments described herein should not be construed as being limited to the specific shapes of regions shown herein, but should include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may typically have rough and / or non-linear features. Additionally, sharp corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shape of a region and are not intended to limit the scope of the appended claims.

[0063] Figure 1 is a block diagram showing an exemplary embodiment of a display device according to the present invention.

[0064] Reference Figure 1, the display device 1000 may include a substrate SUB, a plurality of pixels PX, a driving unit for driving the pixels PX, and scan lines SL1 to SLn, emission control lines EL1 to ELn, data lines DL1 to DLm, and power lines (not shown), where n is a natural number, m is a natural number, and the power lines connect the pixels PX and the driving unit.

[0065] The substrate SUB may have various shapes. In an exemplary embodiment, for example, the substrate SUB may have a closed polygon shape including linear edges. In an exemplary embodiment, the substrate SUB may have a shape such as a circle or an ellipse including curved edges. In an exemplary embodiment, the substrate SUB may have a shape such as a semi-circle or a semi-ellipse including linear edges and curved edges. The substrate SUB may include a display area DA and a non-display area NDA located at the periphery of the display area DA, where the display area DA includes the pixels PX.

[0066] The pixels PX may be arranged in the display area DA of the substrate SUB. Each of the pixels PX may include at least one transistor, a storage capacitor, and a light-emitting element. In an exemplary embodiment, for example, the light-emitting element may be an organic light-emitting diode (“OLED”). However, this is merely illustrative, and the light-emitting element is not limited thereto.

[0067] The driving unit may include a scan driver 200, an emission driver 300, a data driver 400, and a timing controller 500. Although Figure 1 the case where the scan driver 200, the emission driver 300, and the data driver 400 are provided on the substrate SUB is shown, the position of the driving unit is not limited thereto.

[0068] The scan lines SL1 to SLn, the data lines DL1 to DLm, and the power lines may be connected to the pixels PX. The scan lines SL1 to SLn may supply scan signals to the pixels PX, and the data lines DL1 to DLm may supply data signals to the pixels PX.

[0069] The pixels PX may be supplied with a first power voltage ELVDD, a second power voltage ELVSS, an initialization power voltage VINT, etc. from an external power source (power supply). The first power voltage ELVDD may be applied to the pixels PX through a power line PL (refer to Figure 2 ), and the initialization power voltage VINT may be applied to the pixels PX through an initialization line VIL (refer to Figure 2 ).

[0070] The scan driver 200 may supply scan signals to the scan lines SL1 to SLn in response to a scan start signal SFLM received from the timing controller 500.

[0071] The emission driver 300 may supply emission control signals to the emission control lines EL1 to ELn in response to an emission control start signal EFLM received from the timing controller 500.

[0072] The data driver 400 may supply analog data signals RGB to the data lines DL1 to DLm in response to a data control signal DCS received from the timing controller 500.

[0073] The timing controller 500 may supply a scan start signal SFLM to the scan driver 200, an emission control start signal EFLM to the emission driver 300, and a data control signal DCS and analog data signals RGB to the data driver 400 based on timing signals supplied from the outside.

[0074] Figure 2 It is a circuit diagram showing Figure 1 an example of a pixel included in the display device.

[0075] Figure 2 The pixel PX of is, for example, a pixel connected to the j-th data line DLj and the i-th scan line SLi (j and i are natural numbers).

[0076] Reference Figure 1 and Figure 2 According to and, the pixel PX may include an organic light-emitting diode OLED, a first transistor T1 to a seventh transistor T7, and a storage capacitor Cst.

[0077] The anode electrode of the organic light-emitting diode OLED may be connected to the first transistor T1 via the sixth transistor T6, and the cathode electrode of the organic light-emitting diode OLED may receive a second power supply voltage ELVSS. The organic light-emitting diode OLED may generate light having a predetermined luminance corresponding to the amount of current supplied from the first transistor T1.

[0078] The first power supply voltage ELVDD supplied to the first transistor T1 may be set to a voltage higher than the second power supply voltage ELVSS so that current may flow through the organic light-emitting diode OLED.

[0079] The seventh transistor T7 may be connected between the initialization power supply voltage VINT and the anode electrode of the organic light-emitting diode OLED. In an exemplary embodiment, the gate electrode of the seventh transistor T7 may be connected to the i-th scan line SLi. The seventh transistor T7 may be turned on when a scan signal is supplied to the i-th scan line SLi to supply the initialization power supply voltage VINT to the anode electrode of the organic light-emitting diode OLED. In other words, the seventh transistor T7 may be a transistor for initializing the anode voltage of the organic light-emitting diode OLED.

[0080] The initialization power supply voltage VINT may be set to a voltage lower than the data voltage. However, the scan line connected to the gate electrode of the seventh transistor T7 is merely illustrative, and the present invention is not limited thereto. In an exemplary embodiment, for example, one of the (i-2)th scan line SLi-2, the (i-1)th scan line SLi-1, and the (i+1)th scan line SLi+1 may be connected to the gate electrode of the seventh transistor T7.

[0081] The sixth transistor T6 may be connected between the first transistor T1 and the organic light emitting diode OLED. The gate electrode of the sixth transistor T6 may be connected to the ith emission control line ELi.

[0082] The fifth transistor T5 may be connected between the first power supply voltage ELVDD and the first transistor T1. The gate electrode of the fifth transistor T5 may be connected to the ith emission control line ELi.

[0083] The first electrode of the first transistor (also referred to as a driving transistor) T1 may receive the first power supply voltage ELVDD via the fifth transistor T5, and the second electrode of the first transistor T1 may be connected to the anode electrode of the organic light emitting diode OLED via the sixth transistor T6. The gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control the amount of current flowing through the organic light emitting diode OLED.

[0084] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be connected to the ith scan line SLi. The third transistor T3 may be turned on when a scan signal is supplied to the ith scan line SLi to electrically connect the second electrode of the first transistor T1 and the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be diode-connected, and the threshold voltage of the first transistor T1 may be compensated. In other words, the third transistor T3 may be a transistor for compensating the threshold voltage of the first transistor T1.

[0085] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply voltage VINT. The gate electrode of the fourth transistor T4 may be connected to the (i-1)th scan line SLi-1. The fourth transistor T4 may be turned on when a scan signal is supplied to the (i-1)th scan line SLi-1 to supply the initialization power supply voltage VINT to the first node N1. In other words, the fourth transistor T4 may be a transistor for initializing the gate voltage of the first transistor T1.

[0086] The second transistor T2 may be connected between the j-th data line DLj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the i-th scan line SLi. The second transistor T2 may be turned on when a scan signal is supplied to the i-th scan line SLi to electrically connect the j-th data line DLj and the first electrode of the first transistor T1.

[0087] The storage capacitor Cst may be connected between the first power supply voltage ELVDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to a data signal and the threshold voltage of the first transistor T1.

[0088] Figure 3 is a plan view showing an example of a pixel of Figure 2 . Figure 4 is Figure 3 a cross-sectional view taken along line I-I' of the pixel of Figure 5 is Figure 3 a cross-sectional view taken along line II-II' of the pixel of Figure 6 is Figure 3 a cross-sectional view taken along line III-III' of the pixel of

[0089] Hereinafter, the scan line SLi connected to the second transistor T2 and the third transistor T3 may be understood as a gate write line GW, the scan line SLi-1 connected to the fourth transistor T4 may be understood as a gate initialization control line GI, and the scan line SLi connected to the seventh transistor T7 may be understood as an anode initialization control line GB.

[0090] Referring to Figures 1 to 6 , the display device 1000 may include a substrate SUB, a plurality of conductive lines, and pixels PX connected to the conductive lines.

[0091] For ease of description, Figure 3 , Figure 5 and Figure 6 the organic light-emitting diodes are omitted in Figure 4 , and the stacked structure of the organic light-emitting diode OLED is exemplarily shown in

[0092] The pixel PX may include a pixel circuit provided with the first transistor T1 to the seventh transistor T7 and the storage capacitor Cst, and an organic light-emitting diode connected to the pixel circuit. The pixel circuit may be electrically connected to the scan lines SLi and SLi-1, the data line DLj, the power line PL, and the initialization line VIL.

[0093] The substrate SUB may be set as a bottom plate substrate or a base substrate. The substrate SUB may include a transparent insulating material to enable light to transmit through the substrate SUB. In an exemplary embodiment, for example, the substrate SUB may be a flexible substrate. In an exemplary embodiment, the substrate SUB may be one of a film substrate and a plastic substrate including a polymer organic material. In an exemplary embodiment, for example, the substrate SUB may include polyimide.

[0094] In an exemplary embodiment, a buffer layer and / or a barrier layer may be provided on the substrate SUB. The buffer layer and / or the barrier layer may prevent the diffusion of impurities, moisture, etc. generated from the substrate SUB, and are used to adjust the heat propagation speed during the crystallization process for forming a semiconductor pattern. In an exemplary embodiment, for example, the buffer layer and / or the barrier layer may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ). The buffer layer and / or the barrier layer may have a single-layer or multi-layer structure including a silicon compound.

[0095] The first transistor T1 to the seventh transistor T7 may be provided on the substrate SUB. Each of the first transistor T1 to the seventh transistor T7 may include an active pattern provided on the substrate SUB, source and drain electrodes respectively connected to the active pattern, a gate electrode provided on the active pattern, an insulating intermediate layer including a first insulating intermediate layer IL1, a second insulating intermediate layer IL2, and a third insulating intermediate layer IL3, and a protective layer PSV provided on the insulating intermediate layer, wherein a gate insulating layer GIL overlapping the active pattern is interposed between the gate electrode and the active pattern, and the first insulating intermediate layer IL1, the second insulating intermediate layer IL2, and the third insulating intermediate layer IL3 cover the gate electrode and are sequentially stacked.

[0096] The power line PL may include a first conductive pattern PL1, a second conductive pattern PL2, and a third conductive pattern PL3. For ease of description, the first conductive pattern PL1, the second conductive pattern PL2, and the third conductive pattern PL3 may be respectively understood as a first power line PL1, a second power line PL2, and a third power line PL3.

[0097] The first conductive pattern PL1 may extend in a first direction DR1 and be disposed on a first insulating intermediate layer IL1. The second conductive pattern PL2 may extend in the first direction DR1 and be disposed on a second insulating intermediate layer IL2. The first conductive pattern PL1 and the second conductive pattern PL2 may be connected to each other through a first contact hole CNT1. In an exemplary embodiment, the first conductive pattern PL1 and the second conductive pattern PL2 may overlap at least a part of a lower electrode LE of a storage capacitor Cst. In addition, an area of the first conductive pattern PL1 overlapping with the lower electrode LE may be greater than an area of the second conductive pattern PL2 overlapping with the lower electrode LE.

[0098] In an exemplary embodiment, for example, the first conductive pattern PL1 may include molybdenum (Mo) or an alloy thereof. However, this is merely illustrative, and the material included in the first conductive pattern PL1 is not limited thereto. In an exemplary embodiment, for example, the first conductive pattern PL1 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0099] In an exemplary embodiment, the second conductive pattern PL2 may include a low-resistance material. The second conductive pattern PL2 may have a resistance lower than that of the first conductive pattern PL1. In an exemplary embodiment, for example, the second conductive pattern PL2 may have an aluminum alloy structure in which titanium (Ti), aluminum ("Al"), and titanium (Ti) are sequentially stacked. However, this is merely illustrative, and the material of the second conductive pattern PL2 is not limited thereto. In an exemplary embodiment, for example, the second conductive pattern PL2 may include gold (Au), silver (Ag), Al, platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum alloy, aluminum nitride (AlN x ), silver alloy, tungsten (W), tungsten nitride (WN x ), copper alloy, molybdenum alloy, titanium nitride (TiN x ), tantalum nitride (TaN x ), strontium ruthenium oxide (SrRu x O y ), zinc oxide (ZnO x ), indium tin oxide ("ITO"), tin oxide (SnO x ), indium oxide (InO x ), gallium oxide (GaO x ), indium zinc oxide ("IZO"), etc. They may be used alone or in combination thereof.

[0100] In an exemplary embodiment, the first conductive pattern PL1 and the second conductive pattern PL2 may overlap with the first transistor T1.

[0101] The third conductive pattern PL3 may extend in the second direction DR2 and be disposed on the third insulating interlayer IL3. The third conductive pattern PL3 may be connected to the second conductive pattern PL2 via the second contact hole CNT2. The third conductive pattern PL3 may include a low-resistance metal. In an exemplary embodiment, for example, the third conductive pattern PL3 may have an aluminum alloy structure in which titanium (Ti), Al, and titanium (Ti) are sequentially stacked. In an exemplary embodiment, for example, the third conductive pattern PL3 may have the same material as that of the second conductive pattern PL2.

[0102] The first conductive pattern PL1 and the second conductive pattern PL2 may extend in the horizontal direction (e.g., the first direction DR1), and the third conductive pattern PL3 may extend in the vertical direction (e.g., the second direction DR2). By connecting the first conductive pattern PL1 to the third conductive pattern PL3, the power line PL may have a mesh structure provided with three conductive layers.

[0103] The first conductive pattern PL1, the second conductive pattern PL2, and the third conductive pattern PL3 may be electrically connected to each other via the first contact hole CNT1 and the second contact hole CNT2. That is, the first conductive pattern PL1, the second conductive pattern PL2, and the third conductive pattern PL3 may transmit the same first power supply voltage ELVDD. In addition, the power line PL may have a double wiring structure including the first conductive pattern PL1 and the second conductive pattern PL2 that extend in the horizontal direction and partially overlap each other. The voltage drop (i.e., IR drop) of the first power supply voltage ELVDD in the first direction DR1 may be reduced due to the double wiring structure and the second conductive pattern PL2 including a low-resistance metal. Therefore, the luminance uniformity of the display device 1000 may be improved.

[0104] The scan lines SLi and SLi-1 may extend in the first direction DR1. In an exemplary embodiment, for example, the scan lines SLi and SLi-1 may be arranged in the order of the gate initialization control line GI, the gate write line GW, and the anode initialization control line GB along the second direction DR2. Hereinafter, the gate initialization control line GI, the gate write line GW, and the anode initialization control line GB will be described as the first scan line GI, the second scan line GW, and the third scan line GB, respectively.

[0105] At least one of the scan lines GI, GW, and GB may be disposed in the same layer as the second conductive pattern PL2. The scan lines GI, GW, and GB may be respectively connected to the gate electrodes corresponding to the transistors via contact holes.

[0106] In an exemplary embodiment, asFigure 3 and Figure 4 As shown in Figure 4 , the first scan line GI, the second scan line GW, and the third scan line GB can be disposed in the same layer as the second conductive pattern PL2. Accordingly, the first scan line GI, the second scan line GW, and the third scan line GB can include the same material as that of the second conductive pattern PL2. In an exemplary embodiment, for example, the first scan line GI, the second scan line GW, and the third scan line GB can include a low-resistance metal material such as aluminum alloy. Therefore, the resistance of the first scan line GI, the second scan line GW, and the third scan line GB is reduced, so that the resistance-capacitance ("RC") delay of the scan signal can be reduced. In addition, the scan lines GI, GW, and GB are provided by a bridging structure between the gate electrode and the conductive pattern on the second insulating intermediate layer IL2, so that the influence from peripheral interference and static electricity can be reduced.

[0107] The first scan line GI can be connected to the gate electrode of the fourth transistor T4 via the third contact hole CNT3. The second scan line GW can be connected to the gate electrode of the second transistor T2 and the gate electrode of the third transistor T3 via the fourth contact hole CNT4 and the fifth contact hole CNT5, respectively. In an exemplary embodiment, the second scan line GW can be connected to the gate electrode of the third transistor T3 of the pixel on the (j - 1)th column and the gate electrode of the second transistor T2 of the pixel on the jth column via the fourth contact hole CNT4, and connected to the gate electrode of the third transistor T3 of the pixel on the jth column and the gate electrode of the second transistor T2 of the pixel on the (j + 1)th column via the fifth contact hole CNT5.

[0108] The third scan line GB can be connected to the gate electrode of the seventh transistor T7 via the sixth contact hole CNT6.

[0109] The emission control line ELi can be disposed in the same layer as the gate electrode. However, this is merely illustrative, and the emission control line ELi can be disposed in the same layer as the second conductive pattern PL2. Accordingly, the emission control line ELi can be connected to the gate electrodes of the fifth transistor T5 and the sixth transistor T6 via contact holes. When the emission control line ELi is disposed in the same layer as the second conductive pattern PL2 with low resistance, the RC delay of the emission control signal can be reduced due to the resistance of the emission control line ELi.

[0110] The initialization line VIL (refer to Figure 2)An initialization power supply voltage VINT may be supplied to the pixel PX. The initialization line VIL may include a first initialization conductive pattern VIL1 extending in a first direction DR1 and a second initialization conductive pattern VIL2 extending in a second direction DR2. That is, the initialization line VIL may have a mesh structure in which the first initialization conductive pattern VIL1 and the second initialization conductive pattern VIL2 cross each other. For ease of description, the first initialization conductive pattern VIL1 and the second initialization conductive pattern VIL2 may be understood as a first initialization line VIL1 and a second initialization line VIL2, respectively.

[0111] The first initialization conductive pattern VIL1 may be disposed in the same layer as the second conductive pattern PL2 and extend in the first direction DR1. In an exemplary embodiment, the first initialization conductive pattern VIL1 may be connected to the drain electrode (or source electrode) of the fourth transistor T4 and the drain electrode (or source electrode) of the seventh transistor T7 via a seventh contact hole CNT7. In an exemplary embodiment, as Figure 3 shown, the first initialization conductive pattern VIL1 located at the lower end of the i-th pixel may be simultaneously connected to the seventh transistor T7 of the i-th pixel and the fourth transistor T4 of the (i + 1)-th pixel via the seventh contact hole CNT7.

[0112] The second initialization conductive pattern VIL2 may be disposed in the same layer as the third conductive pattern PL3. The second initialization conductive pattern VIL2 may be connected to the first initialization conductive pattern VIL1 via an eighth contact hole CNT8.

[0113] When the initialization conductive patterns VIL1 and VIL2 are arranged as described above, the non-uniformity of the parasitic capacitance caused by the connection between the existing initialization conductive patterns may be minimized.

[0114] Each of the first transistor T1 to the seventh transistor T7 may include a source electrode, a drain electrode, and an active pattern provided by patterning a semiconductor layer, and a gate electrode provided by patterning a gate electrode layer. In an exemplary embodiment, the active pattern, the source electrode, and the drain electrode may include a semiconductor layer that is not doped with impurities or is doped with impurities. In an exemplary embodiment, for example, the source electrode and the drain electrode may include a semiconductor layer doped with impurities, and the active pattern may include a semiconductor layer not doped with impurities. The drain electrode and the source electrode may be arbitrarily defined according to the voltage applied to each of the first transistor T1 to the seventh transistor T7.

[0115] The storage capacitor Cst may include a lower electrode LE disposed in the same layer as the gate electrode and an upper electrode UE disposed on the first insulating intermediate layer IL1 and overlapping the lower electrode LE at the same time. The lower electrode LE may be provided as the gate electrode of the first transistor T1. The upper electrode UE may be provided as the first conductive pattern PL1.

[0116] There is no defined opening in the upper electrode UE that overlaps with the lower electrode LE. That is, the first conductive pattern PL1 that constitutes the upper electrode UE is not connected to other components (e.g., transistors) other than the components that form the power line PL, and thus, the upper electrode UE and the lower electrode LE are not short-circuited with other components. Therefore, in the storage capacitor Cst according to an exemplary embodiment of the present invention, the opening existing in the existing storage capacitor is removed, so that the capacitance change caused by the formation of the opening is eliminated, and the capacitance (i.e., the area of the electrode) can be increased. Accordingly, display spots and image crosstalk caused by the capacitance change of the storage capacitor Cst can be minimized.

[0117] Hereinafter, reference will be made to Figures 4 to 6 Describe the structure of the display device according to an exemplary embodiment of the present invention along the stacking order.

[0118] Active patterns ACT1 to ACT7 (hereinafter referred to as ACT) may be provided on the substrate SUB. The active pattern ACT (refer to Figure 7 ) may include the first active pattern ACT1 to the seventh active pattern ACT7. The first active pattern ACT1 to the seventh active pattern ACT7 may include a semiconductor material. The active pattern ACT may include an inorganic semiconductor (e.g., amorphous silicon or polysilicon), an organic semiconductor, etc.

[0119] The gate insulating layer GIL may be provided on the substrate SUB on which the active pattern ACT is provided. The gate insulating layer GIL may include at least one of an organic insulating layer and an inorganic insulating layer. In an exemplary embodiment, for example, the gate insulating layer GIL may include an inorganic material, and the inorganic material includes at least one of silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiON).

[0120] The emission control lines ELi and the first gate electrodes GE1 to GE7 of the corresponding first transistors T1 to T7 may be provided on the gate insulating layer GIL. In an exemplary embodiment, the gate electrodes GE1 to GE7 (hereinafter referred to as GE) may be conductive patterns having an island shape. In an exemplary embodiment, for example, the gate electrode GE (refer to Figure 8 ) and the emission control line ELi may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. They may be used alone or in combination.

[0121] The first gate electrode GE1 may be the lower electrode LE of the storage capacitor Cst. The fifth gate electrode GE5 and the sixth gate electrode GE6 may be integral with the emission control line ELi.

[0122] The first insulating intermediate layer IL1 may be disposed on the gate insulating layer GIL on which the gate electrode GE is disposed. The first insulating intermediate layer IL1 may include at least one of an organic insulating layer and an inorganic insulating layer. In an exemplary embodiment, for example, the first insulating intermediate layer IL1 may include the same material as that of the gate insulating layer GIL.

[0123] The upper electrode UE of the storage capacitor Cst and the first power line (first conductive pattern) PL1 may be disposed on the first insulating intermediate layer IL1. The upper electrode UE may cover the lower electrode LE. The upper electrode UE and the lower electrode LE together may form the storage capacitor Cst, and the first insulating intermediate layer IL1 is interposed between the upper electrode UE and the lower electrode LE. The upper electrode UE may be a part of the first power line PL1. The first power line PL1 may extend in the first direction DR1. The first power line PL1 may transmit the first power supply voltage ELVDD.

[0124] The upper electrode UE and the first power line PL1 may include the same material. In an exemplary embodiment, for example, the upper electrode UE and the first power line PL1 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0125] The second insulating intermediate layer IL2 may be disposed on the first insulating intermediate layer IL1 on which the upper electrode UE and the first power line PL1 are disposed. The second insulating intermediate layer IL2 may include at least one of an organic insulating layer and an inorganic insulating layer.

[0126] The first scan line GI, the second scan line GW, and the third scan line GB (i.e., SLi-1 and SLi), the second power line (second conductive pattern) PL2, and the first initialization line (first initialization conductive pattern) VIL1 may be disposed on the second insulating intermediate layer IL2. The first scan line GI, the second scan line GW, and the third scan line GB, the second power line PL2, and the first initialization line VIL1 may extend in the first direction DR1. The first scan line GI, the second scan line GW, and the third scan line GB, the second power line PL2, and the first initialization line VIL1 may include the same material, which includes a low-resistance metal. In an exemplary embodiment, the low-resistance metal may have an aluminum alloy structure in which titanium (Ti), Al, and titanium (Ti) are sequentially stacked. However, this is merely illustrative, and the low-resistance metal is not limited thereto.

[0127] The first scan line GI, the second scan line GW, and the third scan line GB (i.e., SLi-1 and SLi) can be connected to the gate electrodes corresponding to the first scan line GI, the second scan line GW, and the third scan line GB through the contact holes CNT3 to CNT6 that penetrate the first insulating intermediate layer IL1 and the second insulating intermediate layer IL2. The second power line PL2 can be connected to the first power line PL1 through the first contact hole CNT1 that penetrates the second insulating intermediate layer IL2. The first initialization line VIL1 can be connected to the fourth gate electrode GE4 and the seventh gate electrode GE7 through the seventh contact hole CNT7 that penetrates the first insulating intermediate layer IL1 and the second insulating intermediate layer IL2.

[0128] The third insulating intermediate layer IL3 can be disposed on the second insulating intermediate layer IL2 on which the first scan line GI, the second scan line GW, and the third scan line GB, the second power line (second conductive pattern) PL2, and the first initialization line VIL1 are disposed. The third insulating intermediate layer IL3 can include at least one of an organic insulating layer and an inorganic insulating layer.

[0129] The third power line (third conductive pattern) PL3, the second initialization line (second initialization conductive pattern) VIL2, and the data line DLj can be disposed on the third insulating intermediate layer IL3. The third power line PL3, the second initialization line VIL2, and the data line DLj can extend in the second direction DR2. The third power line PL3, the second initialization line VIL2, and the data line DLj can include the same material, which includes a low-resistance metal.

[0130] The third power line PL3 can be connected to the second power line PL2 through the second contact hole CNT2 that penetrates the third insulating intermediate layer IL3. The second initialization line VIL2 can be connected to the first initialization line VIL1 through the eighth contact hole CNT8 that penetrates the third insulating intermediate layer IL3. The data line DLj can be connected to the source electrode SE2 (or drain electrode DE2) of the second transistor T2 through the twelfth contact hole CNT12 that penetrates the third insulating intermediate layer IL3.

[0131] The protective layer PSV can be disposed on the third insulating intermediate layer IL3 on which the third power line PL3, the second initialization line VIL2, and the data line DLj are disposed. The protective layer PSV can include at least one of an organic insulating layer and an inorganic insulating layer. In an exemplary embodiment, for example, the protective layer PSV can include an organic insulating layer.

[0132] The organic light-emitting diode OLED can be disposed on the protective layer PSV. The organic light-emitting diode OLED can include a first electrode AD, a second electrode CD, and an emission layer EML disposed between the first electrode AD and the second electrode CD.

[0133] The first electrode AD may be disposed on the protective layer PSV. The first electrode AD may be connected to the first bridging pattern BRP1 via the tenth contact hole CNT10 penetrating the protective layer PSV. The first bridging pattern BRP1 may be a conductive pattern for connecting the source electrode SE7 of the seventh transistor T7 and the first electrode AD. The first bridging pattern BRP1 may be disposed on the third insulating intermediate layer IL3.

[0134] The first bridging pattern BRP1 may be connected to the second bridging pattern BRP2 via the ninth contact hole CNT9 penetrating the third insulating intermediate layer IL3. The second bridging pattern BRP2 may be a conductive pattern disposed on the second insulating intermediate layer IL2. The second bridging pattern BRP2 may be connected to the source electrode SE7 (and the drain electrode DE6 of the sixth transistor T6) of the seventh transistor T7 via the eleventh contact hole CNT11 sequentially penetrating the gate insulating layer GIL, the first insulating intermediate layer IL1, and the second insulating intermediate layer IL2.

[0135] Therefore, the first electrode AD may be finally connected to the source electrode SE7 of the seventh transistor T7 and the drain electrode DE6 of the sixth transistor T6 via the first bridging pattern BRP1 and the second bridging pattern BRP2.

[0136] The pixel defining layer PDL that defines the light emitting range corresponding to each pixel may be disposed on the protective layer PSV on which the first electrode AD is disposed. The pixel defining layer PDL may expose the upper surface of the first electrode AD and protrude from the protective layer PSV along the perimeter of the pixel PX. In an exemplary embodiment, the light emitting range may be defined as the upper surface of the first electrode AD exposed by the pixel defining layer PDL.

[0137] The emission layer EML may be disposed on the exposed first electrode AD, and the second electrode CD may be disposed on the emission layer EML. The encapsulation layer ECL covering the second electrode CD may be disposed above the second electrode CD.

[0138] One of the first electrode AD and the second electrode CD may be an anode electrode, and the other of the first electrode AD and the second electrode CD may be a cathode electrode. In an exemplary embodiment, for example, the first electrode AD may be an anode electrode, and the second electrode CD may be a cathode electrode.

[0139] The first electrode AD may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. They may be used alone or in combination. The pixel defining layer PDL may include an organic material or an inorganic material. In an exemplary embodiment, the pixel defining layer PDL may be formed using an organic material. The second electrode CD may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. They may be used alone or in combination.

[0140] The emission layer EML may have a multi-layer thin film structure including a light generation layer ("LGL"). The emission layer EML may include a hole injection layer ("HIL"), a hole transport layer ("HTL"), an LGL, a hole blocking layer ("HBL"), an electron transport layer ("ETL"), and an electron injection layer ("EIL"). In addition, the HIL, HTL, HBL, ETL, and EIL in the emission layer EML may be common layers commonly provided in adjacent pixels PX.

[0141] In an exemplary embodiment, the color of the light generated in the LGL may be one of red, green, blue, and white, but the present invention is not limited thereto. In an exemplary embodiment, for example, the color of the light generated in the LGL may be one of magenta, cyan, and yellow.

[0142] Figure 7 is a diagram showing Figures 3 to 6 a plan view of the active pattern, source electrode, and drain electrode shown in Figure 8 is a diagram showing Figures 3 to 6 a plan view of the gate electrode and emission control line shown in

[0143] Refer to Figures 2 to 8 , a semiconductor layer including first active patterns ACT1 to seventh active patterns ACT7, first source electrodes SE1 to seventh source electrodes SE7, and first drain electrodes DE1 to seventh drain electrodes DE7 may be provided on a substrate SUB.

[0144] The first active patterns ACT1 to seventh active patterns ACT7 may be provided in the same layer by the same process. The first active patterns ACT1 to seventh active patterns ACT7 may correspond to first transistors T1 to seventh transistors T7, respectively.

[0145] The first source electrodes SE1 to seventh source electrodes SE7 may correspond to first transistors T1 to seventh transistors T7, respectively. The first drain electrodes DE1 to seventh drain electrodes DE7 may correspond to first transistors T1 to seventh transistors T7, respectively.

[0146] In an exemplary embodiment, the first active patterns ACT1 to seventh active patterns ACT7 may include a semiconductor layer not doped with impurities, and the first source electrodes SE1 to seventh source electrodes SE7 and the first drain electrodes DE1 to seventh drain electrodes DE7 may include a semiconductor layer doped with impurities.

[0147] One end of the first active pattern ACT1 may be connected to the first source electrode SE1, and the other end of the first active pattern ACT1 may be connected to the first drain electrode DE1. One end of the second active pattern ACT2 may be connected to the second source electrode SE2, and the other end of the second active pattern ACT2 may be connected to the second drain electrode DE2. One end of the third active pattern ACT3 may be connected to the third source electrode SE3, and the other end of the third active pattern ACT3 may be connected to the third drain electrode DE3. One end of the fourth active pattern ACT4 may be connected to the fourth source electrode SE4, and the other end of the fourth active pattern ACT4 may be connected to the fourth drain electrode DE4. One end of the fifth active pattern ACT5 may be connected to the fifth source electrode SE5, and the other end of the fifth active pattern ACT5 may be connected to the fifth drain electrode DE5. One end of the sixth active pattern ACT6 may be connected to the sixth source electrode SE6, and the other end of the sixth active pattern ACT6 may be connected to the sixth drain electrode DE6. One end of the seventh active pattern ACT7 may be connected to the seventh source electrode SE7, and the other end of the seventh active pattern ACT7 may be connected to the seventh drain electrode DE7.

[0148] The first active pattern ACT1 may have a rod shape extending in the first direction DR1 and have a shape that is bent multiple times along the extending length direction. In a plan view, the first active pattern ACT1 may overlap with the first gate electrode GE1. The first active pattern ACT1 is set to be long such that the channel region of the first transistor T1 may be set to be long. Accordingly, the driving range of the gate voltage applied to the first transistor T1 may be widened.

[0149] In an exemplary embodiment, the third transistor T3 and the fourth transistor T4 may be arranged in a double-gate structure to prevent leakage current. The third transistor T3 may include a 3a transistor and a 3b transistor. The 3a transistor may include a 3a gate electrode GE3a, a 3a active pattern ACT3a, a 3a source electrode SE3a, and a 3a drain electrode DE3a. The 3b transistor may include a 3b gate electrode GE3b, a 3b active pattern ACT3b, a 3b source electrode SE3b, and a 3b drain electrode DE3b. The fourth transistor T4 may include a 4a transistor and a 4b transistor. The 4a transistor may include a 4a gate electrode GE4a, a 4a active pattern ACT4a, a 4a source electrode SE4a, and a 4a drain electrode DE4a. The 4b transistor may include a 4b gate electrode GE4b, a 4b active pattern ACT4b, a 4b source electrode SE4b, and a 4b drain electrode DE4b.

[0150] The first gate electrode GE1 to the seventh gate electrode GE7, the lower electrode LE of the storage capacitor Cst, and the emission control line ELi may be disposed on the gate insulating layer GIL on which the semiconductor layer is disposed. The first active pattern ACT1 to the seventh active pattern ACT7 may respectively correspond to the portions of the semiconductor layer overlapping with the first gate electrode GE1 to the seventh gate electrode GE7.

[0151] The first gate electrode GE1 to the seventh gate electrode GE7, the lower electrode LE of the storage capacitor Cst, and the emission control line ELi may include the same material in the same layer through the same process.

[0152] In an exemplary embodiment, the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, the fourth gate electrode GE4, and the seventh gate electrode GE7 may be conductive patterns having an island shape. Accordingly, the influence caused by an undesired antenna effect can be reduced.

[0153] That is, different from the arrangement of the existing scan lines disposed in the same layer as the gate electrode, the scan lines may be disposed in a layer different from the layer in which the gate electrode is disposed. The first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, the fourth gate electrode GE4, and the seventh gate electrode GE7 may be respectively connected to the upper scan line via contact holes.

[0154] The first gate electrode GE1 may be integral with the lower electrode LE, and the fifth gate electrode GE5 and the sixth gate electrode GE6 may be integral with the emission control line ELi.

[0155] However, this is merely illustrative, and the arrangement of the emission control line ELi is not limited thereto. In an exemplary embodiment, the emission control line ELi may include the same material as the scan line and the second conductive pattern (second power line) PL2 in the same layer through the same process as the scan line and the second conductive pattern (second power line) PL2. In an exemplary embodiment, for example, the emission control line ELi may be disposed on the second insulating intermediate layer IL2 and electrically connected to the fifth gate electrode GE5 and the sixth gate electrode GE6 via predetermined contact holes.

[0156] Figure 9 Is a plan view of the first conductive pattern of the power line shown Figures 3 to 6 in the figure.

[0157] Refer to Figures 2 to 9 and the first power line (first conductive pattern) PL1 and the upper electrode UE of the storage capacitor Cst may be disposed on the first insulating intermediate layer IL1 covering the first gate electrode GE1 to the seventh gate electrode GE7, the lower electrode LE of the storage capacitor Cst, and the emission control line ELi.

[0158] In an exemplary embodiment, although not shown in Figure 3 , a shielding pattern SDP and a repair line pattern RLP may also be provided on the first insulating intermediate layer IL1 ( Figure 12 and Figure 13 as shown in). The first power line PL1, the upper electrode UE of the storage capacitor Cst, the shielding pattern SDP, and the repair line pattern RLP may include the same material in the same layer through the same process.

[0159] The first power line PL1 may extend in the first direction DR1 and transmit the first power supply voltage ELVDD.

[0160] The upper electrode UE may be integral with the first power line PL1. That is, the storage capacitor Cst may be formed by the lower electrode LE and the upper electrode UE, and the lower electrode LE and the upper electrode UE are arranged such that the first insulating intermediate layer IL1 is interposed therebetween. In an exemplary embodiment, the upper electrode UE may have an area larger than that of the lower electrode LE. In addition, there is no defined opening (hole) in the upper electrode UE.

[0161] In a plan view, the shielding pattern SDP may be disposed between the data line DLj and the gate node (gate electrode GE1) of the first transistor T1 so as to be spaced apart from the data line DLj and the gate node (gate electrode GE1) of the first transistor T1. According to the arrangement of the shielding pattern SDP, the electrical influence (e.g., coupling capacitance) between the data line DLj and the gate node may be reduced. Therefore, image crosstalk may be minimized.

[0162] The repair line pattern RLP may extend in the first direction DR1. The repair line pattern RLP may connect an organic light emitting diode that has been connected to a pixel circuit determined to be a defective pixel circuit to a repair pixel circuit outside the display area. In an exemplary embodiment, for example, the defective pixel circuit is disconnected from the organic light emitting diode, and the corresponding organic light emitting diode may be electrically connected to the repair pixel circuit through the repair line pattern RLP.

[0163] Figure 10 is a plan view showing Figures 3 to 6 the first scan line to the third scan line, the second conductive pattern of the power line, and the first initialization line shown in.

[0164] Referring to Figures 2 to 10 , the first scan line GI, the second scan line GW, and the third scan line GB, the second power line (second conductive pattern) PL2, and the first initialization line (first initialization conductive pattern) VIL1 may be provided on the second insulating intermediate layer IL2 covering the first power line PL1 and the upper electrode UE of the storage capacitor Cst.

[0165] In an exemplary embodiment, a second bridging pattern BRP2 to a fourth bridging pattern BRP4 may also be provided on the second insulating intermediate layer IL2.

[0166] The second bridging pattern BRP2 to the fourth bridging pattern BRP4, the first scan line GI, the second scan line GW, and the third scan line GB, the second power line PL2, and the first initialization line VIL1 may include the same material in the same layer and are electrically connected to the underlying conductive layer via a plurality of contact holes.

[0167] The first scan line GI may extend in the first direction DR1. The first scan line GI may be connected to the fourth gate electrode GE4 via the third contact hole CNT3.

[0168] The second scan line GW may extend in the first direction DR1. The second scan line GW may be connected to the second gate electrode GE2 and the third gate electrode GE3 via the fourth contact hole CNT4 and the fifth contact hole CNT5, respectively. In an exemplary embodiment, for example, the second scan line GW may be connected to the gate electrode of the third transistor T3 of the pixel on the (j - 1)th column and the gate electrode of the second transistor T2 of the pixel on the jth column via the fourth contact hole CNT4, and connected to the gate electrode of the third transistor T3 of the pixel on the jth column and the gate electrode of the second transistor T2 of the pixel on the (j + 1)th column via the fifth contact hole CNT5.

[0169] The third scan line GB may extend in the first direction DR1. The third scan line GB may be connected to the seventh gate electrode GE7 via the sixth contact hole CNT6.

[0170] As described above, the first scan line GI, the second scan line GW, and the third scan line GB may be provided in a conductive layer (i.e., a layer different from the layer in which the gate electrode is provided) including a low-resistance material (such as aluminum alloy) and are connected to the gate electrode via contact holes. Therefore, the resistance of the first scan line GI, the second scan line GW, and the third scan line GB is reduced, so that the RC delay can be minimized.

[0171] The second power line PL2 may extend in the first direction DR1. The second power line PL2 may be connected to the first power line PL1 via the first contact hole CNT1. The second power line PL2 may be connected to the fifth source electrode SE5 via the thirteenth contact hole CNT13. In an exemplary embodiment, for example, the thirteenth contact hole CNT13 may penetrate the gate insulating layer GIL, the first insulating intermediate layer IL1, and the second insulating intermediate layer IL2.

[0172] In an exemplary embodiment, the area of the first power line PL1 overlapping with the lower electrode LE may be greater than the area of the second power line PL2 overlapping with the lower electrode LE. However, this is merely illustrative, and the areas of the first power line PL1 and the second power line PL2 are not limited thereto.

[0173] The first power line PL1 and the second power line PL2 may be disposed in a double wiring structure in which at least a portion of the first conductive pattern PL1 and the second conductive pattern PL2 extends in a horizontal direction to overlap each other. The voltage drop (i.e., IR drop) of the first power supply voltage ELVDD in the first direction DR1 may be reduced due to the double wiring structure and the second conductive pattern PL2 including a low-resistance metal. Accordingly, the luminance uniformity of the display device 1000 may be improved.

[0174] The first initialization line VIL1 may extend in the first direction DR1. The first initialization line VIL1 may be connected to the seventh drain electrode DE7 (or the seventh source electrode SE7) and the fourth drain electrode DE4 (or the fourth source electrode SE4) via the seventh contact hole CNT7. In an exemplary embodiment, for example, the first initialization line VIL1 may be connected to the seventh drain electrode DE7 (or the seventh source electrode SE7) of the i-th pixel (i.e., the pixel on the i-th row) and the fourth drain electrode DE4 (or the fourth source electrode SE4) of the (i + 1)-th pixel (i.e., the pixel on the (i + 1)-th row) via the seventh contact hole CNT7.

[0175] In an exemplary embodiment, the first initialization line VIL1 may be connected to the shielding pattern SDP via the fourteenth contact hole CNT14 penetrating the second insulating intermediate layer IL2. Accordingly, the shielding pattern SDP floats to the initialization power supply voltage VINT which is a direct current (“DC”) voltage, and accordingly, the electrical influence between the data line DLj and the gate node may be eliminated.

[0176] The second bridging pattern BRP2 may be connected to the seventh source electrode SE7 (and the sixth drain electrode DE6) via the eleventh contact hole CNT11 penetrating the gate insulating layer GIL, the first insulating intermediate layer IL1, and the second insulating intermediate layer IL2. The second bridging pattern BRP2 may adjust the electrical connection between the seventh source electrode SE7 and the first electrode AD of the organic light emitting diode OLED.

[0177] The third bridging pattern BRP3 may be connected to the second source electrode SE2 via the twelfth contact hole CNT12 penetrating the gate insulating layer GIL, the first insulating intermediate layer IL1, and the second insulating intermediate layer IL2. The third bridging pattern BRP3 may adjust the electrical connection between the second source electrode SE2 and the data line DLj.

[0178] The fourth bridging pattern BRP4 can be connected to the first gate electrode GE1 via the fifteenth contact hole CNT15 that penetrates the first intermediate insulating layer IL1 and the second intermediate insulating layer IL2. In addition, the fourth bridging pattern BRP4 can be connected to the third drain electrode DE3 (and the fourth source electrode SE4) via the sixteenth contact hole CNT16 that penetrates the gate insulating layer GIL, the first intermediate insulating layer IL1, and the second intermediate insulating layer IL2. That is, the fourth bridging pattern BRP4 can correspond to the first node N1 of the Figure 2 pixel PX. The fourth bridging pattern BRP4 can adjust the electrical connection between the first gate electrode GE1 and the third drain electrode DE3 (and the fourth source electrode SE4).

[0179] Figure 11 is a plan view showing Figures 3 to 6 the third conductive pattern of the data line, the second initialization line, and the power line shown in

[0180] Referring to Figures 2 to 11 , the data lines DLj-1, DLj, ……, the third power line (third conductive pattern) PL3, and the second initialization line (second initialization conductive pattern) VIL2 can be disposed on the third intermediate insulating layer IL3 covering the first scan line GI, the second scan line GW, and the third scan line GB, the second power line PL2, and the first initialization line VIL1.

[0181] In an exemplary embodiment, the first bridging pattern BRP1 can also be disposed on the third intermediate insulating layer IL3.

[0182] The first bridging pattern BRP1, the data lines DLj-1, DLj, ……, the third power line PL3, and the second initialization line VIL2 can include the same material in the same layer by the same process and are electrically connected to the underlying conductive layer via a plurality of contact holes.

[0183] The data line DLj can extend in the second direction DR2. The data line DLj can be connected to the third bridging pattern BRP3 via the contact hole CNT12' that penetrates the third intermediate insulating layer IL3. Therefore, the data line DLj can ultimately be connected to the second source electrode SE2. The data signal transmitted through the data line DLj can be supplied to the pixel PX via the second transistor T2 (e.g., the second source electrode SE2).

[0184] The third power line PL3 can extend in the second direction DR2. The third power line PL3 can transmit the first power supply voltage ELVDD in the second direction DR2.

[0185] The third power line PL3 can be connected to the second power line PL2 via a second contact hole CNT2 that penetrates the third insulating intermediate layer IL3. The third power line PL3 can ultimately be connected to the first power line PL1, the fifth source electrode SE5, and the upper electrode UE of the storage capacitor Cst.

[0186] According to the connection relationships of the first power line PL1 to the third power line PL3, the power lines PL can be arranged in a mesh structure in Figure 1 the display area DA.

[0187] The second initialization line VIL2 can extend in the second direction DR2. The second initialization line VIL2 can be connected to the first initialization line VIL1 via an eighth contact hole CNT8 that penetrates the third insulating intermediate layer IL3. According to the connection relationships of the first initialization line VIL1 and the second initialization line VIL2, the initialization line VIL (refer to Figure 2 ) can be arranged in a mesh structure in Figure 1 the display area DA.

[0188] In an exemplary embodiment, one second initialization line VIL2 can be provided for every two pixel columns to ensure the aperture ratio.

[0189] The first bridging pattern BRP1 can be connected to the second bridging pattern BRP2 via a ninth contact hole CNT9 that penetrates the third insulating intermediate layer IL3. Together, the first bridging pattern BRP1 and the second bridging pattern BRP2 can adjust the electrical connection between the seventh source electrode SE7 and the first electrode AD of the organic light-emitting diode OLED.

[0190] Figure 12 is a plan view showing another example of Figure 2 the pixel. Figure 13 is a cross-sectional view taken along the line IV-IV' of Figure 12 .

[0191] In Figure 12 , components that are the same as those described with reference to Figure 3 are denoted by the same reference numerals, and repeated descriptions thereof will be omitted. In addition, except for the shielding pattern SDP and the repair line pattern RLP, Figure 12 the pixel can have a configuration that is substantially the same as or similar to the configuration of the pixel of Figure 3 .

[0192] Referring to Figures 2 to 12 , the display device 1000 can include a substrate SUB, a plurality of conductive lines, and pixels PX connected to the conductive lines.

[0193] The shielding pattern SDP and the repair line pattern RLP may be included in the same layer as the first power line PL1 and the upper electrode UE of the storage capacitor Cst, and may be made of the same material as the first power line PL1 and the upper electrode UE of the storage capacitor Cst, through the same process as the first power line PL1 and the upper electrode UE of the storage capacitor Cst.

[0194] In a plan view, the shielding pattern SDP may be disposed between the data line DLj and the gate node ( Figure 2 the first node N1) of the first transistor T1 (e.g., the fourth bridging pattern BRP4), and may be spaced apart from the data line DLj and the gate node N1 of the first transistor T1. The shielding pattern SDP may be connected to the first initialization line VIL1 via the fourteenth contact hole CNT14, and one end of the shielding pattern SDP may be floating.

[0195] According to the arrangement of the shielding pattern SDP, the electrical influence (e.g., coupling capacitance) between the data line DLj and the gate node can be reduced. Therefore, image crosstalk can be minimized.

[0196] The repair line pattern RLP may extend in the first direction DR1. The repair line pattern RLP may connect the organic light-emitting diode connected to the pixel circuit determined to be a defective pixel circuit to the repair pixel circuit outside the display area. In an exemplary embodiment, for example, the defective pixel circuit is disconnected from the organic light-emitting diode, and the corresponding organic light-emitting diode may be electrically connected to the repair pixel circuit through the repair line pattern RLP.

[0197] Figure 14 is a plan view showing an example of the power lines included in the Figure 1 display device.

[0198] Referring to Figure 1 , Figure 3 , Figure 9 , Figure 10 , Figure 11 and Figure 14 , the display device 1000 may include a plurality of power lines PL that supply a first power voltage ELVDD to the pixels PX.

[0199] The power line PL may include first to third conductive patterns PL1 to PL3 (hereinafter referred to as the first to third power lines) that are electrically connected to each other.

[0200] The first power line PL1 may be disposed on the first insulating intermediate layer IL1 and extend in the first direction DR1. In an exemplary embodiment, for example, the first direction DR1 may be a horizontal direction (or pixel row direction), and the second direction DR2 may be a vertical direction (pixel column direction) intersecting the first direction DR1. In an exemplary embodiment, a part of the first power line PL1 may be the upper electrode UE of the storage capacitor Cst. The area of the first power line PL1 may be larger than the area of the second power line PL2. Therefore, the resistance of the first power line PL1 can be reduced.

[0201] The second power line PL2 may be disposed on the second insulating intermediate layer IL2 and extend in the first direction DR1. The second power line PL2 may be electrically connected to the first power line PL1 via the first contact hole CNT1.

[0202] Since the second power line PL2 includes a low-resistance metal, the width (or area) of the second power line PL2 in the second direction DR2 may be smaller than the area of the first power line PL1 in the second direction DR2.

[0203] The third power line PL3 may be disposed on the third insulating intermediate layer IL3 and extend in the second direction DR2. The third power line PL3 may be electrically connected to the second power line PL2 via the second contact hole CNT2. Thus, all of the first power line PL1 to the third power line PL3 may be electrically connected to each other. However, this is merely illustrative, and the stacking order of the first power line PL1 to the third power line PL3 is not limited thereto. In addition, the power line extending in the second direction DR2 may have a double wiring structure. Further, the power line may have a stacked wiring structure of three or more (i.e., a plurality of) in one direction.

[0204] As described above, by connecting the first power line PL1 to the third power line PL3, the power line PL may have a mesh structure provided with three conductive layers. The first power line PL1 and the second power line PL2 may be disposed in a double wiring structure in which at least a part of the first conductive pattern PL1 and the second conductive pattern PL2 extends in the first direction DR1 to overlap each other. Therefore, the voltage drop (i.e., IR drop) of the first power supply voltage ELVDD can be reduced. Accordingly, the luminance uniformity of the display device 1000 can be improved.

[0205] Figure 15 is a plan view showing an example of a scan line included in a Figure 1 display device.

[0206] Reference Figure 1 、 Figure 2 、 Figure 3 、 Figure 8 、 Figure 10 and Figure 15, the display device 1000 may include a plurality of scan lines GI, GW, and GB that provide scan signals to the pixels PX.

[0207] The first scan line GI, the second scan line GW, and the third scan line GB may extend in a first direction DR1 and be disposed on a second insulating intermediate layer IL2. The first scan line GI, the second scan line GW, and the third scan line GB may be electrically connected to gate electrodes GE2, GE3, GE4, and GE7 corresponding to the first scan line GI, the second scan line GW, and the third scan line GB via predetermined contact holes CNT3, CNT4, CNT5, and CNT6.

[0208] The first scan line GI, the second scan line GW, and the third scan line GB include a conductive layer including a low-resistance material, such that the resistance of the first scan line GI, the second scan line GW, and the third scan line GB is reduced. Accordingly, the RC delay of the scan signal may be minimized. The scan lines GI, GW, and GB are provided through a bridging structure between the gate electrodes and a conductive pattern on the second insulating intermediate layer IL2, such that the influence from peripheral interference and static electricity may be reduced.

[0209] In an exemplary embodiment, an emission control line ELi may also be disposed on the second insulating intermediate layer IL2. That is, the emission control line ELi may include the same material as the first scan line GI, the second scan line GW, and the third scan line GB in the same layer as the first scan line GI, the second scan line GW, and the third scan line GB.

[0210] Figure 16 is a plan view showing another example of a scan line included in a Figure 1 display device.

[0211] In Figure 16 , components identical to those described with reference to Figure 15 are denoted by the same reference numerals, and repeated descriptions thereof will be omitted. In addition, except for the third scan line GB, Figure 16 the scan lines of Figure 15 may have a configuration substantially the same as or similar to the configuration of the scan lines of

[0212] Reference Figure 16 , the third scan line GB may include the same material as the emission control line ELi in the same layer as the emission control line ELi through the same process.

[0213] The third scan line GB is used to control the initialization of the first electrode AD of the organic light-emitting diode OLED before or after data is written, and is less affected by RC delay. In addition, the emission control signal transmitted to the emission control line ELi has a sufficiently long on / off state, and thus, the emission control line ELi is less affected by RC delay. Therefore, the third scan line GB and the emission control line ELi can be integrated with the gate electrode in the same layer as the predetermined gate electrode.

[0214] However, this is merely illustrative, and at least one of the first scan line GI and the second scan line GW can be provided in the same layer as the gate electrode. The scan line not provided in the same layer as the gate electrode can be provided in the same layer as the second conductive pattern PL2.

[0215] Figure 17 is a plan view showing Figure 2 an example of a pixel. Figure 18 is a plan view showing Figure 1 an example of a power line included in the display device.

[0216] In Figure 17 and Figure 18 , components identical to those described with reference to Figure 3 are denoted by the same reference numerals, and their repeated description will be omitted. In addition, except for the positions where some of the conductive patterns are provided, Figure 17 the pixels of Figure 3 may have a configuration substantially the same as or similar to the configuration of the pixels of

[0217] Referring to Figure 1 , Figure 17 and Figure 18 , the display device 1000 may include a substrate SUB, a plurality of conductive lines, and pixels PX connected to the conductive lines.

[0218] The pixel PX may include a pixel circuit provided with first to seventh transistors T1 to T7 and a storage capacitor Cst, and an organic light-emitting diode connected to the pixel circuit. The pixel circuit may be electrically connected to scan lines SLi and SLi-1, data line DLj, power line PL, and initialization line VIL.

[0219] Figure 17 The j-th data line DLj included in the pixel PX of

[0220] As Figure 18As shown, the power line PL may include a first power line PL1, a second power line PL2, and a third power line PL3. The first power line PL1 and the second power line PL2 may extend in a horizontal direction, and the third power line PL3 may extend in a vertical direction.

[0221] The first power line PL1 and the second power line PL2 may be disposed in different layers and are electrically connected to each other via a first contact hole CNT1 and a second contact hole CNT2. In an exemplary embodiment, for example, the first power line PL1 and the second power line PL2 may be electrically connected to each other via the first contact hole CNT1, and the second power line PL2 and the third power line PL3 may be electrically connected to each other via the second contact hole CNT2.

[0222] The first power line PL1 and the second power line PL2 are disposed in a double wiring structure in the horizontal direction so that the voltage drop (i.e., IR drop) of the first power supply voltage ELVDD can be reduced. Accordingly, the brightness uniformity of the display device 1000 can be improved.

[0223] As described above, the power line PL of the display device 1000 according to an exemplary embodiment of the present invention has a double wiring structure in which at least a part of the conductive pattern extends in a first direction to overlap each other, so that the voltage drop (i.e., IR drop) of the first power supply voltage ELVDD can be reduced.

[0224] In addition, the first scan line GI, the second scan line GW, and the third scan line GB may include a low-resistance metal material such as aluminum alloy. Accordingly, the resistance of the scan lines GI, GW, and GB is reduced, so that the RC delay of the scan signal can be reduced. In addition, at least one of the scan lines GI, GW, and GB is disposed in a conductive layer (i.e., a layer different from the gate electrode) including a low-resistance material (such as aluminum alloy) and is connected to the gate electrode via a contact hole. Accordingly, the resistance of the scan lines G1, GW, and GB is reduced, so that the RC delay of the scan signal can be minimized. Consequently, the influence from peripheral interference and static electricity can be reduced.

[0225] In addition, in the storage capacitor Cst according to an exemplary embodiment of the present invention, an opening existing in an existing storage capacitor is removed, so that a capacitance change caused by the formation of the opening is eliminated, and the capacitance (i.e., the area of the electrode) can be increased. Consequently, display spots and image crosstalk caused by a capacitance change of the storage capacitor Cst can be minimized.

[0226] Figure 19 is a plan view showing an example of an initialization line included in a Figure 1 display device.

[0227] Refer to Figure 1 , Figure 4 , Figure 11 andFigure 19 , the initialization line VIL (refer to Figure 2 ) may include a first initialization line (first initialization conductive pattern) VIL1 extending in a first direction DR1 and a second initialization line (second initialization conductive pattern) VIL2 extending in a second direction DR2.

[0228] According to the connection relationship between the first initialization line VIL1 and the second initialization line VIL2, the initialization line VIL may be arranged in a mesh structure in Figure 1 the display area DA.

[0229] In an exemplary embodiment, the first initialization line VIL1 may include the same material as the active pattern in the same layer as the active pattern. In an exemplary embodiment, for example, the first initialization line VIL1 may include a semiconductor layer doped with impurities.

[0230] The second initialization line VIL2 may be arranged on a third insulating intermediate layer IL3. The second initialization line VIL2 may include the same material as the third conductive pattern PL3 in the same layer as the third conductive pattern PL3.

[0231] In an exemplary embodiment, the second initialization line VIL2 may be connected to the first initialization line VIL1 via a contact hole CNT penetrating through the first insulating intermediate layer IL1, the second insulating intermediate layer IL2, the third insulating intermediate layer IL3, and the gate insulating layer GIL.

[0232] However, this is merely illustrative, and the first initialization line VIL1 is not limited thereto. In an exemplary embodiment, for example, the first initialization line VIL1 may also be arranged in the same layer as the second conductive pattern PL2 arranged on the second insulating intermediate layer IL2. The first initialization line arranged on the second insulating intermediate layer IL2 may be connected to the first initialization line VIL1 and / or the second initialization line VIL2 arranged in the same layer as the active pattern via a predetermined contact hole.

[0233] The present invention can be applied to a display device and an electronic device including the display device. In an exemplary embodiment, for example, an organic light-emitting display device can be applied not only to electronic devices such as computers, mobile phones, smart phones, and smart tablets, but also to vehicle navigation systems, head-mounted displays, etc. In addition, the organic light-emitting display device can be applied to a wearable display device wearable on a user's body.

[0234] In the display device according to the present invention, the resistance of the power line and the scan line is reduced, so that the RC delay of the scan signal and the voltage drop through the power line can be minimized. In addition, an improved capacitance of the storage capacitor can be ensured uniformly. Therefore, the brightness uniformity and image quality of the display device can be improved.

[0235] Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some instances, as will be apparent to those of ordinary skill in the art upon the filing of the present application, features, characteristics and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and / or elements described in connection with other exemplary embodiments, unless otherwise specifically indicated. Accordingly, those skilled in the art will appreciate that various changes may be made in form and detail without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. Display device, comprising: a substrate including a display area and a non-display area; a plurality of pixels located in the display area, each of the plurality of pixels including at least one transistor, a storage capacitor connected to the at least one transistor, and a light-emitting element connected to the at least one transistor; a plurality of scan lines connected to each of the plurality of pixels, the plurality of scan lines extending in a first direction; data lines connected to each of the plurality of pixels, the data lines extending in a second direction; and a power line supplying a first power supply voltage to the light-emitting element, wherein the at least one transistor includes: an active pattern disposed on the substrate; a source electrode and a drain electrode each connected to the active pattern; a gate electrode disposed on the active pattern, and a gate insulating layer overlapping the active pattern is interposed between the gate electrode and the active pattern; an insulating intermediate layer covering the gate electrode and including a first insulating intermediate layer, a second insulating intermediate layer, and a third insulating intermediate layer stacked in sequence; and a protective layer disposed on the insulating intermediate layer, and wherein the power line includes: a first conductive pattern extending in the first direction, the first conductive pattern disposed on the first insulating intermediate layer; a second conductive pattern extending in the first direction, the second conductive pattern disposed on the second insulating intermediate layer, the second conductive pattern being connected to the first conductive pattern via a first contact hole; and a third conductive pattern extending in the second direction, the third conductive pattern disposed on the third insulating intermediate layer, the third conductive pattern being connected to the second conductive pattern via a second contact hole.

2. The display device according to claim 1, wherein, the storage capacitor includes: a lower electrode disposed in the same layer as the gate electrode; and an upper electrode overlapping the lower electrode, the upper electrode disposed on the first insulating intermediate layer.

3. The display device according to claim 2, wherein, at least a part of the first conductive pattern and the second conductive pattern overlaps with the lower electrode of the storage capacitor.

4. The display device according to claim 2, wherein, the area of the first conductive pattern overlapping with the lower electrode is larger than the area of the second conductive pattern overlapping with the lower electrode.

5. The display device according to claim 2, wherein, in a plan view, no opening is defined in the upper electrode.

6. The display device according to claim 1, wherein, through the connection of the first conductive pattern, the second conductive pattern, and the third conductive pattern, the power line has a mesh structure.

7. The display device according to claim 1, wherein, some of the plurality of scan lines are disposed in the same layer as the second conductive pattern and are connected to the gate electrode.

8. The display device according to claim 7, wherein, the remaining scan lines of the plurality of scan lines are disposed in the same layer as the gate electrode.

9. The display device according to claim 7, wherein, the gate electrode is a conductive pattern having an island shape.

10. The display device according to claim 7, wherein, at least one of the scan lines includes aluminum alloy.

11. The display device according to claim 7, further comprising: an emission control line connected to each of the plurality of pixels, the emission control line extending in the first direction.

12. The display device according to claim 11, wherein, the emission control line is disposed in the same layer as the gate electrode.

13. The display device according to claim 11, wherein, the emission control line is disposed in the same layer as the second conductive pattern.

14. The display device according to claim 1, further comprising: an initialization line for supplying an initialization voltage to the plurality of pixels, wherein the initialization line includes a first initialization conductive pattern disposed in the same layer as the second conductive pattern, the first initialization conductive pattern extending in the first direction.

15. The display device according to claim 14, wherein, the initialization line further includes: a second initialization conductive pattern disposed in the same layer as the third conductive pattern, the second initialization conductive pattern extending in the second direction.

16. The display device according to claim 14, further comprising: a shielding pattern disposed in the same layer as the first conductive pattern, the shielding pattern being connected to the first initialization conductive pattern.

17. The display device according to claim 16, wherein, the at least one transistor includes a driving transistor for controlling a driving current flowing through the light emitting element, wherein, in a plan view, the shielding pattern includes a portion located between the data line and the gate node of the driving transistor.

18. The display device according to claim 1, further comprising: an initialization line for supplying an initialization voltage to the plurality of pixels, wherein the initialization line includes: a first initialization conductive pattern disposed in the same layer as the active pattern, the first initialization conductive pattern extending in the first direction; and a second initialization conductive pattern disposed in the same layer as the third conductive pattern, the second initialization conductive pattern extending in the second direction.

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