Semiconductor package and method of manufacturing the same, and method of manufacturing a redistribution structure

Abstract

A method of manufacturing a semiconductor package can include forming a lower redistribution layer, forming a stack on a portion of the lower redistribution layer, and stacking a semiconductor die on a top surface of the lower redistribution layer. The forming of the stack can include applying a photoimageable dielectric material to form a first insulating layer on the top surface of the lower redistribution layer, forming a first via to penetrate the first insulating layer, applying a photoimageable dielectric material to form a second insulating layer on a top surface of the first insulating layer, and forming a second via to penetrate the second insulating layer.

Description

[0001] Cross-reference to related applications

[0002] Korean Patent Application No. 10-2018-0119089, filed on October 5, 2018, with the Korean Intellectual Property Office and entitled "Semiconductor Package, Method of Fabricating Semiconductor Package, and Method of Fabricating Re-Distribution Structure", is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to a semiconductor package, and more particularly to a semiconductor package including a redistribution layer. Background Technology

[0004] When an integrated circuit (IC) chip is provided in the form of a semiconductor package, the IC chip can be easily used as part of an electronic product. A semiconductor package may include a printed circuit board (PCB) and a semiconductor chip, with the semiconductor chip mounted on the PCB and electrically connected to the PCB via bonding wires or bumps. Summary of the Invention

[0005] The embodiment aims to provide a semiconductor package comprising: a lower redistribution layer; a stack on a first region of a top surface of the lower redistribution layer; and a semiconductor chip on a second region of the top surface of the lower redistribution layer. The stack may include: a first insulating layer on the top surface of the lower redistribution layer; a second insulating layer on the top surface of the first insulating layer; a first via penetrating the first insulating layer; and a second via penetrating the second insulating layer, wherein the second via has a vertically extending central axis spaced apart from the vertically extending central axis of the first via.

[0006] The embodiments also aim at a method of manufacturing a redistribution structure, the method comprising: forming a lower redistribution layer; and forming a stack on the lower redistribution layer. The formation of the stack may include: forming a first insulating layer on a top surface of the lower redistribution layer; forming a first via to penetrate the first insulating layer; forming a second insulating layer on the top surface of the first insulating layer; and forming a second via to penetrate the second insulating layer.

[0007] The embodiments also aim at a method of manufacturing a semiconductor package, the method comprising: forming a lower redistribution layer; forming a stack on a portion of the lower redistribution layer; and stacking a semiconductor chip onto a top surface of the lower redistribution layer. The formation of the stack may include: coating a photoimageable dielectric material to form a first insulating layer on the top surface of the lower redistribution layer; forming a first channel to penetrate the first insulating layer; coating a photoimageable dielectric material to form a second insulating layer on the top surface of the first insulating layer; and forming a second channel to penetrate the second insulating layer. Attached Figure Description

[0008] The features will become apparent to those skilled in the art from the detailed description of the exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 A flowchart of a method for manufacturing a semiconductor package according to an example embodiment is shown.

[0010] Figure 2 A cross-sectional view of a carrier substrate according to an example embodiment is shown.

[0011] Figure 3 It shows according to Figure 1 The flowchart shows a cross-sectional view of the steps involved in forming the lower redistribution layer.

[0012] Figures 4A to 4I It shows according to Figure 1 The flowchart shows a cross-sectional view of the steps involved in forming the stack.

[0013] Figure 5 It shows according to Figure 1 The flowchart is a cross-sectional view of the steps for stacking semiconductor chips.

[0014] Figure 6 It shows according to Figure 1 A cross-sectional view of the molding step in the flowchart.

[0015] Figure 7 It shows according to Figure 1 The flowchart shows a cross-sectional view of the steps involved in forming the upper redistribution layer.

[0016] Figure 8 A cross-sectional view is shown of the steps for removing the carrier substrate according to an example embodiment.

[0017] Figure 9A It shows according to Figure 1 The flowchart shows a cross-sectional view of the steps involved in stacking the upper package.

[0018] Figure 9B A plan view of a semiconductor package according to an example embodiment is shown.

[0019] Figure 10 A cross-sectional view of a semiconductor package according to an example embodiment is shown.

[0020] Figure 11 A cross-sectional view of a semiconductor package according to an example embodiment is shown.

[0021] Figure 12 A cross-sectional view of a semiconductor package according to an example embodiment is shown.

[0022] Figure 13 A cross-sectional view of a semiconductor package according to an example embodiment is shown. Detailed Implementation

[0023] Figure 1 It is a flowchart illustrating a method for manufacturing a semiconductor package, and Figures 2 to 9A It shows the basis Figure 1 The flowchart shows a cross-sectional view of the process for manufacturing semiconductor packages.

[0024] In the following text, Figure 2 The direction D1 will be referred to as the first direction or the upward direction, and Figure 2 The direction D2 will be referred to as the second direction or the rightward direction.

[0025] See Figure 1 The method S for manufacturing a semiconductor package may include: forming a lower redistribution layer (in S1), forming a stack (in S2), stacking semiconductor chips (in S3), performing a molding process (in S4), forming an upper redistribution layer (in S5), and stacking an upper package (in S6).

[0026] See Figure 1 and Figure 2 A carrier substrate 8 can be provided for forming the lower redistribution layer (in S1). See also Figure 3 The lower redistribution layer 1 can be formed on the top surface of the carrier substrate 8. In an example embodiment, the lower redistribution layer 1 can be formed by the following process: depositing or coating a photosensitive material on the carrier substrate 8, forming holes in the photosensitive material by exposure and development processes, and filling the holes with a conductive material.

[0027] The lower redistribution layer 1 may include a lower redistribution insulator 11, a lower redistribution external terminal 131, a lower redistribution pattern 133, a lower redistribution connecting terminal 135, and a lower redistribution passage 15. A lower redistribution hole 17 may be provided in the bottom surface of the lower redistribution insulator 11.

[0028] The lower redistribution insulator 11 may include a photoimageable dielectric (PID), i.e., a photosensitive material. In an example embodiment, the photosensitive material may be a photosensitive polymer or may include a photosensitive polymer. The photosensitive polymer may be or may include photosensitive polyimide (PSPI), polybenzoxazole (PBO), phenolic polymers, benzocyclobutene (BCB) polymers, or combinations thereof.

[0029] The lower redistribution insulator 11 can serve as the main body of the lower redistribution layer 1. The lower redistribution insulator 11 can protect the lower redistribution pattern 133. The lower redistribution insulator 11 can be a multilayer structure.

[0030] In an example embodiment, a plurality of lower redistribution patterns 133 may be provided in the first direction D1 and the second direction D2. The lower redistribution patterns 133 may be spaced apart from each other in the first direction D1 and may be configured to form multiple layers.

[0031] The lower redistribution path 15 can be used to electrically connect lower redistribution patterns 133 that are spaced apart from each other in the first direction D1. In this specification, the term "electrically connected element" can mean a direct connection between elements or an indirect connection between elements via another conductive element. The lower redistribution path 15 may have an increasing width in the direction along the first direction D1. In another example embodiment, the width of the lower redistribution path 15 may be constant in the first direction D1, or it may vary in various other ways.

[0032] The lower redistribution external terminal 131 may be disposed on a first region of the top surface of the lower redistribution insulator 11. The first region may be an edge region of the top surface of the lower redistribution insulator 11. In an example embodiment, the lower redistribution external terminal 131 may be a pad. In an example embodiment, multiple lower redistribution external terminals 131 may be provided. The lower redistribution external terminal 131 may be used to electrically connect at least one of the lower redistribution patterns 133 to the semiconductor chip 5 (e.g., see...). Figure 9A Integrated circuit (not shown).

[0033] The lower redistribution connection terminal 135 may be located on a second region of the top surface of the lower redistribution insulator 11. The second region may be a central region of the top surface of the lower redistribution insulator 11. For example, the second region may be located within a region enclosed by a first region. Therefore, the first region may be closer to the side surface of the lower redistribution insulator 11 than the second region. In an example embodiment, the lower redistribution connection terminal 135 may be a pad. In an example embodiment, multiple lower redistribution connection terminals 135 may be provided. The lower redistribution connection terminal 135 may be used to electrically connect at least one of the lower redistribution patterns 133 to the semiconductor chip 5 (e.g., see...). Figure 9A).

[0034] Each of the lower redistribution external terminal 131, the lower redistribution pattern 133, the lower redistribution connection terminal 135, and the lower redistribution passage 15 may be formed of or include a conductive material. In an example embodiment, the conductive material may include a metallic material, such as copper or aluminum. The lower redistribution hole 17 may be formed in the bottom surface of the lower redistribution layer 1 to have a specific depth in the first direction D1, thereby exposing at least one of the lower redistribution patterns 133.

[0035] See Figure 1 and Figure 4A Forming a stack (in S2) may include forming a stack 3 on the lower redistribution layer 1 (e.g., see...). Figure 9A The first preliminary insulating layer 3111 can be formed by depositing or coating a photoimageable dielectric (PID) (i.e., a photosensitive material) on the top surface of the lower redistribution layer 1. In an example embodiment, the photosensitive material may include a photosensitive polymer. The photosensitive polymer may be or include photosensitive polyimide (PSPI), polybenzoxazole (PBO), phenolic polymers, benzocyclobutene (BCB) polymers, or combinations thereof. The first preliminary insulating layer 3111 may cover the lower redistribution external terminal 131 and the lower redistribution connection terminal 135.

[0036] See Figure 4B The first initial insulating layer 3111 can be patterned using exposure and development processes. The first insulating layer 311 can be formed using exposure and development processes on the first initial insulating layer 3111. The development process used to form the first insulating layer 311 can include a positive development (PTD) process or a negative development (NTD) process. In an example embodiment, the bottom surface of the first insulating layer 311 can contact the top surface of the lower redistribution layer 1. In an example embodiment, when the lower redistribution insulator 11 is a multilayer structure, the first insulating layer 311 can be thicker than one of the layers constituting the lower redistribution insulator 11.

[0037] Due to the exposure and development processes, a first via 311h can be formed to penetrate at least a portion of the first initial insulating layer 3111 from the top surface of the first initial insulating layer 3111 to the top surface of the lower redistribution layer 1. For example, the first via 311h can be formed to expose the lower redistribution outer terminal 131. In an example embodiment, the first via 311h can be formed to have a decreasing width or a constant width in the direction from the top surface of the first insulating layer 311 toward the lower redistribution layer 1. In an example embodiment, a plurality of first vias 311h can be provided. The first vias 311h can be spaced apart from each other in the second direction D2.

[0038] Due to the exposure and development processes, the first hole 311h' can be formed to penetrate at least a portion of the first initial insulating layer 3111 from the top surface of the first initial insulating layer 3111 to the top surface of the lower redistribution layer 1. For example, the first hole 311h' can be formed to expose the lower redistribution connection terminal 135. The first hole 311h' can be formed in the second region. Here, the first hole 311h' can refer to the empty space between the first inner surfaces 311c. Semiconductor chip 5 (e.g., see...) Figure 9A It can be located in the first hole 311h'. This will be described in more detail below.

[0039] See Figure 4C A conductor can be formed in the first through-hole 311h of the first insulating layer 311. In an example embodiment, the conductor can be formed by an electroplating process. Hereinafter, the conductor formed in the first through-hole 311h will be referred to as the first via 315. A conductor, referred to as the first interconnect 313, can be formed on the top surface of the first via 315 and the top surface 311b of the first insulating layer 311. The first via 315 and the first interconnect 313 can be electrically connected to each other. For example, the first via 315 and the first interconnect 313 can be formed of copper or include copper. The first via 315 can be electrically connected to the lower redistribution external terminal 131. For example, the first via 315 can be electrically connected to the lower redistribution pattern 133 via the lower redistribution external terminal 131. The first via 315 and / or the first insulating layer 311 can be formed to cover all the top surfaces of the lower redistribution external terminal 131. Therefore, the lower redistribution external terminal 131 may not be exposed to the outside. Therefore, oxidation of the lower redistributed external terminals 131 can be prevented during the formation of the stack (in S2). As a result, the reliability of the lower redistributed external terminals 131 can be improved.

[0040] See Figure 4DThe second initial insulating layer 3311 can be formed on the top surface 311b of the first insulating layer 311 and on the top surface of the lower redistribution layer 1. The second initial insulating layer 3311 can be formed of or include a photoimageable dielectric (PID), i.e., a photosensitive material. The second initial insulating layer 3311 can be formed by a deposition or coating process. In an example embodiment, the photosensitive material can be or includes a photosensitive polymer. For example, the photosensitive polymer can be or includes photosensitive polyimide (PSPI), polybenzoxazole (PBO), phenolic polymers, benzocyclobutene (BCB) polymers, or combinations thereof. The second initial insulating layer 3311 can be formed to cover the first interconnect 313 and the lower redistribution connection terminal 135. The first top surface 331b of the second initial insulating layer 3311 on the first interconnect 313 can be located at a higher level than the second top surface 331x of the second initial insulating layer 3311 on the lower redistribution connection terminal 135. The first top surface 331b and the second top surface 331x can be connected to each other via the inclined surface 331y. In an example embodiment, the second initial insulating layer 3311 can be formed to cover a structure including the first insulating layer 311 with a substantially uniform thickness.

[0041] See Figure 4E The second initial insulating layer 3311 can be patterned by exposure and development processes. The second insulating layer 331 can be formed by exposure and development processes on the second initial insulating layer 3311. The development process used to form the second insulating layer 331 can include a positive development (PTD) process or a negative development (NTD) process.

[0042] Due to the exposure and development processes, a second via 331h can be formed to penetrate at least a portion of the second initial insulating layer 3311 from the top surface of the second initial insulating layer 3311 to the top surface of the lower redistribution layer 1 or the top surface 311b of the first insulating layer 311. For example, the second via 331h can be formed to expose the first interconnect 313. In an example embodiment, the second via 331h can be formed to have a decreasing width or a constant width in the direction from the top surface of the second insulating layer 331 toward the first insulating layer 311. In an example embodiment, a plurality of second vias 331h can be provided. The second vias 331h can be spaced apart from each other in the second direction D2.

[0043] Due to the exposure and development processes, at least a portion of the second initial insulating layer 3311 can be recessed from the top surface of the second initial insulating layer 3311 to the top surface of the lower redistribution layer 1 to expose the lower redistribution connection terminal 135. For example, at least a portion of the second initial insulating layer 3311 can be removed from the first hole 311h' to re-expose the lower redistribution connection terminal 135. Furthermore, due to the exposure and development processes, a second hole 331h' can be formed on the first hole 311h'. The second hole 331h' may refer to the empty space between the second inner surfaces 331c. The second hole 331h' and the first hole 311h' can be connected to form a single empty space. Semiconductor chip 5 (e.g., see...) Figure 9A The first initial insulating layer 3311 can be located in the first hole 311h'. This will be described in more detail below. The second initial insulating layer 3311 can be patterned by exposure and development processes to form the second insulating layer 331. The development process used to form the second insulating layer 331 can include a positive development (PTD) process or a negative development (NTD) process.

[0044] The first insulating layer 311 and the second insulating layer 331 may form a stepped structure in the direction toward the lower redistribution connection terminal 135. Therefore, when viewed in a plan view, the first inner surface 311c of the first insulating layer 311 may not be aligned with the second inner surface 331c of the second insulating layer 331. The first inner surface 311c may be located within the second inner surface 331c. Therefore, when viewed in a plan view, the first inner surface 311c may be closer to the lower redistribution connection terminal 135 than the second inner surface 331c. The area of ​​the second top surface 331b of the second insulating layer 331 may be smaller than the area of ​​the first top surface 311b of the first insulating layer 311. In an example embodiment, the second insulating layer 331 may be formed on the first insulating layer 311 to expose a portion 311b' of the first insulating layer 311. The exposed portion 311b' may be adjacent to the first inner surface 311c.

[0045] See Figure 4F A conductor can be formed in the second via 331h of the second insulating layer 331. In an example embodiment, the conductor can be formed by an electroplating process. Hereinafter, the conductor formed in the second via 331h will be referred to as the second via 335. Conductors disposed on the top surface of the second via 335 and the top surface 331b of the second insulating layer 331 will be referred to as the second interconnect 333. The second via 335 and the second interconnect 333 can be electrically connected to each other. For example, the second via 335 and the second interconnect 333 can be formed of copper or include copper. The second via 335 can be electrically connected to the first interconnect 313. For example, the second via 335 can be electrically connected to the first via 315 through the first interconnect 313.

[0046] In an example embodiment, when viewed in a plan view, the first passage 315 and the second passage 335 may be off-center from each other. For example, the vertically extending central axis C1 of the first passage 315 may be spaced apart from the vertically extending central axis C2 of the second passage 335. The off-center first passage 315 and the second passage 335 may be connected to each other via a first interconnect 313. By accommodating an off-centered arrangement between the first passage 315 and the second passage 335, the technical limitations in setting the lower redistribution pattern 133 of the lower redistribution layer 1 can be reduced.

[0047] See Figure 4G The third initial insulating layer 3511 may be formed on the top surface 331b of the second insulating layer 331 and on the top surface of the lower redistribution layer 1. The third initial insulating layer 3511 may be formed of or include a photoimageable dielectric (PID), i.e., a photosensitive material. The third initial insulating layer 3511 may be formed by a deposition or coating process. In an example embodiment, the photosensitive material may include a photosensitive polymer. For example, the photosensitive polymer may be or include photosensitive polyimide (PSPI), polybenzoxazole (PBO), phenolic polymers, benzocyclobutene (BCB) polymers, or combinations thereof. The third initial insulating layer 3511 may cover the second interconnect 333 and the lower redistribution connection terminal 135. The first top surface 351b of the third initial insulating layer 3511 on the second interconnect 333 may be located at a higher level than the second top surface 351x of the third initial insulating layer 3511 on the lower redistribution connection terminal 135. The first top surface 351b and the second top surface 351x can be connected to each other via two inclined surfaces 351y and 351z. The first insulating layer 311 and the second insulating layer 331 can form a stepped structure. Therefore, when the third initial insulating layer 3511 is formed, abrupt changes in the height difference of the underlying structure can be prevented. Therefore, the third initial insulating layer 3511 can be formed to have a substantially uniform thickness.

[0048] See Figure 4H The third initial insulating layer 3511 can be patterned through exposure and development processes to form the third insulating layer 351. The development process used to form the third insulating layer 351 may include a positive development (PTD) process or a negative development (NTD) process.

[0049] Due to the exposure and development processes, at least a portion of the third initial insulating layer 3511 can be recessed from the top surface of the third initial insulating layer 3511 to the top surface of the lower redistribution layer 1 or the top surface 331b of the second insulating layer 331 to expose the lower redistribution connection terminal 135 and the second interconnect 333. For example, a third via 351h can be formed to expose the second interconnect 333. In an example embodiment, the third via 351h can be formed to have a decreasing width or a constant width in the direction from the top surface of the third insulating layer 351 toward the second insulating layer 331. In an example embodiment, a plurality of third vias 351h can be provided. The third vias 351h can be spaced apart from each other in the second direction D2.

[0050] Due to the exposure and development processes, at least a portion of the third initial insulating layer 3511 can be recessed from the top surface of the third initial insulating layer 3511 to the top surface of the lower redistribution layer 1 to expose the lower redistribution connection terminal 135. For example, at least a portion of the third initial insulating layer 3511 can be removed from the first hole 311h' and the second hole 331h' to expose the lower redistribution connection terminal 135 again. Furthermore, the third hole 351h' can be formed on the second hole 331h'. The third hole 351h' can refer to the empty space between the third inner surfaces 351c. The third hole 351h' can be connected to the first hole 311h' and the second hole 331h' to form a single empty space. Semiconductor chip 5 (e.g., see...) Figure 9A The third initial insulating layer 3511 can be located in the first aperture 311h'. This will be described in more detail below. The third initial insulating layer 3511 can be patterned by exposure and development processes to form the third insulating layer 351. The development process used to form the third insulating layer 351 can include a positive development (PTD) process or a negative development (NTD) process.

[0051] The second insulating layer 331 and the third insulating layer 351 may form a stepped structure in the direction toward the lower redistribution connection terminal 135. Therefore, when viewed in a plan view, the second inner surface 331c of the second insulating layer 331 may not be aligned with the third inner surface 351c of the third insulating layer 351. The second inner surface 331c may be located inside the third inner surface 351c. Therefore, when viewed in a plan view, the second inner surface 331c may be closer to the lower redistribution connection terminal 135 than the third inner surface 351c. The area of ​​the third top surface 351b' of the third insulating layer 351 may be smaller than the area of ​​the second top surface 331b of the second insulating layer 331. In an example embodiment, the third insulating layer 351 may be formed on the second insulating layer 331 to expose a portion 331b' of the second top surface 331b of the second insulating layer 331. The exposed portion 331b' may be adjacent to the second inner surface 331c.

[0052] See Figure 4I A conductor can be formed in the third through-hole 351h of the third insulating layer 351. In an example embodiment, the conductor can be formed by an electroplating process. The conductor formed in the third through-hole 351h will be referred to as the third passage 355. The conductors formed on the top surface of the third passage 355 and the third top surface 351b of the third insulating layer 351 will be referred to as the upper terminal 353. The third passage 355 and the upper terminal 353 can be electrically connected to each other. For example, the third passage 355 and the upper terminal 353 can be formed of copper or include copper. The third passage 355 can be electrically connected to the second interconnect 333. For example, the third passage 355 can be electrically connected to the second passage 335 via the second interconnect 333.

[0053] In an exemplary embodiment, the second passage 335 and the third passage 355 may be eccentric to each other when viewed in a plan view. For example, when viewed in a plan view, the vertically extending central axis C2 of the second passage 335 may be spaced apart from the vertically extending central axis C3 of the third passage 355. The eccentrically positioned second passage 335 and third passage 355 may be connected to each other via a second interconnect 333. By accommodating the eccentric arrangement between the second passage 335 and the third passage 355, the number of terminals (e.g., see below) in the lower redistribution pattern 133 of the lower redistribution layer 1 and / or the upper package 9 can be reduced. Figure 9A Technical limitations at the time.

[0054] An example of a stack 3 comprising a first insulating layer 311, a second insulating layer 331, and a third insulating layer 351, as well as a first passage 315, a second passage 335, and a third passage 355, has been described above. In another example embodiment, the stack 3 may be configured to include one insulating layer and one passage layer. In another example embodiment, the stack 3 may be configured to include two insulating layers and two passage layers, or to include four or more insulating layers and four or more passage layers. The stack 3 disposed on the lower redistribution layer 1 may be referred to as a redistribution structure.

[0055] See Figure 1 and Figure 5 The stacked semiconductor chip (in S3) may include a stacked semiconductor chip 5 on the top surface of the lower redistribution layer 1. The semiconductor chip 5 may include at least one of a memory chip, a logic chip, or a combination thereof. The semiconductor chip 5 may be electrically connected to the lower redistribution connection terminal 135 of the lower redistribution layer 1 via an intermediate ball 22. Therefore, the semiconductor chip 5 may be electrically connected to the lower redistribution pattern 133. The semiconductor chip 5 may be disposed with its bottom surface 53 facing the top surface of the lower redistribution layer 1. For example, the intermediate ball 22 may be a solder ball.

[0056] When the semiconductor chip 5 is stacked on the top surface of the lower redistribution layer 1 and the intermediate ball 22 is located between the semiconductor chip 5 and the top surface of the lower redistribution layer 1, a bonding process can be performed. For example, the bonding process can be a reflow process or a hot-pressing process. The intermediate ball 22 and the lower redistribution connection terminal 135 can be bonded to each other through the bonding process.

[0057] In an example embodiment, the top surface 51 of the semiconductor chip 5 may be located at a level lower than the third top surface 351b of the third insulating layer 351. The semiconductor chip 5 may be located in an empty space defined by the stack 3. For example, the semiconductor chip 5 may be positioned with its side surfaces facing the first inner surface 311c, the second inner surface 331c, and / or the third inner surface 351c.

[0058] See Figure 1 and Figure 6 The molding process (in S4) may include forming a molding layer 4 to cover at least one of the surfaces of the semiconductor chip 5. The molding layer 4 can protect the semiconductor chip 5 from external attacks. Due to the molding layer 4, the semiconductor chip 5 can be protected from external heat, moisture, and / or impact. The molding layer 4 may be configured to dissipate heat generated from the semiconductor chip 5, the lower redistribution layer 1, and / or the stack 3 to the outside. In an example embodiment, the molding layer 4 may cover the top surface 51 of the semiconductor chip 5. In an example embodiment, the molding layer 4 may cover the outer surface (not shown) of the stack 3. The molding layer 4 may be configured to fill the gap region between the side surfaces of the semiconductor chip 5 and the first inner surface 311c, the second inner surface 331c, and / or the third inner surface 351c of the stack 3. A bottom filler 6 may also be provided around the lower redistribution connection terminal 135. In an example embodiment, the molding layer 4 may be formed of or include an epoxy molding compound (EMC) material. The molding process may include placing a lower redistribution layer 1 in a mold, stacking a semiconductor chip 5 and a stack 3 on the lower redistribution layer 1, and then injecting material for the molding layer 4 into the mold. In an example embodiment, the molding layer 4 may include an Ajinomoto build-up film (ABF). In another example embodiment, another insulator may be used for the molding layer 4.

[0059] See Figure 1 and Figure 7Forming the upper redistribution layer (in S5) may include forming the upper redistribution layer 7 on the top surface of the molded layer 4 and / or on the top of the stack 3 after the molding process. In an example embodiment, the upper redistribution layer 7 may be formed by depositing or coating a photosensitive material on the top surface of the molded layer 4 and / or on the top of the stack 3, forming holes in the photosensitive material by an exposure or development process, and filling the holes with a conductive material. The upper redistribution layer 7 may include a first upper redistribution insulating layer 711, a second upper redistribution insulating layer 713, an upper redistribution pattern 731, a first upper redistribution passage 751, a second upper redistribution passage 753, and an upper redistribution terminal 733.

[0060] A first upper redistribution insulating layer 711 may be disposed on the molding layer 4 and the stack 3. A second upper redistribution insulating layer 713 may be disposed on the first upper redistribution insulating layer 711. The first upper redistribution insulating layer 711 and the second upper redistribution insulating layer 713 may include a photoimageable dielectric (PID) material, i.e., a photosensitive material. The first upper redistribution insulating layer 711 and the second upper redistribution insulating layer 713 may protect the upper redistribution pattern 731, the first upper redistribution path 751 and the second upper redistribution path 753.

[0061] The first upper redistribution path 751 can be configured to penetrate the first upper redistribution insulation layer 711. In an example embodiment, a plurality of first upper redistribution paths 751 may be arranged along the second direction D2. At least one of the first upper redistribution paths 751 may be electrically connected to the upper terminal 353.

[0062] The upper redistribution pattern 731 may be disposed on the first upper redistribution path 751. In an example embodiment, a plurality of upper redistribution patterns 731 may be disposed. At least one of the upper redistribution patterns 731 may extend in the second direction D2. The upper redistribution pattern 731 may be electrically connected to the first upper redistribution path 751.

[0063] The second upper redistribution path 753 can be configured to penetrate the second upper redistribution insulating layer 713. In an example embodiment, a plurality of second upper redistribution paths 753 may be arranged along a second direction D2. The second upper redistribution paths 753 may be electrically connected to the upper redistribution pattern 731.

[0064] The upper redistribution terminal 733 may be disposed on the second upper redistribution path 753. In an example embodiment, multiple upper redistribution terminals 733 may be disposed. The upper redistribution terminal 733 may be electrically connected to the second upper redistribution path 753. In an example embodiment, the upper redistribution terminal 733 may be a pad.

[0065] Each of the upper redistribution pattern 731, the first upper redistribution path 751, the second upper redistribution path 753, and the upper redistribution terminal 733 may be formed of or include a conductive material. In an example embodiment, the conductive material may include a metallic material, such as copper or aluminum.

[0066] By providing the upper redistribution layer 7 on the semiconductor chip 5, the terminals of the upper package 9 can be freely configured (for example, see...). Figure 9A Therefore, the difficulty of designing the upper package 9 can be reduced.

[0067] See Figure 8 The carrier substrate 8 can be removed from the bottom surface of the lower redistribution layer 1. After removing the carrier substrate 8, a lower ball 21 can be formed on the lower redistribution pattern 133 exposed through the lower redistribution hole 17. The lower redistribution pattern 133 can be electrically connected to another package or board through the lower ball 21.

[0068] See Figure 1 and Figure 9A Stacking the upper package (in S6) may include stacking the upper package 9 on the upper redistribution layer 7. The upper package 9 may include an upper substrate 91, an upper semiconductor chip 93, an upper molding layer 95, upper wiring 97, etc. The upper package 9 and the upper redistribution terminal 733 may be electrically connected to each other via upper balls 23. For example, the upper balls 23 may be solder balls. The upper balls 23 and the upper redistribution terminal 733 may be bonded to each other. For example, the bonding process may be a reflow process or a hot-pressing process. The upper semiconductor chip 93 may be electrically connected to the upper wiring 97, the upper substrate 91, and the upper balls 23. Therefore, the upper package 9 may be electrically connected to the lower redistribution layer 1 via the upper redistribution layer 7 and the stack 3.

[0069] Figure 9B It is based on Figure 9A A plan view of a semiconductor package. Figure 9A It is along Figure 9B The cross-sectional view taken from line I-I' in the diagram.

[0070] See Figure 9B When viewed in a plan view, the semiconductor package can be constructed such that the area of ​​the semiconductor chip 5 is smaller than the area of ​​the stack 3. When viewed in a plan view, the semiconductor chip 5 can be located inside the stack 3. Figure 9B An example is shown in which the boundary of the stack 3 is located outside the boundary of the semiconductor chip 5 in all directions. For example, the boundary of the stack 3 may be located outside the boundary of the semiconductor chip 5 in the second direction D2, but the boundary of the semiconductor chip 5 may coincide with the boundary of the stack 3 in a third direction perpendicular to the first direction D1 and the second direction D2.

[0071] In an example embodiment, when viewed in a plan view, the area of ​​the lower redistribution layer 1 may be larger than the area of ​​the stack 3. In another example embodiment, the area of ​​the stack 3 may be substantially equal to the area of ​​the lower redistribution layer 1.

[0072] In the method for manufacturing a semiconductor package according to the example embodiment, a lower redistribution layer having a stack can be formed, and then a semiconductor chip can be stacked thereon. This allows the semiconductor package to use a lower redistribution layer, a stack, and a semiconductor chip that have already been identified as good products, and thus increases the overall yield of the semiconductor package. Furthermore, the lower redistribution layer having a stack can be formed by a separate process, which can be performed simultaneously with the formation of the semiconductor chip. Therefore, the overall process time for manufacturing the semiconductor package can be reduced.

[0073] In a semiconductor package according to an example embodiment, deposition, coating, exposure, and / or development processes can be used to form a stack. This can reduce the size of the vias. This can reduce the overall size of the semiconductor package. Furthermore, this can reduce the technical limitations associated with the height of the stack and with the size of the semiconductor chips allowed by the stack.

[0074] In the semiconductor package according to the example embodiment, the vias can be arranged to form various paths within the stack. Therefore, this reduces the technical limitations of setting the connection terminals of the lower redistribution layer, upper redistribution layer, and / or upper package, as well as designing the overall structure of the semiconductor package.

[0075] In a semiconductor package according to an example embodiment, the upper redistribution layer may allow for reduction of technical limitations related to the connection terminals of the lower redistribution layer and / or stack, as well as technical limitations in designing the overall structure of the semiconductor package.

[0076] In the semiconductor package according to the example embodiment, the first insulating layer and the second insulating layer can form a stepped structure. Therefore, a third initial insulating layer, which will serve as the third insulating layer, can be formed with a substantially uniform thickness. Thus, the third insulating layer can be formed to have the desired properties.

[0077] Figure 10 This is a cross-sectional view showing a semiconductor package according to an example embodiment.

[0078] In the following description, for the sake of brevity, elements similar to or the same as those in the foregoing embodiments will be identified by the same reference numerals as those in the foregoing embodiments, without repeating their description.

[0079] See Figure 10The stack 3 may include a first insulating layer 311', a first via 315', a first interconnect 313', a second insulating layer 331', a second via 335', ​​and a second interconnect 333'. The first inner surface 311'c of the first insulating layer 311' may be formed to be coplanar with the second inner surface 331'c of the second insulating layer 331'. Therefore, the first insulating layer 311' and the second insulating layer 331' may be formed without a stepped structure. For example, the second insulating layer 331' may be stacked on top of the first insulating layer 311' so that the first top surface 311'b of the first insulating layer 311' is not exposed.

[0080] An example of a stack 3 comprising two insulating layers (e.g., 311' and 331') has been described. The stack 3 may be constructed to include three or more insulating layers.

[0081] Figure 11 This is a cross-sectional view showing a semiconductor package according to an example embodiment.

[0082] In the following description, for the sake of brevity, elements similar to or the same as those in the foregoing embodiments will be identified by the same reference numerals as those in the foregoing embodiments, without repeating their description.

[0083] See Figure 11 The outer surface of the stack 3 may not be covered by the molding layer 4. For example, the first outer surface 311'a of the first insulating layer 311' and / or the second outer surface 331'a of the second insulating layer 311' may be exposed. The first outer surface 311'a and / or the second outer surface 331'a may be aligned to be coplanar with the outer surface of the lower redistribution layer 1.

[0084] Figure 12 This is a cross-sectional view showing a semiconductor package according to an example embodiment.

[0085] In the following description, for the sake of brevity, elements similar to or the same as those in the foregoing embodiments will be identified by the same reference numerals as those in the foregoing embodiments, without repeating their description.

[0086] See Figure 12 The stack 3 and the upper package 9 can be connected to each other without an upper redistribution layer between them. The second interconnect 333' can be in direct contact with the upper ball 23. The second interconnect 333' can be electrically connected to the upper package 9 via the upper ball 23.

[0087] Figure 13 This is a cross-sectional view showing a semiconductor package according to an example embodiment.

[0088] In the following description, for the sake of brevity, elements similar to or the same as those in the foregoing embodiments will be identified by the same reference numerals as those in the foregoing embodiments, without repeating their description.

[0089] See Figure 13 The top surface 4b of the molding layer 4 and the top surface 51' of the semiconductor chip 5 can be substantially coplanar with each other. For example, the molding layer 4 can be formed to expose the top surface 51' of the semiconductor chip 5.

[0090] By summarizing and reviewing, semiconductor package devices may include multiple semiconductor chips mounted on a package substrate, or may have a structure in which a package is stacked on another package.

[0091] As described above, embodiments may provide a method for manufacturing a semiconductor package with a redistribution layer using a chip-last process. Embodiments may also provide a method for reducing the via size in a semiconductor package.

[0092] In the method of manufacturing a semiconductor package according to the example embodiment, a post-chip process can be used to manufacture the package structure including the redistribution layer, and the redistribution layer and the semiconductor chip can be formed by separate processes.

[0093] In the method for manufacturing semiconductor packages according to the example embodiment, manufacturing time can be reduced and output can be increased.

[0094] In the method of manufacturing a semiconductor package according to the example embodiment, the size of the vias can be reduced, the technical limitations of constructing the vias can be reduced, and the overall volume of the semiconductor package can be reduced.

[0095] Example embodiments have been disclosed herein, and while specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor package, comprising: Lower redistribution layer; A stacked body, located on a first region of the top surface of the lower redistribution layer; as well as A semiconductor chip, located on a second region of the top surface of the lower redistribution layer, wherein: The stack includes: A first insulating layer is located on the top surface of the lower redistribution layer; A second insulating layer is formed on the top surface of the first insulating layer; A first pathway, which penetrates the first insulating layer; A first interconnect is located on the top surface of the first insulating layer and the top surface of the first passage, and has a bottom surface that is coplanar with the bottom surface of the second insulating layer. A second path, which penetrates the second insulating layer, and has a bottom surface that contacts the top surface of the first interconnect, for connection to the first path via the first interconnect; and A second interconnect is located on the top surface of the second insulating layer and the top surface of the second passage, and is connected to the second passage. The second passage has a vertically extending central axis, which is spaced apart from the vertically extending central axis of the first passage. The first insulating layer and the second insulating layer form a stepped structure in the direction toward the semiconductor chip.

2. The semiconductor package according to claim 1, wherein: The first path and the second path have an upwardly increasing width.

3. The semiconductor package of claim 2, wherein, The stack also includes: A third insulating layer, which is on the top surface of the second insulating layer; and A third pathway, which penetrates the third insulating layer, and The second interconnect connects the second path to the third path.

4. The semiconductor package of claim 1, further comprising an upper redistribution layer on the semiconductor chip and the stack, wherein, The upper redistribution layer is electrically connected to the lower redistribution layer through the stack.

5. The semiconductor package according to claim 1, wherein, The first insulating layer and the second insulating layer comprise a photo-imageable dielectric material.

6. The semiconductor package according to claim 2, wherein: The lower redistribution layer includes: Lower redistribution insulator; The lower redistribution external terminal is disposed on the lower redistribution insulator and electrically connected to the first passage; A lower redistribution pattern disposed within the lower redistribution insulator and electrically connected to the lower redistribution external terminals; and A lower redistribution connection terminal is disposed on the lower redistribution insulator and electrically connected to the lower redistribution pattern. The semiconductor chip is electrically connected to the lower redistribution connection terminal, and The first passage and the first insulating layer are configured to contact the top surface of the lower redistributed external terminal.

7. A method for manufacturing a redistributed structure, the method comprising: Forming a lower redistribution layer; as well as A stack is formed on the lower redistribution layer, the formation of the stack comprising: A first insulating layer is formed on the top surface of the lower redistribution layer; A first through-hole is formed to penetrate the first insulating layer and expose a portion of the edge region of the lower redistribution layer; a first hole is formed to penetrate the first insulating layer and expose the central region of the lower redistribution layer; A first passage is formed to fill the first through hole; A first interconnect is formed on the top surface of the first path and on the top surface of the first insulating layer; A second insulating layer is formed on the top surface of the first insulating layer, and the bottom surface of the second insulating layer is coplanar with the bottom surface of the first interconnect. A second via is formed to penetrate the second insulating layer and expose the first interconnect; A second hole is formed to penetrate the second insulating layer and connect to the first hole; Forming a second passage to fill the second through hole; and A second interconnect is formed on the top surface of the second path and on the top surface of the second insulating layer. Wherein, the size of the second hole is larger than the size of the first hole, and The first insulating layer and the second insulating layer form a stepped structure in the direction toward the semiconductor chip.

8. The method according to claim 7, wherein: The first and second paths are configured to have an upwardly increasing width.

9. The method of claim 7, wherein, The second passage has a vertically extending central axis, which is spaced apart from the vertically extending central axis of the first passage.

10. The method according to claim 7, wherein: The lower redistribution layer includes a lower redistribution external terminal electrically connected to the first path, and The first passage and the first insulating layer are formed to contact the top surface of the lower redistributed external terminal.

11. A semiconductor package, comprising: Lower redistribution layer; The lower semiconductor chip is located on the lower redistribution layer; A stack, which is located on the lower redistribution layer and laterally spaced from the lower semiconductor chip, wherein the lower semiconductor chip is surrounded by the stack in a plan view; An upper package is located on the lower semiconductor chip and the stack; as well as An upper redistribution layer is located on the lower semiconductor chip and the stack, and is electrically connected to the stack, wherein... The stack includes: A first insulating layer is located on the lower redistribution layer; A first pathway, which penetrates the first insulating layer; A first interconnect is located on the top surface of the first insulating layer and the top surface of the first passage; A second insulating layer is formed on the first insulating layer, and the first interconnect has a bottom surface that is coplanar with the bottom surface of the second insulating layer. A second path, penetrating the second insulating layer, and having a bottom surface contacting the top surface of the first interconnect for connection to the first path via the first interconnect, and the second path having a vertically extending central axis spaced apart from the vertically extending central axis of the first path; and A second interconnect is located on the top surface of the second insulating layer and the top surface of the second passage, and is connected to the second passage. The upper encapsulation component includes: The upper semiconductor chip is located on the upper redistribution layer, and The first insulating layer and the second insulating layer form a stepped structure in the direction toward the semiconductor chip.

12. The semiconductor package of claim 11, wherein, The first path and the second path have an upwardly increasing width.

13. The semiconductor package of claim 11, wherein, The stack also includes: A third insulating layer, which is on the top surface of the second insulating layer; and A third pathway, which penetrates the third insulating layer, and A second interconnect connects the second path to the third path.

14. The semiconductor package of claim 11, wherein, The upper redistribution layer is electrically connected to the lower redistribution layer through the stack, and The upper redistribution layer is electrically connected to the upper package via an upper ball disposed under the upper package.

15. The semiconductor package of claim 11, wherein, The first insulating layer and the second insulating layer comprise a photo-imageable dielectric material.

16. The semiconductor package of claim 11, wherein: The lower redistribution layer includes: Lower redistribution insulator; The lower redistribution external terminal is disposed on the lower redistribution insulator and electrically connected to the first passage; A lower redistribution pattern disposed within the lower redistribution insulator and electrically connected to the lower redistribution external terminals; and A lower redistribution connection terminal is disposed on the lower redistribution insulator and electrically connected to the lower redistribution pattern. The lower semiconductor chip is electrically connected to the lower redistribution connection terminal, and The first passage and the first insulating layer are configured to contact the top surface of the lower redistributed external terminal.

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