Low Latency Adaptive Timing

Abstract

A device for low-latency adaptive timing is provided, the device including: a first power supply rail for providing a first power; a second power supply rail for providing a second power; a third power supply rail for providing a third power; a voltage divider coupled to the first power supply rail, the second power supply rail, and the third power supply rail; a bias generator coupled to the voltage divider and the third power supply rail; an oscillator coupled to the bias generator and the first supply rail; and a clock distribution network for providing the output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail.

Description

[0001] Priority Claim

[0002] This application claims priority to U.S. Provisional Application Serial No. 62 / 562,335, entitled "Low Latency Analog Adaptive Timing," filed on September 22, 2017, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to power management in a processor system, and more particularly, to low latency adaptive timing. Background Art

[0004] A clock signal may be generated by a phase-locked loop (PLL). The clock signal may be distributed throughout the processor to facilitate the operation of the processor. For example, state elements (e.g., flip-flops, latches, etc.) located at different points within a processor die may operate synchronously by operating in accordance with the clock signal. When a large, sudden current demand occurs, the on-die voltage supply provided to the state elements may "droop" (e.g., for a few nanoseconds), while the PLL continues to generate the clock signal at a fixed frequency. Note that other voltage droop events may last even longer. To ensure that the processor operates during these droop events, a high voltage margin is provided to the state elements even during normal operation (e.g., when there is no voltage droop). That is, the processor is designed to operate at the highest specified frequency and simultaneously at the lowest potential voltage.

[0005] Since power has a quadratic dependence on voltage, a large amount of power may be wasted during normal operation to ensure functionality during infrequent voltage droops. Moreover, as processor speed and integration increase, the amount of power required may become a limiting factor. For example, the cost of designing and cooling a power-consuming processor may become impractical.

[0006] Existing analog PLLs implement adaptive frequency scaling (AFS) to compensate for power supply voltage droop and overshoot. One such AFS technique is described in U.S. Patent No. 6,922,111. The current analog implementation of the AFS technique directly modulates the VCO supply through resistive coupling of a digital power supply. The current analog implementation does not fully utilize all the benefits of the AFS technique at lower voltages and lower frequencies. Brief Description of the Drawings

[0007] Embodiments of the present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of the embodiments of the present disclosure, which, however, should not be taken to limit the present disclosure to the specific embodiments, but are for explanation and understanding only.

[0008] Figure 1The figure shows a simulated phase-locked loop (PLL) with adaptive frequency scaling (AFS) applied to a bias generator according to some embodiments of the present disclosure.

[0009] Figure 2 The figure shows a device according to some embodiments, showing a bias generator and showing the delay state of an oscillator, where the bias generator operates on the power supply provided by the AFS.

[0010] Figures 3A - 3B The figure shows plots respectively showing the improvement of timing margin using AFS for a bias generator according to some embodiments.

[0011] Figure 4 The figure shows a digital PLL (DPLL) with AFS applied to a digitally controlled oscillator (DCO) and / or a loop filter according to some embodiments of the present disclosure.

[0012] Figure 5 The figure shows an intelligent device or a computer system or a system-on-chip (SoC) having AFS for a bias generator and / or for a digital loop filter (DLF) and a DCO according to some embodiments of the present disclosure. Detailed Description

[0013] Relative to other techniques that trade off response time over a range of supported supply levels, the embodiments enable reducing adaptive frequency scaling (AFS) to a lower power distribution supply voltage with an almost instantaneous response time. Due to supply droops that cause the clock and data to slow down by different amounts, a significant amount of performance is put on hold. AFS (Adaptive Frequency System) addresses this problem by slowing down the PLL in response to any droop sensed on the noisy supply rail VccDist used by the clock distribution and the data path.

[0014] One AFS implementation in an analog PLL uses a potentiometer between the noisy power distribution supply VccDist and the regulated PLL supply VccPLL to inject some of the noise on VccDist onto the supply of the voltage-controlled oscillator (VCO) to affect the frequency change. This provides a very fast response time, but due to the headroom requirements of the VCO, the range of VccDist on which AFS can be employed is limited to a threshold voltage (e.g., approximately 0.85V).

[0015] Each embodiment has many technical effects. For example, the low-latency adaptive timing device of each embodiment applies AFS for clock data compensation to minimize the frequency guard band (or reduce the frequency guard band). A potentiometer (of the AFS) is used to sense the noise on VccDist and inject it onto the bias. The noise on the bias modulates the output frequency of the VCO clock (the output of the VCO). Thus, without using a traditional droop detector and associated circuitry, a lower-latency adaptive timing environment is obtained. From the various figures and embodiments, other technical effects will be apparent.

[0016] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail, so as not to obscure the embodiments of the present disclosure.

[0017] Note that in the corresponding figures of the embodiments, signals are represented by lines. Some lines may be thicker to indicate a greater number of component signal paths, and / or have arrows at one or more ends to indicate the primary information flow direction. Such indications are not intended to be restrictive. Instead, the lines may be used in conjunction with one or more exemplary embodiments to facilitate a more ready understanding of the circuit or logic unit. As dictated by design requirements or preferences, any represented signal may actually include one or more signals that may travel in either direction and may be implemented using any suitable type of signal scheme.

[0018] Throughout the specification and in the claims, the term "connected" means a direct connection between the connected objects, such as an electrical, mechanical, or magnetic connection, without any intermediate device.

[0019] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the connected objects or an indirect connection through one or more passive or active intermediate devices.

[0020] The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide the desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a / an" and "the" include plural references. The meaning of "in" includes "in" and "on".

[0021] The term "scaling" generally refers to the conversion of a design (schematic and layout) from one process technology to another, and is subsequently reduced in the layout area. The term "scaling" generally also refers to the reduction of layout and device dimensions within the same technology node. The term "scaling" can also refer to the adjustment of a signal frequency relative to another parameter (e.g., power supply level) (e.g., deceleration or acceleration - i.e., reduction or magnification, respectively). The terms "substantially", "close", "approximate", "near", and "about" generally refer to within + / - 10% of the target value.

[0022] Unless otherwise specified, the use of ordinal terms such as "first", "second", and "third" to describe common objects only indicates that different instances of the same object are being referred to, and is not intended to imply that the objects so described must be in a given order in terms of ranking or in any other way, whether in time or in space.

[0023] For the purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0024] In the specification and claims, if terms such as "left", "right", "front", "rear", "top", "bottom", "upper", "lower", etc. appear, they are for descriptive purposes and not necessarily for describing a permanent relative position.

[0025] For the purposes of the embodiments, the transistors in the various circuits and logic blocks described herein are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include a drain, a source, a gate, and a body terminal. Transistors and / or MOS transistor derivatives also include triple-gate transistors and fin field-effect transistors, gate-all-around cylindrical transistors, tunneling FETs (TFETs), square wire or rectangular strip transistors, ferroelectric FETs (FeFETs), or other devices that implement transistor functionality, such as carbon nanotubes or spintronic devices. The source and drain terminals of a MOSFET are symmetric, i.e., they are the same terminals and are used interchangeably herein. On the other hand, a TFET device has asymmetric source and drain terminals. Those skilled in the art will appreciate that other transistors (e.g., bipolar junction transistors - (BJT PNP / NPN), BiCMOS, CMOS, etc.) can be used without departing from the scope of the present disclosure.

[0026] It is noted that those elements in the drawings that have the same reference numerals (or names) as elements in any other drawing can operate or function in any manner similar to the manner described, but are not limited thereto.

[0027] Figure 1 The figure shows an apparatus 100 according to some embodiments of the present disclosure. The apparatus 100 includes an analog PLL having an AFS applied to a bias generator. The analog PLL includes a phase frequency detector (PFD) 101, a charge pump (CO) 102, a low-pass filter (LPF) including a capacitor C 1 The output VCOClk of the VCO 105 is divided by a divider 106 at a certain ratio, and that divided output FbClk (feedback clock) is received by a phase detector that compares the phase and frequency of the feedback clock with the phase and frequency of a reference clock RefClk. Accordingly, the PFD 101 generates up / down signals for the CP 102. The output v1 of the CP 102 is filtered using the capacitor C1 and provided as an input to the N bias generator 103. The N bias generator 103 generates Nbias (N bias) to bias another bias generator called the P bias generator (Pbias Gen.) 104. The N bias generator 103 also generates a version of v1 called Vctrl. The Nbias is used by the P bias generator 104 which uses the Nbias to generate Pbias (P bias). The Pbias is provided to the VCO 105 to control the oscillation frequency of the VCO 105 according to the output of the PFD 101. The Pbias is the same as Vctrl (control voltage), and the Pbias is also used to adjust the frequency of the VCOClk.

[0028] In some embodiments, the apparatus 100 includes a voltage generator 111 (e.g., a DC-DC converter, a low-dropout (LDO) regulator, etc.) that uses an input power supply (input supply) to provide a power supply VccPLL for the analog PLL. In some embodiments, the AFS 112 includes a voltage divider having programmable and / or fixed resistors Rl, R2, and R3 as shown. The outputs of the AFS are VccAFS and VccDist. The percentage of the noise amount from VccDist added to VccAFS depends on the ratio of the resistors Rl, R2, and R3 of the voltage divider of the AFS.

[0029] In some embodiments, the apparatus 100 includes a clock distribution (Clk Distr.) 107 network (e.g., flip-flops and buffers / inverters) that receives the output VCOClk or a buffered version thereof and drives the buffered version to other locations on the chip. In some embodiments, power from a power generator or source (e.g., a DC-DC converter, an LDO converter 111) is supplied to VccPLL to power the P bias generator 104 and the VCO 105, while the N bias generator 103 is powered by VccAFS, and the clock distribution (Clk Distr) 107 network is powered by VccDist. In this example, the data path including flip-flop 108, combinational logic (CL) 109, and flip-flop 110 is also powered by VccDist. The input data din and the provided output data dout are sampled using the clock from the clock distribution 107.

[0030] In some embodiments, supply noise is injected into the supply of Nbias (using a potentiometer such as AFS112 between VccPLL and VccDist) rather than onto the VCO. In some embodiments, modulation of Nbias directly affects the frequency of the VCO. Since the N bias generator 103 consumes far less current than the VCO, it has less stringent headroom requirements and can support AFS down to lower voltages (e.g., less than 0.85V). In the embodiments herein, a droop detector that may add latency (e.g., approximately 200 - 500 picoseconds) is not used, thus providing an almost instantaneous response to supply noise.

[0031] In some embodiments, AFS112 helps maintain or increase the timing margin in the path by slowing down the clock in response to a voltage droop in the power distribution / data path supply (VccDist). For example, analyzing the total margin in the timing path for different VccDist levels provides an indication of the lowest VccDist level at which AFS can be used. In some embodiments, both the N bias generator and the P bias generator blocks / circuits are powered by VccAFS, while the VCO is powered by VccPLL.

[0032] Here, according to some embodiments, AFS 112 is used for clock data compensation to minimize (or reduce) the frequency guard band. A potentiometer (of the AFS) is used to sense the noise on VccDist and inject it onto Nbias. The noise on Nbias modulates the output frequency of the VCO clock (the output of the VCO). In some embodiments, VCO 105 is an inductor-capacitor (LC) oscillator (LCO). In the LCO, the frequency of VCOClk is adjusted by a reference voltage and / or by switching in a variable number of smaller capacitors using a coarse and / or fine code. These coarse and / or fine codes can be generated by converting Pbias (or Vctrl) into a digital code (e.g., a coarse and / or fine code) for a varactor of the LCO.

[0033] Figure 2 The figure shows a device 200 according to some embodiments, showing the delay stages of the bias generators (104 and 105) and the VCO 105, where the bias generators 103 and 104 operate on the power supply provided by AFS 112. In the example, both the N-bias generator 103 and the P-bias generator 104 are powered by VccAFS, while the VCO 105 (one delay unit is shown here) is powered by VccPLL.

[0034] The N-bias generator 103 includes an amplifier 103a, a p-type device MP1, and n-type devices MN1 and MN2 coupled together as shown. The input V1 is received by the amplifier 103a, which adjusts the current strength of the transistor MN2 such that the input Vctrl and V1 are substantially equal. The transistor MN1 is powered by VccAFS. The transistor MP1 is diode-connected and provides Vctrl. In some embodiments, the entire circuit and devices of the N-bias generator 103 are powered by VccAFS. In some embodiments, the amplifier 103a is powered by VccPLL while the other devices are powered by VccAFS. The N-bias generator 103 provides one or two outputs - Vctrl and Nbias. Nbias is used to bias the n-type devices of the subsequent circuit.

[0035] The P-bias generator 104 includes a p-type transistor MP2 and n-type transistors MN3 and MN4 coupled together as shown. The circuit architecture of the P-bias generator 104 is similar to that of the Nbias 103 minus the amplifier 103a and the associated circuit. The transistor MN4 is biased by Nbias, the transistor MN3 is biased by VccAFS, and the transistor MP2 is diode-connected and powered by VccAFS.

[0036] Here, a delay stage is illustrated for the VCO 105. Those skilled in the art will appreciate that multiple delay stages coupled together in a ring form are used to form an oscillator. The delay stage includes p-type transistors MP3, MP4, MP5, and MP6 and n-type devices MN5, MN5b, and MN6 coupled together as shown. The output of the delay stage is the differential outputs Out and Outb. The transistor MN6 is biased by Nbias, and Vctrl or Pbias is used to bias the transistors MP4 and MP5. Each delay stage receives the outputs (e.g., differential outputs) from its adjacent delay stage as inputs In and Inb.

[0037] In embodiments, the delay stages of the VCO 105 are powered by VccPLL. In some embodiments, the N bias generator 103 is powered by VccAFS, and the P bias generator 104 is powered by VccPLL. In some embodiments, the P bias generator 104 is powered by VccAFS, and the N bias generator 103 is powered by VccPLL. In some embodiments, the amplifier 103a of the N bias generator 103 circuit is powered by VccPLL.

[0038] Figures 3A - 3B Plots 300 and 320 are illustrated showing timing margin improvement using AFS for bias generators according to some embodiments. The results in the plots compare the timing margin in a given path between the AFS scheme on the VCO and the AFS scheme on the N bias generator at the strongest AFS setting (e.g., the setting that injects the most noise). The results indicate that injecting noise into the supply of the VCO may not be used when below 0.85V as the margin gradually approaches 0ps, while the proposed scheme of the embodiments (e.g., at the strongest AFS setting) can be used all the way down to 0.8V or lower with sufficient timing margin. This enables the proposed scheme of the embodiments to also be used at much lower voltages.

[0039] Figure 4 An apparatus 400 is illustrated according to some embodiments of the present disclosure, the apparatus 400 including a digital PLL with AFS applied to a DCO 405 (digitally controlled oscillator) and / or a loop filter. A digital PLL as opposed to an analog PLL mainly uses digital circuits and signals to control clock frequency generation and retention.

[0040] Here, the term "analog signal" is any continuous signal for which the time-varying characteristic (variable) of the signal is a representation of some other time-varying quantity, i.e., similar to another time-varying signal. Here, the term "digital signal" is a physical signal representing a series of discrete values (quantized discrete-time signal) that represents, for example, any bit stream or a digitized (sampled and analog-to-digital converted) analog signal.

[0041] In some embodiments, the digital PLL of apparatus 400 includes a time-to-digital converter (TDC) 401, a digital loop filter (DLF) 403, a digitally controlled oscillator (DCO) 405, and other circuits similar to those described. The TDC 401 receives RefClk and FbClk and provides a digital stream as an output TDCOut that represents the phase difference between RefClk and FbClk in digital form. The TDC may include a delay line having a plurality of delay stages (e.g., buffers or inverters), and the output of each delay stage (and the input of the first delay stage) is sampled by a flip-flop that uses the reference clock as a sampling clock. The input to the first delay stage in the delay line is FbClk. Thus, FbClk is regularly sampled by RefClk. The outputs of the flip-flops are then combined to provide the digital stream TDCOut. TDCOut is then received by the DLF 403, which filters out any noise in TDCOut using a filtering equation. The filter may be implemented using any suitable digital filter, such as a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter. A controller (not shown as a separate circuit but integrated in the DLF 403) generates a coarse code and a fine code, which are control codes for significantly or slightly changing the frequency of the VCOClk from the DCO 405. Figure 1

[0042] The DCO 405 may be any suitable digital oscillator, such as a delay line having adjustable loading (e.g., capacitive loading) at the output of each delay stage. These adjustable loadings may be controlled by the coarse and / or fine codes (e.g., added to or subtracted from the loading). In some embodiments, the DCO 405 is an inductor-capacitor (LC) oscillator (LCO). In an LCO, the frequency of the VCOClk is adjusted by switching among a variable number of smaller capacitors using the coarse and / or fine codes.

[0043] In some embodiments, the TDC 401 is powered by VccPLL (just as Figure 1 ​The PFD 101 of the analog PLL is powered by VccPLL (the same applies to others). In some embodiments, the clock distribution is powered by VccDist. In some embodiments, the DFL 403 and DCO 405 are powered by VccAFS. Thus, the coarse code and the fine code (digital signals) are adjusted according to the noise injected onto VccAFS. This noise then adjusts the frequency of the DCO in a manner with a low latency effect. In some embodiments, the noise on the DCO405 modulates the frequency. In some embodiments, using VccAFS to supply the DLF 403 and DCO 405 removes the need for a level shifter. The level shifter causes latency loss, and this loss is removed here. In various embodiments, the AFS112 (e.g., a voltage divider) senses the noise on VccDist and injects the sensed noise onto the DLF 403 via VccAFS. Subsequently, the sensed noise is converted into coarse and / or fine codes, which are the outputs of the DLF 403. Thus, the frequency of the VCOClk is modulated by the sensed noise.

[0044] Figure 5 FIG. shows an intelligent device or a computer system or an SoC (System on Chip) 1600 having means for low-latency adaptive timing according to an embodiment of the present disclosure. The means for low-latency adaptive timing may include Figure 1 an architecture for analog PLL-derived timing or Figure 4 an architecture for digital PLL-derived timing. As described with reference to various embodiments, by providing a filtered supply to each component of the PLL, the droop detector circuit is removed, allowing for a quick response to any droop in the input supply.

[0045] Figure 5 FIG. shows a block diagram of an embodiment of a mobile device in which a planar interface connector can be used. In some embodiments, the computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or a smart phone, a wireless-enabled e-reader, or other wireless mobile devices. It will be understood that certain components are shown schematically and not all components of such devices are shown in the computing device 1600.

[0046] In some embodiments, the computing device 1600 includes a first processor 1610 having means for low-latency adaptive timing according to some of the embodiments discussed. According to some embodiments, other blocks of the computing device 1600 may also include means for low-latency adaptive timing. Various embodiments of the present disclosure may also include a network interface (such as a wireless interface) within 1670, such that the system embodiments can be incorporated into a wireless device (e.g., a cellular phone or a personal digital assistant).

[0047] In some embodiments, processor 1610 (and / or processor 1690) may include one or more physical devices, such as a microprocessor, an application processor, a microcontroller, a programmable logic device, or other processing devices. Processing operations performed by processor 1610 include the execution of an operating platform or operating system on which application and / or device functions are executed. Processing operations include operations related to I / O (input / output) with a human user and / or with other devices, operations related to power management, and / or operations related to connecting the computing device 1600 to another device. Processing operations may also include operations related to audio I / O and / or display I / O.

[0048] In some embodiments, computing device 1600 includes an audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. Audio functionality may include speaker and / or headphone output and microphone input. Devices for such functionality may be integrated into computing device 1600 or connected to computing device 1600. In one embodiment, a user interacts with computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0049] In some embodiments, computing device 1600 includes a display subsystem 1630. Display subsystem 1630 represents hardware (e.g., a display device) and software (e.g., drivers) components that provide a visual and / or tactile display for a user to interact with computing device 1600. Display subsystem 1630 includes a display interface 1632, which includes a particular screen or hardware device for providing a display to the user. In one embodiment, display interface 1632 includes logic separate from processor 1610 for performing at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touchpad) device that provides both output and input to the user.

[0050] In some embodiments, computing device 1600 includes an I / O controller 1640. The I / O controller 1640 represents the hardware devices and software components related to interaction with the user. The I / O controller 1640 is operable to manage the hardware that is part of the audio subsystem 1620 and / or the display subsystem 1630. Additionally, the I / O controller 1640 illustrates connection points for additional devices that are connected to the computing device 1600 through which the user can interact with the system. For example, devices that can be attached to the computing device 1600 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices for use with a particular application (such as, a card reader or other device).

[0051] As mentioned above, the I / O controller 1640 can interact with the audio subsystem 1620 and / or the display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands to one or more applications or functions of the computing device 1600. Additionally, audio output can be provided as an alternative or addition to the display output. In another example, if the display subsystem 1630 includes a touch screen, the display device also acts as an input device that can be at least partially managed by the I / O controller 1640. There may also be additional buttons or switches on the computing device 1600 to provide I / O functions managed by the I / O controller 1640.

[0052] In some embodiments, the I / O controller 1640 manages devices such as an accelerometer, a camera, a light sensor or other environmental sensors, or other hardware that may be included in the computing device 1600. The input can be part of a direct user interaction and also provide environmental input to the system to affect its operation (such as, filtering noise, adjusting the display for brightness detection, applying the flash or other features of the camera).

[0053] In some embodiments, the computing device 1600 includes a power management 1650 that manages battery power usage, battery charging, and features related to power saving operations. The memory subsystem 1660 includes memory devices for storing information in the computing device 1600. The memory can include non-volatile (the state does not change if power to the memory device is interrupted) and / or volatile (the state is indeterminate if power to the memory device is interrupted) memory devices. The memory subsystem 1660 can store application data, user data, music, photos, documents or other data, and system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0054] The components of the embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing computer-executable instructions (e.g., instructions for implementing any other process discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memories (PCMs), or other types of machine-readable media suitable for storing electronic instructions or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS), which may be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem or a network connection) in the form of a data signal.

[0055] In some embodiments, computing device 1600 includes connectivity device 1670. Connectivity device 1670 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) for enabling computing device 1600 to communicate with external devices. Computing device 1600 may be a separate device such as other computing devices, wireless access points, or base stations, as well as peripheral devices such as head-mounted devices, printers, or other devices.

[0056] Connectivity device 1670 may include a variety of different types of connectivity devices. For the sake of overview, computing device 1600 is illustrated as having cellular connectivity device 1672 and wireless connectivity device 1674. Cellular connectivity device 1672 generally refers to cellular network connectivity devices provided by wireless carriers, such as via GSM (Global System for Mobile Communications) or its variants or derivatives, CDMA (Code Division Multiple Access) or its variants or derivatives, TDM (Time Division Multiplexing) or its variants or derivatives, or other cellular service standards. Wireless connectivity device (or wireless interface) 1674 refers to wireless connectivity devices that are not cellular and may include personal area networks (such as Bluetooth, near field, etc.), local area networks (such as Wi-Fi), and / or wide area networks (such as WiMax) or other wireless communications.

[0057] In some embodiments, computing device 1600 includes a peripheral connection 1680. The peripheral connection 1680 includes hardware interfaces and connectors for making peripheral connections, as well as software components (e.g., drivers, protocol stacks). It will be understood that the computing device 1600 can be either a peripheral device connected to other computing devices ("to" 1682), or can have peripheral devices connected to the computing device 1600 ("from" 1684). The computing device 1600 typically has a purpose of connecting to other computing devices for purposes such as managing (e.g., downloading and / or uploading, changing, synchronizing) content on the computing device 1600. Additionally, a docking connector can allow the computing device 1600 to connect to certain peripheral devices that allow the computing device 1600 to control, for example, content output to an audiovisual or other system.

[0058] In addition to dedicated docking connectors or other dedicated connection hardware, the computing device 1600 can also establish the peripheral connection 1680 via common or standards-based connectors. Common types can include Universal Serial Bus (USB) connectors (which can include any one of several different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High-Definition Multimedia Interface (HDMI), FireWire, or other types.

[0059] References in the specification to "an embodiment", "one embodiment", "some embodiments", or "other embodiments", etc., mean that the particular features, structures, or characteristics described in connection with these embodiments are included in at least some embodiments, but not necessarily in all embodiments. Various occurrences of "an embodiment", "one embodiment", or "some embodiments" do not necessarily refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may", "can", or "could" be included, that particular component, feature, structure, or characteristic is not necessarily included. If the specification or claims refer to "a" element, it does not mean there is only one of that element. If the specification or claims refer to "additional" elements, it does not exclude the presence of more than one of the additional elements.

[0060] Furthermore, specific features, structures, functions, or characteristics can be combined in one or more embodiments in any suitable manner. For example, the first embodiment can be combined with the second embodiment as long as the specific features, structures, functions, or characteristics associated with the first and second embodiments are not mutually exclusive.

[0061] Although the present disclosure has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. Embodiments of the present disclosure are intended to embrace all such alternatives, modifications, and variations that fall within the broad scope of the appended claims.

[0062] In addition, for simplicity of illustration and discussion, and so as not to obscure the present disclosure, power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented figures. Further, to avoid obscuring the present disclosure and also in view of the fact that details regarding the implementation of such block diagrams largely depend on the platform on which the present disclosure is to be implemented, the arrangement may be shown in block diagram form (i.e., such details should be entirely within the purview of those of ordinary skill in the art). In cases where specific details (e.g., circuits) are set forth to describe example embodiments of the present disclosure, it should be apparent to those of ordinary skill in the art that the present disclosure may be practiced without these specific details or with variations of these specific details. The description is, therefore, to be regarded as illustrative rather than restrictive.

[0063] The following examples relate to further embodiments. Details in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0064] Example 1. An apparatus includes: a first power supply rail for providing a first power; a second power supply rail for providing a second power; a third power supply rail for providing a third power; a voltage divider coupled to the first power supply rail, the second power supply rail, and the third power supply rail; a bias generator coupled to the voltage divider and the third power supply rail; an oscillator coupled to the bias generator and the first supply rail; and a clock distribution network for providing the output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail.

[0065] Example 2. The apparatus of Example 1, wherein the bias generator includes an amplifier coupled to the second power supply rail.

[0066] Example 3. The apparatus of Example 1, including a voltage regulator coupled to the first power supply rail, wherein the voltage regulator is for providing the first power to the first power supply rail.

[0067] Example 4. The apparatus of Example 3, wherein the voltage regulator includes a low dropout circuit.

[0068] Example 5. The apparatus of Example 1, wherein the oscillator is a voltage controlled oscillator.

[0069] Example 6. The apparatus as described in Example 1 includes a phase frequency detector coupled to a first power supply rail, wherein the phase frequency detector is configured to receive a reference clock and a feedback clock as inputs and to generate one or more outputs indicative of a phase difference between the reference clock and the feedback clock.

[0070] Example 7. The apparatus as described in Example 6 includes a frequency divider coupled to an oscillator and a phase frequency detector, wherein the frequency divider is configured to divide the output of the oscillator and provide a feedback clock, and wherein the frequency divider is coupled via the first power supply rail.

[0071] Example 8. The apparatus as described in Example 1, wherein the voltage divider includes one or more programmable resistive devices.

[0072] Example 9. The apparatus as described in Example 8, wherein the voltage divider is configured to sense noise on a second power supply rail and to inject the sensed noise onto a bias generator such that the output of the bias generator adjusts the frequency of the oscillator based on the injected sensed noise.

[0073] Example 10. An apparatus includes: a first power supply rail for providing a first power; a second power supply rail for providing a second power; a third power supply rail for providing a third power; a voltage divider coupled to the first power supply rail, the second power supply rail, and the third power supply rail; a digital loop filter coupled to the voltage divider and the third power supply rail; an oscillator coupled to the digital loop filter and the third power supply rail; a clock distribution network for providing the output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail; and a time-to-digital converter (TDC) coupled to the digital loop filter, wherein the TDC is coupled to the first power supply rail.

[0074] Example 11. The apparatus as described in Example 10 includes a voltage regulator coupled to the first power supply rail, wherein the voltage regulator is configured to provide the first power to the first power supply rail.

[0075] Example 12. The apparatus as described in Example 11, wherein the voltage regulator includes a low dropout circuit.

[0076] Example 13. The apparatus as described in Example 10, wherein the oscillator includes a numerically controlled oscillator.

[0077] Example 14. The apparatus as described in Example 10, wherein the oscillator includes an LC oscillator.

[0078] Example 15. A system includes: a memory; a processor coupled to the memory, the processor including: a first power supply rail for providing a first power; a second power supply rail for providing a second power; a third power supply rail for providing a third power; a voltage divider coupled to the first power supply rail, the second power supply rail, and the third power supply rail; a bias generator coupled to the voltage divider and the third power supply rail; an oscillator coupled to the bias generator and the first supply rail; and a clock distribution network for providing the output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail; and a wireless interface for allowing the processor to communicate with another device.

[0079] Example 16. The system of Example 15, wherein the voltage divider includes one or more programmable resistive devices.

[0080] Example 17. The system of Example 15, wherein the voltage divider is configured to sense noise on the second power supply rail and to inject the sensed noise onto the bias generator such that the output of the bias generator modulates the frequency of the oscillator based on the injected sensed noise.

[0081] Example 18. A system includes: a memory; a processor coupled to the memory, the processor including: a first power supply rail for providing a first power; a second power supply rail for providing a second power; a third power supply rail for providing a third power; a voltage divider coupled to the first power supply rail, the second power supply rail, and the third power supply rail; a digital loop filter coupled to the voltage divider and the third power supply rail; an oscillator coupled to the digital loop filter and the third power supply rail; a clock distribution network for providing the output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail; and a time-to-digital converter (TDC) coupled to the digital loop filter, wherein the TDC is coupled to the first power supply rail; and a wireless interface for allowing the processor to communicate with another device.

[0082] The system of Example 18 includes a voltage regulator coupled to the first power supply rail, wherein the voltage regulator is configured to provide the first power to the first power supply rail.

[0083] The system of Example 18, wherein the oscillator includes one of the following: a numerically controlled oscillator; or an LC oscillator.

[0084] A summary is provided that will allow the reader to understand the nature and gist of the technical disclosure. It should be understood that the summary will not be used to limit the scope or meaning of the claims. The appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. An apparatus with low-latency adaptive timing, the apparatus comprising: A first power supply rail for providing a first power; A second power supply rail for providing a second power; A third power supply rail for providing a third power; A voltage divider coupled to the first power supply rail, the second power supply rail, and the third power supply rail; A bias generator coupled to the voltage divider and the third power supply rail; An oscillator coupled to the bias generator and the first supply rail; and A clock distribution network for providing the output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail.

2. The apparatus according to claim 1, wherein the bias generator includes an amplifier coupled to the first power supply rail.

3. The apparatus according to claim 1, comprising a voltage regulator coupled to the first power supply rail, wherein the voltage regulator is for providing the first power to the first power supply rail.

4. The apparatus according to claim 3, wherein the voltage regulator includes a low dropout circuit.

5. The apparatus according to claim 1, wherein the oscillator is a voltage controlled oscillator.

6. The apparatus according to claim 1, wherein the oscillator includes an LC oscillator.

7. The apparatus according to claim 1, comprising a phase frequency detector coupled to the first power supply rail, wherein the phase frequency detector is for receiving a reference clock and a feedback clock as inputs and for generating one or more outputs indicative of a phase difference between the reference clock and the feedback clock.

8. The apparatus according to claim 7, comprising a frequency divider coupled to the oscillator and the phase frequency detector, wherein the frequency divider is for dividing the output of the oscillator and providing the feedback clock, and wherein the frequency divider is coupled through the first power supply rail.

9. The apparatus according to claim 1, wherein the voltage divider includes one or more programmable resistive devices.

10. The apparatus according to claim 1, wherein the voltage divider is for sensing noise on the second power supply rail and for injecting the sensed noise onto the bias generator such that the output of the bias generator modulates the frequency of the oscillator according to the injected sensed noise.

11. An apparatus with low-latency adaptive timing, the apparatus comprising: A first power supply rail for providing a first power; A second power supply rail for providing a second power; A third power supply rail for providing a third power; A voltage divider coupled to the first power supply rail, the second power supply rail, and the third power supply rail; A digital loop filter coupled to the voltage divider and the third power supply rail; An oscillator coupled to the digital loop filter and the third power supply rail; A clock distribution network for providing the output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail; and A time-to-digital converter (TDC), coupled to the digital loop filter, wherein the TDC is coupled to the first power supply rail.

12. The apparatus according to claim 11, comprising a voltage regulator coupled to the first power supply rail, wherein, the voltage regulator is configured to supply the first power to the first power supply rail.

13. The apparatus according to claim 12, wherein, the voltage regulator includes a low-dropout circuit.

14. The apparatus according to claim 11, wherein, the oscillator includes a numerically controlled oscillator.

15. The apparatus according to claim 11, wherein, the voltage divider is configured to sense noise on the second power supply rail and to inject the sensed noise onto the digital loop filter or the oscillator such that the frequency of the oscillator is modulated by the sensed noise.

16. An electronic system, comprising: a memory; a processor, coupled to the memory, the processor including: a first power supply rail for supplying a first power; a second power supply rail for supplying a second power; a third power supply rail for supplying a third power; a voltage divider, coupled to the first power supply rail, the second power supply rail, and the third power supply rail; a bias generator, coupled to the voltage divider and the third power supply rail; an oscillator, coupled to the bias generator and the first supply rail; and a clock distribution network for providing the output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail; and a wireless interface for allowing the processor to communicate with another device.

17. The system according to claim 16, wherein, the voltage divider includes one or more programmable resistive devices.

18. The system according to claim 16, wherein, the voltage divider is configured to sense noise on the second power supply rail and to inject the sensed noise onto the bias generator such that the output of the bias generator modulates the frequency of the oscillator according to the injected sensed noise.

19. The system according to claim 16, wherein, the oscillator includes one of the following: a voltage-controlled oscillator; or an LC oscillator.

20. An electronic system, comprising: a memory; a processor, coupled to the memory, the processor including: a first power supply rail for supplying a first power; a second power supply rail for supplying a second power; a third power supply rail for supplying a third power; a voltage divider, coupled to the first power supply rail, the second power supply rail, and the third power supply rail; a digital loop filter, coupled to the voltage divider and the third power supply rail; an oscillator, coupled to the digital loop filter and the third power supply rail; a clock distribution network for providing the output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail; and a time-to-digital converter (TDC), coupled to the digital loop filter, wherein the TDC is coupled to the first power supply rail; and A wireless interface for allowing the processor to communicate with another device.

21. The system according to claim 20, comprising a voltage regulator coupled to the first power supply rail, wherein, the voltage regulator is configured to supply the first power to the first power supply rail.

22. The system according to claim 20, wherein, the voltage divider is configured to sense noise on the second power supply rail and to inject the sensed noise onto the digital loop filter or the oscillator such that the frequency of the oscillator is modulated by the sensed noise.

23. A method for low-latency adaptive timing, the method comprising: supplying a first power on a first power supply rail; supplying a second power to a second power supply rail; supplying a third power to a third power supply rail; coupling a voltage divider to the first power supply rail, the second power supply rail, and the third power supply rail; coupling a bias generator to the voltage divider and the third power supply rail; coupling an oscillator to the bias generator and the first power supply rail; and providing an output of the oscillator to one or more logics via a clock distribution network; and coupling the clock distribution network to the second power supply rail.

24. The method according to claim 23, wherein: the bias generator includes an amplifier coupled to the first power supply rail; the oscillator is a voltage-controlled oscillator; or the oscillator includes an LC oscillator.

25. The method according to any one of claims 23 to 24, comprising: sensing noise on the second power supply rail; and injecting the sensed noise onto the bias generator such that the output of the bias generator modulates the frequency of the oscillator according to the injected sensed noise.

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