A groove protection ring structure and its forming method

Abstract

A trench protection ring structure and a forming method thereof, the forming method comprising: providing a substrate, the substrate having a plurality of chip regions, and setting a protection ring region between adjacent chip regions; forming a trench in the protection ring region, forming a word line structure in the trench, and the upper surface of the word line structure is not higher than the upper surface of the substrate; stacking a plurality of metal interconnection layers on the substrate, setting an intermetallic dielectric layer between adjacent metal interconnection layers, forming a plurality of first connectors in the intermetallic dielectric layer to connect adjacent metal interconnection layers, setting an interlayer dielectric layer between the bottom metal interconnection layer and the substrate, setting a plurality of second connectors in the interlayer dielectric layer, and at least one of the plurality of second connectors connects the bottom metal interconnection layer to the word line structure, thereby forming a trench protection ring structure. The trench protection ring structure formed by the method of the present invention can reduce the leakage path of the word line channel and can prevent the floating node potential from floating.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory manufacturing process, and in particular to a memory component device structure and process. Background Art

[0002] The main chip protection ring is an important protective barrier for wafer packaging and dicing. The chip protection ring can prevent damage to the wafer caused by external moisture and stress to achieve good product reliability. The traditional protection ring is formed by a simple silicon substrate and a metal interconnect layer and channel thereon, similar to a "wall" structure. However, the chip protection ring of the existing technology has problems such as electrical leakage path and node potential floating, and a better solution is needed. Summary of the invention

[0003] The present invention provides a trench protection ring structure and a forming method thereof, which can reduce the electrical leakage of the protection ring structure and also prevent the potential floating of the node.

[0004] The present invention provides a method for forming a trench protection ring structure, comprising: providing a substrate, the substrate having a plurality of chip regions, and setting a protection ring region between adjacent chip regions. Forming a trench in the protection ring region, forming a word line structure in the trench, and the upper surface of the word line structure is not higher than the upper surface of the substrate. Stacking a plurality of metal interconnection layers on the substrate, setting an intermetallic dielectric layer between adjacent metal interconnection layers, forming a first connector in the intermetallic dielectric layer to connect adjacent metal interconnection layers, setting an interlayer dielectric layer between the bottom metal interconnection layer and the substrate, and setting a second connector in the interlayer dielectric layer to connect the bottom metal interconnection layer with the word line structure, thereby forming a trench protection ring structure.

[0005] In some embodiments of the present invention, the potential of the word line structure in the trench in the guard ring region is grounded.

[0006] In some embodiments of the present invention, the trench protection ring structure includes a plurality of trenches and a plurality of word line structures, the number of the trenches is the same as the number of the word line structures, and the number of the word lines and the number of the trenches is 2 or a multiple of 2.

[0007] In some embodiments of the present invention, the bottommost metal interconnect layer is connected to at least one of the plurality of word line structures via a second connection member.

[0008] In some embodiments of the present invention, while various components in the trench protection ring structure are formed in the protection ring area, corresponding identical or similar components are also formed in the chip area, and the components include trenches, word line structures, interlayer dielectric layers, second connectors, metal interconnect layers, intermetallic dielectric layers, and first connectors.

[0009] In some embodiments of the present invention, the metal interconnect layer, the first connector, the second connector, and the word line structure in the guard ring region are not connected to corresponding identical or similar components in the chip region.

[0010] The present invention also provides a groove protection ring structure, comprising: a substrate, a groove, a word line structure, a plurality of metal interconnection layers, an intermetallic dielectric layer and an interlayer dielectric layer. The substrate has a plurality of chip regions and a protection ring region between adjacent chip regions. The groove is located in the protection ring region. The word line structure is located in the groove. A plurality of metal interconnection layers are located on the substrate and are arranged in a stacked manner. The intermetallic dielectric layer is located between adjacent metal interconnection layers, wherein the intermetallic dielectric layer has a first connector, and the first connector connects the upper and lower adjacent metal interconnection layers. The interlayer dielectric layer is located between the bottom metal interconnection layer and the substrate, wherein the interlayer dielectric layer has a second connector, and the second connector connects the bottom metal interconnection layer and the word line structure.

[0011] In some embodiments of the present invention, the potential of the word line structure in the trench in the guard ring region is grounded.

[0012] In some embodiments of the present invention, the trench protection ring structure includes a plurality of trenches and a plurality of word line structures. The number of the trenches is the same as the number of the word line structures. The number of the word lines and the number of the trenches is 2 or a multiple of 2.

[0013] In some embodiments of the present invention, the bottommost metal interconnect layer is connected to at least one of the plurality of word line structures via a second connection member.

[0014] In some embodiments of the present invention, the chip area includes components that are the same as or similar to those in the trench protection ring area, including trenches, word line structures, interlayer dielectric layers, second connectors, metal interconnect layers, intermetallic dielectric layers, and first connectors.

[0015] In some embodiments of the present invention, the metal interconnect layer, the first connector, the second connector, and the word line structure in the guard ring region are not connected to corresponding identical or similar components in the chip region.

[0016] The beneficial effect of the present invention is that by arranging two word line structures in the substrate within the protection ring area, the word line structure potential is grounded to reduce the electrical leakage path of the protection ring structure. At the same time, at least one of the multiple word line structures is connected to the metal interconnection layer through a connector to avoid node potential floating. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic cross-sectional view of a substrate including a groove protection ring structure of the prior art;

[0018] Figure 2It is a schematic cross-sectional view of a substrate including a groove protection ring structure of the present invention.

[0019] Figure 3 Schematic top view of the substrate of the present invention. DETAILED DESCRIPTION

[0020] The following is an explanation of the implementation methods of the "groove protection ring structure" and the "method for forming a groove protection ring structure" disclosed in the present invention through specific examples. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. The following implementation methods will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention.

[0021] See also Figure 1 and Figure 2 as well as Figure 3 . Figure 1 is a schematic cross-sectional view of a substrate including a groove protection ring structure of the prior art; Figure 2 is a schematic cross-sectional view of a substrate including a groove protection ring structure of the present invention; Figure 3 is a schematic top view of a substrate of the present invention. The present invention provides a method for forming a trench protection ring structure: first, a substrate W is provided, and the substrate W has a plurality of chip regions C. For example, referring to Figure 2 as well as Figure 3 ,like Figure 2 The schematic cross-sectional view of the substrate including the trench protection ring structure shown in FIG. is a cross-sectional view of the boundary portion of a chip region C. In this portion, a protection ring region P is provided. Figure 3As shown, each chip region C has a protection ring region P at its periphery. In other words, a protection ring region P is provided between adjacent chip regions. The substrate of this part is a silicon substrate, and semiconductor materials such as gallium nitride, silicon carbide, and silicon germanium can also be used. Ion implantation is performed on the substrate to dope group III element ions (such as boron ions) to form a P-type well region or dope group V element ions (such as arsenic ions) to form an N-type well region; group V element ions (such as arsenic ions) are doped in the P-type well region to form an N+ region or group III element ions (such as boron ions) are doped in the N-type well region to form a P+ region. Shallow trench isolation (STI, Shallow Trench Isolation) is provided at the edge of the P-type well region and the edge of the N-type well region; multiple trenches are formed in the P-type well region under the protection ring region, and the trenches themselves form trench rings. Word line structures (WL, Word Line) are formed in the multiple trenches respectively, the word line structure potential is grounded, and the upper surface of the word line structure is not higher than the upper surface of the substrate. The number of trenches is the same as the number of word line structures. That is, a word line structure is formed in each groove, and the word line potential is grounded to terminate the electrical leakage path of the protection ring structure. The word line structure filling material can be made of metal materials such as tungsten, titanium or titanium nitride. A plurality of metal interconnection layers are arranged above the protection ring area on the substrate. Here, four metal interconnection layers are taken as an example, namely M0, M1, M2, and M3. An interlayer dielectric layer is arranged between the bottom metal interconnection layer M0 and the substrate, and one or more groove channels are arranged in the interlayer dielectric layer. The groove channels are filled with second connectors to connect the metal interconnection layer M0 to the word line structure WL. If there are multiple second connectors, at least one of the second connectors is connected to at least one word line structure, and the other second connectors can be connected to the N+ region or P+ region on the substrate. An intermetallic dielectric layer is arranged between the metal interconnection layers, and a groove channel is formed in the intermetallic dielectric layer. The first connectors VIA0, VIA1, and VIA2 are filled in the groove channels to connect adjacent metal interconnection layers. For example, Figure 2 As shown, VIA0 is formed between M0 and M1, VIA1 is formed between M1 and M2, VIA2 is formed between M2 and M3, and so on. Similar to the above, the number of trench channels in the intermetallic dielectric layer can also be one or more. These first connecting members form a "wall"-like structure in the vertical direction, and together with the word line structure, form a trench protection ring structure.

[0022] In this embodiment, the metal interconnect layer, the first connector, and the second connector may be made of metal materials such as copper, aluminum, or tungsten; the intermetallic dielectric layer and the interlayer dielectric layer may be made of insulating dielectric materials such as silicon dioxide and silicon nitride.

[0023] Specifically in this embodiment, there are four metal interconnection layers. In some other embodiments, the metal interconnection layers may be less or more, and correspondingly, the metal inter-dielectric layers may be reduced or increased accordingly. For example, the metal interconnection layer may be 2 layers, and the corresponding metal inter-dielectric layer may be 1 layer. Those skilled in the art may choose according to actual needs. In this embodiment, the number of grooves and the number of word line structures are both 2. In some other embodiments, there may be more grooves and more word line structures. In some preferred embodiments, the number of grooves and the number of word line structures are multiples of 2. In this embodiment, the groove channels between each metal interconnection layer and its adjacent upper metal interconnection layer and lower metal interconnection layer are staggered. As Figure 2 As shown, for example, the first connector VIA2 between the metal interconnection layer M2 and the metal interconnection layer M3 on its upper side and the first connector VIA1 between M2 and the metal interconnection layer M1 on its lower side are always staggered in the vertical direction. However, in some other embodiments, these first connectors may also be aligned in the vertical direction. The specific situation can be selected by those skilled in the art according to the actual situation, and the present invention is not limited thereto. In this embodiment, there are two first connectors between each metal interconnection layer. That is, there are only two first connectors in each intermetallic dielectric layer. However, in some other embodiments, there may be one or more first connectors in each intermetallic dielectric layer, and those skilled in the art may select according to actual needs. In this embodiment, the number of second connectors is three, one of which is connected to the word line structure WL, and the rest are connected to other parts of the substrate. In some other embodiments, the number of second connectors may also be less or more, but at least one connects the word line structure WL and the bottom metal interconnection layer M0. In addition, there may be multiple second connectors connecting the bottom metal interconnection layer M0 and the word line structure WL. In addition, in this embodiment, the trench and word line structure are formed in the P-type well region, and in other embodiments of the present invention, they can also be formed in the N-type well region. Those skilled in the art can make a choice according to actual needs, and the present invention is not limited thereto.

[0024] In some embodiments, while the above method forms various components in the trench guard ring structure in the guard ring region, corresponding identical or similar components are also formed in the chip region, including: trenches, word line structures, interlayer dielectric layers, second connectors, metal interconnect layers, intermetallic dielectric layers, and first connectors. Furthermore, the trenches, word line structures, second connectors, metal interconnect layers, and first connectors in the chip region are not connected to the corresponding identical or similar components in the guard ring region.

[0025] In the present invention, the "same or similar" in the above method specifically refers to the same or similar process steps, shapes, structures, materials or functions. For example, when a groove is formed in the protection ring area, the same or similar groove is also formed in the chip area. When a word line structure is filled in the groove of the protection ring area, the same or similar word line structure is also filled in the groove of the chip area. The process steps, shapes, structures and materials of the two are the same or similar, but in terms of function, the former is used as a part of the protection ring structure to prevent electrical leakage and avoid the potential floating of the node, while the latter acts as a gate in the transistor device to play a switching role. For another example, when a dual damascene process is used to form a groove and fill a metal material in the intermetallic dielectric layer of the protection ring area to form a first connector, the same dual damascene process is used to form a hole in the intermetallic dielectric layer of the chip area and fill the same metal material to form a component similar to the first connector. The two are the same in structure and both connect the upper and lower adjacent metal interconnection layers, but in terms of shape, the former is filled in the groove to form the first connector, and the latter is filled in the hole.

[0026] According to the above method, the present invention also provides a trench protection ring structure, including a substrate, a trench, a word line structure, a plurality of metal interconnect layers, an intermetallic dielectric layer, and an interlayer dielectric layer. The substrate W has a plurality of chip regions C. For example, referring to Figure 2 as well as Figure 3 ,like Figure 2 The schematic cross-sectional view of the substrate including the trench protection ring structure shown in FIG. is a cross-sectional view of the boundary portion of a chip region C. In this portion, a protection ring region P is provided. Figure 3As shown, each chip region C has a protection ring region P at its periphery. In other words, a protection ring region P is provided between adjacent chip regions C. The substrate of this part is a silicon substrate, and semiconductor materials such as gallium nitride, silicon carbide, and silicon germanium can also be used. Ion implantation is performed on the substrate to dope group III element ions (such as boron ions) to form a P-type well region or dope group V element ions (such as arsenic ions) to form an N-type well region; group V element ions (such as arsenic ions) are doped in the P-type well region to form an N+ region or group III element ions (such as boron ions) are doped in the N-type well region to form a P+ region. The edges of the P-type well region and the edges of the N-type well region are shallow trench isolation (STI); there are multiple trenches in the P-type well region of the protection ring region, and the trenches themselves form trench rings. There are word line structures (WL) in each of the multiple trenches, the word line structure potential is grounded, and the upper surface of the word line structure is not higher than the upper surface of the substrate. The number of trenches is the same as the number of word line structures. That is, a word line structure is formed in each groove, and the word line potential is grounded to terminate the electrical leakage path of the protection ring structure. The word line structure filling material can be made of metal materials such as tungsten, titanium or titanium nitride. There are multiple metal interconnection layers above the protection ring area on the substrate. Here, four metal interconnection layers are taken as an example, namely M0, M1, M2, and M3. There is an interlayer dielectric layer between the bottom metal interconnection layer M0 and the substrate, and the interlayer dielectric layer has one or more groove channels. The groove channels are filled with second connectors to connect the metal interconnection layer M0 to the word line structure (WL). If there are multiple second connectors, at least one of the second connectors is connected to at least one word line structure, and the other second connectors can be connected to the N+ region or P+ region on the substrate. There is an intermetallic dielectric layer between the metal interconnection layers, and the intermetallic dielectric layer has a groove channel. The groove channels are filled with first connectors VIA0, VIA1, and VIA2 to connect adjacent metal interconnection layers. For example, Figure 2 As shown, VIA0 is formed between M0 and M1, VIA1 is formed between M1 and M2, VIA2 is formed between M2 and M3, and so on. Similar to the above, the number of trench channels in the intermetallic dielectric layer can also be one or more. These first connecting members form a "wall"-like structure in the vertical direction, and together with the word line structure, form a trench protection ring structure.

[0027] In this embodiment, the metal interconnect layer, the first connector, and the second connector may be made of metal materials such as copper, aluminum, or tungsten; the intermetallic dielectric layer and the interlayer dielectric layer may be made of insulating dielectric materials such as silicon dioxide and silicon nitride.

[0028] Specifically in this embodiment, the metal interconnection layer has four layers. In some other embodiments, the metal interconnection layer can be less or more, and correspondingly, the metal inter-dielectric layer is reduced or increased accordingly. For example, the metal interconnection layer can be 2 layers, and the corresponding metal inter-dielectric layer is 1 layer. Those skilled in the art can choose according to actual needs. In this embodiment, the number of grooves and the number of word line structures are both 2. In some other embodiments, there can also be more grooves and more word line structures. In some preferred embodiments, the number of grooves and the number of word line structures are multiples of 2. In this embodiment, the connector groove channels between each metal interconnection layer and its adjacent upper metal interconnection layer and lower metal interconnection layer are staggered. As Figure 2 As shown, for example, the first connector VIA2 between the metal interconnection layer M2 and the metal interconnection layer M3 on its upper side and the first connector VIA1 between M2 and the metal interconnection layer M1 on its lower side are always staggered in the vertical direction. However, in some other embodiments, these first connectors may also be aligned in the vertical direction. The specific situation can be selected by those skilled in the art according to the actual situation, and the present invention is not limited thereto. Moreover, in this embodiment, there are two first connectors between each metal interconnection layer. That is, there are only two first connectors in each intermetallic dielectric layer. However, in some other embodiments, there may also be one or more first connectors in each intermetallic dielectric layer, and those skilled in the art may select according to actual needs. In this embodiment, the number of second connectors is three, one of which is connected to the word line structure (WL), and the rest are connected to other parts of the substrate. In some other embodiments, the number of second connectors may also be less or more, but at least one connects the word line structure (WL) and the bottom metal interconnection layer M0. Furthermore, there may be multiple second connectors connecting the bottom metal interconnect layer M0 and the word line structure (WL). Those skilled in the art may select according to actual needs. In addition, in this embodiment, the trench and the word line structure are formed in the P-type well region. In other embodiments of the present invention, they may also be formed in the N-type well region. Those skilled in the art may select according to actual needs, and the present invention is not limited thereto.

[0029] In some embodiments, the substrate also forms the same components as those in the trench protection ring region in the chip region, including: trenches, word line structures, interlayer dielectric layers, second connectors, metal interconnect layers, intermetallic dielectric layers, and first connectors. Furthermore, the trenches, word line structures, interlayer dielectric layers, second connectors, metal interconnect layers, intermetallic dielectric layers, and first connectors in the chip region are not connected to the same or similar components as those in the protection ring region.

[0030] In the present invention, the above-mentioned "same or similar" specifically refers to the same or similar process steps, shapes, structures, materials or functions. For example, when there are grooves in the protection ring area, there are also the same or similar grooves in the chip area. When the grooves in the protection ring area are filled with word line structures, the grooves in the chip area are also filled with the same or similar word line structures. The process steps, shapes, structures and materials of the two are the same or similar, but in terms of function, the former is a part of the protection ring structure to prevent electrical leakage and avoid the potential floating of the node, while the latter acts as a gate in the transistor device to play a switching role. For another example, when a dual damascene process is used to form a groove and fill a metal material in the intermetallic dielectric layer in the protection ring area to form a first connector, the same dual damascene process is used to form a hole in the intermetallic dielectric layer in the chip area and fill the same metal material to form a component similar to the first connector. The two are the same in structure and both connect the upper and lower adjacent metal interconnection layers, but in terms of shape, the former is filled in the groove to form the first connector, and the latter is filled in the hole.

[0031] As described above, the beneficial effect of the present invention is that by setting two word lines on the substrate under the guard ring area, the word line potential is grounded to reduce the leakage path of the word line channel. At the same time, one of the two word lines is connected to the metal interconnect layer through a connector to avoid node potential floating. Compared with the prior art in which no word line is usually set, the word line channel has less leakage and the node potential floating is smaller.

[0032] The above are some embodiments of the groove protection ring and the method for forming the same provided by the present invention. Through the description of the embodiments, it is believed that those skilled in the art can understand the technical solution of the present invention and its operating principle. However, the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art may make appropriate modifications to the technical solution provided by the present invention according to actual needs, and the modifications and equivalent transformations made shall not depart from the scope of protection claimed by the present invention. The scope of rights claimed for protection by the present invention shall be subject to the attached claims.

Claims

1. A method for forming a trench protection ring structure, comprising: Providing a substrate, wherein the substrate has a plurality of chip regions, and a protection ring region is arranged between adjacent chip regions; A trench is formed in the protection ring region, a word line structure is formed in the trench, an upper surface of the word line structure is not higher than an upper surface of the substrate, and a potential of the word line structure in the trench in the protection ring region is grounded; A plurality of metal interconnection layers are stacked on the substrate, an intermetallic dielectric layer is disposed between adjacent metal interconnection layers, a first connector is formed in the intermetallic dielectric layer to connect adjacent metal interconnection layers, an interlayer dielectric layer is disposed between the bottom metal interconnection layer and the substrate, a second connector is disposed in the interlayer dielectric layer to connect the bottom metal interconnection layer with the word line structure, thereby forming a trench protection ring structure; Among them, the trench protection ring structure includes a plurality of the trenches and a plurality of the word line structures, the number of the trenches is the same as the number of the word line structures, and the number of the word lines and the trenches is 2 or a multiple of 2, and the bottom metal interconnect layer is connected to at least one of the plurality of word line structures through the second connecting member.

2. The method for forming a trench protection ring structure according to claim 1, wherein: While the various components in the trench protection ring structure are formed in the protection ring area, corresponding identical or similar components are also formed in the chip area, and the components include the trench, the word line structure, the interlayer dielectric layer, the second connector, the metal interconnect layer, the intermetallic dielectric layer and the first connector.

3. The method for forming a trench protection ring structure according to claim 2, wherein: The metal interconnect layer, the first connector, the second connector, and the word line structure in the protection ring region are not connected to corresponding identical or similar components in the chip region.

4. A groove protection ring structure, characterized in that: include: A substrate, wherein the substrate has a plurality of chip regions and a protection ring region located between adjacent chip regions; A groove located in the protection ring area; A word line structure is located in the trench, an upper surface of the word line structure is not higher than an upper surface of the substrate, and a potential of the word line structure in the trench in the protection ring region is grounded; A plurality of metal interconnection layers are located on the substrate and are arranged in a stacked manner; An intermetallic dielectric layer is located between adjacent metal interconnection layers, wherein the intermetallic dielectric layer has a first connector, and the first connector connects the upper and lower adjacent metal interconnection layers; An interlayer dielectric layer, located between the bottom metal interconnect layer and the substrate, wherein the interlayer dielectric layer has a second connector, and the second connector connects the bottom metal interconnect layer and the word line structure; Among them, the trench protection ring structure includes a plurality of the trenches and a plurality of the word line structures, the number of the trenches is the same as the number of the word line structures, and the number of the word lines and the trenches is 2 or a multiple of 2, and the bottom metal interconnect layer is connected to at least one of the plurality of word line structures through the second connecting member.

5. The trench protection ring structure as described in claim 4, wherein the chip area includes components that are the same as or similar to the corresponding components in the trench protection ring area, and the components include the trench, the word line structure, the interlayer dielectric layer, the second connector, the metal interconnect layer, the intermetallic dielectric layer and the first connector.

6. The trench protection ring structure according to claim 4, wherein: The metal interconnect layer, the first connector, the second connector, and the word line structure in the protection ring region are not connected to corresponding identical or similar components in the chip region.

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