Display Devices

Abstract

A display device includes a substrate member, a plurality of transistors, a plurality of pad portions, a plurality of signal lines, and a blocking pad. Each of the plurality of transistors includes a control electrode, an input electrode, and an output electrode, and is disposed on a central region. The blocking pad is disposed between two adjacent signal lines among the plurality of signal lines. A portion of the blocking pad is disposed on the same layer as at least any one of the control electrode, the input electrode, and the output electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0136696, filed on November 8, 2018, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to various display devices used in multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, and game consoles. Background Art

[0004] At present, in order to realize a display device in which the size of the frame is minimized, a technology of disposing a connection electrode in the side surface of the display panel to electrically connect the display panel with the driving chip is being developed. Here, the connection electrode can be disposed on the display panel in the form of a whole plate and then patterned using a laser patterning technology.

[0005] However, there is a problem that the display panel is damaged by the laser in the process of patterning the connection electrode.

[0006] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] The device constructed according to the exemplary embodiments and the method of the present invention can provide a display device that prevents a display panel from being damaged and improves durability.

[0008] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0009] Exemplary embodiments of the inventive concept provide a display device including a first base substrate, a second base substrate, a liquid crystal layer, a first connection electrode, a second connection electrode, a first signal transmitting part, a second signal transmitting part, and a first blocking pad.

[0010] The first base substrate may include an upper surface, a lower surface, and a plurality of side surfaces connecting the upper surface and the lower surface, and the upper surface may include a first portion and a second portion configured to surround the first portion.

[0011] The second base substrate may face the first base substrate.

[0012] The liquid crystal layer may be disposed between the first base substrate and the second base substrate, and configured to overlap the first portion and not overlap the second portion.

[0013] The first connection electrode may be provided on a first side surface among the plurality of side surfaces.

[0014] The second connection electrode may be disposed on the first side surface and separated from the first connection electrode.

[0015] The first signal transmitting portion may be disposed on the upper surface, extend in the first direction, and be configured to contact the first connection electrode and receive an electrical signal.

[0016] The second signal transmitting portion may be disposed on the upper surface, extend in the first direction, and be configured to contact the second connection electrode and receive an electrical signal.

[0017] The first blocking pad may be configured to overlap the second portion of the upper surface, be disposed between the first signal transmission portion and the second signal transmission portion, and be separated from the first signal transmission portion and the second signal transmission portion.

[0018] The first blocking pad may be insulated from the first and second signal transmitting portions and extend in a second direction intersecting the first direction.

[0019] The first signal transmission portion may include: a first pad portion configured to contact the first connecting electrode; a first line portion extending from the first pad portion and having a smaller width than the first pad portion; and the second signal transmission portion may include: a second pad portion configured to contact the second connecting electrode; and a second line portion extending from the second pad portion and having a smaller width than the second pad portion.

[0020] The first barrier pad may be disposed between the first line portion and the second line portion.

[0021] The display device may further include a transistor including a control electrode, an input electrode, and an output electrode and disposed on the first portion of the upper surface. At least a portion of the first blocking pad may be disposed on the same layer as at least one of the control electrode, the input electrode, and the output electrode.

[0022] The first blocking pad may include: a first sub-barrier pad provided in the same process as the control electrode; and a second sub-barrier pad provided in the same process as the input electrode and the output electrode.

[0023] The display device may further include a gate driving circuit and a data driving circuit, wherein any one of the gate driving circuit and the data driving circuit is electrically connected to the first connection electrode and the second connection electrode.

[0024] The display device may further include a third connection electrode, a fourth connection electrode, a third signal transmitting portion, a fourth signal transmitting portion, and a second blocking pad.

[0025] The third connection electrode may be disposed on a second side surface among the plurality of side surfaces of the first base substrate.

[0026] The fourth connection electrode may be disposed on the second side surface and separated from the third connection electrode.

[0027] The third signal transmitting portion may be disposed on the upper surface, extend in the second direction, and be configured to contact the third connection electrode to receive an electrical signal.

[0028] The fourth signal transmitting portion may be disposed on the upper surface, extend in the second direction, and be configured to contact the fourth connection electrode to receive an electrical signal.

[0029] The second blocking pad may be configured to overlap the second portion of the upper surface, be disposed between the third signal transmission portion and the fourth signal transmission portion, and be separated from the third signal transmission portion and the fourth signal transmission portion.

[0030] The other one of the gate driving circuit and the data driving circuit may be electrically connected to the third link electrode and the fourth link electrode.

[0031] The second blocking pad may be insulated from the third and fourth signal transmitting portions and extend in the first direction.

[0032] In an exemplary embodiment of the present inventive concept, a display device includes a substrate member, a plurality of transistors, a plurality of pad portions, a plurality of signal lines, and a blocking pad.

[0033] The base member may include a central region and an edge region configured to surround the central region.

[0034] Each of the plurality of transistors may include a control electrode, an input electrode, and an output electrode, and be disposed in the central region.

[0035] A plurality of pad portions may be provided in the edge region.

[0036] The plurality of signal lines may be electrically and respectively connected to the plurality of pad portions, and electrically and respectively connected to the plurality of transistors.

[0037] The barrier pad may be disposed in the edge region and disposed between two adjacent signal lines among the plurality of signal lines.

[0038] At least a portion of the barrier pad may be disposed on the same layer as at least any one of the control electrode, the input electrode, and the output electrode.

[0039] The display device may further include a plurality of light emitting elements disposed on the base member, configured to overlap the central region, and electrically connected to the plurality of transistors.

[0040] The display device may further include a plurality of connection electrodes disposed on one side surface of the base member and configured to contact the plurality of pad portions, respectively.

[0041] The barrier pad may include a first sub-barrier pad and a second sub-barrier pad. The first sub-barrier pad may include the same material as the control electrode, the second sub-barrier pad may include the same material as at least one of the input electrode and the output electrode, and the first sub-barrier pad may overlap with the second sub-barrier pad.

[0042] The blocking pad may be insulated from the plurality of signal lines.

[0043] Each of the multiple signal lines can extend in a first direction, the blocking pad extends in a second direction intersecting the first direction, the width of each of the multiple signal lines can be smaller than the width of each of the multiple pad portions, and at least a portion of the blocking pad can overlap with at least any one of the multiple pad portions in the first direction.

[0044] The barrier pad may be provided in plural, and each of the plurality of barrier pads may be disposed between the plurality of signal lines.

[0045] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0047] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the inventive concept.

[0048] Figure 2 yes Figure 1 An exploded perspective view of a display device is shown in FIG.

[0049] Figure 3A yes Figure 2 An exploded perspective view of a display module is shown in FIG.

[0050] Figure 3B yes Figure 3A A perspective view of a first base substrate is shown in FIG.

[0051] Figure 4 is a block diagram of a display module according to an exemplary embodiment of the inventive concept.

[0052] Figure 5 is a plan view of a display module according to an exemplary embodiment of the inventive concept.

[0053] Figure 6 is an equivalent circuit diagram according to an exemplary embodiment of the inventive concept.

[0054] Figure 7 is along Figure 4 A cross-sectional view taken along line II' shown in FIG.

[0055] Figure 8 is an enlarged plan view in which the first base substrate is Figure 3A The area corresponding to the area AA shown in FIG. 1 is enlarged.

[0056] Fig. 9 is an enlarged plan view in which the first base substrate is Figure 3A The area corresponding to the area BB shown in FIG. 1 is enlarged.

[0057] Fig. 10A is along Figure 8 A cross-sectional view taken along line II-II' is shown in FIG.

[0058] Fig. 10B is along Figure 8 A cross-sectional view taken along line III-III' is shown in FIG.

[0059] Fig.11A is along Fig. 9 A cross-sectional view taken along line IV-IV' is shown in FIG.

[0060] Fig. 11B is along Fig. 9 A cross-sectional view taken along line V-V' shown in FIG.

[0061] Fig.12 is a block diagram of an organic light emitting display module according to an exemplary embodiment of the inventive concept.

[0062] Fig.13 is an equivalent circuit diagram of a pixel of an organic light emitting display panel according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0063] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other examples, well-known structures and devices are shown in block diagram form to avoid unnecessary confusion of various exemplary embodiments. In addition, various exemplary embodiments may be different, but do not have to be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0064] Unless otherwise specified, the exemplary embodiments shown should be understood as providing exemplary features of varying details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments can be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0065] The use of cross hatching and / or shadow in the drawings is generally provided to make the boundaries between adjacent elements clear. Therefore, unless otherwise specified, the presence or absence of cross hatching or shadow does not convey or indicate any preference or demand for a specific material, material properties, dimensions, ratios, commonalities between the elements shown, and / or any other features, attributes, properties, etc. of the elements. In addition, in the drawings, for clarity and / or descriptive purposes, the size and relative size of the elements may be exaggerated. When the exemplary embodiments can be implemented differently, a specific process can be performed in an order different from the described order. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals refer to the same elements.

[0066] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical, electrical, and / or fluid connection with or without intervening elements. Additionally, the DR1 axis, DR2 axis, and DR3 axis (see Figure 1) is not limited to the three axes of a rectangular coordinate system (e.g., x, y, and z axes), and may be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0067] Although the terms "first", "second", etc. can be used in this article to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element.

[0068] For descriptive purposes, spatially relative terms such as "under," "below," "below," "below," "above," "above," "above," "above," "side" (e.g., as in "sidewall"), and the like may be used herein and thereby describe the relationship of one element to another element(s) as shown in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is flipped, an element described as "under" or "beneath" other elements or features would subsequently be oriented "over" the other elements or features. Thus, the exemplary term "under" can encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein will be interpreted accordingly.

[0069] The terms used herein are for the purpose of describing a particular embodiment, and are not intended to be limiting. As used herein, the singular "one" and "the (described)" are also intended to include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "include", "comprise" and their variants specify the existence of stated features, integral bodies, steps, operations, elements, parts and / or their groups, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "roughly", "about" and other similar terms are used as approximate terms and not as terms of degree, and are therefore used to consider the inherent deviations in the values ​​measured, calculated and / or provided that will be recognized by those of ordinary skill in the art.

[0070] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Therefore, changes from the illustrated shapes, for example due to manufacturing techniques and / or tolerances, will be expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be interpreted as being limited to the shapes of the specifically illustrated areas, but will include deviations in shape, for example, due to manufacturing. In this way, the areas shown in the figures may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and therefore need not be intended to be limited.

[0071] As is customary in the art, some exemplary embodiments are described and shown in the accompanying drawings in the form of functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, and the like, which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the blocks, units and / or modules are implemented by microprocessors or other similar hardware, the microprocessors or other similar hardware can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also conceivable that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and related circuits) for performing other functions. Moreover, without departing from the scope of the inventive concept, each block, unit and / or module of some exemplary embodiments can be physically divided into two or more interacting and discrete blocks, units and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules.

[0072] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0073] The front surface (or upper surface) and the rear surface (or lower surface) of each member or each part described below are distinguished by the third directional axis DR3. However, the first to third directional axes DR1, DR2 and DR3 shown in the present embodiment are only exemplary, and the directions indicated by the first to third directional axes DR1, DR2 and DR3 are relative concepts and can therefore be changed to other directions. In the following, the first to third directions are directions indicated by the first to third directional axes DR1, DR2 and DR3, respectively, and refer to the same figure marks.

[0074] Figure 1 is a perspective view of a display device DD according to an exemplary embodiment of the inventive concept. Figure 2 yes Figure 1 0047 is an exploded perspective view of a display device DD shown in FIG.

[0075] like Figure 1 and Figure 2 As shown, the display device DD may include a top cover TC, a display panel DP, a main circuit board PB, a gate driving part GDC, a data driving part DDC, a backlight unit BLU, and a bottom member BC. The backlight unit BLU may include an optical member OPS, a reflective member RFS, and a light source LS.

[0076] Although not shown in the drawings, the display device DD may further include a bottom cover The bottom cover is disposed at a lower portion of the bottom member BC and may protect the display device DD from external impact or contamination.

[0077] like Figure 1 As shown in , the display device DD includes a display area DA and a non-display area NDA. The display area DA may be provided on a plane parallel to a plane defined by a first direction DR1 and a second direction DR2 perpendicular to the first direction DR1. The non-display area NDA may be defined by a top cover TC. The non-display area NDA corresponds to a frame of the display device DD.

[0078] In another exemplary embodiment of the present inventive concept, the top cover TC may be omitted. For the display device DD without the top cover TC, the non-display area NDA may be defined by a sealing member or a mold, or the like.

[0079] The display area DA provides image IM information to consumers. Figure 1 , a butterfly is shown as an example of an image IM.

[0080] The top cover TC may protect the display panel DP or the like from external impact or contamination. An opening portion OP-TC of the top cover TC exposes a front surface of the display panel DP to define a display area DA.

[0081] The display panel DP may include a first base substrate BS1 and a second base substrate BS2 configured to face the first base substrate BS1. The first base substrate BS1 and the second base substrate BS2 may be provided using a glass substrate or a plastic substrate, but are not limited thereto, and may include various materials that may be bent or folded. The base substrate may be referred to as a base member.

[0082] The display panel DP is parallel to a surface defined by the first direction DR1 and the second direction DR2. The normal direction of the display panel DP is indicated by the third direction DR3. The third direction DR3 indicates the thickness direction of the display device DD. The front surface and the rear surface of each member are classified by the third direction DR3. However, the directions indicated by the first to third directions DR1, DR2 and DR3 are relative concepts and can be changed to other directions.

[0083] According to exemplary embodiments of the inventive concept, the display panel DP may be provided using any one of an organic light emitting display panel, a liquid crystal display panel, a plasma display panel, an electrophoretic display panel, a microelectromechanical system (MEMS) display panel, and an electrowetting display panel.

[0084] exist Figure 1 and Figure 2 In the embodiment, the display panel DP is exemplarily shown in a plate type, but exemplary embodiments of the inventive concept are not limited thereto. In another exemplary embodiment of the inventive concept, the display panel DP may be curved with a prescribed curvature.

[0085] The optical member OPS may include at least one of a diffuser, a first prism sheet (or a horizontal prism sheet), a second prism sheet (or a vertical prism sheet), or a brightness enhancement member.

[0086] The diffuser may diffuse the incident light and provide the incident light to the display panel DP. The diffuser may have a plate shape or a sheet shape. The first prism sheet may adjust the directional direction of the incident light to a first direction DR1. The second prism sheet may adjust the directional direction of the incident light to a second direction DR2 orthogonal to the first direction DR1.

[0087] However, the type of the optical member OPS is not limited thereto, and may be a sheet for changing or enhancing characteristics of incident light.

[0088] The light source LS provides light to the display panel DP. The light source LS may include a plurality of point light sources PLS and a plurality of circuit boards CB.

[0089] Each of the point light sources PLS may include an LED chip and a lens. The LED chip may be mounted in the circuit board CB and emit light in a visible wavelength band of about 430nm to about 780nm. The lens may control the direction of light emitted from the LED chip.

[0090] The reflective member RFS may be disposed between the lens and the circuit board CB. The reflective member RFS may reflect light emitted through the lens after being generated by the LED chip.

[0091] In an exemplary embodiment of the present inventive concept, the reflective member RFS may have a sheet shape having a thickness of several micrometers to several hundred micrometers. In another embodiment, the reflective member RFS may have a shape coated on the bottom member BC.

[0092] Although not shown, a plurality of optical member supporters may be provided on the reflective member RFS. The optical member supporters may support the optical member OPS.

[0093] exist Figure 2, the backlight unit BLU is shown as having a direct type structure, but is not limited thereto. In another exemplary embodiment of the inventive concept, the backlight unit BLU may have an edge type structure including a light guide member. The display module DM includes a display panel DP, a main circuit board PB, a gate driving portion GDC having a gate circuit board GCB and a gate driving chip GC, and a data driving portion DDC having a data circuit board DCB and a data driving chip DC.

[0094] Although not shown, when the display panel DP of the display module DM is an organic light emitting display panel DP, the backlight unit BLU is omitted in the display device DD.

[0095] Figure 3A yes Figure 2 FIG. 4 is an exploded perspective view of the display module DM shown in FIG. Figure 3B yes Figure 3A 2 is a perspective view of a first base substrate BS1 shown in FIG. Figure 4 is a cross-sectional view of a display module DM according to an exemplary embodiment of the inventive concept.

[0096] about Figure 3A The display module DM includes a display panel DP, a main circuit board PB, a gate driving part GDC, a data driving part DDC, and a connection electrode CNE. The connection electrode CNE includes a gate connection electrode G-CNE and a data connection electrode D-CNE.

[0097] One side surface of the first base substrate BS1 may face the gate circuit board GCB of the gate driving part GDC, and the other side surface of the first base substrate BS1 may face the data circuit board DCB of the data driving part DDC.

[0098] The connection electrode CNE may include a metal such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta) or titanium (Ti), or an alloy thereof. Specifically, as a scheme for providing the connection electrode CNE in each of the side surfaces of the first base substrate BS1, a scheme of providing an electrode by laser patterning after deposition of a metal material, a screen scheme, or the like may be adopted in various ways.

[0099] The adhesive member (not shown) can electrically connect the gate connection electrode G-CNE with the gate drive pad (not shown) of the gate circuit board GCB. In addition, the adhesive member can electrically connect the data connection electrode D-CNE with the data drive pad (not shown) of the data circuit board DCB. According to an exemplary embodiment of the inventive concept, the adhesive member can be provided using an anisotropic conductive film. When the anisotropic conductive film is used as the adhesive member, the adhesive member includes an adhesive film having an adhesive property and conductive particles provided in the adhesive film. The conductive particles make the gate connection electrode G-CNE and the gate drive pad conductive, and make the data connection electrode D-CNE and the data drive pad conductive.

[0100] about Figure 3B The first base substrate BS1 includes an upper surface US, a lower surface DS, and a plurality of side surfaces SS1 and SS2 configured to connect the upper surface US and the lower surface DS. Figure 3B , as examples of the plurality of side surfaces SS1 and SS2 , the first side surface SS1 and the second side surface SS2 are illustrated.

[0101] about Figure 4 , the display panel DP including the first base substrate BS1 and the second base substrate BS2 includes a display area DA-DP and a non-display area NDA-DP adjacent to the display area DA. According to an exemplary embodiment of the inventive concept, the non-display area NDA-DP is shown to surround the display area DA-DP, but is not limited thereto. The non-display area NDA-DP may be adjacent to one side of the display area DA-DP or omitted.

[0102] In this specification, the first portion or the center area may be used as a meaning corresponding to the display area DA. In this specification, the frame area, the second portion or the edge area may be used as a meaning corresponding to the non-display area NDA.

[0103] The first base substrate BS1 includes a plurality of gate lines GL 1 To GL i , is configured to be aligned with the gate line GL 1 To GL i Intersecting multiple data lines DL 1 To DL j , and connected to the gate line GL 1 To GL i and data line DL 1 To DL j Multiple pixels PX 11 To PX ij . Gate line GL 1 To GL i Connected to the gate drive part GDC. Data line DL 1 To DL jConnected to the data driver DDC. On the other hand, Figure 4 Only the gate line GL is shown 1 To GL i 、Data line DL 1 To DL j and Pixel PX 11 To PX ij part.

[0104] The pixels PX can be set according to the color to be displayed. 11 To PX ij In other words, the pixels PX 11 To PX ij One of the primary colors can be displayed. The primary colors may include red, green, and blue. On the other hand, the primary colors are not limited thereto and may also include various colors such as yellow, cyan, and magenta.

[0105] The signal control part SC is installed in the main circuit board PB and outputs an overall driving signal required for driving the display panel DP. As an example, in response to an external control signal, the signal control part SC generates a gate control signal for controlling the gate driving part GDC and transmits the gate control signal to the gate driving part GDC. In response to the external control signal, the signal control part SC generates a data control signal for controlling the data driving part DDC and transmits the data control signal to the data driving part DDC.

[0106] The gate driving part GDC generates a gate signal based on the gate control signal during a plurality of frame periods. The gate driving part GDC outputs the gate signal to the gate line GL. 1 To GL i The gate signals may be sequentially outputted corresponding to the horizontal periods. In addition, although not shown, a plurality of gate circuit boards GCB may be electrically connected to each other.

[0107] On the other hand, although it is described that the gate driving part GDC is provided as a plurality, it is not limited thereto. In other words, the gate driving part GDC can be provided as a single gate driving part GDC to generate a gate signal. For example, a display module DM including a single gate driving part GDC can be applied to a mobile phone, etc.

[0108] Each of the gate driving parts GDC may include a gate driving chip GC and a gate circuit board GCB on which the gate driving chip GC is mounted. The gate circuit board GCB may be provided using a flexible printed circuit board and may be provided as many as the number corresponding to the number of the gate driving chips GC.

[0109] The data driving part DDC generates a grayscale voltage according to the image data provided from the signal control part SC based on the data control signal received from the signal control part SC. The data driving part DDC outputs the grayscale voltage as a data signal to the data line DL. 1 To DL j .

[0110] On the other hand, although it is described that a plurality of data driving parts are provided, it is not limited thereto. In other words, the data driving part DDC is provided as a single data driving part to generate grayscale voltages. For example, a display module DM including a single gate driving part GDC can be applied to a mobile phone, etc.

[0111] Each of the data driving parts DDC may include a data driving chip DC and a data circuit board DCB on which the data driving chip DC is mounted. The data circuit board DCB may be provided using a flexible printed circuit board. The data circuit board DCB electrically connects the main circuit board PB and the first base substrate BS1. The data driving chip DC is electrically connected to a plurality of data lines DL 1 To DL j The corresponding data line.

[0112] The gate control signal output from the signal control part SC may be provided to the gate circuit board GCB via the data circuit board DCB that is most adjacent to the gate circuit board GCB. To this end, the data circuit board DCB may include an auxiliary dummy line BSL configured to transmit the gate control signal output from the signal control part SC to the gate circuit board GCB.

[0113] According to an exemplary embodiment of the inventive concept, the gate driving part GDC may be disposed on one side surface of the first base substrate BS1 and one side surface of the second base substrate BS2 aligned with the one side surface of the first base substrate BS1. The gate driving part GDC may be provided in a tape carrier package (TCP) type.

[0114] According to an exemplary embodiment of the inventive concept, the data driving part DDC may be disposed on the other side surface of the first base substrate BS1 and the other side surface of the second base substrate BS2 aligned with the other side surface of the first base substrate BS1. The data driving part DDC may be provided in a tape carrier package (TCP) type.

[0115] Figure 5 is a plan view of a display module DM according to an exemplary embodiment of the inventive concept.

[0116] about Figure 5The gate driving part GDC and the data driving part DDC may be disposed on one side surface and the other side surface of the display panel DP, respectively. Here, one side surface and the other side surface of the display panel DP may correspond to one side surface and the other side surface of the first base substrate BS1 or the second base substrate BS2, respectively.

[0117] When the gate driving part GDC and the data driving part DDC are not disposed on the side surface of the first base substrate BS1 but are disposed on the upper surface of the first base substrate BS1, a pad part electrically connected to the gate driving part GDC and the data driving part DDC is disposed on the upper surface of the first base substrate BS1. When the pad part is disposed on the upper surface of the first base substrate BS1, the bezel area NDA may increase an area as large as that of the pad part.

[0118] However, according to an exemplary embodiment of the inventive concept, as described above, since the gate circuit board GCB is disposed on the side surface of the display panel DP, the pad portion is not disposed on the upper surface of the first base substrate BS1. As a result, the non-display area NDA may be reduced by an area corresponding to the pad portion.

[0119] Figure 6 is a pixel PX according to an exemplary embodiment of the inventive concept ij Equivalent circuit diagram of . Figure 7 is an exemplary embodiment according to the inventive concept. Figure 4 A cross-sectional view taken along line II' shown in FIG.

[0120] Figure 4 The plurality of pixels PX shown in 11 To PX ij Each of can have Figure 6 The circuit shown is equivalent to the circuit shown.

[0121] like Figure 6 As shown, the pixel PX ij The pixel thin film transistor TRP (hereinafter, pixel transistor), the liquid crystal capacitor Clc, and the storage capacitor Cst are included. In an exemplary embodiment of the present inventive concept, the storage capacitor Cst may be omitted.

[0122] The pixel transistor TRP is electrically connected to the i-th gate line GL i and the jth data line DL j The pixel transistor TRP responds to the gate line GL from the i-th gate line. i The gate signal received is outputted from the jth data line DL j The pixel voltage corresponding to the received data signal.

[0123] The liquid crystal capacitor Clc is charged with the pixel voltage output from the pixel transistor TRP. The amount of charge charged in the liquid crystal capacitor Clc is changed according to the amount of charge charged in the liquid crystal capacitor Clc. Figure 7 ) The light incident to the liquid crystal layer LCL is transmitted or blocked according to the arrangement of the liquid crystal directors.

[0124] The storage capacitor Cst is connected to the liquid crystal capacitor Clc in parallel. The storage capacitor Cst maintains the arrangement of the liquid crystal director during a certain period.

[0125] like Figure 7 As shown in FIG. 1 , the pixel transistor TRP includes a gate line connected to the i-th gate line GL. i (See Figure 4 ), an activation layer ALP (hereinafter, a pixel activation layer) configured to overlap with the pixel control electrode CEP, and a j-th data line DL j (See Figure 4 ) of the pixel input electrode IEP (hereinafter, pixel input electrode), and an output electrode OEP (hereinafter, pixel output electrode) set separately from the pixel input electrode IEP.

[0126] The liquid crystal capacitor Clc includes a pixel electrode PE and a common electrode CE. The storage capacitor Cst includes the pixel electrode PE and a portion of a storage line STL configured to overlap the pixel electrode PE.

[0127] The i-th gate line GL i The pixel control electrode CEP is connected to the i-th gate line GL. i The i-th gate line GL i The storage line STL may include a metal such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti), or an alloy thereof. i The storage line STL may include a multi-layer structure of, for example, a titanium layer and a copper layer.

[0128] A first insulating layer 10 provided to cover the pixel control electrode CEP and the storage line STL is disposed on one surface of the first base substrate BS1. The first insulating layer 10 may include at least any one of an inorganic material and an organic material. The first insulating layer 10 may be an organic film or an inorganic film. The first insulating layer 10 may include a multilayer structure of, for example, a silicon nitride layer and a silicon oxide layer.

[0129] The pixel activation layer ALP configured to overlap the pixel control electrode CEP is disposed on the first insulating layer 10. The pixel activation layer ALP may include a semiconductor layer (not shown) and an ohmic contact layer (not shown).

[0130] The pixel activation layer ALP may include amorphous silicon or polycrystalline silicon. In addition, the pixel activation layer ALP may include a metal oxide semiconductor.

[0131] The pixel output electrode OEP and the pixel input electrode IEP are disposed on the pixel activation layer ALP. The pixel output electrode OEP and the pixel input electrode IEP are disposed separately from each other. Each of the pixel output electrode OEP and the pixel input electrode IEP may partially overlap with the pixel control electrode CEP.

[0132] Figure 7 An exemplary pixel transistor TRP having a staggered structure is shown, but the structure of the pixel transistor TRP is not limited thereto. The pixel transistor TRP may have a planar structure.

[0133] The second insulating layer 20 provided to cover the pixel active layer ALP, the pixel output electrode OEP, and the pixel input electrode IEP is disposed on the first insulating layer 10. The second insulating layer 20 provides a flat surface. The second insulating layer 20 may include an organic material.

[0134] The pixel electrode PE is disposed on the second insulating layer 20. The pixel electrode PE is connected to the pixel output electrode OEP through the second insulating layer 20 and a contact hole CH configured to penetrate the second insulating layer 20. An alignment film 30 configured to cover the pixel electrode PE may be disposed on the second insulating layer 20.

[0135] The color filter layer CF is disposed on one surface of the second base substrate BS2. The common electrode CE is disposed on one surface of the color filter layer CF. A common voltage is applied to the common electrode CE. The common voltage and the pixel voltage have different values. An orientation film (not shown) configured to cover the common electrode CE may be disposed on the common electrode CE. Another insulating layer may be disposed between the color filter layer CF and the common electrode CE.

[0136] The pixel electrode PE and the common electrode CE with the liquid crystal layer LCL interposed therebetween form a liquid crystal capacitor Clc. In addition, the pixel electrode PE and the portion of the storage line STL with the first insulating layer 10 and the second insulating layer 20 interposed therebetween form a storage capacitor Cst. The storage line STL receives a storage voltage having a value different from the pixel voltage. The storage voltage may have the same value as the common voltage.

[0137] also, Figure 7 The pixel PX shown in ij The cross-section is only exemplary. Figure 7 Unlike those shown in , at least one of the color filter layer CF and the common electrode CE may be disposed on the first base substrate BS1. In other words, the liquid crystal display panel according to an exemplary embodiment of the inventive concept may include pixels in a mode such as a vertical alignment (VA) mode, a patterned vertical alignment (PVA) mode, an in-plane switching (IPS) mode, a fringe field switching (FFS) mode, or a plane-to-line switching (PLS) mode.

[0138] Figure 8 is an enlarged plan view in which the first base substrate BS1 is Figure 3A The area corresponding to the area AA shown in FIG. 1 is enlarged. Fig. 9 is an enlarged plan view in which the first base substrate BS1 is Figure 3A The area corresponding to the area BB shown in FIG. 1 is enlarged.

[0139] Figure 8 and Fig. 9 A portion of a region corresponding to the non-display area NDA-DP of the display panel DP may be shown.

[0140] about Figure 8 The gate connection electrode G-CNE may be disposed on the first side surface SS1 of the first base substrate BS1 (see Figure 3B )superior.

[0141] However, exemplary embodiments of the inventive concept are not limited thereto, and in another exemplary embodiment of the inventive concept, the data link electrode D-CNE may be disposed on the first side surface SS1.

[0142] Each of the gate connection electrodes G-CNE may be electrically connected to each gate line GL and receive an electrical signal. In this specification, the gate line GL may be referred to as a signal transmission portion.

[0143] The gate line GL may contact the gate connection electrode G-CNE and receive an electrical signal, and is disposed on the upper surface US of the first base substrate BS1 to extend in the first direction DR1.

[0144] The gate line GL may include a gate pad portion GL-P and a gate signal line portion GL-L. The gate pad portion GL-P may contact the gate connection electrode G-CNE and receive an electrical signal. Figure 8 , the gate pad portion GL-P extends shorter in the second direction DR2 than the gate connection electrode G-CNE. However, exemplary embodiments of the inventive concept are not limited thereto, and the gate pad portion GL-P may extend longer than the gate connection electrode G-CNE.

[0145] The gate signal line portion GL-L extends from the gate pad portion GL-P and may have a smaller width than the gate pad portion GL-P in the second direction DR2.

[0146] In an exemplary embodiment of the present inventive concept, in order to drive the gate driving part GDC (see Figure 3A ) are electrically connected to each other, and the connection pad CL-P1 may be provided on the upper surface US of the first base substrate BS1. The connection pad CL-P1 is connected to another adjacent connection pad CL-P1 via a connection line CL1 and becomes conductive.

[0147] In an exemplary embodiment of the inventive concept, each of the first blocking pads CD1 may overlap the non-display area NDA-DP of the first base substrate BS1 and be disposed between two adjacent gate lines GL.

[0148] The first blocking pads CD1 may be disposed separately from the gate lines GL. However, exemplary embodiments of the inventive concept are not limited thereto. Although not shown, each of the first blocking pads CD1 may contact any one of two adjacent gate lines GL and have an integral shape with the contacted gate line GL.

[0149] The first barrier pad CD1 may be provided and insulated from the gate line GL and extend in the second direction DR2.

[0150] In an exemplary embodiment of the inventive concept, a portion of the first blocking pad CD1 may be disposed between two adjacent gate signal line portions GL-L.

[0151] When the width of the gate signal line portion GL-L is smaller than the width of the gate pad portion GL-P, at least a portion of the first barrier pad CD1 may overlap at least a portion of the gate pad portion GL-P in the first direction DR1.

[0152] In an exemplary embodiment of the inventive concept, a portion of the first barrier pad CD1 may be disposed between two adjacent connection pads CL-P1 or between two facing portions of the connection line CL1.

[0153] In an exemplary embodiment of the inventive concept, the gate connection electrodes G-CNE may be disposed separately from each other. In a manufacturing process of the gate connection electrodes G-CNE, first, an electrode may be printed in a paste state on one side surface of the display panel DP corresponding to each of the gate driving parts GDC. After curing the printed electrode, each gate connection electrode G-CNE may be manufactured using a laser patterning scheme.

[0154] When the gate connection electrode G-CNE is manufactured using a laser patterning scheme, there is no usual separate blocking member, and thus the laser may pass through the panel that is not blocked by the gate pad portion GL-P. In this case, the internal structure of the panel, such as the wiring portion including the gate signal line portion GL-L and the connection line CL1 inside the display panel DP, and the first base substrate BS1 may be damaged. Therefore, defects such as open circuits or backlight leakage occur, the damaged structure causes external air or moisture to penetrate through the damaged structure, and the heat generated during the operation of the display device DD rapidly corrodes the interior of the panel, which results in poor durability.

[0155] However, in an exemplary embodiment of the inventive concept, each of the first blocking pads CD1 may be disposed between the gate line GL, the connection pad CL-P1, and the connection line CL1. Therefore, although the laser is irradiated to manufacture the gate connection electrode G-CNE, the laser is blocked, and thus damage to the panel and the wiring may be prevented or reduced. Therefore, even in an environment where air and moisture permeate or in a high temperature environment, high durability may still be achieved.

[0156] about Fig. 9 The data link electrode D-CNE may be disposed on the second side surface SS2 of the first base substrate BS1 (see Figure 3B )superior.

[0157] Each of the data connection electrodes D-CNE may be electrically connected to each of the data lines DL and receive an electrical signal. In this specification, the data line DL may be referred to as a signal transmission portion.

[0158] The data line DL may contact the data link electrode D-CNE and receive an electrical signal, and is disposed on the upper surface of the first base substrate BS1 to extend in the second direction DR2.

[0159] The data line DL may include a data pad portion DL-P and a data signal line portion DL-L. The data pad portion DL-P may contact the data connection electrode D-CNE and receive an electrical signal. Fig. 9 , the data pad portion DL-P extends shorter in the second direction DR2 than the data link electrode D-CNE. However, exemplary embodiments of the inventive concept are not limited thereto, and the data pad portion DL-P may extend longer than the data link electrode D-CNE.

[0160] The data signal line portion DL-L extends from the data pad portion DL-P and may have a smaller width than the data pad portion DL-P in the first direction DR1. At least a portion of each of the data signal line portions DL-L adjacent to the data pad portion DL-P may have a winding shape so as to have substantially the same resistance value as the other data signal line portions DL-L.

[0161] In an exemplary embodiment of the inventive concept, in order to electrically connect the data driving part DDC (see Figure 3A ), the connection pad CL-P2 may be disposed on the upper surface US of the first base substrate BS1. The connection pad CL-P2 is connected to another adjacent connection pad CL-P2 via a connection line CL2 and becomes conductive.

[0162] In an exemplary embodiment of the inventive concept, each of the second blocking pads CD2 may overlap the second portion (non-display area NDA) of the first base substrate BS1 and be disposed between two adjacent data lines DL. The second blocking pads CD2 may extend in the first direction DR1.

[0163] Here, for the description about the second blocking pad CD2, substantially the same content as the description about the first blocking pad CD1 may be applied, and thus detailed description about it will be omitted below. When substantially the same content is applied, the gate line GL, the gate pad portion GL-P, and the gate signal line portion GL-L may correspond to the data line DL, the data pad portion DL-P, and the data signal line portion DL-L, respectively, and the connection pad CL-P2 and the connection line CL2 may correspond to the connection pad CL-P1 and the connection line CL1, respectively.

[0164] When the data link electrode D-CNE is manufactured using a laser patterning scheme, there is no conventional separate blocking member, and thus the laser may pass through the panel without being blocked by the data pad portion DL-P.

[0165] In this case, the internal structure of the panel, such as the wiring portion including the data signal line portion DL-L and the connection line CL2 inside the display panel DP, and the first base substrate BS1 may be damaged. Therefore, defects such as open circuit or backlight leakage occur, the damaged structure causes external air or moisture to penetrate through the damaged structure, and the heat generated during the operation of the display device DD quickly corrodes the inside of the panel, which leads to poor durability.

[0166] However, in an exemplary embodiment of the inventive concept, the second blocking pad CD2 is disposed between the data line DL, the connection pad CL-P2, and the connection line CL2. Therefore, although the laser is irradiated to manufacture the data connection electrode D-CNE, the laser is blocked, and thus damage to the panel and the wiring can be prevented or reduced. Therefore, even in an environment where air and moisture permeate or in a high temperature environment, high durability can be achieved.

[0167] Fig. 10A is along Figure 8 A cross-sectional view taken along line II-II' is shown in FIG. Fig. 10B is along Figure 8 A cross-sectional view taken along line III-III' is shown in FIG.

[0168] about Fig. 10A , the connection pad CL-P1 and the connection line CL1 extending from the connection pad CL-P1 may be provided on the upper surface of the first base substrate BS1. The auxiliary electrode SPD may be provided on the connection pad CL-P1. Since the auxiliary electrode SPD is provided, the surface on which the connection pad CL-P1 and the gate connection electrode G-CNE contact each other becomes quite wide, and thus the electrical signal transmitted from the gate connection electrode G-CNE can be better transmitted.

[0169] According to the drawing, the auxiliary electrode SPD does not completely overlap the connection pad CL-P1 when viewed from the third direction DR3. However, exemplary embodiments are not limited thereto, and the auxiliary electrode SPD may be disposed to completely overlap the connection pad CL-P1 when viewed from the third direction DR3.

[0170] about Fig. 10B , the first blocking pad CD1 is disposed on the connection line CL1 (see Fig. 10A ) between the parts.

[0171] about Figure 7 and Fig. 10B, at least a portion of the first blocking pad CD1 may be disposed on the same layer as at least any one of the control electrode CEP, the input electrode IEP, and the output electrode OEP. At least a portion of the first blocking pad CD1 may be provided using the same material as at least any one of the control electrode CEP, the input electrode IEP, and the output electrode OEP. The first blocking pad CD1 may include a first sub-blocking pad CDS1 provided in the same process as the control electrode CEP, and a second sub-blocking pad CDS2 provided in the same process as the input electrode IEP and the output electrode OEP. The first sub-blocking pad CDS1 may include the same material as the control electrode CEP, and the second sub-blocking pad CDS2 may include the same material as at least any one of the input electrode IEP and the output electrode OEP.

[0172] When the first blocking pad CD1 is manufactured using the same material and process as other structures of the display device DD, additional processes and costs may not be generated. However, exemplary embodiments of the present inventive concept are not limited thereto and may include various materials capable of blocking laser light that may be employed by those skilled in the art.

[0173] The first sub-barrier pad CDS1 may have substantially the same height as the gate pad portion GL-P, and the second sub-barrier pad CDS2 may have substantially the same height as the auxiliary electrode SPD. In this manner, the first barrier pad CD1 is provided with two layers, and thus other wiring portions having a height equal to or lower than that of the first barrier pad CD1 may be effectively protected from the laser generated in the laser patterning process.

[0174] Fig.11A is along Fig. 9 A cross-sectional view taken along line IV-IV' is shown in FIG. Fig. 11B is along Fig. 9 A cross-sectional view taken along line V-V' shown in FIG.

[0175] about Fig.11A , the data pad portion DL-P and the data signal line portion DL-L extending from the data pad portion DL-P may be disposed on the upper surface of the first base substrate BS1. The auxiliary electrode SPD may be disposed on the data pad portion DL-P. Since the auxiliary electrode SPD is disposed, the surface on which the data pad portion DL-P and the data connection electrode D-CNE contact each other becomes considerably wide, and thus the electrical signal transmitted from the data connection electrode D-CNE may be better transmitted.

[0176] As shown in the figure, the auxiliary electrode SPD does not completely overlap the data pad portion DL-P when viewed from the third direction DR3. However, exemplary embodiments are not limited thereto, and the auxiliary electrode SPD may be disposed to completely overlap the data pad portion DL-P when viewed from the third direction DR3.

[0177] about Fig. 11B , the second blocking pad CD2 is disposed between the plurality of data lines DL.

[0178] about Figure 7 and Fig. 11B According to an exemplary embodiment of the inventive concept, at least a portion of the second blocking pad CD2 may be disposed adjacent to the control electrode CEP (see Figure 7 ), input electrode IEP (see Figure 7 ) and the output electrode OEP (see Figure 7 ). At least a portion of the second blocking pad CD2 may be provided using the same material as at least any one of the control electrode CEP, the input electrode IEP, and the output electrode OEP. The second blocking pad CD2 may include a first sub-blocking pad CDS1-1 provided in the same process as the control electrode CEP, and a second sub-blocking pad CDS2-1 provided in the same process as the input electrode IEP and the output electrode OEP. The first sub-blocking pad CDS1-1 may include the same material as the control electrode CEP, and the second sub-blocking pad CDS2-1 may include the same material as at least any one of the input electrode IEP and the output electrode OEP.

[0179] When the second blocking pad CD2 is manufactured in the same process using the same material as other structures of the display device DD, additional processes and costs may not be generated. However, exemplary embodiments of the inventive concept are not limited thereto and may include various materials employable by those skilled in the art.

[0180] The first sub-blocking pad CDS1-1 may have substantially the same height as the data pad portion DL-P, and the second sub-blocking pad CDS2-1 may have substantially the same height as the auxiliary electrode SPD. In this manner, the second blocking pad CD2 is provided with two layers, and thus other wiring portions having a height equal to or lower than that of the second blocking pad CD2 may be effectively protected from the laser generated in the laser patterning process.

[0181] In the above, the display device DD is exemplarily described as a liquid crystal display device, but in the following, when the display device DD is exemplarily an organic light-emitting display device, the description will be provided. However, exemplary embodiments of the inventive concept are not limited to organic light-emitting display devices, and for example, the display device DD may be a micro light-emitting display device including micro LEDs.

[0182] Fig.12 is a block diagram of an organic light emitting display module DM-1 according to an exemplary embodiment of the inventive concept. Fig.13 is an organic light emitting display panel DP-1 (see Fig.12 ) is an equivalent circuit diagram of pixel PX-1.

[0183] Fig.12 It is shown that a plurality of gate signals and a plurality of emission control signals are output from one scan driving part 100, but the exemplary embodiments of the inventive concept are not limited thereto. In an exemplary embodiment of the inventive concept, a plurality of scan driving parts divide and output a plurality of gate signals, and divide and output a plurality of emission control signals. In addition, in an exemplary embodiment of the inventive concept, a driving circuit configured to generate and output a plurality of gate signals may be separated from a driving circuit configured to generate and output a plurality of emission control signals.

[0184] The data driving part 200 receives a data control signal (not shown) and image data (not shown) from the timing control part. The data driving part 200 converts the image data into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm which are insulated from the gate lines GL1 to GLn and are configured to intersect the gate lines GL1 to GLn. The data signal has an analog voltage corresponding to the grayscale value of the image data.

[0185] The organic light emitting display module DM-1 includes a plurality of gate lines GL1 to GLn, a plurality of emission lines EL1 to ELn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX-1. The plurality of gate lines GL1 to GLn extend in a first direction DR1 and are arranged in a second direction DR2 orthogonal to the first direction DR1. Each of the emission lines EL1 to ELn may be arranged in parallel with a corresponding gate line among the plurality of gate lines GL1 to GLn. The plurality of data lines DL1 to DLm and the plurality of gate lines GL1 to GLn are insulated from each other and intersect.

[0186] Each of the plurality of pixels PX- 1 is connected to a corresponding gate line among a plurality of gate lines GL1 to GLn, a corresponding emission line among a plurality of emission lines EL1 to ELn, and a corresponding data line among a plurality of data lines DL1 to DLm.

[0187] Fig.13 is an equivalent circuit diagram of one of a plurality of pixels PX-1 of an organic light emitting display panel DP-1 according to an exemplary embodiment of the inventive concept. Fig.13 As shown in FIG. 1 , each pixel in the pixel PX- 1 includes an organic light emitting element OLED and a circuit portion configured to control the organic light emitting element OLED. The circuit portion includes a first transistor TR1, a second transistor TR2 and a capacitor CAP. On the other hand, the equivalent circuit diagram is not limited to Fig.13 Rather, the invention is not shown in the drawings, but can be modified and practiced in various other embodiments.

[0188] The first transistor TR1 includes a control electrode connected to the gate line GL, an input electrode connected to the data line DL, and an output electrode. The first transistor TR1 outputs a data signal applied to the data line DL in response to a gate signal applied to the gate line GL.

[0189] The capacitor CAP includes an electrode connected to the first transistor TR1 and an electrode configured to receive the first power voltage ELVDD. The capacitor CAP is charged with a voltage corresponding to a data signal received from the first transistor TR1.

[0190] The second transistor TR2 includes a control electrode connected to the output electrode of the first transistor TR1 and the electrode of the capacitor CAP, an input electrode configured to receive the first power supply voltage ELVDD, and an output electrode. The output electrode of the second transistor TR2 is connected to the organic light emitting element OLED. The second transistor TR2 controls the driving current flowing through the organic light emitting element OLED corresponding to the voltage stored in the capacitor CAP.

[0191] The organic light emitting element OLED includes a first electrode ED1 (or anode) connected to the second transistor TR2 and configured to receive a first power supply voltage ELVDD, and a second electrode ED2 (or cathode) configured to receive a second power supply voltage ELVSS. In addition, the organic light emitting element OLED includes an emission layer (not shown) disposed between the first electrode ED1 and the second electrode ED2. The organic light emitting element OLED emits light during a conduction period of the second transistor TR2.

[0192] According to exemplary embodiments of the present inventive concept, Figures 8 to 11B The first and second barrier pads CD1 and CD2 of the described exemplary embodiments may be substantially identically applied to the organic light emitting display panel DP.

[0193] According to exemplary embodiments of the inventive concept, since the barrier pad is disposed between the signal lines, damage to the display panel that may occur in a laser patterning process for providing a connection electrode may be prevented or reduced.

[0194] According to exemplary embodiments of the inventive concept, damage to a display panel may be prevented or reduced in a manufacturing process, and thus durability of a display device may be improved under a high temperature and high humidity environment.

[0195] Although specific exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements apparent to those of ordinary skill in the art.

Claims

1. A display device, comprising: a first base substrate including an upper surface, a lower surface, and a plurality of side surfaces connecting the upper surface and the lower surface, and the upper surface includes a first portion and a second portion configured to surround the first portion; a second base substrate configured to face the first base substrate; a liquid crystal layer disposed between the first base substrate and the second base substrate and configured to overlap with the first portion and not overlap with the second portion; A first connection electrode is disposed on a first side surface among the plurality of side surfaces; a second connection electrode disposed on the first side surface and separated from the first connection electrode; a first signal transmission portion, disposed on the upper surface, extending in a first direction, and configured to contact the first connection electrode and receive an electrical signal; a second signal transmission portion, disposed on the upper surface, extending in the first direction, and configured to contact the second connection electrode and receive an electrical signal; a transistor including a control electrode, an input electrode, and an output electrode, and disposed on the first portion of the upper surface; as well as a first blocking pad configured to overlap the second portion of the upper surface, disposed between the first signal transmission portion and the second signal transmission portion, and separated from the first signal transmission portion and the second signal transmission portion, wherein the first blocking pad includes a first sub-blocking pad provided in the same process as the control electrode and a second sub-blocking pad provided in the same process as the input electrode and the output electrode, and The first sub-blocking pad has the same height as a pad portion of the first signal transmitting portion, and the second sub-blocking pad has the same height as an auxiliary electrode disposed on the pad portion. 2 . The display device of claim 1 , wherein the first blocking pad is insulated from the first signal transmitting portion and the second signal transmitting portion. 3 . The display device of claim 2 , wherein the first barrier pad extends in a second direction intersecting the first direction.

4. The display device according to claim 3, wherein the first signal transmission part comprises: a first pad portion configured to contact the first connection electrode; as well as a first line portion extending from the first pad portion and having a smaller width than the first pad portion, and The second signal transmission part comprises: a second pad portion configured to contact the second connection electrode; as well as A second line portion extends from the second pad portion and has a smaller width than the second pad portion. 5 . The display device of claim 4 , wherein the first barrier pad is disposed between the first line portion and the second line portion. 6 . The display device of claim 1 , wherein at least a portion of the first blocking pad is disposed on a same layer as at least one of the control electrode, the input electrode, and the output electrode.

7. The display device according to claim 1, further comprising: Gate drive circuit and data drive circuit, Any one of the gate driving circuit and the data driving circuit is electrically connected to the first connecting electrode and the second connecting electrode.

8. The display device according to claim 7, further comprising: a third connection electrode disposed on a second side surface among the plurality of side surfaces of the first base substrate; a fourth connection electrode disposed on the second side surface and separated from the third connection electrode; a third signal transmission portion disposed on the upper surface, extending in a second direction intersecting the first direction, and configured to contact the third connection electrode to receive an electrical signal; a fourth signal transmission portion disposed on the upper surface, extending in the second direction, and configured to contact the fourth connection electrode to receive an electrical signal; as well as A second blocking pad configured to overlap the second portion of the upper surface is disposed between the third signal transmission portion and the fourth signal transmission portion and is separated from the third signal transmission portion and the fourth signal transmission portion.

9. A display device, comprising: a base member including a central region and an edge region configured to surround the central region; a plurality of transistors, each of the plurality of transistors comprising a control electrode, an input electrode, and an output electrode, and disposed in the central region; a plurality of pad portions disposed in the edge region; a plurality of signal lines electrically and respectively connected to the plurality of pad portions and electrically and respectively connected to the plurality of transistors; as well as a blocking pad disposed in the edge region and disposed between two adjacent signal lines among the plurality of signal lines, wherein the blocking pad includes a first sub-blocking pad provided in the same process as the control electrode and a second sub-blocking pad provided in the same process as the input electrode and the output electrode, and The first sub-barrier pad has the same height as the pad portion, and the second sub-barrier pad has the same height as the auxiliary electrode disposed on the pad portion.

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