Memory device including arithmetic circuit and neural network system including the same

Abstract

A memory device including an arithmetic circuit and a neural network system including the device are provided. The memory device includes: a memory bank including a plurality of memory cells arranged in an area where a plurality of word lines and a plurality of bit lines of the memory device intersect each other; a sense amplifier configured to amplify a signal transmitted through a selected bit line among the plurality of bit lines; and an arithmetic circuit configured to receive a first operand from the sense amplifier, receive a second operand from outside the memory device, and perform an arithmetic operation by using the first operand and the second operand based on an internal arithmetic control signal generated in the memory device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of and priority to Korean Patent Application No. 10-2018-0141950 filed in the Korean Intellectual Property Office on November 16, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a memory device and a neural network system, and more particularly, to a memory device including an arithmetic circuit and a neural network system including the memory device. Background Art

[0004] Semiconductor memory devices can be classified into volatile memory devices that require power to maintain stored information and nonvolatile memory devices that maintain stored information even when their power supply is interrupted. Volatile memory devices have high read / write speeds. On the other hand, nonvolatile memory devices have lower read / write speeds than volatile memory devices.

[0005] A neural network refers to a computing architecture that mimics a biological brain. Recently, with the development of neural network technology, research has been actively conducted to analyze input data and extract effective information in various types of electronic systems by using a neural network device that uses one or more neural network models. Summary of the invention

[0006] At least one embodiment of the inventive concept provides a method and apparatus for reducing a time required for data transmission and improving power efficiency of a system in a memory device, and a neural network system including the memory device.

[0007] According to an exemplary embodiment of the present invention, there is provided a memory device, comprising: a memory body including a plurality of memory cells arranged in an area where a plurality of word lines and a plurality of bit lines intersect each other; a sense amplifier configured to amplify a signal transmitted through a selected bit line among the plurality of bit lines; and an arithmetic circuit configured to receive a first operand from the sense amplifier, receive a second operand from outside the memory device, and perform an arithmetic operation by using the first operand and the second operand based on an internal arithmetic control signal generated in the memory device.

[0008] According to an exemplary embodiment of the inventive concept, a memory device is provided, comprising: at least one memory bank including a plurality of memory cells; control logic configured to generate an internal arithmetic control signal including an internal read signal based on an arithmetic control signal received from a processor located outside the memory device; and an arithmetic circuit configured to perform all or some of a plurality of convolution operations of the processor on input feature data and kernel data based on the internal arithmetic control signal provided by the control logic. Based on the internal read signal generated by the control logic, at least one of the input feature data and the kernel data is input from the at least one memory bank to the arithmetic circuit through a path including a sense amplifier.

[0009] According to an exemplary embodiment of the present invention, there is provided a neural network system for performing neural network operations, the neural network system comprising: a neural network processor configured to generate an arithmetic control signal for controlling an arithmetic operation of a memory device; and a memory device configured to generate an internal arithmetic control signal including an internal read signal based on the arithmetic control signal provided from the neural network processor, and when the internal read signal is generated, at least one of input feature data and kernel data is internally read from a memory body, and calculated data is generated by performing all or some of a plurality of convolution operations of the neural network processor using the input feature data and the kernel data, and the calculated data is provided to the neural network processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Exemplary embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A data processing system according to an exemplary embodiment of the inventive concept is shown;

[0012] Figure 2 A neural network system according to an exemplary embodiment of the inventive concept is shown;

[0013] Figure 3 The structure of a convolutional neural network is shown as an example of a neural network structure;

[0014] Figure 4A and Figure 4B is a diagram illustrating a convolution operation of a neural network;

[0015] Figure 5 A memory device according to an exemplary embodiment of the inventive concept is shown;

[0016] Figure 6 A memory device according to an exemplary embodiment of the inventive concept is shown;

[0017] Figure 7An arithmetic circuit according to an exemplary embodiment of the inventive concept is shown;

[0018] Figure 8 A multiplication and accumulation circuit according to an exemplary embodiment of the inventive concept is shown;

[0019] Fig. 9 An arithmetic circuit according to an exemplary embodiment of the inventive concept is shown;

[0020] Fig.10 An arithmetic circuit according to an exemplary embodiment of the inventive concept is shown;

[0021] Fig.11 shows an arithmetic circuit and an internal arithmetic control signal according to an exemplary embodiment of the inventive concept;

[0022] Fig.12 shows a configuration of a memory device for describing an internal read operation according to an exemplary embodiment of the inventive concept;

[0023] Fig.13 shows a configuration of a memory device for describing an internal write operation according to an exemplary embodiment of the inventive concept;

[0024] Fig.14 shows an internal arithmetic control signal according to an exemplary embodiment of the inventive concept;

[0025] Fig.15 A memory device according to an exemplary embodiment of the inventive concept is shown;

[0026] Fig.16 shows a structure of a memory device according to an exemplary embodiment of the inventive concept; and

[0027] Fig.17 An electronic system according to an exemplary embodiment of the inventive concept is shown. DETAILED DESCRIPTION

[0028] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0029] Figure 1A data processing system 10 according to an exemplary embodiment of the inventive concept is shown. The data processing system 10 includes a host 100 (e.g., a host device), a memory controller 200 (e.g., a control circuit), and a memory device 300. The data processing system 10 can be applied to various electronic devices that require memory, such as servers, desktop computers, notebook computers, smart phones, tablet personal computers (PCs), printers, scanners, monitors, digital cameras, digital music players, digital media recorders, and portable game consoles, but is not limited thereto.

[0030] The host 100 may provide data DATA and a request REQ to the memory controller 200. For example, the host 100 may provide a request REQ, such as a read request or a write request for the data DATA, to the memory controller 200. In addition, the host 100 may provide commands, addresses, priority information, etc. to the memory controller 200, but is not limited thereto. The host 100 and the memory controller 200 may exchange data and signals with each other based on at least one of various interface protocols, such as a Universal Serial Bus (USB) protocol, a Multimedia Card (MMC) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, and an Integrated Drive Electronic (IDE) protocol. The host 100 may be implemented as a system on chip (SoC) or an application processor, including a central processing unit (CPU) and / or a graphic processing unit (GPU) together with the memory controller 200 .

[0031] The memory controller 200 may control the memory device 300 in response to a request REQ of the host 100. For example, the memory controller 200 may control the memory device 300 so that the memory device 300 writes data DATA in response to a write request received from the host 100, or reads data DATA in response to a read request received from the host 100. To this end, the memory controller 200 may provide a command CMD and an address ADDR to the memory device 300, and data DQ to be written and data DQ to be read may be exchanged between the memory controller 200 and the memory device 300. In an embodiment, the memory controller 200 provides an arithmetic control signal CTRL_Ari to the memory device 300 so that the memory device 300 performs an arithmetic operation. In an embodiment, the memory controller 200 provides a control signal for controlling a write operation and / or a read operation to the memory device 300, and the memory controller 200 provides the arithmetic control signal CTRL_Ari to the memory device 300 through a line (e.g., a conductive signal line) through which the control signal is transmitted.

[0032] The memory device 300 includes at least one memory bank 310 and an arithmetic circuit 370. The at least one memory bank 310 may include a memory cell array and may include a plurality of memory cells. For example, the at least one memory bank 310 may include a plurality of memory cells arranged in an area where a plurality of word lines and a plurality of bit lines intersect each other. The plurality of memory cells included in the memory bank 310 may be addressed by an address ADDR, and the address ADDR may include a plurality of bits for addressing the plurality of memory cells.

[0033] In an embodiment, the memory device 300 may be implemented as a volatile memory device. The volatile memory device may be implemented as a random access memory (Random Access Memory, RAM), a dynamic RAM (Dynamic DRAM) or a static RAM (Static SRAM), but is not limited thereto. For example, the memory device 300 may correspond to a double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM), a low power double data rate (Low Power Double Data Rate, LPDDR) SDRAM, a graphics double data rate (Graphics Double Data Rate, GDDR) SDRAM or a memory bus dynamic random access memory (Rambus Dynamic Random Access Memory, RDRAM). Optionally, the memory device 300 may be implemented as a high bandwidth memory (High Bandwidth Memory, HBM). On the other hand, in an embodiment, the memory device 300 may be implemented as a non-volatile memory device. As an example, the memory device 300 may be implemented as a resistive memory, such as a phase change RAM (Phase change RAM, PRAM), a magnetic RAM (Magnetic RAM, MRAM), or a resistive RAM (Resistive RAM, RRAM).

[0034] According to an exemplary embodiment of the inventive concept, the memory device 300 includes an arithmetic circuit 370. The arithmetic circuit 370 may perform an arithmetic operation by using a plurality of operands. In an embodiment, the arithmetic circuit 370 performs an arithmetic operation based on an internal arithmetic control signal iCTRL_Ari generated in the memory device 300. In an embodiment, at least some of the plurality of operands are data stored in at least one memory bank 310. For example, the arithmetic circuit 370 may perform an arithmetic operation by using a first operand and a second operand, and at least one of the first operand and the second operand may be data stored in the memory bank 310. The arithmetic circuit 370 may generate calculated data by performing an arithmetic operation using a plurality of operands. The calculated data generated by the arithmetic circuit 370 may be provided to the memory controller 200 through a path including a data input / output buffer.

[0035] In an embodiment, the internal arithmetic control signal iCTRL_Ari includes an internal read signal and an internal write signal. In an exemplary embodiment, when the internal read signal is generated, the memory device 300 sends the operand from the memory bank 310 to the arithmetic circuit 370 through a path including a sense amplifier. Therefore, a series of processes for sending the operand from the memory bank 310 to the arithmetic circuit 370 can be referred to as an internal read operation. In an exemplary embodiment, when the internal write signal is generated, the memory device 300 sends the operand provided from the outside of the memory device 300 (e.g., from the memory controller 200) to the arithmetic circuit 370 through a path including a data input / output buffer. Therefore, a series of processes for sending the operand from the outside of the memory device 300 to the arithmetic circuit 370 can be referred to as an internal write operation. Furthermore, in an embodiment, the internal arithmetic control signal iCTRL_Ari also includes at least one of an arithmetic operation start signal (start signal) for starting an arithmetic operation of the arithmetic circuit 370, an arithmetic initialization signal for initializing the arithmetic circuit 370, and an output signal for controlling the arithmetic circuit 370 to output calculated data. Fig.11 The internal arithmetic control signal iCTRL_Ari is described in more detail.

[0036] In an embodiment, arithmetic circuit 370 performs all or some of the convolution operations. For example, memory controller 200 may be configured to perform convolution operations, but may also offload some or all of these convolution operations to arithmetic circuit 370. Figures 2 to 4B As described above, the neural network system can perform convolution operations, and the arithmetic circuit 370 included in the memory device 300 can perform all or some of the convolution operations. To this end, the arithmetic circuit 370 may include a multiplication and accumulation circuit for performing multiplication and addition operations, which will be referred to in detail. Figure 7 and Figure 8 In addition, in an embodiment, the arithmetic circuit 370 includes multiplication and accumulation circuits connected in a ring form, which will be referred to as Fig. 9 In addition, in an exemplary embodiment of the present invention, the arithmetic circuit 370 further includes a nonlinear function processor and a quantizer, which will be referred to in detail. Fig.10 Describe in more detail.

[0037] In the embodiment, the arithmetic circuit 370 is arranged in the region where the input / output sense amplifier is arranged. In other words, the arithmetic circuit 370 can receive the signal amplified by the input / output sense amplifier as an operand from the input / output sense amplifier. Figure 6An embodiment in which the arithmetic circuit 370 is arranged in an area where the input / output sense amplifier is arranged is described in more detail. However, the inventive concept is not limited thereto, and the arithmetic circuit 370 may be arranged in an area where the bit line sense amplifier is arranged. In other words, the arithmetic circuit 370 may receive a signal amplified by the bit line sense amplifier as an operand from the bit line sense amplifier. Fig.16 An embodiment in which the arithmetic circuit 370 is arranged in a region where the bit line sense amplifier is located is described in more detail.

[0038] In the data processing system 10 according to the exemplary embodiment of the inventive concept, since the arithmetic circuit 370 of the memory device 300 performs an arithmetic operation on the operand based on the internal arithmetic control signal iCTRL_Ari generated in the memory device 300 and transmits the calculated data to the memory controller 200, the amount of data exchanged between the memory controller 200 and the memory device 300 can be reduced. Therefore, the time for transmitting data from the memory device 300 to the memory controller 200 can also be reduced, and thus the data transmission overhead of the data processing system 10 can be reduced. In addition, since the amount of data exchanged between the memory controller 200 and the memory device 300 is reduced, the power efficiency of the data processing system 10 can be improved.

[0039] Figure 2 A neural network system 20 according to an exemplary embodiment of the inventive concept is shown. The neural network system 20 includes a neural network processor 400 and a memory device 300, and the neural network processor 400 includes a processor 100 and a memory controller 200. In an embodiment, the neural network processor 400 or the processor 100 is a microprocessor that is specialized in accelerating a machine learning algorithm such as an artificial neural network. Figure 2 ,and Figure 1 compared to, Figure 2 The processor 100 may correspond to Figure 1 The host 100, and Figure 2 The memory controller 200 and the memory device 300 may correspond to Figure 1 For the sake of simplicity, the memory controller 200 and the memory device 300 are omitted. Figure 2 Relative to Figure 1 Redundant description of .

[0040] The neural network processor 400 can generate a neural network, train or learn a neural network, or perform an arithmetic operation based on the received input data, and can generate an information signal or retrain the neural network based on the result of performing the arithmetic operation. The model of the neural network may include various types of models, such as a convolutional neural network (CNN), a region with a convolutional neural network (RNN), a region proposal network (RPN), a recurrent neural network (RNN), a stacked deep neural network (S-DNN), a state-space dynamic neural network (S-SDNN), a deconvolution network, a deep belief network (DBN), a restricted Boltzmann machine (RBM), a fully convolutional network, a long short-term memory (LSTM) network, and a classification network (such as GoogleNet, AlexNet, and VGG network), but is not limited thereto. The processor 100 may perform operations according to the model of the neural network. In addition, the neural network processor 400 may include a separate memory for storing a program corresponding to a model of a neural network. The neural network processor 400 may be additionally referred to as a neural network processing device or a neural network processing unit (NPU).

[0041] The neural network processor 400 can perform a convolution operation by using the input feature map and the kernel, as shown in FIG. Figures 3 to 4B The data included in the input feature map will be referred to as input feature data, and the data included in the kernel will be referred to as kernel data.

[0042] When performing a convolution operation, a general neural network system receives both input feature data and kernel data from a memory device. Therefore, in a general neural network system, as the number of convolution operations and / or the amount of data increases, the amount of data exchanged between the neural network processor and the memory device may also increase. Therefore, a general neural network system has limitations in terms of increased data transmission overhead and increased power consumption.

[0043] In the neural network system 20 according to an exemplary embodiment of the inventive concept, since the arithmetic circuit 370 of the memory device 300 performs all or some of the convolution operations by using the input feature data and the kernel data based on the internal arithmetic control signal iCTRL_Ari generated in the memory device 300, and transmits the calculated data to the memory controller 200, the amount of data exchanged between the memory controller 200 and the memory device 300 can be reduced. For example, instead of transmitting the input feature data and / or the kernel data from the memory device 300 to the neural network processor 400 for processing by the neural network processor 400, some or all of the convolution operations that would otherwise be performed by the neural network processor 400 can be offloaded to the arithmetic circuit 370 of the memory device 300. Therefore, the time for transmitting data from the memory device 300 to the memory controller 200 can also be reduced, and thus the data transmission overhead of the neural network system 20 can be reduced. In addition, since the amount of data exchanged between the neural network processor 400 and the memory device 300 is reduced, the power efficiency of the neural network system 20 can be improved.

[0044] Figure 3 The structure of a convolutional neural network is shown as an example of a neural network structure. The neural network NN (NeuralNetwork) may include a plurality of layers L1 to Ln. Each of the plurality of layers L1 to Ln may be a linear layer or a nonlinear layer. In an embodiment, at least one linear layer and at least one nonlinear layer are combined and referred to as one layer. For example, a linear layer may include a convolutional layer and a fully connected layer, and a nonlinear layer may include a pooling layer and an activation layer.

[0045] For example, the first layer L1 may be a convolutional layer, the second layer L2 may be a pooling layer, and the nth layer Ln may be a fully connected layer as an output layer. The neural network NN may also include activation layers, and may also include layers for performing other types of operations.

[0046] Each of the multiple layers L1 to Ln can receive input data (e.g., image data of an image frame or a frame of a display panel) or a feature map generated in the previous layer as an input feature map, and generate an output feature map or a recognition signal REC by operating the input feature map. In this case, the feature map may mean data representing various features of the input data. The feature maps FM1, FM2, and FMn may have the form of, for example, a two-dimensional (2D) matrix or a three-dimensional (3D) matrix (or tensor). The feature maps FM1, FM2, and FMn may have a width W (or column), a height H (or row), and a depth D, which may correspond to the x-axis, y-axis, and z-axis on the coordinates, respectively. In this case, the depth D may be referred to as the number of channels.

[0047] The first layer L1 can generate a second feature map FM2 by convolving (winding) the first feature map FM1 with the weight map WM. The weight map WM can filter the first feature map FM1 and can also be referred to as a filter or a kernel. In an embodiment, the depth of the weight map WM, that is, the number of channels, is equal to the depth of the first feature map FM1, that is, the number of channels, and the same channels of the weight map WM and the first feature map FM1 are convolved (winded) with each other. The weight map WM can be moved as a sliding window in such a way that the first feature map FM1 is traversed. The amount of movement can be referred to as a "stride length" or "stride". In an exemplary embodiment, during each movement, each of the weight values ​​included in the weight map WM is multiplied and added with all feature data in the overlapping area with the first feature map FM1. The data of the first feature map FM1 in the area where each of the weight values ​​included in the weight map WM overlaps with the first feature map FM1 can be referred to as extracted data. Since the first feature map FM1 and the weight map WM are convolved together, one channel of the second feature map FM2 is generated. Although in Figure 3 One weight map WM is shown in FIG, but multiple weight maps may be convolved with the first feature map FM1 to generate multiple channels of the second feature map FM2. In other words, the number of channels of the second feature map FM2 may correspond to the number of weight maps.

[0048] In an exemplary embodiment, the second layer L2 generates a third feature map FM3 by changing the spatial size of the second feature map FM2 by pooling. Pooling can be referred to as sampling or downsampling. The 2D pooling window PW can be moved on the second feature map FM2 in units of the size of the pooling window PW, and the maximum value (or the average value of the feature data) of the feature data in the area overlapping with the pooling window PW can be selected. Therefore, the third feature map FM3 with the changed spatial size can be generated from the second feature map FM2. In an exemplary embodiment, the number of channels of the third feature map FM3 and the number of channels of the second feature map FM2 are equal to each other.

[0049] The nth layer Ln can classify the category CL of the input data by combining the features of the nth feature map FMn. In addition, the nth layer Ln can generate a recognition signal REC corresponding to the category CL. In an embodiment, the input data corresponds to frame data included in a video stream, and by extracting a category CL corresponding to an object included in an image represented by the frame data based on the nth feature map FMn provided from the previous layer, the nth layer Ln can recognize the object and generate a recognition signal REC corresponding to the recognized object.

[0050] Figure 4A and Figure 4B is a diagram illustrating a convolution operation of a neural network.

[0051] refer to Figure 4A , the input feature map 401 may include D channels, and the input feature map of each channel may have a size of H rows and W columns (D, H, and W are natural numbers). Each of the kernels 402 may have a size of R rows and S columns, and the kernel 402 may include a plurality of channels corresponding to the number of channels (or depth) D of the input feature map 401 (R and S are natural numbers). The output feature map 403 may be generated by a 3D convolution operation between the input feature map 401 and the kernel 402, and may include Y channels according to the convolution operation.

[0052] You can refer to Figure 4B Describes a process of generating an output feature map by a convolution operation between an input feature map and a kernel, and can be performed by performing a convolution operation between the input feature map 401 of all channels and the kernel 402 of all channels, Figure 4B The 2D convolution operation shown is used to generate the output feature map 403 of all channels.

[0053] refer to Figure 4B, for convenience of description, it is assumed that the input feature map 410 has a size of 6x6, the original kernel 420 has a size of 3x3, and the output feature map 430 has a size of 4x4; however, the inventive concept is not limited thereto, and the neural network can be implemented by feature maps and kernels of various sizes. In addition, the values ​​defined in the input feature map 410, the original kernel 420, and the output feature map 430 are merely example values, and embodiments according to the inventive concept are not limited thereto.

[0054] The original kernel 420 may perform a convolution operation while sliding in the input feature map 410 in units of a 3x3 window. The convolution operation may represent an operation for obtaining each feature data of the output feature map 430 by summing all values ​​obtained by multiplying each feature data of the window of the input feature map 410 and each of the weight values ​​of the corresponding positions in the original kernel 420. The data included in the window of the input feature map 410 may be referred to as extracted data extracted from the input feature map 410. Specifically, the original kernel 420 may first perform a convolution operation with the first extracted data 411 of the input feature map 410. That is, the respective feature data 1, 2, 3, 4, 5, 6, 7, 8, and 9 of the first extracted data 411 may be multiplied by the corresponding weight values ​​-1, -3, 4, 7, -2, -1, -5, 3, and 1 of the original kernel 420, respectively, and -1, -6, 12, 28, -10, -6, -35, 24, and 9 may be obtained as the result thereof. Next, "15" may be obtained as a result of adding all the obtained values ​​-1, -6, 12, 28, -10, -6, -35, 24, and 9, and the feature data 431 of the first row and the first column of the output feature map 430 may be determined as "15". Here, the feature data 431 in the first row and the first column of the output feature map 430 may correspond to the first extracted data 411. Similarly, by performing a convolution operation between the original kernel 420 and the second extracted data 412 of the input feature map 410, the feature data 432 of the first row and the second column of the output feature map 430 may be determined as "4". Finally, by performing a convolution operation between the original kernel 420 and the 16th extracted data 413 (i.e., the last extracted data) of the input feature map 410, the feature data 433 of the fourth row and the fourth column of the output feature map 430 may be determined as "11".

[0055] In other words, a convolution operation between an input feature map 410 and an original kernel 420 can be processed by repeatedly performing multiplication of the extracted data of the input feature map 410 and the corresponding weight values ​​of the original kernel 420 and summing the multiplication results, and an output feature map 430 can be generated as a result of the convolution operation.

[0056] Figure 5A memory device 300 according to an exemplary embodiment of the inventive concept is shown. The memory device 300 includes a memory bank 310, a row decoder 320 (e.g., a decoder circuit), a column decoder 330 (e.g., a decoder circuit), and a peripheral circuit 340. The peripheral circuit 340 includes an input / output sense amplifier 350, a control logic 360 (e.g., a logic circuit), and an arithmetic circuit 370. For ease of description, Figure 5 3 shows a case where the memory device 300 includes one memory bank 310; however, the number of memory banks is not limited thereto. For example, the memory device 300 may include a plurality of memory banks. For the sake of simplicity, the description of Figure 5 Relative to Figure 1 A redundant description of the memory device 300 is provided.

[0057] The memory bank 310 may include a plurality of memory cells arranged in a region where a plurality of word lines WL and a plurality of bit lines BL intersect each other. In an embodiment, each of the plurality of memory cells is a DRAM cell including a transistor and a capacitor. The memory bank 310 may be driven by a row decoder 320 and a column decoder 330.

[0058] The row decoder 320 may select at least one word line among the word lines WL under the control of the peripheral circuit 340. The row decoder 320 may receive an input of a row decoder control signal ROW_CTRL and a row address ROW_ADDR from the peripheral circuit 340. The row decoder control signal ROW_CTRL and the row address ROW_ADDR may be determined by the peripheral circuit 340 based on the Figure 1 The command CMD and address ADDR provided by the memory controller 200 located outside the memory device 300 are generated. For example, when the activation command and the word line address to be activated are input to the memory device 300, the peripheral circuit 340 can activate the row decoder control signal ROW_CTRL and generate the row address ROW_ADDR. The row decoder 320 can select at least one word line based on the row decoder control signal ROW_CTRL and the row address ROW_ADDR. A group of memory cells connected to the selected word line can be considered as a selected page.

[0059] The column decoder 330 may select at least one bit line among the bit lines BL under the control of the peripheral circuit 340. The bit line selected by the column decoder 330 may be connected to the global input / output line GIO. The column decoder 330 may receive an input of a column decoder control signal COL_CTRL and a column address COL_ADDR from the peripheral circuit 340. For example, after the activation command, a write command or a read command may be input to the memory device 300 to store data in a selected page or read data from a selected page. The peripheral circuit 340 may activate the column decoder control signal COL_CTRL and generate a column address COL_ADDR.

[0060] The peripheral circuit 340 may receive input of a command CMD and an address ADDR from a memory controller 200 located outside the memory device 300. The peripheral circuit 340 may generate a row decoder control signal ROW_CTRL, a row address ROW_ADDR, a column decoder control signal COL_CTRL, and a column address COL_ADDR based on the command CMD and the address ADDR. The peripheral circuit 340 may provide the row decoder control signal ROW_CTRL and the row address ROW_ADDR to the row decoder 320, and provide the column decoder control signal COL_CTRL and the column address COL_ADDR to the column decoder 330. The peripheral circuit 340 may exchange data DQ with the outside of the memory device 300. For example, the peripheral circuit 340 may exchange data DQ with the outside through a data input / output pad of the memory device 300.

[0061] The peripheral circuit 340 may include an input / output sense amplifier 350 , a control logic 360 , and an arithmetic circuit 370 .

[0062] The input / output sense amplifier 350 may be connected to a global input / output line GIO connected to a bit line BL selected by the column decoder 330. The input / output sense amplifier 350 may amplify a signal transmitted from the memory bank 310 through the global input / output line GIO.

[0063] The control logic 360 may control the overall operation of the memory device 300. In an embodiment, the control logic 360 includes a command decoder (e.g., a decoder circuit), and may internally generate a decoded command signal by decoding command (CMD) related signals such as a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and a clock enable signal CKE. In an embodiment, the control logic 360 generates an internal arithmetic control signal iCTRL_Ari based on an arithmetic control signal CTRL_Ari provided by a memory controller 200 located outside the memory device 300. The control logic 360 may provide the internal arithmetic control signal iCTRL_Ari to the arithmetic circuit 370.

[0064] In an embodiment, the control logic 360 controls the memory device 300 in an operation in which the first operand OP1 and / or the second operand OP2 are stored in the memory bank 310. For example, it is assumed that the first operand OP1 is stored in the memory bank 310. The control logic 360 may control the first operand OP1 to be stored in the memory bank 310 by configuring an address of the memory bank 310 to store the first operand OP1 so that the first operand OP1 may be sequentially input to the arithmetic circuit 370.

[0065] The arithmetic circuit 370 may perform an arithmetic operation by using the first operand OP1 and the second operand OP2 based on the internal arithmetic control signal iCTRL_Ari provided by the control logic 360. At least one of the first operand OP1 and the second operand OP2 may be obtained from the memory bank 310 through a path including the input / output sense amplifier 350. For example, the arithmetic circuit 370 may obtain both the first operand OP1 and the second operand OP2 from the memory bank 310. In addition, for example, the arithmetic circuit 370 may obtain any one of the first operand OP1 and the second operand OP2 from the memory bank 310, and obtain the other of the first operand OP1 and the second operand OP2 from the outside of the memory device 300. The arithmetic circuit 370 may generate calculated data Data_cal by performing an arithmetic operation using the first operand OP1 and the second operand OP2, and output the calculated data Data_cal to the outside of the memory device 300. For example, the arithmetic circuit 370 may multiply the first operand OP1 by the second operand OP2 to generate first multiplication data, add the first multiplication data to the second multiplication data, etc. In an embodiment, the arithmetic operation may include all or some of the convolution operations, where the first operand OP1 is input feature data included in the input feature map, and the second operand OP2 is kernel data included in the kernel.

[0066] According to an embodiment, the arithmetic circuit 370 may be implemented in various forms in the memory device 300, and the arithmetic circuit 370 may be implemented in a hardware form or a software form. For example, when the arithmetic circuit 370 is implemented in a hardware form, the arithmetic circuit 370 may include a circuit for performing an arithmetic operation. In addition, for example, when the arithmetic circuit 370 is implemented in a software form, the arithmetic operation may be performed by the control logic 360 or at least one processor in the memory device 300 by running a random input / output code and / or a program (or instruction) stored in the memory device 300. However, the inventive concept is not limited to the above embodiments, and the arithmetic circuit 370 may be implemented as a combination of software and hardware, such as firmware.

[0067] Figure 6 1 shows a memory device 300 according to an exemplary embodiment of the inventive concept. For the sake of simplicity, the description of Figure 6 The memory device 300 is relative to Figure 5 Redundant description of .

[0068] The memory device 300 includes a memory bank 310 , a row decoder 320 , a column decoder 330 , an input / output sense amplifier 350 , and an arithmetic circuit 370 .

[0069] The memory body 310 may include a plurality of sub-memory cell arrays arranged in a matrix along the direction of a plurality of word lines WL and a plurality of bit lines BL. Each of the sub-memory cell arrays may include a plurality of memory cells. Among the plurality of word lines WL, the word line connected to the sub-memory cell array will be referred to as a sub-word line SWL, and among the plurality of bit lines BL, the bit line connected to the sub-memory cell array will be referred to as a sub-bit line SBL. The memory body 310 may include N (N is a natural number) sub-memory cell arrays in the word line direction, and may include M (M is a natural number) sub-memory cell arrays in the bit line direction.

[0070] The memory body 310 may include a plurality of bit line sense amplifiers (BLSA), a plurality of sub word line drivers (SWD), and a plurality of junctions (CJT). In an embodiment, each junction includes a power driver for driving one of the bit line sense amplifiers with a non-ground voltage and / or a ground driver for driving a bit line sense amplifier with a ground voltage. Each of the plurality of sub word line drivers may drive a sub word line connected to the sub word line driver. Each of the plurality of bit line sense amplifiers may amplify a voltage difference between a sub bit line SBL and a complementary sub bit line SBLB. In other words, the bit line sense amplifier may amplify a signal sent through the sub bit line SBL. A plurality of sub word line drivers and a plurality of bit line sense amplifiers may be repeatedly arranged between a plurality of sub memory cell arrays.

[0071] Data stored in memory cells of the memory bank 310 may be transmitted to the input / output sense amplifier 350 through the bit lines BL and the global input / output lines GIO.

[0072] In an embodiment, the arithmetic circuit 370 is arranged in a region where the input / output sense amplifier 350 is arranged. In addition, the arithmetic circuit 370 can obtain at least one of the first operand and the second operand from the memory bank 310 through a path including the input / output sense amplifier 350. For ease of description,

[0073] Figure 6 An embodiment is shown in which the arithmetic operation of the arithmetic circuit 370 is all or some of the convolution operation, the first operand is the input feature data IFD, and the second operand is the kernel data KND. In other words, based on the internal read signal included in the internal arithmetic control signal iCTRL_Ari generated in the memory device 300, the arithmetic circuit 370 obtains at least one of the input feature data IFD and the kernel data KND from the memory bank 310 through a path including the input / output sense amplifier 350. The arithmetic circuit 370 can generate the calculated data Data_cal by performing all or some of the convolution operation using the input feature data IFD and the kernel data KND. The arithmetic circuit 370 can output the calculated data Data_cal.

[0074] Figure 7 FIG. 3 shows an arithmetic circuit 370 according to an exemplary embodiment of the inventive concept. For the sake of simplicity, the description of Figure 7 The arithmetic circuit 370 is relative to Figure 1 , Figure 2 , Figure 5 and Figure 6 Redundant description of . Figure 6describe Figure 7 .

[0075] Figure 7 A case is shown in which the input feature data IFD is input from outside the memory device 300 and the kernel data KND is obtained from the memory bank 310. However, this is only for convenience of description, and the input feature data IFD may also be obtained from the memory bank 310.

[0076] The arithmetic circuit 370 includes a plurality of multiplication and accumulation circuits. For example, the arithmetic circuit 370 may include a first multiplication and accumulation circuit 372_1 to an Nth multiplication and accumulation circuit 372_N. Here, N may be equal to Figure 6 The number of sub-memory cell arrays in the word line direction in the memory body 310 of FIG. The input feature data IFD may include first input feature data IFD_1 to N-th input feature data IFD_N, and the kernel data KND may include first kernel data KND_1 to N-th kernel data KND_N. Each of the first input feature data IFD_1 to N-th input feature data IFD_N may be n-bit data (n is a natural number), and the first kernel data KND_1 to N-th kernel data KND_N may be n-bit data. As a non-limiting example, the first input feature data IFD_1 to N-th input feature data IFD_N and the first kernel data KND_1 to N-th kernel data KND_N may be 8-bit data.

[0077] The first multiplication and accumulation circuit 372_1 may generate first calculated data Data_cal_1 by performing a multiplication operation and an addition operation using the first input feature data IFD_1 and the first kernel data KND_1, and output the first calculated data Data_cal_1. For example, the first multiplication and accumulation circuit 372_1 may output the first calculated data Data_cal_1 in response to an output signal included in the internal arithmetic control signal iCTRL_Ari. As a non-limiting example, the first calculated data Data_cal_1 may be 2n-bit data or (2n+1)-bit data. As shown in FIG. Figure 4A and Figure 4B As described above, in the case of a convolution operation, the process of multiplying the input feature data and the kernel data multiple times and then summing them may be included. To this end, the first multiplication and accumulation circuit 372_1 may perform a multiplication operation and an addition operation.

[0078] Similarly, the second multiplication and accumulation circuit 372_2 can generate second calculated data Data_cal_2 by performing multiplication and addition operations using the second input feature data IFD_2 and the second kernel data KND_2, and output the second calculated data Data_cal_2. For example, the second multiplication and accumulation circuit 372_2 can output the second calculated data Data_cal_2 in response to an output signal included in the internal arithmetic control signal iCTRL_Ari.

[0079] Likewise, the Nth multiplication and accumulation circuit 372_N may generate the Nth calculated data Data_cal_N by performing multiplication and addition operations using the Nth input feature data IFD_N and the Nth kernel data KND_N, and output the Nth calculated data Data_cal_N. For example, the Nth multiplication and accumulation circuit 372_N may output the Nth calculated data Data_cal_N in response to an output signal included in the internal arithmetic control signal iCTRL_Ari.

[0080] The calculated data may include at least one of first to Nth calculated data Data_cal_1 to Data_cal_N.

[0081] Figure 8 1 shows a multiplication and accumulation circuit according to an exemplary embodiment of the present invention. For ease of description, Figure 8 Shows Figure 7 The first multiplication and accumulation circuit 372_1. Figure 7 The second multiplication and accumulation circuit 372_2 to the Nth multiplication and accumulation circuit 372_N may also include Figure 8 For the sake of simplicity, the first multiplication and accumulation circuit 372_1 relative to Figure 7 Redundant description of .

[0082] The first multiplication and accumulation circuit 372_1 includes a multiplier 373 (eg, a multiplier circuit), an adder 374 (eg, an adder circuit), and a register 375 .

[0083] The multiplier 373 may generate multiplication data Data_mul by multiplying the first input feature data IFD_1 by the first kernel data KND_1 and provide the multiplication data Data_mul to the adder 374 .

[0084] The register 375 may temporarily store the calculated data. The register 375 may provide the stored calculated data to the adder 374 as the accumulated data Data_acc.

[0085] The adder 374 may generate updated data Data_upd by adding the multiplication data Data_mul to the accumulation data Data_acc provided from the register 375. In other words, the adder 374 may update the calculated data by adding the multiplication data Data_mul to the calculated data provided by the register 375. The register 375 may output the calculated data as the first calculated data Data_cal_1 at a specific time. For example, when the output signal is input to the arithmetic circuit 370, the register 375 may output the first calculated data Data_cal_1.

[0086] In this way, the first multiplication and accumulation circuit 372_1 may perform a multiplication operation by using the multiplier 373 , and may accumulate data by using the adder 374 and the register 375 .

[0087] Fig. 9 FIG. 3 shows an arithmetic circuit 370 according to an exemplary embodiment of the inventive concept. Figure 7 compared to, Fig. 9 An embodiment is shown in which a plurality of multiplication and accumulation circuits are connected in a ring form. In the embodiment, although Fig. 9 Not shown, but the adder 374_1 of the first multiplication and accumulation circuit 372_1 also receives data from the register 375_N of the Nth multiplication and accumulation circuit 372_N.

[0088] The multiplier 373_1 of the first multiplication and accumulation circuit 372_1 can multiply the first input feature data IFD_1 by the first kernel data KND_1 to generate first multiplication data, the adder 374_1 of the first multiplication and accumulation circuit 372_1 can add the first multiplication data with a given initial value or data provided from the register 375_N of the Nth multiplication and accumulation circuit 372_N to generate a first result value, and the register 375_1 can temporarily store the first result value and then provide it to the adder 374_2 of the second multiplication and accumulation circuit 372_2.

[0089] The multiplier 373_2 of the second multiplication and accumulation circuit 372_2 can multiply the second input feature data IFD_2 by the second kernel data KND_2 to generate second multiplication data, the adder 374_2 of the second multiplication and accumulation circuit 372_2 can add the second multiplication data with the data provided from the register 375_1 of the first multiplication and accumulation circuit 372_1 to generate a second result value, and the register 375_2 can temporarily store the second result value and then provide it to the adder of the third multiplication and accumulation circuit.

[0090] In the case of a convolution operation, it may include an operation of multiplying a plurality of input feature data and a plurality of kernel data and then summing them. Therefore, since the arithmetic circuit 370 has a structure in which a plurality of multiplication and accumulation circuits are connected in a ring form, the second multiplication and accumulation circuit 372_2 may use the result calculated by the first multiplication and accumulation circuit 372_1, and the third multiplication and accumulation circuit may use the result calculated by the second multiplication and accumulation circuit 372_2 to perform an arithmetic operation.

[0091] The registers 375_1 to 375_N may output calculated data Data_cal at a specific time. For example, when an output signal is input to the arithmetic circuit 370, the registers 375_1 to 375_N may output calculated data Data_cal. The calculated data Data_cal may include at least one of first to Nth calculated data Data_cal_1 to Data_cal_N.

[0092] Fig.10 FIG. 3 shows an arithmetic circuit 370 according to an exemplary embodiment of the inventive concept. Figure 7 compared to, Fig.10 An embodiment is shown in which the arithmetic circuit 370 further includes a plurality of nonlinear function processors 376_1 to 376_N, a plurality of quantizers 377_1 to 377_N, and a plurality of buffer memories 378_1 to 378_N.

[0093] The first nonlinear function processor 376_1 operates a nonlinear function on the data multiplied and accumulated by the first multiplication and accumulation circuit 372_1. For example, the nonlinear function may include functions such as a sigmoid function, a hyperbolic tangent function, and a rectified linear unit function (Rectified Linear Unit function, ReLU). The first nonlinear function processor 376_1 may provide the nonlinear function-processed data to the first quantizer 377_1 by operating a nonlinear function on the data provided by the first multiplication and accumulation circuit 372_1.

[0094] The data input to the first quantizer 377_1 may be 2n-bit data or (2n+1)-bit data. The first quantizer 377_1 may quantize the 2n-bit data with n-bit data. In an exemplary embodiment, the first quantizer 377_1 performs a truncation or rounding operation on the data it receives. In an exemplary embodiment, the first quantizer 377_1 converts the 2n-bit data into n-bit data using a truncation or rounding operation.

[0095] The data quantized by the first quantizer 377_1 may be temporarily stored in the first buffer memory 378_1 and sequentially output as first calculation data Data_cal_1.

[0096] The second nonlinear function processor 376_2 to the Nth nonlinear function processor 376_N can be understood as operating similarly to the first nonlinear function processor 376_1, the second quantizer 377_2 to the Nth quantizer 377_N can be understood as operating similarly to the first quantizer 377_1, and the second buffer memory 378_2 to the Nth buffer memory 378_N can be understood as operating similarly to the first buffer memory 378_1.

[0097] The calculated data Data_cal output by the arithmetic circuit 370 may include at least one of first to Nth calculated data Data_cal_1 to Data_cal_N.

[0098] Fig.11 1 shows an arithmetic circuit 370 and an internal arithmetic control signal iCTRL_Ari according to an exemplary embodiment of the inventive concept. Figure 5 describe Fig.11 .

[0099] The internal arithmetic control signal iCTRL_Ari may be generated in the memory device 300. For example, the internal arithmetic control signal iCTRL_Ari may be generated by the control logic 360 of the memory device 300. In an embodiment, the control logic 360 generates the internal arithmetic control signal iCTRL_Ari based on the arithmetic control signal CTRL_Ari provided by the memory controller 200 located outside the memory device 300.

[0100] In an exemplary embodiment, the internal arithmetic control signal iCTRL_Ari includes an internal read signal iRD and an internal write signal iWR. In an exemplary embodiment, the internal arithmetic control signal iCTRL_Ari includes at least one of an arithmetic operation start signal iOP, an arithmetic initialization signal iRST, and an output signal OUT.

[0101] In an exemplary embodiment, when the internal read signal iRD is received by the arithmetic circuit 370, the memory device 300 transmits an operand used in an arithmetic operation of the arithmetic circuit 370 from the memory bank 310 to the arithmetic circuit 370 through a path including the input / output sense amplifier 350. In other words, the memory device 300 reads the operand from the memory bank 310 to the arithmetic circuit 370 based on the internal read signal iRD. Unlike a general read operation in which data stored in a memory cell is transmitted to the outside of the memory device 300 through a data input / output buffer, in the internal read operation, the data stored in the memory cell is read only to the arithmetic circuit 370.

[0102] In an exemplary embodiment, when the internal write signal iWR is received by the arithmetic circuit 370, the memory device 300 transmits operands used in arithmetic operations of the arithmetic circuit 370 from outside the memory device 300 to the arithmetic circuit 370 through a path including a data input / output buffer. In other words, the memory device 300 writes operands from outside the memory device 300 to the arithmetic circuit 370 based on the internal write signal iWR. Unlike a general write operation in which external data is transmitted to a memory cell, in the internal write operation, the external data is only written to the arithmetic circuit 370.

[0103] In an exemplary embodiment, when the arithmetic operation start signal iOP is received by the arithmetic circuit 370, the arithmetic circuit 370 starts the execution of the arithmetic operation by using a plurality of operands. For example, the arithmetic circuit 370 may start all or some of the convolution operations performed on the input feature data and the kernel data based on the arithmetic operation start signal iOP.

[0104] In an exemplary embodiment, the arithmetic circuit 370 is initialized when the arithmetic initialization signal iRST is received by the arithmetic circuit 370. For example, temporary data stored in a register included in the arithmetic circuit 370 may be erased based on the arithmetic initialization signal iRST.

[0105] In an exemplary embodiment, when the output signal OUT is received by the arithmetic circuit 370, the arithmetic circuit 370 outputs the calculated data Data_cal. In other words, the output signal OUT may control the arithmetic circuit 370 to output the calculated data Data_cal.

[0106] As described above, in order for the arithmetic circuit 370 to perform an arithmetic operation by using operands, the memory device 300 may generate the internal arithmetic control signal iCTRL_Ari.

[0107] Fig.121 shows a configuration of a memory device 300 for describing an internal read operation according to an exemplary embodiment of the inventive concept. The memory device 300 includes a memory bank 310, a column decoder 330, an input / output sense amplifier 350, and an arithmetic circuit 370. For the sake of simplicity, the description of the memory device 300 relative to the reference will be omitted. Figures 1 to 12 Redundant description of the description. Figure 5 describe Fig.12 .

[0108] The control logic 360 may generate an internal read signal iRD based on an arithmetic control signal CTRL_Ari received from the outside.

[0109] When the arithmetic circuit 370 receives the internal read signal iRD, the memory device 300 reads the operand OP from the memory bank 310 to the arithmetic circuit 370 through the path including the input / output sense amplifier 350. In other words, the transmission path of the operand OP may be the same as the first path 301. In other words, according to the internal read operation, data is not transmitted to the outside of the memory device 300.

[0110] Fig.13 1 shows a configuration of a memory device 300 for describing an internal write operation according to an exemplary embodiment of the inventive concept. The memory device 300 includes an arithmetic circuit 370, a data input / output buffer 380, and a data input / output pad 390. For the sake of simplicity, the description of the memory device 300 relative to the reference will be omitted. Figures 1 to 12 Redundant description of the description. Figure 5 describe Fig.13 .

[0111] The control logic 360 generates an internal write signal iWR based on the arithmetic control signal CTRL_Ari received from the outside.

[0112] When the arithmetic circuit 370 receives the internal write signal iWR, the memory device 300 transmits the operand OP from outside the memory device 300 to the arithmetic circuit 370 through a path including the data input / output pad 390 and the data input / output buffer 380. In other words, the transmission path of the operand OP may be the same as the second path 302. In other words, according to the internal write operation, data is not transmitted to the memory cell of the memory device 300.

[0113] Fig.14 An internal arithmetic control signal iCTRL_Ari according to an exemplary embodiment of the inventive concept is shown. The internal arithmetic control signal iCTRL_Ari may include an internal read signal iRD, an internal write signal iWR, and an arithmetic operation start signal iOP.

[0114] In an embodiment, two or more of the internal read signal iRD, the internal write signal iWR, and the arithmetic operation start signal iOP are generated simultaneously.

[0115] Because as a basis Fig.12 The first path 301 of the transfer path of the internal read signal iRD in the internal read operation of the data and the Fig.13 The second paths 302 of the data transfer paths in the internal write operation of the internal write signal iWR do not overlap with each other, so unlike general read commands and write commands, the internal read signal iRD and the internal write signal iWR can be generated at the same time.

[0116] In an embodiment, Fig.12 In the embodiment, when the internal read signal iRD, the internal write signal iWR, and the arithmetic operation start signal iOP are activated at the same time, the arithmetic circuit can perform the arithmetic operation in a shorter time.

[0117] Fig.15 1 shows a memory device 300 according to an exemplary embodiment of the inventive concept. For the sake of simplicity, the description of Fig.15 The memory device 300 is relative to Figure 1 , Figure 2 and Figure 5 Redundant description of Figure 6 to describe the difference Fig.15 .

[0118] The arithmetic circuit may be arranged in an area where the bit line sense amplifier (BLSA) is arranged. In other words, the memory device 300 may include a plurality of arithmetic circuits, and the plurality of arithmetic circuits may be included in the memory bank 310 and may be repeatedly arranged between a plurality of sub-memory cell arrays. The plurality of arithmetic circuits may receive a signal amplified by the bit line sense amplifier as an operand and perform an arithmetic operation by using the operand.

[0119] When an arithmetic circuit is arranged in a region where a bit line sense amplifier is arranged to perform an arithmetic operation, the operation speed of the memory device 300 can be further improved.

[0120] Fig.16 2 shows a structure of a memory device 300 according to an exemplary embodiment of the inventive concept. In an embodiment, Fig.16The structure of the memory device 300 implemented as an MRAM may be represented. The memory device 300 includes first to fourth memory banks 310_1 to 310_4, first row decoders 320_1 to fourth row decoders 320_4, first column decoders 330_1 to fourth column decoders 330_4, and an arithmetic circuit 370. In addition, the memory device 300 may include a peripheral region where peripheral circuits are arranged and a data input / output buffer region where a data input / output buffer is located. The number of memory banks, the number of row decoders, the number of column decoders, and their detailed arrangement configurations are merely examples and are not limited thereto. Fig.16 structure.

[0121] In an exemplary embodiment, at least some of the memory cells included in the first to fourth memory banks 310_1 to 310_4 are implemented as MRAMs.

[0122] The arithmetic circuit 370 may be arranged in the data input / output buffer area. The arithmetic circuit 370 may be electrically connected to the first column decoder 330_1 to the fourth column decoder 330_4 to obtain operands required for arithmetic operations from the first memory bank 310_1 to the fourth memory bank 310_4, and may perform arithmetic operations by using the operands. For example, the arithmetic circuit 370 may perform all or some of the convolution operations by using the input feature data and the kernel data. To this end, the arithmetic circuit 370 may include a plurality of multiplication and accumulation circuits. In addition, in an embodiment, the plurality of multiplication and accumulation circuits included in the arithmetic circuit 370 may be arranged in a matrix form.

[0123] Because the arithmetic circuit 370 performs all or some of the convolution operations, the amount of data transmitted / received by the memory device 300 may be reduced.

[0124] Fig.17 An electronic system 1000 according to an exemplary embodiment of the inventive concept is shown. The electronic system 1000 includes a neural network processing unit 1100, a random access memory (RAM) 1200, a processor 1300, a memory 1400, and a sensor module 1500. The neural network processing unit 1100 may correspond to Figure 2 The neural network processor 400, and the RAM 1200 may correspond to Figure 2 A memory device 300 is provided.

[0125] The electronic system 1000 can be applied to a drone, a robotic device (such as an Advanced Driver Assistance System (ADAS)), a smart TV, a smart phone, a medical device, a mobile device, an image display device, a measuring device, or an Internet of Things (IoT) device, and can also be installed on one of various other types of electronic devices.

[0126] The technology for connecting the components included in the electronic system 1000 may include a connection method based on the system bus. For example, the Advanced Microcontroller Bus Architecture (AMBA) protocol of Advanced RISC Machine (ARM) can be applied as the standard of the system bus. The bus types of the AMBA protocol may include Advanced High-Performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI), AXI4 and AXI Coherency Extensions (ACE). In the above bus types, AXI can be an interface protocol between IPs, and multiple outstanding address functions and data interleaving functions can be provided. In addition, other types of protocols such as SONICs' uNetwork, IBM's CoreConnect and OCP-IP's Open Core Protocol can also be applied to the system bus.

[0127] The RAM 1200 may temporarily store programs, data, or commands (instructions). For example, the programs and / or data stored in the memory 1400 may be temporarily loaded into the RAM 1200 according to the control of the boot code or the processor 1300. The RAM 1200 may be implemented by using a memory such as a dynamic RAM (DRAM) or a static RAM (SRAM).

[0128] The processor 1300 may control the overall operation of the electronic system 1000, and as an example, the processor 1300 may be a central processing unit (CPU). The processor 1300 may include a processor core or may include a plurality of processor cores (multi-core). The processor 1300 may process or run programs and / or data stored in the RAM 1200 and the memory 1400. For example, the processor 1300 may control the functions of the electronic system 1000 by running a program stored in the memory 1400.

[0129] The memory 1400 may be a storage device for storing data, and may store, for example, an operating system (OS), various programs, and various data. The memory 1400 may be a DRAM, but is not limited thereto. The memory 1400 may include at least one of a volatile memory or a non-volatile memory. The non-volatile memory may include, for example, a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and / or a ferroelectric RAM (Ferroelectric RAM, FRAM). The volatile memory may include, for example, a dynamic RAM (DRAM), a static RAM (SRAM), a synchronous DRAM (SDRAM), a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and / or a ferroelectric RAM (Ferroelectric RAM, FeRAM). In addition, in an embodiment, the memory 1400 may include at least one of a hard disk drive (HDD), a solid state drive (SSD), a compact flash (CF), a secure digital (SD), a micro secure digital (Micro-SD), a mini secure digital (Mini SecureDigital, Mini-SD), an extreme digital (xD), and a memory stick.

[0130] The sensor module 1500 may collect information about the electronic system 1000. The sensor module 1500 may sense or receive an image signal from outside the electronic system 1000, and may convert the sensed or received image signal into image data, i.e., an image frame. To this end, the sensor module 1500 may include a sensing device, for example, at least one of various types of sensing devices (such as a camera, an imaging device, an image sensor, a light detection and ranging (Light Detection And Ranging, LIDAR) sensor, an ultrasonic sensor, and an infrared sensor), or may receive a sensing signal from a sensing device. In an embodiment, the sensor module 1500 provides an image frame to the neural network processing unit 1100. For example, the sensor module 1500 may include an image sensor, and may generate a video stream by capturing an image of the external environment of the electronic system 1000, and sequentially provide continuous image frames of the video stream to the neural network processing unit 1100.

[0131] According to an exemplary embodiment of the inventive concept, the RAM 1200 includes an arithmetic circuit 1270. The arithmetic circuit 1270 may perform an arithmetic operation on an operand based on an internal arithmetic control signal generated in the RAM 1200. For example, the arithmetic circuit 1270 may output calculated data Data_cal to the neural network processing unit 1100 by performing all or some of the convolution operations on the operands. Figures 1 to 16 The features described may be applied to specific operations on arithmetic circuit 1270 .

[0132] The exemplary embodiments of the inventive concept have been described above with reference to the accompanying drawings. Although specific terms are used herein to describe the embodiments, they are only used to describe the technical ideas of the inventive concept and are not intended to limit the scope of the inventive concept. Therefore, it will be understood by those skilled in the art that various modifications and other equivalent embodiments can be derived therefrom.

Claims

1. A memory device, include: a memory bank including a plurality of memory cells arranged in a region where a plurality of word lines and a plurality of bit lines of a memory device cross each other; a sense amplifier connected to the memory bank through the plurality of bit lines and configured to amplify a signal transmitted through a selected bit line from among the plurality of bit lines; as well as Arithmetic circuits, wherein the memory device generates an internal arithmetic control signal including an internal read signal and an internal write signal in response to receiving an arithmetic control signal from a device located outside the memory device, reads a first operand from a sense amplifier to an arithmetic circuit in response to the internal read signal, writes a second operand received from a device located outside the memory device from a data input / output buffer of the memory device to the arithmetic circuit in response to the internal write signal, and The arithmetic circuit performs an arithmetic operation by using a first operand and a second operand.

2. The memory device according to claim 1, in, The internal arithmetic control signal also includes at least one of an arithmetic operation start signal for starting an arithmetic operation of the arithmetic circuit, an arithmetic initialization signal for initializing the arithmetic circuit, and an output signal for controlling the arithmetic circuit to output calculated data.

3. The memory device according to claim 2, in, The memory device simultaneously generates two or more of an internal read signal, an internal write signal, and an arithmetic operation start signal.

4. The memory device according to claim 1, in, The internal arithmetic control signals are generated by control logic configured to control the configuration of the memory device.

5. The memory device according to claim 1, in, The arithmetic circuit includes a multiplication and accumulation circuit, wherein the multiplication and accumulation circuit is configured to perform a multiplication operation and an accumulation operation by using a first operand and a second operand.

6. The memory device according to claim 5, in, The multiplication and accumulation circuits include: a multiplier configured to generate multiplication data by multiplying a first operand by a second operand; a register configured to temporarily store computation data; and The adder is configured to update the calculation data by adding the multiplication data to the calculation data stored in the register.

7. The memory device according to claim 5, in, The arithmetic circuit also includes: a nonlinear function processor configured to perform nonlinear function processing on the data calculated by the multiplication and accumulation circuit; and The quantizer is configured to quantize the data processed by the nonlinear function.

8. The memory device according to claim 5, in, The arithmetic circuit includes a plurality of multiplication and accumulation circuits, wherein the plurality of multiplication and accumulation circuits include a multiplication and accumulation circuit, and The plurality of multiplication and accumulation circuits are connected to each other in a ring form.

9. The memory device according to claim 1 , further comprising a column decoder, wherein the column decoder is connected to a memory bank through the plurality of bit lines and is configured to perform a decoding operation to select some of the plurality of bit lines, in, The sense amplifier includes an input / output sense amplifier, wherein the input / output sense amplifier is connected to the column decoder through a global input / output line and is configured to amplify a signal transmitted through the global input / output line, and The arithmetic circuit is configured to receive a first operand from the input / output sense amplifier.

10. The memory device according to claim 7, in, The memory bank includes a plurality of sub-memory cell arrays arranged in a matrix along the directions of the plurality of word lines and the plurality of bit lines. the sense amplifier includes a plurality of bit line sense amplifiers, wherein each of the plurality of bit line sense amplifiers is connected to sub bit lines respectively connected to the plurality of sub memory cell arrays and is configured to amplify a signal transmitted through the sub bit lines, and An arithmetic circuit is included in the memory bank and is configured to receive a first operand from the plurality of bit line sense amplifiers.

11. A memory device, include: at least one memory bank including a plurality of memory cells; control logic configured to generate internal arithmetic control signals including an internal read signal and an internal write signal based on an arithmetic control signal received from a processor located external to the memory device; as well as Arithmetic circuits, wherein the memory device reads a first operand from at least one memory bank to the arithmetic circuit via a path including a sense amplifier in response to an internal read signal, wherein the memory device writes a second operand received from the processor from a data input / output buffer of the memory device into the arithmetic circuit in response to the internal write signal, and The arithmetic circuit performs an arithmetic operation by using a first operand and a second operand.

12. The memory device according to claim 11, in, In response to an internal write signal generated by the control logic, one of the input feature data and the core data is input to the arithmetic circuit through a path including a data input / output buffer of the memory device.

13. The memory device according to claim 11, in, The internal arithmetic control signal also includes at least one of an arithmetic operation start signal for starting an arithmetic operation of the arithmetic circuit, an arithmetic initialization signal for initializing the arithmetic circuit, and an output signal for controlling the arithmetic circuit to output calculated data.

14. The memory device according to claim 11, in, The control logic is also configured to: control the memory device to store at least one of the input characteristic data and the kernel data in the at least one storage body by configuring the address of the at least one storage body to store at least one of the input characteristic data and the kernel data so that at least one of the input characteristic data and the kernel data is sequentially input to the arithmetic circuit based on an internal read signal.

15. The memory device according to claim 11, in, The at least one memory bank comprises: a plurality of sub-memory cell arrays; and a bit line sense amplifier connected to the plurality of sub memory cell arrays through sub bit lines and configured to amplify a signal transmitted through the sub bit lines, The memory device further includes an input / output sense amplifier, wherein the input / output sense amplifier is configured to amplify a signal transmitted from the at least one memory bank through a global input / output line, and The arithmetic circuit is located in a region where the bit line sense amplifiers are arranged or in a region where the input / output sense amplifiers are arranged.

16. A neural network system for performing a neural network operation, the neural network system include: a neural network processor configured to generate an arithmetic control signal for controlling an arithmetic operation of the memory device; as well as a memory device configured to generate an internal arithmetic control signal including an internal read signal and an internal write signal based on an arithmetic control signal provided from a neural network processor located outside the memory device, to internally read a first operand from a sense amplifier of the memory device to an arithmetic circuit of the memory device when the internal read signal is generated, and to write a second operand received from the neural network processor from a data input / output buffer of the memory device to the arithmetic circuit when the internal write signal is generated, The arithmetic circuit performs an arithmetic operation by using a first operand and a second operand.

17. The neural network system according to claim 16, in, The internal arithmetic control signal also includes an arithmetic operation start signal, and The arithmetic circuit is configured as: When the internal read signal is generated, reading any one of the input feature data and the core data from a bank of the memory device through a path including a sense amplifier; when the internal write signal is generated, obtaining the other of the input feature data and the kernel data through the data input / output buffer via a path that does not include a memory bank; and When the arithmetic operation start signal is generated, an arithmetic operation is performed by using the input feature data and the kernel data.

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