A static simulated load shedding test integrated test system and test method

Abstract

A static simulated load rejection test integrated test system relates to the technical field of thermal automation and solves the problems of low integration of test equipment and low calculation efficiency of test data; the system comprises a frequency generating circuit, an OPC instruction acquisition circuit, a signal processing circuit, an HMI touch screen interface, an analog quantity acquisition channel interface unit and a test cabinet; the frequency generating circuit is connected to the signal processing circuit, the OPC instruction acquisition circuit is connected to the signal processing circuit, the HMI touch screen interface is connected to the signal processing circuit, the analog quantity acquisition channel interface unit is connected to the signal processing circuit, and the test cabinet is respectively connected to the frequency generating circuit, the OPC instruction acquisition circuit, the HMI touch screen interface and the analog quantity acquisition channel interface unit; the test method comprises: connecting a unit to be tested to the test cabinet; controlling a regulating valve of the unit to be tested to close; processing and displaying a signal; and improving the integration of the test equipment and the calculation efficiency of the test data.

Description

Technical Field

[0001] The invention belongs to the technical field of thermal automation, and in particular relates to a static simulation load rejection test integrated test system and a test method. Background Art

[0002] The load rejection test of the steam turbine in a thermal power plant is an important test to examine the turbine regulating system's ability to control the speed. It is an important means to check the quality of the steam turbine regulating system and prevent the unit from overspeeding. All thermal power plants must carry out this test. Before the actual load rejection test, a static simulated load rejection test should be carried out to test whether the action delay time and closing time of the regulating valve meet the requirements of the regulations.

[0003] The test of static simulated load rejection test data in the prior art mainly uses a signal generator to simulate the speed increase, and uses a data acquisition instrument to collect OPC instructions and feedback signals of regulating valves. Since OPC instructions are dry contact signals (i.e., the signal is only on and off), existing data acquisition instruments cannot directly collect them. If you want to collect the changes in the OPC instruction signal, you must add batteries and resistors, and collect the voltage changes at both ends of the battery to determine whether the OPC instruction is connected or disconnected. Therefore, the tester also needs to prepare a signal generator, battery, resistor, switch and other auxiliary tools. The test equipment has a low integration level and is prone to tool loss. Moreover, after the test, the tester also needs to intercept data from the data acquisition instrument to obtain the required measurement time, resulting in low test efficiency.

[0004] The Chinese invention patent "A New Simulated DC Load Shedding Test Method" with authorization announcement number CN106680620B discloses a new simulated DC load shedding test method. The method provides a new simulated DC load shedding test method. Through the relay protection instrument, the test is simulated under two conditions: grid-connected and no-load conditions. It verifies whether the excitation regulation system operates normally after receiving the "island operation" signal and the "DC shutdown" signal, thereby testing the control logic and regulation ability of the excitation regulator. Compared with the real test method, this method simplifies the test process and avoids the impact of the real test on the safe and stable operation of the power grid. However, the patent does not solve the above problems. Summary of the invention

[0005] The technical problem to be solved by the present invention is: how to improve the integration of static simulated load shedding test equipment and the calculation efficiency of test data.

[0006] The present invention solves the above technical problems through the following technical solutions.

[0007] A static simulated load shedding test integrated test system comprises a frequency generating circuit (1), an OPC instruction acquisition circuit (2), a signal processing circuit (3), an HMI touch screen interface (4), an analog quantity acquisition channel interface unit (5) and a test cabinet (10); the frequency generating circuit (1) is connected to the signal processing circuit (3), the OPC instruction acquisition circuit (2) is connected to the signal processing circuit (3), the HMI touch screen interface (4) is connected to the signal processing circuit (3), the analog quantity acquisition channel interface unit (5) is connected to the signal processing circuit (3), and the test cabinet (10) is respectively connected to the frequency generating circuit (1), the OPC instruction acquisition circuit (2), the HMI touch screen interface (4) and the analog quantity acquisition channel interface unit (5).

[0008] The technical solution of the present invention provides an integrated test system, which integrates various tools and instruments required for the test into a test cabinet, thereby improving the integration of static simulated load shedding test equipment; at the same time, the collected data is automatically calculated through signal processing to obtain the data to be tested, and the data is directly output and displayed through the HMI touch screen interface, without the need to intercept data from the data acquisition instrument to obtain the required measurement data, thereby improving the efficiency of test data testing.

[0009] As a further improvement of the technical solution of the present invention, the frequency generating circuit (1) comprises a square wave generator (11), a double-pole single-throw switch (12), and a frequency output channel interface (13); the square wave generator (11) and the double-pole single-throw switch (12) are connected in series, and the frequency output channel interface (13) is connected between the square wave generator (11) and the double-pole single-throw switch (12);

[0010] As a further improvement of the technical solution of the present invention, the OPC instruction acquisition circuit (2) comprises a battery (21), a resistor (22), a double-pole single-throw switch (12), and a DI acquisition channel interface (23); the battery (21), the resistor (22), and the double-pole single-throw switch (12) are connected in series in sequence; the DI acquisition channel interface (23) is connected between the battery (21) and the double-pole single-throw switch (12); and both ends of the resistor (22) are connected to the signal processing circuit (3) as output ends of the OPC instruction acquisition circuit (2).

[0011] As a further improvement of the technical solution of the present invention, the signal processing circuit (3) comprises an A / D converter (31), a controller (32), a communication unit (33), a power supply unit (34), a clock unit (35), and a D / A converter (36);

[0012] The clock unit (35) is connected to the A / D converter (31) and the controller (32) respectively, and is used to synchronize the time between the A / D converter (31) and the controller (32);

[0013] The power supply unit (34) is connected to the controller (32) and is used to supply power to the controller (32);

[0014] The communication unit (33) is connected to the HMI touch screen interface (4) and the controller (32) respectively, and is used for data communication between the controller (32) and the HMI touch screen interface (4);

[0015] The controller (32) is used for data preprocessing and data calculation, and sends the calculation results to the HMI touch screen interface (4) through the communication unit (33);

[0016] The A / D converter (31) is respectively connected to the controller (32), the output end of the OPC instruction acquisition circuit (2) and the analog quantity acquisition channel interface unit (5), and is used to convert the analog quantity signal output from the output end of the OPC instruction acquisition circuit (2) and the analog quantity signal input to the analog quantity acquisition channel interface unit (5) into a digital quantity signal that can be processed by the controller (32);

[0017] The D / A converter (36) is connected to the controller (32) and is used to convert the digital signal output by the controller (32) into an analog signal and input the analog signal into the square wave generator (11); the square wave generator (11) generates a frequency signal according to the input analog signal.

[0018] As a further improvement of the technical solution of the present invention, the analog quantity acquisition channel interface unit (5) comprises eight analog quantity acquisition channel interfaces for acquiring analog quantity signals of the test unit.

[0019] As a further improvement of the technical solution of the present invention, the test cabinet (10) comprises a cabinet body (101), a control display panel (102), and a plug-in backplane (103); the control display panel (102) is installed on the front view surface of the cabinet body (101), and the plug-in backplane (103) is installed on the rear view surface of the cabinet body (101);

[0020] The control display panel (102) comprises an HMI touch screen (1021), a test button (1022), and a power socket (1023);

[0021] The HMI touch screen (1021) is connected to the HMI touch screen interface (4) of the static simulation load shedding test integrated test system; the test button (1022) is connected to the double-pole single-throw switch (12) of the static simulation load shedding test integrated test system; and the power socket (1023) is connected to the power supply unit (34) of the static simulation load shedding test integrated test system.

[0022] As a further improvement of the technical solution of the present invention, the plug-in backplane (103) comprises a frequency socket (1031), a DI socket (1032), and eight analog quantity acquisition channel sockets, and the frequency socket (1031), the DI socket (1032), and the eight analog quantity acquisition channel sockets are respectively connected to the frequency output channel interface (13), the DI acquisition channel interface (23), and the eight analog quantity acquisition channel interfaces of the static simulation load shedding test integrated test system.

[0023] As a further improvement of the technical solution of the present invention, during the test of the static simulated load rejection test integrated test system, the speed channel of the unit to be tested is connected to the frequency socket (1031) of the test cabinet; the OPC command signal of the unit to be tested is connected to the DI socket (1032) of the test cabinet; the regulating valve feedback signal of the unit to be tested is connected to the analog quantity acquisition channel socket of the test cabinet; after the wiring is completed, the test button (1022) of the test cabinet is closed, and the regulating valve of the unit to be tested is controlled by adjusting the given frequency signal value through the HMI touch screen (1021) until the regulating valve of the unit to be tested is completely closed; the controller (32) of the signal processing circuit (3) calculates the action delay time of the regulating valve, the closing process time of the regulating valve, and the total closing time of the regulating valve according to the collected OPC command signal of the unit to be tested and the regulating valve feedback signal of the unit to be tested, and transmits the calculated result to the HMI touch screen (1021) for display through the communication unit (33).

[0024] A test method applied to the static simulated load rejection test integrated test system comprises the following steps:

[0025] Step 1: Connect the unit to be tested to the test cabinet;

[0026] Specifically, the speed channel of the unit to be tested is connected to the frequency socket (1031) of the test cabinet; the OPC command signal of the unit to be tested is connected to the DI socket (1032) of the test cabinet; the regulating valve feedback signal of the unit to be tested is connected to the analog quantity acquisition channel socket of the test cabinet;

[0027] Step 2: Control the regulating valve of the unit to be tested to close;

[0028] After the wiring is completed, the test button (1022) of the test cabinet is closed, and the given frequency signal value is adjusted through the HMI touch screen (1021) to control the regulating valve of the unit to be tested until the regulating valve of the unit to be tested is completely closed;

[0029] Step 3: Process the signal and display it;

[0030] The controller (32) of the signal processing circuit (3) calculates the action delay time of the regulating valve, the closing process time of the regulating valve, and the total closing time of the regulating valve based on the collected OPC command signal of the unit to be tested and the regulating valve feedback signal of the unit to be tested, and transmits the calculated result to the HMI touch screen (1021) for display via the communication unit (33).

[0031] As a further improvement of the technical solution of the present invention, in the step 3, the method for calculating the action delay time of the regulating valve, the closing process time of the regulating valve, and the total closing time of the regulating valve is as follows:

[0032] t1=k2-k1 Formula (1)

[0033] t2=k3-k2 Formula (2)

[0034] t=t1+t2 Formula (3)

[0035] Among them, t1 is the action delay time of the regulating valve; t2 is the closing process time of the regulating valve; t is the total closing time of the regulating valve; k1 is the rising edge time of the captured OPC command signal of the unit under test; k2 is the time when the regulating valve of the unit under test starts to close; k3 is the time when the regulating valve of the unit under test is completely closed.

[0036] As a further improvement of the technical solution of the present invention, the method of capturing the rising edge time of the OPC command signal of the unit to be tested, capturing the time when the regulating valve of the unit to be tested starts to close, and capturing the time when the regulating valve of the unit to be tested is completely closed is as follows:

[0037] (1) The digital quantity of the signal is stored in the input variable array;

[0038] The collected OPC command signal of the unit to be tested and the regulating valve feedback signal of the unit to be tested are converted into digital quantities by an A / D converter (31) and stored in an input variable array x(); the input variables include the OPC command signal of the unit to be tested and the regulating valve feedback signal of the unit to be tested;

[0039] (2) Find the range of the numerical value of the input variable and calculate the Sigmoid function;

[0040] Find the maximum and minimum values ​​of each input variable, then the range of the digital quantity corresponding to the input variable is [x min ,x max ]; and calculated according to the following formula:

[0041]

[0042]

[0043]

[0044] Where x() is the input variable array; u() is the intermediate variable array function; g() is the Sigmoid function; y is the output classification function; x max is the maximum value of the input variable, x min Minimum value of input variable; k i is the capture time; i is the counting factor, i takes the value of 1, 2 or 3;

[0045] (3) Capture time;

[0046] 1) For the OPC command signal of the unit to be tested: when y=0, the OPC command is not triggered; when y=1, the OPC command signal of the unit to be tested is triggered, and the time at this time is recorded as k1;

[0047] 2) For the regulating valve feedback signal of the unit under test: when y=1, the regulating valve of the unit under test begins to close, and the time at this time is recorded as k2; when y=0, the regulating valve of the unit under test is completely closed, and the time at this time is recorded as k3.

[0048] The present invention has the following advantages:

[0049] (1) The technical solution of the present invention provides an integrated test system that integrates various tools and instruments required for testing into a test cabinet, thereby improving the integration of static simulated load shedding test equipment.

[0050] (2) The technical solution of the present invention provides an integrated test system, which automatically calculates the data to be tested through signal processing from the collected data, and directly outputs and displays it through the HMI touch screen interface. There is no need to intercept data from the data acquisition instrument to obtain the required measurement data, thereby improving the efficiency of test data testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a structural diagram of a static simulated load shedding test integrated test system according to the first embodiment of the present invention;

[0052] Figure 2This is a front view of a test cabinet of a static simulated load rejection test integrated test system according to the first embodiment of the present invention;

[0053] Figure 3 It is a rear view of a test cabinet of a static simulated load rejection test integrated test system according to the first embodiment of the present invention;

[0054] Figure 4 This is a flow chart of a testing method of a static simulated load shedding test integrated testing system according to a second embodiment of the present invention;

[0055] Figure 5 It is a flow chart of a method for capturing time in a test method of a static simulation load shedding test integrated test system according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in combination with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and specific embodiments:

[0058] Embodiment 1

[0059] like Figure 1-3 As shown, a static simulated load shedding test integrated test system includes a frequency generating circuit 1, an OPC instruction acquisition circuit 2, a signal processing circuit 3, an HMI touch screen interface 4, an analog quantity acquisition channel interface unit 5 and a test cabinet 10; the frequency generating circuit 1 is connected to the signal processing circuit 3, the OPC instruction acquisition circuit 2 is connected to the signal processing circuit 3, the HMI touch screen interface 4 is connected to the signal processing circuit 3, the analog quantity acquisition channel interface unit 5 is connected to the signal processing circuit 3, and the test cabinet 10 is respectively connected to the frequency generating circuit 1, the OPC instruction acquisition circuit 2, the HMI touch screen interface 4 and the analog quantity acquisition channel interface unit 5.

[0060] The frequency generating circuit 1 includes a square wave generator 11, a double-pole single-throw switch 12, and a frequency output channel interface 13; the square wave generator 11 is connected in series with the double-pole single-throw switch 12, and the frequency output channel interface 13 is connected between the square wave generator 11 and the double-pole single-throw switch 12.

[0061] The OPC instruction acquisition circuit 2 includes a battery 21, a resistor 22, a double-pole single-throw switch 12, and a DI acquisition channel interface 23. The battery 21, the resistor 22, and the double-pole single-throw switch 12 are connected in series in sequence, and the DI acquisition channel interface 23 is connected between the battery 21 and the double-pole single-throw switch 12; the two ends of the resistor 22 are connected to the signal processing circuit 3 as the output ends of the OPC instruction acquisition circuit 2.

[0062] The signal processing circuit 3 includes an A / D converter 31, a controller 32, a communication unit 33, a power supply unit 34, a clock unit 35, and a D / A converter 36; the clock unit 35 is connected to the A / D converter 31 and the controller 32 respectively, and is used to synchronize the time between the A / D converter 31 and the controller 32; the power supply unit 34 is connected to the controller 32, and is used to supply power to the controller 32; the communication unit 33 is connected to the HMI touch screen interface 4 and the controller 32 respectively, and is used for data communication between the controller 32 and the HMI touch screen interface 4; the controller 32 is used for data preprocessing and data calculation, and calculates the data. The result is sent to the HMI touch screen interface 4 through the communication unit 33; the A / D converter 31 is respectively connected to the controller 32, the output end of the OPC instruction acquisition circuit 2 and the analog acquisition channel interface unit 5, and is used to convert the analog signal output from the output end of the OPC instruction acquisition circuit 2 and the analog signal input from the analog acquisition channel interface unit 5 into a digital signal that can be processed by the controller 32; the D / A converter 36 is connected to the controller 32, and is used to convert the digital signal output by the controller 32 into an analog signal and input it into the square wave generator 11; the square wave generator 11 generates a frequency signal according to the input analog signal.

[0063] The analog quantity acquisition channel interface unit 5 includes eight analog quantity acquisition channel interfaces for acquiring analog quantity signals of the test unit.

[0064] The test cabinet 10 includes a cabinet body 101, a control display panel 102, and a plug-in backplane 103; the control display panel 102 is installed on the main viewing surface of the cabinet body 101, and the plug-in backplane 103 is installed on the rear viewing surface of the cabinet body 101; the control display panel 102 includes an HMI touch screen 1021, a test button 1022, and a power socket 1023; the HMI touch screen 1021 is connected to the HMI touch screen interface 4 of the static simulation load shedding test integrated test system; the test button 1022 is connected to the double-pole single-throw switch 12 of the static simulation load shedding test integrated test system; the power socket 1023 is connected to the power unit 34 of the static simulation load shedding test integrated test system.

[0065] The plug-in backplane 103 includes a frequency socket 1031, a DI socket 1032, and eight analog quantity acquisition channel sockets. The frequency socket 1031, the DI socket 1032, and the eight analog quantity acquisition channel sockets are respectively connected to the frequency output channel interface 13, the DI acquisition channel interface 23, and the eight analog quantity acquisition channel interfaces of the static simulation load shedding test integrated test system.

[0066] During the test of the static simulated load rejection test integrated test system, the speed channel of the unit to be tested is connected to the frequency socket 1031 of the test cabinet; the OPC command signal of the unit to be tested is connected to the DI socket 1032 of the test cabinet; the regulating valve feedback signal of the unit to be tested is connected to the analog quantity acquisition channel socket of the test cabinet; after the wiring is completed, the test button 1022 of the test cabinet is closed, and the regulating valve of the unit to be tested is controlled by adjusting the given frequency signal value through the HMI touch screen 1021 until the regulating valve of the unit to be tested is completely closed; the controller 32 of the signal processing circuit 3 calculates the action delay time of the regulating valve, the closing process time of the regulating valve, and the total closing time of the regulating valve according to the collected OPC command signal of the unit to be tested and the regulating valve feedback signal of the unit to be tested, and transmits the calculated result to the HMI touch screen 1021 through the communication unit 33 for display.

[0067] Embodiment 2

[0068] like Figure 4 As shown, a test method applied to the static simulated load rejection test integrated test system comprises the following steps:

[0069] Step 1: Connect the unit to be tested to the test cabinet;

[0070] Specifically, the speed channel of the unit to be tested is connected to the frequency socket 1031 of the test cabinet; the OPC command signal of the unit to be tested is connected to the DI socket 1032 of the test cabinet; the regulating valve feedback signal of the unit to be tested is connected to the analog quantity acquisition channel socket of the test cabinet;

[0071] Step 2: Control the regulating valve of the unit to be tested to close;

[0072] After the wiring is completed, the test button 1022 of the test cabinet is closed, and the given frequency signal value is adjusted through the HMI touch screen 1021 to control the regulating valve of the unit to be tested until the regulating valve of the unit to be tested is completely closed;

[0073] Step 3: Process the signal and display it;

[0074] The controller 32 of the signal processing circuit 3 calculates the action delay time of the regulating valve, the closing process time of the regulating valve, and the total closing time of the regulating valve according to the collected OPC command signal of the unit to be tested and the regulating valve feedback signal of the unit to be tested, and transmits the calculated results to the HMI touch screen 1021 through the communication unit 33 for display.

[0075] In the step 3, the method for calculating the action delay time of the regulating valve, the closing process time of the regulating valve, and the total closing time of the regulating valve is as follows:

[0076] t1=k2-k1 Formula (1)

[0077] t2=k3-k2 Formula (2)

[0078] t=t1+t2 Formula (3)

[0079] Among them, t1 is the action delay time of the regulating valve; t2 is the closing process time of the regulating valve; t is the total closing time of the regulating valve; k1 is the rising edge time of the captured OPC command signal of the unit under test; k2 is the time when the regulating valve of the unit under test starts to close; k3 is the time when the regulating valve of the unit under test is completely closed.

[0080] The method of capturing the rising edge time of the OPC command signal of the unit to be tested, capturing the time when the regulating valve of the unit to be tested starts to close, and capturing the time when the regulating valve of the unit to be tested is completely closed is as follows:

[0081] (1) The digital quantity of the signal is stored in the input variable array;

[0082] The collected OPC command signal of the unit to be tested and the regulating valve feedback signal of the unit to be tested are converted into digital quantities by the A / D converter 31 and stored in the input variable array x(); the input variables include the OPC command signal of the unit to be tested and the regulating valve feedback signal of the unit to be tested;

[0083] (2) Find the range of the numerical value of the input variable and calculate the Sigmoid function;

[0084] Find the maximum and minimum values ​​of each input variable, then the range of the digital quantity corresponding to the input variable is [x min ,x max ]; and calculated according to the following formula:

[0085]

[0086]

[0087]

[0088] Where x() is the input variable array; u() is the intermediate variable array function; g() is the Sigmoid function; y is the output classification function; x max is the maximum value of the input variable, x min Minimum value of input variable; k i is the capture time; i is the counting factor, i takes the value of 1, 2 or 3;

[0089] (3) Capture time;

[0090] 1) For the OPC command signal of the unit to be tested: when y=0, the OPC command is not triggered; when y=1, the OPC command signal of the unit to be tested is triggered, and the time at this time is recorded as k1;

[0091] 2) For the regulating valve feedback signal of the unit under test: when y=1, the regulating valve of the unit under test begins to close, and the time at this time is recorded as k2; when y=0, the regulating valve of the unit under test is completely closed, and the time at this time is recorded as k3.

[0092] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A static simulated load rejection test integrated test system, characterized in that: The invention comprises a frequency generating circuit (1), an OPC instruction acquisition circuit (2), a signal processing circuit (3), an HMI touch screen interface (4), an analog quantity acquisition channel interface unit (5) and a test cabinet (10); the frequency generating circuit (1) is connected to the signal processing circuit (3), the OPC instruction acquisition circuit (2) is connected to the signal processing circuit (3), the HMI touch screen interface (4) is connected to the signal processing circuit (3), the analog quantity acquisition channel interface unit (5) is connected to the signal processing circuit (3), and the test cabinet (10) is respectively connected to the frequency generating circuit (1), the OPC instruction acquisition circuit (2), the HMI touch screen interface (4) and the analog quantity acquisition channel interface unit (5); The frequency generating circuit (1) comprises a square wave generator (11), a double-pole single-throw switch (12), and a frequency output channel interface (13); the square wave generator (11) and the double-pole single-throw switch (12) are connected in series, and the frequency output channel interface (13) is connected between the square wave generator (11) and the double-pole single-throw switch (12); The OPC instruction acquisition circuit (2) comprises a battery (21), a resistor (22), a double-pole single-throw switch (12), and a DI acquisition channel interface (23); the battery (21), the resistor (22), and the double-pole single-throw switch (12) are sequentially connected in series; the DI acquisition channel interface (23) is connected between the battery (21) and the double-pole single-throw switch (12); and both ends of the resistor (22) are connected to a signal processing circuit (3) as output ends of the OPC instruction acquisition circuit (2).

2. A static simulated load rejection test integrated test system according to claim 1, characterized in that: The signal processing circuit (3) comprises an A / D converter (31), a controller (32), a communication unit (33), a power supply unit (34), a clock unit (35), and a D / A converter (36); The clock unit (35) is connected to the A / D converter (31) and the controller (32) respectively, and is used to synchronize the time between the A / D converter (31) and the controller (32); The power supply unit (34) is connected to the controller (32) and is used to supply power to the controller (32); The communication unit (33) is connected to the HMI touch screen interface (4) and the controller (32) respectively, and is used for data communication between the controller (32) and the HMI touch screen interface (4); The controller (32) is used for data preprocessing and data calculation, and sends the calculation results to the HMI touch screen interface (4) through the communication unit (33); The A / D converter (31) is respectively connected to the controller (32), the output end of the OPC instruction acquisition circuit (2) and the analog quantity acquisition channel interface unit (5), and is used to convert the analog quantity signal output from the output end of the OPC instruction acquisition circuit (2) and the analog quantity signal input to the analog quantity acquisition channel interface unit (5) into a digital quantity signal that can be processed by the controller (32); The D / A converter (36) is connected to the controller (32) and is used to convert the digital signal output by the controller (32) into an analog signal and input the analog signal into the square wave generator (11); the square wave generator (11) generates a frequency signal according to the input analog signal.

3. A static simulated load rejection test integrated test system according to claim 2, characterized in that: The analog quantity acquisition channel interface unit (5) comprises eight analog quantity acquisition channel interfaces, which are used to acquire analog quantity signals of the test unit.

4. A static simulated load rejection test integrated test system according to claim 3, characterized in that: The test cabinet (10) comprises a cabinet body (101), a control display panel (102), and a plug-in backplane (103); the control display panel (102) is installed on the front view surface of the cabinet body (101), and the plug-in backplane (103) is installed on the rear view surface of the cabinet body (101); The control display panel (102) comprises an HMI touch screen (1021), a test button (1022), and a power socket (1023); The HMI touch screen (1021) is connected to the HMI touch screen interface (4) of the static simulation load shedding test integrated test system; the test button (1022) is connected to the double-pole single-throw switch (12) of the static simulation load shedding test integrated test system; and the power socket (1023) is connected to the power supply unit (34) of the static simulation load shedding test integrated test system.

5. A static simulated load rejection test integrated test system according to claim 4, characterized in that: The plug-in backplane (103) comprises a frequency socket (1031), a DI socket (1032), and eight analog quantity acquisition channel sockets, and the frequency socket (1031), the DI socket (1032), and the eight analog quantity acquisition channel sockets are respectively connected to the frequency output channel interface (13), the DI acquisition channel interface (23), and the eight analog quantity acquisition channel interfaces of the static simulation load rejection test integrated test system.

6. A static simulated load rejection test integrated test system according to claim 5, characterized in that: During the test of the static simulated load rejection test integrated test system, the speed channel of the unit to be tested is connected to the frequency socket (1031) of the test cabinet; the OPC command signal of the unit to be tested is connected to the DI socket (1032) of the test cabinet; the regulating valve feedback signal of the unit to be tested is connected to the analog quantity acquisition channel socket of the test cabinet; after the wiring is completed, the test button (1022) of the test cabinet is closed, and the regulating valve of the unit to be tested is controlled by adjusting the given frequency signal value through the HMI touch screen (1021) until the regulating valve of the unit to be tested is completely closed; the controller (32) of the signal processing circuit (3) calculates the action delay time of the regulating valve, the closing process time of the regulating valve, and the total closing time of the regulating valve according to the collected OPC command signal of the unit to be tested and the regulating valve feedback signal of the unit to be tested, and transmits the calculated result to the HMI touch screen (1021) for display through the communication unit (33).

7. A test method applied to the static simulated load rejection test integrated test system according to claims 1-6, characterized in that: The testing method comprises the following steps: Step 1: Connect the unit to be tested to the test cabinet; Specifically, the speed channel of the unit to be tested is connected to the frequency socket (1031) of the test cabinet; the OPC command signal of the unit to be tested is connected to the DI socket (1032) of the test cabinet; the regulating valve feedback signal of the unit to be tested is connected to the analog quantity acquisition channel socket of the test cabinet; Step 2: Control the regulating valve of the unit to be tested to close; After the wiring is completed, the test button (1022) of the test cabinet is closed, and the given frequency signal value is adjusted through the HMI touch screen (1021) to control the regulating valve of the unit to be tested until the regulating valve of the unit to be tested is completely closed; Step 3: Process the signal and display it; The controller (32) of the signal processing circuit (3) calculates the action delay time of the regulating valve, the closing process time of the regulating valve, and the total closing time of the regulating valve based on the collected OPC command signal of the unit to be tested and the regulating valve feedback signal of the unit to be tested, and transmits the calculated result to the HMI touch screen (1021) for display via the communication unit (33).

8. The testing method of a static simulated load rejection test integrated test system according to claim 7, characterized in that: In the step 3, the method for calculating the action delay time of the regulating valve, the closing process time of the regulating valve, and the total closing time of the regulating valve is as follows: t1= k2- k1 Formula (1) t2= k3- k2 formula (2) t=t1+t2 Formula (3) Among them, t1 is the action delay time of the regulating valve; t2 is the closing process time of the regulating valve; t is the total closing time of the regulating valve; k1 is the rising edge time of the captured OPC command signal of the unit under test; k2 is the time when the regulating valve of the unit under test starts to close; k3 is the time when the regulating valve of the unit under test is completely closed.

9. According to the test method of a static simulated load rejection test integrated test system of claim 8, the method of capturing the rising edge time of the OPC command signal of the unit under test, capturing the time when the regulating valve of the unit under test starts to close, and capturing the time when the regulating valve of the unit under test is completely closed is as follows: 1) The digital quantity of the signal is stored in the input variable array; The collected OPC command signal of the unit to be tested and the regulating valve feedback signal of the unit to be tested are converted into digital quantities by an A / D converter (31) and stored in an input variable array x(); the input variables include the OPC command signal of the unit to be tested and the regulating valve feedback signal of the unit to be tested; 2) Find the range of the numerical value of the input variable and calculate the Sigmoid function; Find the maximum and minimum values ​​of each input variable, then the range of the digital quantity corresponding to the input variable is [x min ,x max ]; and calculated according to the following formula: Where x() is the input variable array; u() is the intermediate variable array function; g() is the Sigmoid function; y is the output classification function; x max is the maximum value of the input variable, x min Minimum value of input variable; k i is the capture time; i is the counting factor, i takes the value of 1, 2 or 3; 3) Capture time; a) For the OPC command signal of the unit to be tested: when y=0, the OPC command is not triggered; when y=1, the OPC command signal of the unit to be tested is triggered, and the time at this time is recorded as k1; b) For the feedback signal of the regulating valve of the unit to be tested: when y=1, the regulating valve of the unit to be tested begins to close, and the time at this time is recorded as k2; when y=0, the regulating valve of the unit to be tested is completely closed, and the time at this time is recorded as k3.

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