Access restriction management within a system-on-chip

Abstract

Embodiments of the present disclosure relate to access restriction management within a system on chip. A system includes multiple master device items, and multiple slave device items, each master device item having a programming interface. Interconnection circuits are coupled between the master device items and the slave device items. Each transaction is assigned an attribute, which can take at least two attribute values ​​corresponding to at least two states for the master device. Each slave device item is associated with an identifier, which can take at least two values, which respectively correspond to at least two characteristics for the slave device. Each master device item automatically inherits the characteristics of its programming interface. The filtering circuit is configured to, in the presence of a transaction for a slave device, compare the corresponding attribute value with the identifier value of the intended slave device, and based on the comparison, reject or do not reject the transaction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French patent application No. 1872038, filed on November 29, 2018, which is hereby incorporated by reference. Technical Field

[0003] The present disclosure relates generally to electronic systems and methods and, in particular embodiments, to access restriction management within a system on a chip (SoC). Background Art

[0004] To help ensure the reliability of the system on a chip, access to certain resources (slaves) by one or more master devices may be required to be restricted. Such a feature is often referred to as "isolation" by those skilled in the art.

[0005] The implementation of management of these access restrictions is often complex, especially when this management is dynamic. Summary of the invention

[0006] Some embodiments make the management of access restrictions easy to set up and implement. In particular, some embodiments are directed to situations where the management is dynamic (e.g., when it depends on the application being considered on the system-on-chip), making the management of access restrictions easy to set up and implement.

[0007] Some embodiments relate to the routing of transactions between master and slave device items within a system on a chip (SoC). In some embodiments, the system on a chip is, for example, a microcontroller.

[0008] Some embodiments relate to the management of access restrictions to certain slave equipment items.

[0009] In some embodiments, the system on chip includes a set of master devices. For example, the set of master devices may include one or more processors, a direct memory access (DMA) controller, etc.

[0010] In some embodiments, some master device items of the set of master devices have corresponding programming interfaces. The master device items having the programming interface are referred to as "first master device items" hereinafter.

[0011] The set of master devices may also include one or more master device items lacking a programming interface. In order to distinguish it from the first master device item, the master device item lacking a programming interface is referred to as a "second master device item" hereinafter. In some embodiments, the second master device item may be, for example, a processor.

[0012] In addition, the system on chip includes several slave device items. The programming interface of the first master device item is considered as a slave device item. For example, the slave interface of a specific device, such as a memory, a peripheral device, or a more general resource, is also considered as a slave device item. The slave interface of a specific device is different from the programming interface of the first master device item.

[0013] In addition, the system on chip includes an interconnect circuit (referred to as an "interconnect" by those skilled in the art) that is coupled between the set of master devices and the slave interfaces of specific ones of the slave device items.

[0014] Each master device item is configured to transmit a transaction (eg, a write transaction or a read transaction) to at least one of the slave interfaces of a specific device in the slave device items.

[0015] Each transaction transmitted by the first master item is assigned an attribute capable of taking at least two attribute values ​​corresponding to at least two desired states for this first master item.

[0016] With respect to at least one second master item lacking a programming interface, at least one second master item is also connected to the interconnect circuitry. At least one second master item is configured to assign a fixed value to an attribute of its transaction, the fixed value being taken from at least two attribute values ​​and corresponding to one of the expected states for the second master item.

[0017] For example, the fixed attribute value is hard-coded in the second master equipment item to give it a de facto fixed status.

[0018] Each slave device item is associated with an identifier (e.g., a word of one or more bits) that can take at least two values ​​that correspond to at least two desired characteristics for the slave device item. For example, a first desired characteristic for a slave device item may be the fact that it can only be accessed by one or more authorized master device items from the master device set. For example, a second desired characteristic for the slave device item may be the fact that it can be accessed by any master device item from the master device set.

[0019] In other words, a slave equipment item having the first characteristic is therefore referred to as "isolated", whereas if the slave equipment item has the second characteristic it is referred to as "non-isolated".

[0020] In such a case, the two pairs of characteristics are complementary to each other (ie, a slave equipment item cannot have one of the two characteristics at the same time or not at the same time). Therefore, the values ​​of the identifiers corresponding to the two characteristics are two simple logical values ​​of one bit.

[0021] As a master item of a master set, whether it is the first master item or the second master item, the first desired state for the master item is, for example, the fact that it is authorized to access any slave device. The second desired state for this master item is, for example, the fact that it is not authorized to access one or more slave items selected from the set of slave devices.

[0022] In other words, for example, no matter whether the slave device is "isolated" or "non-isolated", the master device item with the first state can access any slave device. On the contrary, for example, the master device item with the second state cannot access the "isolated" slave device item.

[0023] Furthermore, in some embodiments, each first master device item automatically inherits the characteristics of its programming interface (which, as indicated above, is considered a slave device item) and is configured to assign one of the attribute values ​​to the attributes of its transactions based on the value of the identifier of its programming interface.

[0024] Furthermore, the system on chip comprises a filtering circuit configured to compare the corresponding attribute value with the slave value of the slave identifier of the slave device item if a transaction intended for the slave device item exists, and to reject or not reject the transaction depending on the result of the comparison.

[0025] In some embodiments, the fact that each first master device item automatically inherits the characteristics of its programming interface, and that it assigns one of the values ​​of the attribute to the attribute based on the value of the identifier of its programming interface, advantageously greatly simplifies the management and hardware implementation of access restrictions.

[0026] Therefore, if the programming interface of a first master device item is considered to be "isolated", this first master device item is automatically isolated (i.e. it will be able to have access not only to isolated slave device items, but also to those slave device items that are not isolated).

[0027] On the other hand, if the programming interface of a first master item is considered "non-isolated", then this first master item is automatically non-isolated (ie it will not be able to have access to isolated slave items).

[0028] Therefore, it is not necessarily necessary to specially provide an external signal dedicated to causing the first master item to be isolated or non-isolated.

[0029] Therefore, the first master item defines the value of the attribute of its transaction according to the value of the identifier of its programming interface, thereby also avoiding the use of specific external signals to define the attribute value in this case.

[0030] While the values ​​of identifiers of slave equipment items may be fixed in registers of the system-on-chip, it may be particularly advantageous in certain applications to be able to program these values ​​for at least some of the slave equipment items.

[0031] As indicated previously, slave device items include programming interfaces and slave interfaces of specific devices, such as memory, peripherals, or more generally resources.

[0032] According to one embodiment, the value of the identifier of the at least one slave interface and the value of the identifier of the at least one programming interface are advantageously programmable.

[0033] Furthermore, the system additionally includes a programming circuit configured to program the programmable identifier value via the interconnect circuit.

[0034] By way of non-limiting example, the programming circuitry may include at least one first programmable register associated with at least one programming interface and intended to contain the value of an identifier associated with this programming interface; at least one second programmable register associated with at least one specific item of equipment among the specific items of equipment and intended to contain the value of an identifier associated with this specific item of equipment; instructions of a programming block, such as a hardware state machine, or more often initialization code, configured to program the at least one first programmable register and the at least one second programmable register via an interconnection circuit; and a connecting link, between the at least one first programmable register and the at least one programmable interface, such as one or more "wires" according to the size of the identifier.

[0035] In some embodiments, this "wired" connection is particularly simple to create, thereby easily enabling dynamic management of access restrictions.

[0036] Furthermore, in some embodiments it is particularly advantageous if the connection link extends into a first master device item associated with at least one of the programming interfaces.

[0037] Therefore, the control logic of the programming interface of the first master device item can directly read the contents of the first programmable register in order to know the value of the identifier associated with this programming interface and thus determine whether it has, for example, isolated or non-isolated characteristics in order to reject, for example, the following transactions: transactions from a master device item that does not have access to an isolated slave device item.

[0038] Similarly, the first master item directly receives the value of the identifier associated with its programming interface and thus assigns the actual property value corresponding to such identifier.

[0039] In other words, if the programming interface is isolated, this first master entry will automatically inherit the fact of having, for example, access to any slave device (isolated or non-isolated).

[0040] One or more second master items (eg microprocessors) may perform programming of the programmable register or registers. In other words, one or more second master items may incorporate programming blocks.

[0041] For example, the programming circuit is configured to perform programming during an initialization phase of the system.

[0042] According to one embodiment, the interconnection circuit comprises an interconnection matrix connected to the set of masters, and a stage comprising at least one demultiplexer having an input connected to the interconnection matrix and a number of outputs connected to the slave interfaces.

[0043] The filtering circuit thus comprises a filtering logic located in the stage, connected to at least one second programmable register and configured to compare the value of the attribute intended for one of the slave interfaces with the value of the identifier of this slave interface.

[0044] As indicated above, in some embodiments, the first desired characteristic for a slave device item is the fact that it can only be accessed by one or more authorized master device items taken from the master device set, and the second desired characteristic for this slave device is the fact that it can be accessed by any master device in the master device set.

[0045] Similarly, in some embodiments, a first desired characteristic for a master device item in a master device set is the fact that it is authorized to access any slave device, and a second desired characteristic for a master device item in a master device set is the fact that it is not authorized to access one or more slave device items selected from the slave device set.

[0046] Thus, for example, when the identifier of the programming interface has a first value corresponding to the first characteristic, the attribute of the transaction from the first master item associated with this programming interface has a first attribute value corresponding to the first state.

[0047] And, for example, when the identifier of the programming interface has a second value corresponding to the second characteristic, the attribute of the transaction from the first master item associated with this programming interface has a second attribute value corresponding to the second state.

[0048] Thus, for example, a transaction assigned an attribute having a first attribute value may be intended for any slave device, and a transaction assigned an attribute having a second attribute value and intended for a slave device item whose identifier has the first attribute value will be rejected. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Other advantages and features of the invention will become apparent on the basis of the detailed description of purely non-limiting embodiments and the accompanying drawings, in which:

[0050] Figure 1 schematically illustrates one embodiment of a system on chip according to an embodiment of the present invention;

[0051] Figures 2 to 4 Schematically illustrates an embodiment of the present invention Figure 1 part of a system-on-chip; and

[0052] Figures 5 to 9 The access for managing transactions of various slave equipment items according to an embodiment of the present invention is schematically illustrated. DETAILED DESCRIPTION

[0053] exist Figure 1 In the figure, the reference SYS denotes a system on chip (e.g. a microcontroller), which in this case comprises several first master items: M1, M2 and M3, each having a programming interface SM1, SM2 and SM3. Each programming interface is intended to receive transactions intended for the corresponding first master item, for example in order to program it.

[0054] The system on chip SYS also includes one or more second master equipment items, and the second master equipment lacks a programming interface. In this embodiment, the system on chip SYS only includes one second master equipment item M40. For example, the second master equipment item is a microprocessor. In some embodiments, the system on chip SYS may include more than one second master equipment item.

[0055] The system on chip SYS also comprises several slave equipment items, which include a programming interface.

[0056] More specifically, the slave device item comprises programming interfaces SM1, SM2 and SM3 and also comprises device-specific slave interfaces S1, S2 and S3, wherein the slave interfaces S1, S2 and S3 are different from the programming interfaces.

[0057] These specific equipment items (eg, S1, S2, and S3) are typically resources, such as memory.

[0058] Each master item, whether it is the first master item or the second master item, is configured to transmit a transaction to at least one slave item. In some embodiments, the master transmits the transaction via a master interface, which is not shown here for simplicity. Such a transaction can be, for example, a read transaction, a write transaction, a programming transaction, etc.

[0059] Each transaction TRi coming from a master item Mi is assigned the attribute ATTi.

[0060] In this example implementation, this property can take two property values, which correspond to two desired states for the first master device.

[0061] Similarly, each slave equipment item, whether it is a programming interface or a slave interface, is associated with an identifier capable of taking at least two values ​​corresponding respectively to at least two desired characteristics for the slave equipment item.

[0062] In this example embodiment and implementation, a first desired characteristic for a slave equipment item is the fact that it can only be accessed by an authorized one or more master equipment items obtained from a set of masters.

[0063] In other words, such a slave device item is therefore called "isolated", and it can only be accessed by one or more authorized master components. In this case, the identifier associated with the slave device will have, for example, a logical value of "1".

[0064] A second desired characteristic for a slave device item is the fact that it can be accessed by any master device from the set of master devices.

[0065] In other words, for this second characteristic, the slave equipment item is not “isolated.” Its identifier therefore has, for example, the logical value “0”.

[0066] Regarding a master item, a first desired state for the master item may be the fact that it is authorized to access any slave item, ie isolated or non-isolated slave item (programming interface or resource).

[0067] In this case, the attribute of the transaction from this master item may take, for example, the logical value "1".

[0068] A second desired state for the master equipment item may be the fact that it is not authorized to access one or more slave equipment items selected from the set of slave equipment.

[0069] In other words, the master item will not, for example, be authorized to access one or more slave items that are "isolated". In this case, the attribute associated with the transaction from such a master item in the second state will take, for example, a logical value of "0".

[0070] Furthermore, the state of each first master item is automatically inherited from the characteristics of its programming interface.

[0071] In other words, in this example, if the programming interface of the first master item has an "isolated" property, the first master item is in its first state, which authorizes it to access any slave device, regardless of whether the slave device is isolated or not.

[0072] If the programming interface of the first master item has the "non-isolated" characteristic, this first master item is automatically in its second state, which does not authorize it to access an isolated slave device (programming interface or slave interface).

[0073] And then, the first master item is configured to assign one of the attribute values ​​to the attributes of these transactions according to the value of the identifier of its programming interface.

[0074] With respect to the second master item, in one embodiment, the attribute values ​​of these transactions are fixed (eg, hard-coded) according to the state that the user desires to give to the second master item.

[0075] Thus in this example, the second master item M40 is in a first state which authorizes it to access any slave device, whether isolated or non-isolated.

[0076] In case the system comprises a further second master item, the latter may be, for example, in a second state which does not authorize it to access the isolated slave.

[0077] Furthermore, as will be seen in greater detail below, in this example, the values ​​of certain identifiers are hard-coded in the system, while other identifiers are programmable depending on, for example, the application for which the system-on-chip is intended and / or the nature of the various resources.

[0078] The system on chip also includes a filtering circuit configured to compare the corresponding attribute value with the value of the identifier of the slave device if there is a transaction intended for the slave device item, and to reject the transaction or not reject the transaction based on the comparison result.

[0079] As will be seen in more detail below, the filtering circuitry includes various filtering logic.

[0080] The system-on-chip SYS further comprises an interconnection circuit 1 coupled between the master device item Mi and the slave device items SMi, Si.

[0081] The interconnection circuit 1 comprises an interconnection matrix 10 having several inputs EM1 , EM2, EM3 and EM40 and several outputs, the inputs EM1 , EM2, EM3 and EM40 being connected to master equipment items M1 , M2, M3 and M40 via buses BSS1 , BSS2, BSS3 and BSS40.

[0082] The first output BS1 is connected via a bus BSS7 to an input E100 of a first demultiplexing stage 100 which in this case has three outputs S100A, S100B and S100C connected to slave interfaces S1 , S2 and S3 respectively.

[0083] A further output BS3 is connected to a further demultiplexing stage 101 which in this case also has three outputs which are connected via three buses BSS4, BSS5 and BSS6 respectively to the three programming interfaces SM1, SM2 and SM3.

[0084] A bus BSS8 connects the output BS3 of the interconnection matrix to a demultiplexing stage 101 .

[0085] Finally, in this example, another output BS2 of the interconnection matrix is ​​connected via a bus 9 to a bank of registers RGPS1 , RGPS3 and RGPSM1 .

[0086] As will be seen in more detail below, this output BS2 is accessible only by transactions from the second master item 40 .

[0087] The structure of such interconnect matrices, which are typically multi-layer interconnect matrices, and the protocols that enable switching and routing of transactions within the interconnect matrices are well known to those skilled in the art.

[0088] For example, those skilled in the art may refer, inter alia, to: Venkateswara Rao et al., entitled “A Framework work on AMBA bus based Communication Architecture to improve the RealTime Computing Performance in MPSoC”, International Journal of Computer Applications (0975-8887), Volume 91-No.5, April 2014, or to a comprehensive presentation on these interconnect matrices delivered by A. Gerstlauer in 2015, and available at: http: / / users.ece.utexas.edu / ~gerstl / ee382v_f14 / lectures / lecture_12.pdf.

[0089] Furthermore, by way of indication but not limitation, an interconnect matrix such as that sold by the company ARM under the reference NIC-400 (version R0p3) may be used.

[0090] The various buses may be of any conventional structure for their part, and for example the AHB bus uses a protocol such as described in the document "AMBA 3 AHB-Lite Protocol V1.0 Specification" by ARM Corporation (2001, 2006).

[0091] The register RGPS1 is intended to contain the value of the identifier of the slave interface S1.

[0092] The register RGPS3 is intended to contain the identifier of the slave interface S3 , whereas the register RGPSM1 is intended to contain the identifier of the programming interface SM1 .

[0093] In this case, the values ​​of registers RGPS1, RGPS3 and RGPSM1 are programmable via bus BSS9 by a programming circuit which in this case comprises a programming block MCPM incorporated in the second master item M40 (processor) and a library of registers RGPS1, RGPS3 and RGPSM1.

[0094] In this case, this programming block MCPM is an initialization code intended to be executed during an initialization phase in order to program in particular the contents of the registers RGPS1 , RGPS3 and RGPSM1 bank.

[0095] In some embodiments, the output BS2 of the interconnect matrix 10 is accessible only by the second master item M40 in order to receive programming transactions.

[0096] Furthermore, connection CX (eg, a wire) connects register RGPSM1 to programming interface SM1.

[0097] In this example, it is also assumed that the value of the identifier of the slave interface S2, and the values ​​of the programming interfaces SM2 and SM3 are fixed and hard-coded in registers.

[0098] We will now refer more specifically to Figures 2 to 4 , in order to illustrate in more detail, but still schematically, the internal structure of the programming interface SM1 , the first master item M1 and the demultiplexing stages 100 and 101 .

[0099] The interface SM1 comprises a filtering logic LGS1 coupled to the connection CX.

[0100] This filtering logic LGS1 is configured to compare the value of the identifier of the interface SM1 , which is read in the register RGPSM1 via the connection CX, with the attributes of a transaction arriving on the bus BSS4 .) Based on this comparison, a transaction can be rejected or authorized.

[0101] The connection CX extends into the first master item M1 and more particularly up to a logic LGM1 configured to determine the value of an attribute ATT1 associated with each transaction TR1 delivered by the first master item according to the value of the identifier of the programming interface SM1.

[0102] Therefore, the state of the first master item is automatically inherited from the characteristics of its programming interface.

[0103] More specifically, for example, if the programming interface is what is referred to as an isolated interface, the first master device item will be a device item that is authorized to access any slave device, regardless of whether the slave device is isolated or non-isolated.

[0104] On the other hand, if the interface SM1 is a non-isolated interface, the first master item M1 will automatically be placed in a state that does not allow it to access the isolated slave item.

[0105] The demultiplexing stage 100 also comprises a filtering logic LGCD coupled to a register RGDS2 which, in this example, stores an identifier of the slave interface S2 .

[0106] As indicated previously, in some embodiments, this register RGDS2 is not programmable.

[0107] Therefore, the filtering logic LGCD is configured to compare the attributes of a transaction intended for the slave interface S2 with the identifier of the slave interface S2 , which is stored in the register RGDS2 .

[0108] The demultiplexing stage 100 comprises a further filtering logic LGCM which is coupled to the registers RGPS1 and RGPS3.

[0109] This filtering logic LGCM aims to compare the value of an attribute of a transaction intended for the slave interface S1 with the value of an identifier contained in the register RGPS1 .

[0110] Similarly, in the presence of a transaction intended for the slave interface S3 , the filtering logic LGCM compares the attributes of this transaction with the value of the identifier contained in the register RGPS3 .

[0111] Depending on the results of these comparisons, the transaction or transactions may be rejected.

[0112] In this exemplary embodiment, the demultiplexing stage 101 comprises two registers RGDSM2 and RGDSM3 storing fixed values ​​of identifiers of the programming interfaces SM2 and SM3 respectively, and associated filtering logics LGS2 and LGS3.

[0113] Similar to what has been described above, the filtering logic LGS2 compares the attributes of a transaction intended for the programming interface SM2 with the value of the identifier contained in the register RGDSM2 in order to reject the transaction or not.

[0114] The filtering logic LGS3 compares the attributes of a transaction intended for the programming interface SM3 with the value of the identifier contained in the register RGDSM3 in order to decide on a possible rejection of this transaction.

[0115] The filtering circuit incorporates various filtering logics LGS1, LGCD, LGCM, LGS2 and LGS3.

[0116] Now more specifically with reference to Figures 5 to 9 An example implementation of a method for managing transactional access to various slave equipment items is schematically illustrated.

[0117] As indicated above, and in Figure 5 As illustrated in , in this example, identifiers IDS2, IDSM2 and IDSM3, respectively associated to slave device items S2, SM2 and SM3, are fixed during a hard coding step 50 when the system on chip is produced and are respectively stored in registers RGDS2, RGDSM2 and RGDSM3.

[0118] In the example considered, slave equipment items S2 and SM2 are considered “non-isolated” and therefore have an identifier equal to “0”.

[0119] The first master item M3 is considered to be able to have access to any slave device, whether the latter is isolated or not.

[0120] Therefore, the identifier of the programming interface SM3 is equal to "1".

[0121] Furthermore, because the first master device item M3 may have access to any slave device, the logic incorporated in the device item M3 is configured and hard-coded to assign a value of "1" to the attribute ATT3, which is associated with transactions from the first master device item M3.

[0122] The second master item M40 also has access to any slave, whether the latter is isolated or non-isolated. The attribute ATT40 associated with transactions from this second master item M40 has a hard-coded value of "1".

[0123] The values ​​of the identifiers IDS1, IDS3 and IDSM1 associated with the slave equipment items S1, S3 and SM1, respectively, are themselves programmable.

[0124] In some embodiments, this programming is advantageously performed in an initialization phase 60 during the execution of an initialization program. This programming is performed by the execution of an initialization program code (programming block) MCPM contained in the second master item M40.

[0125] Also, in this example, it is assumed that the slave interface S1 is selected to be non-isolated, and the slave interface S3 is selected to be isolated.

[0126] Furthermore, the programming interface SM1 associated with the first master item M1 is also selected to be isolated, and in such a way that the first master item M1 can have access to any slave device, whether it is isolated or non-isolated.

[0127] Under these conditions, the programming block MCPM assigns the value “1” to the identifiers IDS3 and IDSM1 to be stored in the registers RGPS3 and RGPSM1.

[0128] The programming block assigns the value "0" to the identifier IDS1 stored in the register RGPS1.

[0129] Finally, the logic LGM1 present in the first master item M1 is configured to assign the value “1” to the attribute ATT1 associated with each transaction TR1 coming from this first master item M1 .

[0130] Usually, as in Figure 7 As illustrated in , in the presence of a transaction TRi and its attribute ATTi, various filtering logics perform a comparison 70 between the value of the attribute ATTi and the value of the identifier IDSi of the slave interface for which the transaction is intended.

[0131] Depending on the result of the comparison, access to the slave interface Si can be granted (step 71) or denied (step 72).

[0132] More specifically, in this implementation, if Figure 8 As illustrated in , a transaction TRi associated with an attribute ATTi equal to "1" can be delivered to any slave device SMj or Sj (step 80).

[0133] On the other hand, Fig. 9 As illustrated in , a transaction TRi assigned an attribute ATTi equal to "0" and intended for a slave device item SMj or Sj can be delivered only depending on the result of the comparison between the attribute ATTi and the identifier IDSMj or IDSj of the slave device item under consideration.

[0134] More specifically, in step 90 it is verified whether the identifier adopts the value "1".

[0135] If it is the case that the value "1" is used, a rejection of the transaction TRi (step 92) will occur since, in this case, the transaction is intended for the isolated slave item and comes from a master item that is not authorized to access the isolated slave item.

[0136] However, if the identifier IDSMj or IDSj is equal to 0, access to the transaction will be granted (step 91).

[0137] The invention is not limited to the embodiment that has just been described, but encompasses all variants thereof.

[0138] It is therefore also possible to increase the number of programmable registers, for example by increasing the number of "wired" connections CX, so that the values ​​of all identifiers of all slave equipment items are programmable.

[0139] Furthermore, with regard to the programming interface or programmable values ​​of the interface SMi, it is also conceivable to replace the wired connection CX by commands via the demultiplexing stage 101 and the unused and available signals of the buses BSS8 and BSS4 to BSS6.

[0140] Other variations are possible, such as replacing a logical value "0" with a logical value "1" and vice versa.

Claims

1. A system on chip, comprising: A set of master equipment items, including a plurality of first master equipment items, each of which has a corresponding programming interface; Multiple slave device items, including: a slave interface of the first slave device item, and the respective programming interfaces of the plurality of first master equipment items, wherein each respective slave equipment item of the plurality of slave equipment items has an associated identifier capable of taking a first value and a second value, the first value and the second value corresponding to a first characteristic and a second characteristic of the respective slave equipment item; an interconnection circuit coupled between the set of master equipment items and the slave interface of the first slave equipment item, wherein each master equipment item in the set of master equipment items is configured to transmit transactions to a slave equipment item in the plurality of slave equipment items, wherein each transaction transmitted by a respective first master equipment item is assigned an attribute, the attribute being able to adopt a first attribute value and a second attribute value corresponding to a first state and a second state of the respective first master equipment item, wherein each respective first master equipment item in the plurality of first master equipment items automatically inherits a characteristic of the respective programming interface of the respective first master equipment item, the characteristic of the respective programming interface corresponding to the identifier associated with the respective programming interface, and wherein each respective first master equipment item is configured to assign an attribute value to the attribute assigned to the transaction transmitted by the respective first master equipment item according to the value of the identifier associated with the respective programming interface; and A filtering circuit is configured to compare the attribute value of the first transaction and the value of the identifier to produce a comparison result when a first transaction exists, wherein the first transaction is intended for a slave device item among the plurality of slave device items, the identifier is associated with the intended slave device item, and the filtering circuit is configured to reject or allow the transaction based on the comparison result.

2. A system on chip according to claim 1, wherein the value of the identifier associated with the first slave interface of the slave interfaces of the first slave device item and the value of the identifier associated with the first programming interface are programmable, and the first programming interface is associated with the first first master device item of the multiple first master device items, and the system on chip also includes a programming circuit configured to program the value of the identifier associated with the first slave interface and the value of the identifier associated with the first programming interface via the interconnection circuit.

3. The system on chip according to claim 2, wherein the programming circuit comprises: a first programmable register associated with said first programmable interface and configured to contain said value of said identifier associated with said first programming interface; a second programmable register associated with said first slave interface and configured to contain said value of said identifier associated with said first slave interface; a programming block configured to program the first programmable register and the second programmable register via the interconnection circuit; as well as A connection link is coupled between the first programmable register and the first programming interface.

4. A system on chip according to claim 3, wherein the set of master device items also includes a second master device item lacking a programming interface, the second master device item is coupled to the interconnection circuit, the second master device item is configured to assign a fixed value to the attribute assigned to the transaction, the transaction is transmitted by the second master device item, the fixed value is taken from the first attribute value and the second attribute value, and wherein the second master device item includes the programming block.

5. The system on chip according to claim 3, wherein the connection link extends into the first first master device item.

6. A system on chip according to claim 3, wherein the interconnect circuit includes an interconnect matrix, coupled to the set of master device items, and a stage including a demultiplexer, the demultiplexer having an input coupled to an output of the interconnect matrix and a plurality of outputs coupled to the slave interface of the first slave device item; and wherein the filtering circuit includes filtering logic, the filtering logic is located in the stage and coupled to the second programmable register, and is configured to compare the attribute value of the first transaction with the value of the identifier to produce a comparison result, the value of the identifier being associated with the intended slave device item.

7. The system on chip of claim 2, wherein the programming circuit is configured to program the value of the identifier associated with the first slave interface and the value of the identifier associated with the first programming interface during an initialization phase of the system on chip.

8. The system on chip of claim 1 , wherein the set of master device items further comprises a second master device item lacking a programming interface, the second master device item being coupled to the interconnection circuit, the second master device item being configured to assign a fixed value to the attribute assigned to the transaction, the transaction being transmitted by the second master device item, the fixed value being taken from among the first attribute value and the second attribute value.

9. The system on chip of claim 1, wherein the set of master device items comprises L master device items, where L is an integer greater than 1, wherein the first characteristic of the corresponding slave device item comprises permission to be accessed by M authorized master device items in the set of master device items, where M is an integer greater than or equal to 1 and less than M, and wherein the second characteristic of the corresponding slave device item comprises permission to be accessed by any master device in the set of master device items.

10. The system on chip of claim 9, wherein the first state of the corresponding master device item comprises authorization to access any slave device, and wherein the second state of the corresponding master device item comprises a lack of authorization to access one or more of the plurality of slave device items.

11. The system on chip according to claim 10, wherein: the attribute of a transaction from a first one of the plurality of first master equipment items having a first attribute value corresponding to the first state when the identifier associated with a first programming interface has the first value corresponding to the first characteristic, the first programming interface being associated with the first one of the plurality of first master equipment items having a first attribute value corresponding to the first state; when the identifier associated with the first programming interface has the second value corresponding to the second characteristic, the attribute of the transaction from the first first master item has a second attribute value corresponding to the second state; The filtering circuit is configured to allow transactions that have been assigned an attribute having the first attribute value and are intended for any slave device item of the plurality of slave device items; as well as The filtering circuit is configured to reject transactions that have been assigned an attribute having the second attribute value and that are intended for a slave device item for which the associated identifier has the first value.

12. The system on chip of claim 1 , wherein the first state of the corresponding master device item comprises authorization to access any slave device, and wherein the second state of the corresponding master device item comprises a lack of authorization to access one or more of the plurality of slave device items.

13. The system on chip of claim 1, wherein the system on chip is a microcontroller.

14. A method for access management of a system on chip, the system on chip having a plurality of master device items and a plurality of slave device items, the method comprising: transmitting, via the interconnect circuit, a first transaction from a first master item of the plurality of master items of equipment to a first slave item of the plurality of slave items of equipment, wherein each respective slave item of the plurality of slave items of equipment has an associated identifier, the associated identifier being capable of taking a first value and a second value, the first value and the second value corresponding to a first characteristic and a second characteristic of the respective slave item of equipment, wherein the plurality of slave items of equipment include a first programming interface, the first programming interface being associated with the first master item of equipment, wherein the first programming interface has an associated first identifier, and wherein the first slave item of equipment has an associated second identifier; automatically inheriting, by the first master item, a characteristic of the first programming interface, the characteristic of the first programming interface corresponding to the first identifier; assigning a first attribute to the first transaction, wherein the first attribute can take on first attribute values ​​and second attribute values ​​corresponding to first and second states of the first master item; assigning a first attribute value to the first attribute based on the value of the first identifier; comparing the first attribute value and the value of the second identifier to generate a first comparison result; as well as Based on the first comparison result, the first transaction is denied or allowed.

15. The method of claim 14, further comprising programming the value of the second identifier and the value of the first identifier via the interconnect circuit.

16. The method of claim 15, wherein programming the value of the second identifier and the value of the first identifier comprises: During an initialization phase of the system on chip, the value of the second identifier and the value of the first identifier are programmed.

17. The method according to claim 14, further comprising: transmitting a second transaction from a second master item of the plurality of master items to the first slave item, the second master item lacking an associated programming interface; assigning a second attribute to the second transaction, the second attribute having a second attribute value, the second attribute value being fixed; comparing the second attribute value and the value of the second identifier to produce a second comparison result; as well as Based on the second comparison result, the second transaction is denied or allowed.

18. A method according to claim 14, wherein the plurality of slave device items further include a second slave device item, wherein the first state of the first master device item includes authorization to access the first slave device item and the second slave device item, and wherein the second state of the first master device item includes a lack of authorization to access the second slave device item.

19. A microcontroller comprising: A plurality of master equipment items, including a first master equipment item; a plurality of slave equipment items, including a first slave equipment item, and a first programming interface associated with the first master equipment item, wherein each respective slave equipment item of the plurality of slave equipment items has an associated identifier, the associated identifier being capable of taking a first value and a second value, the first value and the second value corresponding to a first characteristic and a second characteristic of the respective slave equipment item, wherein the first programming interface is configured to have an associated first identifier, and wherein the first slave equipment item is configured to have an associated second identifier; interconnection circuitry, wherein the first master item of equipment is configured to transmit a first transaction to the first slave item of equipment via the interconnection circuitry, wherein the first transaction is configured to have an assigned attribute, the assigned attribute being capable of taking a first attribute value and a second attribute value corresponding to a first state and a second state of the first master item of equipment, wherein the first master item of equipment automatically inherits a characteristic of the first programming interface, the characteristic of the first programming interface corresponding to the first identifier, and wherein the first master item of equipment is configured to assign a first attribute value to the attribute assigned to the first transaction based on the value of the first identifier; as well as The filtering circuit is configured to compare the first attribute value with the value of the second identifier to generate a first comparison result when the first transaction exists, and to deny or allow the first transaction according to the first comparison result.

20. The microcontroller of claim 19, wherein the value of the first identifier and the value of the second identifier are programmable, the microcontroller further comprising a programming circuit configured to program the value of the first identifier and the value of the second identifier via the interconnection circuit.

21. The microcontroller of claim 20, wherein the programming circuit comprises: a first programmable register associated with said first programming interface and configured to contain said value of said first identifier; a second programmable register associated with said first slave device item and configured to contain said value of said second identifier; a programming block configured to program the first programmable register and the second programmable register via the interconnection circuit; as well as A connection link is coupled between the first programmable register and the first programming interface.

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