Stacked element, memory chip, memory element and addressing method

Abstract

A stacked element and a layout design method for an element are provided, the element including two or more identical structures. Each element may have a first die, a second die stacked on the first die, and a third die stacked on the second die. The second die may include a first through silicon via (TSV) and a first circuit, and the third die includes a second TSV and a second circuit. The first TSV and the second TSV may extend linearly together. The first and second circuits may each be a logic circuit having a comparator and a counter for generating a die identifier. The counters of the corresponding element die may be connected in series between the die. Each die may be manufactured using the same mask, but retain a unique logic identifier. A given die in a die stack may therefore be addressed by a single path in the same die layout.

Description

Technical Field

[0001] The present disclosure relates to a stacked element, a memory die, a memory element and an addressing method. Background Art

[0002] The manufacture of integrated circuits (ICs) requires masking techniques, such as the use of masks to etch and process circuit designs. However, due to the ever-shrinking and more complex requirements of integrated circuits, component design is more challenging than ever before. The number of circuit components required in a fixed integrated circuit space is becoming more and more complex. As a result, the cost of mask sets for advanced integrated circuit processes has generally increased, especially as integrated circuit designs shrink. With the ever-increasing mask production costs being an increasing factor in the cost of integrated circuit chips, saving mask costs is a key focus of integrated circuit design.

[0003] Likewise, mask costs can be a significant contribution when an engineering change order (ECO) is required for a new integrated circuit design. To make incremental changes at the wafer level, the design may incorporate spare or dummy cells, including unused wires or metal to minimize the need for new masks in metal-only ECOs. However, the redundancy involved in using dummy lines and the like does not reduce mask costs at the package level. Summary of the invention

[0004] According to some embodiments of the present disclosure, a stacked component includes a first die, a second die, and a third die. The second die is stacked on the first die. The second die includes a first through silicon via (TSV) and a first circuit. The first circuit includes a first memory and a first counter for assigning a first binary address to the first memory. The third die is stacked on the second die. The third die includes a second TSV and a second circuit. The second circuit includes a second memory and a second counter for assigning a second binary address to the second memory. The first TSV and the second TSV extend linearly together.

[0005] According to some embodiments of the present disclosure, a memory die includes: a first through silicon via (TSV) including a first input port; a first output port; a second TSV including a second input port and a second output port; a memory circuit; and a logic circuit. The first input port is used to receive a first input value as a memory die address. The second input port is used to receive a second input value. The logic circuit is used to compare the first input value with the second input value.

[0006] According to some embodiments of the present disclosure, an addressing method includes: transmitting a first address signal, a data signal, and a control signal to a first memory element by a processor; receiving the first address signal by the first memory element through a first through silicon via (TSV); receiving the control signal by the first memory element through a second TSV; generating a second address signal by the first memory element based on the first address signal; determining whether to enable a memory circuit by the first memory element based on the control signal; outputting a second address signal to a second memory element by the first memory element; and outputting a control signal to the second memory element by the first memory die through the second TSV.

[0007] According to some embodiments of the present disclosure, a stacked component includes a processing die and a memory stack. The processing die includes: a microprocessor circuit formed on a front side of the processing die; and an electrical connector formed on a back side of the processing die. The memory stack is disposed above the processing die. The memory stack includes a plurality of memory dies. Each memory die includes: a memory circuit formed on a front side of the memory die; an interconnect structure formed on a back side of the memory die; a through silicon via (TSV) coupling the memory circuit to the interconnect structure; and a counter for assigning a binary address to the memory die.

[0008] According to some embodiments of the present disclosure, a memory element includes a first memory die and a second memory die. The first memory die includes: a first memory circuit formed on the front side of the first memory die; a first interconnect structure formed on the back side of the first memory die; a first through-silicon via (TSV) coupling the first memory circuit to the first interconnect structure; and a first counter formed on the front side of the first memory die. The second memory die is on the first memory die. The second memory die includes: a second memory circuit formed on the front side of the second memory die; a second interconnect structure formed on the back side of the second memory die; a second TSV coupling the second memory circuit to the second interconnect structure; and a second counter formed on the front side of the second memory die, the second counter being electrically connected in series with the first counter. The first memory circuit and the second memory circuit are different from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The various aspects of this disclosure should be read in conjunction with the attached Figure 1 The following embodiments will be best understood when read together. It should be noted that, according to common practice in the industry, the various features are not drawn to scale. In fact, for the sake of clarity of illustration and discussion, the size of the various features may be arbitrarily increased or reduced.

[0010] Figure 1 is a diagram of a system on an integrated chip structure including a memory element according to some embodiments;

[0011] Figure 2 is a diagram of a system on an integrated wafer structure according to some embodiments;

[0012] Figure 3 is a diagram of a system on an integrated chip structure including non-volatile address storage according to some embodiments;

[0013] Figure 4 is a diagram of a system on an integrated wafer structure including address identification provided by through silicon vias according to some embodiments;

[0014] Figure 5 is a diagram of silicon on an integrated wafer structure with coextensive through silicon vias according to some embodiments;

[0015] Figure 6 A diagram showing a cross section of a device having different through-silicon via (TSV) configurations according to some embodiments;

[0016] Figure 7 is a diagram of the same design layout of a component die including a logic circuit according to some embodiments;

[0017] Figure 8 A diagram of a circuit arrangement of a system on an integrated wafer structure according to some embodiments;

[0018] Fig. 9 is a diagram of an arrangement of a system on an integrated die structure including device dies each having logic circuits and a memory array according to some embodiments;

[0019] Fig.10 A flow chart of a method for addressing on integrated wafer structures having the same design layout according to some embodiments.

[0020] The accompanying drawings, which are incorporated in the embodiments of the present disclosure and form a part of this specification, illustrate the embodiments of the present disclosure and, together with the description, further serve to explain the principles of the embodiments of the present disclosure and to enable those skilled in the art to make and use the embodiments of the present disclosure.

[0021]

Explanation of symbols

[0022] 100...SOIC package

[0023] 110...Memory chips

[0024] 112...Addressing circuit

[0025] 115...Through Silicon Via (TSV)

[0026] 120...Memory chips

[0027] 122...Addressing circuit

[0028] 125...Through Silicon Via (TSV)

[0029] 130...Memory chips

[0030] 132...Addressing circuit

[0031] 135...Through Silicon Via (TSV)

[0032] 140...Memory chips

[0033] 142...Addressing circuit

[0034] 145...Through Silicon Via (TSV)

[0035] 150...Processor chips

[0036] 155...Through Silicon Via (TSV)

[0037] 210...Bit unit device die

[0038] 211...Multiplexer

[0039] 212...Reverser

[0040] 215...TSV

[0041] 215.1...Address signal

[0042] 215.2...Address signal

[0043] 215.3...Address signal

[0044] 215.4...Address signal

[0045] 215.5...Address signal

[0046] 215.6...Address signal

[0047] 215.7...Address signal

[0048] 215.8...Address signal

[0049] 220...Bit unit device die

[0050] 221...Multiplexer

[0051] 222...Reverser

[0052] 310...Bit unit device die

[0053] 311...Multiplexer

[0054] 312...Reverser

[0055] 313...Non-volatile storage structure

[0056] 315...TSV

[0057] 315.1...Control signal

[0058] 315.2...Control signal

[0059] 315.3...Control signal

[0060] 315.4...Control signal

[0061] 315.5...Control signal

[0062] 315.6...Control signal

[0063] 315.7...Control signal

[0064] 315.8...Control signal

[0065] 320...bit unit device die

[0066] 321...Multiplexer

[0067] 322...Reverser

[0068] 323...Non-volatile storage structure

[0069] 400...Memory structure

[0070] 410...First memory chip

[0071] 411...Multiplexer

[0072] 412...Reverser

[0073] 413...Connection path

[0074] 415...TSV

[0075] 420...Second memory chip

[0076] 422...Reverser

[0077] 423...Connection path

[0078] 430...Third memory chip

[0079] 432...Reverser

[0080] 433...Connection path

[0081] 440...4th memory chip

[0082] 441...Multiplexer

[0083] 442...Reverser

[0084] 443...Connection path

[0085] 500...SOIC component unit

[0086] 510...First Component Die

[0087] 515...TSV

[0088] 520...Second component chip

[0089] 530...Third component chip

[0090] 532...CE signal circuit

[0091] 540...Fourth component chip

[0092] 542...CE signal circuit

[0093] 550...Processor chip

[0094] 610...Memory device chips

[0095] 612...CE wiring

[0096] 615...TSV bus

[0097] 620...Memory device chips

[0098] 622...CE wiring

[0099] 630...Memory device chips

[0100] 633...CE wiring

[0101] 640...Memory device chips

[0102] 642...CE wiring

[0103] 650...Processor chip

[0104] 700...Memory stack

[0105] 707...Control logic signal

[0106] 710...Memory chip

[0107] 711...Counter

[0108] 712...Comparator

[0109] 715...CE signal line

[0110] 720...Memory chip

[0111] 721...Counter

[0112] 722...Comparator

[0113] 730...Memory chip

[0114] 731...Counter

[0115] 732...Comparator

[0116] 740...Memory chips

[0117] 741...Counter

[0118] 742...Comparator

[0119] 750...processor chip

[0120] 800...Memory circuit

[0121] 801...Memory address signal

[0122] 802...Incremented memory address signal

[0123] 803...Memory operation instructions

[0124] 804...Memory output

[0125] 805...CE signal

[0126] 810...Memory addressing circuit

[0127] 811...Counter

[0128] 812...Comparator

[0129] 813...Comparator output

[0130] 814...Memory array

[0131] 900...Memory components

[0132] 910...The first memory chip

[0133] 911...Counter

[0134] 912...Comparator

[0135] 914...Memory array

[0136] 920...Second memory chip

[0137] 922...Comparator

[0138] 924...Memory array

[0139] 930...Third memory chip

[0140] 940...4th memory chip

[0141] 941...Counter

[0142] 942...Comparator

[0143] 944...Memory array

[0144] 950...processor chip

[0145] 951...Memory address initialization signal

[0146] 952...CE signal

[0147] 954...data_out signal line

[0148] 955...data_in signal

[0149] 956...Memory operation command signal

[0150] 957...Memory operation address signal

[0151] 1000...Method

[0152] 1002...Operation

[0153] 1003...Operation

[0154] 1004...Operation DETAILED DESCRIPTION

[0155] Embodiments of the present disclosure are directed to design methods, for example, design methods for three-dimensional integrated circuit (3DIC) designs. As the cost of mask sets for integrated circuit designs increases, the focus of integrated circuit design is to reduce mask requirements. Embodiments of the present disclosure achieve redundancy between individual mask units in a 3DIC package, thereby improving the efficiency, cost, and yield of 3DIC designs. In embodiments of the present disclosure, 3DIC bit cells of a 3DIC package can be uniquely addressed despite having the same structure. Therefore, the same mask can be used in other independent and unique 3DIC bit cells.

[0156] The benefits of the design methods disclosed in the embodiments of the present disclosure are reduced mask requirements and cost-effectiveness without depending on a specific integrated circuit process technology platform. Also, when migrating from one process technology generation to the next generation, the integrated circuit design can maintain the same method according to the embodiments of the present disclosure. The methods and structural concepts described in the embodiments of the present disclosure do not depend on the specific structural configuration of the corresponding component units. Therefore, the methods can be applied to various 3DIC and integrated circuit system (SOIC) packaging.

[0157] Embodiments of the present disclosure are directed to reducing mask requirements and costs where a device includes multiple parts (e.g., dies), some of which share common logic functions. For example, a memory system (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), magnetoresistive random access memory (MRAM), etc.) may include four bit cell device dies and a controller (or application processor) chip having the same logic functions. The bit cell device dies may have the same design (e.g., the same structural layout).

[0158] In other designs, the bit cell device die may require different functions to enable the bit cell to be uniquely addressed. For example, the wiring between the various bit cell device dies may be different to achieve the addressing of the respective bit cell device dies. In the case of different wiring, the addressing of the bit cell device dies may be performed by connections through different through silicon via (TSV) channels, resulting in the manufacture of bit cell device dies with different light masks.

[0159] In some embodiments, the device may include a four-bit cell device die, which may be a memory die and a controller device die (also referred to as a processor, processor die, or application processor in the disclosed embodiments) having twice the area of ​​each bit cell device die. Where, for example, the controller die counts two mask cells and each bit cell device counts one mask cell, the disclosed embodiments reduce the masking requirements by 50% compared to other designs. Thus, implementing the same design for each individual bit cell device die (also referred to as a memory device die in the disclosed embodiments) reduces the masking requirements to 3 mask cells compared to 6 mask cells in other designs.

[0160] Embodiments of the present disclosure include bit cell architectures that reduce manufacturing complexity, mask requirements, and costs. Embodiments of the present disclosure include uniform bit cell device die that retain unique address identifiers that can be manufactured using a single or reduced mask set. Embodiments described in the present disclosure include, but are not limited to, integrated circuit die such as SOIC, 3DIC, SRAM, DRAM, MRAM, processors, and the like.

[0161] In some embodiments, the SOIC structure includes an active (e.g., having one or more transistors) die stacked one above the other and interconnected vertically using TSVs. The SOIC structure may be a three-dimensional integrated circuit ("3DIC"). For example, a 3DIC includes a stack of similar active die, such as a stack of memory die with a processor (controller logic) on a separate die (such as a bottom die). In alternative embodiments, the 3DIC may include a stack of different wafers. The die may be in a stacked face to back (F2B) form. If in a stacked F2B form, at least two die are stacked, one on top of the other, wherein the active areas of the die are each in the same orientation (e.g., on the face surface) and metallized on the opposite surface. Here, the lower die includes metallization on the back surface of the substrate and an electrical connector (e.g., a hybrid bonding connection, a microbump, etc.) for connecting the upper die (e.g., the first die) to the metallization. The TSVs pass through the substrate of the lower die to connect the electrical connector on the upper die to the active area of ​​the lower die (e.g., the second die) via the back surface metallization. Alternatively, the die can be in a face-to-face (F2F) stack, where the active areas of the lower die and the upper die face each other with an electrical connector that provides connectivity between the die.

[0162] Figure 1An SOIC package 100 according to some embodiments is shown. The SOIC package 100 includes memory dies 110, 120, 130, and 140 stacked on a processor die 150 (which may also be referred to as an application processor (AP) die 150). The memory dies 110, 120, 130, and 140 may include one or more SRAM devices, DRAM devices, MRAM devices, other suitable memory devices, or a combination of the above devices. Before stacking the memory dies 110 to 140, the contact surface of each memory die is planarized and the memory dies are bonded at the contact surfaces using a suitable bonding technique, such as hybrid bonding, fusion bonding, anodic bonding, direct bonding, room temperature bonding, pressure bonding, and / or a combination of the above techniques. Each of the memory dies 110 to 140 has a memory function for storing memory data and an addressing function for generating a unique memory die identifier. Data may be input or retrieved by addressing the unique memory die identifier of the corresponding memory die. Processor die 150 may include one or more microprocessors, central processing units, graphics processing units, other suitable processing units, or a combination thereof.

[0163] like Figure 1 As shown in FIG. 1 , the memory die 110 to 140 and the processor die 150 include through silicon vias (TSVs) 115, 125, 135, 145, and 155, respectively. The memory die 110 to 140 may include addressing circuits 112, 122, 132, and 142, respectively. The structures of the memory die 110 to 140 may be the same. That is, the memory die 110 may have the same structure as the memory die 120, etc.

[0164] According to some embodiments, memory dies 110-140 may be stacked in such a manner that their structural elements overlap linearly when arranged on processor die 150. For example, TSV 115 of memory die 110 may be linearly coextensive with TSV 125 of memory die 120. Likewise, logic circuit 112 of memory die 110 overlaps with logic circuit 122 of memory die 120, and so on. Memory dies 110-140 may be stacked such that TSV 115 linearly coextensive (e.g., in the y-direction).

[0165] Electrical connectors may carry data and address signals through TSVs 115 , 125 , 135 , and 145 to each corresponding memory die. Figure 1 A single TSV is shown in each corresponding memory die, wherein the TSVs are linearly coextensive with respect to each other. Alternatively, each memory die may include multiple TSVs, wherein the multiple TSVs of the memory die overlap and are linearly coextensive.

[0166] A disadvantage of other device architectures is that certain control signals must be uniquely transmitted to each memory die used in the device package to function. For example, even when address and data lines are shared by each memory die, the chip enable (CE) signal used to select each bit cell device die is not shared.

[0167] Embodiments of the present disclosure provide a SOIC package (such as 3DIC, including SRAM, DRAM, MRAM or other memory circuits) that allows signals to be transmitted or received by a common or identical structural arrangement of each individual bit cell device die without excluding unique addressing of each memory device. For example, CE can be transmitted to each bit cell device die in common while achieving the desired selection of each bit cell device die.

[0168] Figures 2 to 4 A method for using TSVs to selectively identify bit cell device die addresses is illustrated. The method includes using a multiplexer to address two bit cell device dies in a portion of an exemplary integrated circuit package. For example, Figure 2 As shown in FIG. 2 , each of the bit cell device dies 210 and 220 includes a multiplexer, a comparator, and a TSV 215 . Each of the bit cell device dies 210 and 220 can be selectively addressed via address signals 215 . 1 to 215 . 8 transmitted through the TSV 215 .

[0169] The bit cell device die 210 includes a multiplexer 211, an inverter 212, and TSVs 215 corresponding to signals 215.1 to 215.8. In an embodiment, each bit cell device die may have the same structure. For example, TSVs 215 may be formed as a TSV architecture across multiple bit cell device dies using the same or a reduced number of masks. As a result, the bit cell device dies may be addressed without regard to a particular bit cell device arrangement or organization. For example, the bit cell device dies 210 and 220 may be similar to the bit cell device dies 210 and 220. Figure 1 , stacked vertically (e.g., in the y-direction) as shown in , or arranged in any other suitable arrangement. Despite the specific arrangement, embodiments of the present design layout method form the same bit cell element die structure. By providing the same die structure, the same layout design method of the present embodiment allows a single or reduced mask set to be used during manufacturing. In addition, providing an integrated circuit design around the same bit cell set simplifies design or redesign, for example, when ECO is required.

[0170] like Figure 2As further shown in FIG. 2 , bit cell component die 210 may be assigned address “00”, in which case multiplexer 211 of bit cell component die 210 selects a connection path through TSV 215. In this case, multiplexer 211 may send a logic high value (e.g., “1”) through the connection path of signal 215.8. Similarly, bit cell component die 220 includes multiplexer 221, inverter 222, and TSV 215. In this example, bit cell component die 220 may be assigned address “01”, achieving a logic high value through the connection path of signal 215.7. In this way, each bit cell component die may be independently addressed using a common arrangement connection path of TSV 215.

[0171] In addition, if Figure 3 As shown in FIG. 1 , the address information of the bit cell device die 310 and 320 can be assigned in the memory using non-volatile storage structures 313 and 323, respectively. The bit cell device die 310 and 320 include multiplexers 311 and 321, inverters 312 and 322, and control signals 315.1 to 315.8 transmitted via TSV 315, respectively. The bit cell device die 310 is assigned address “00”, which is stored in the non-volatile storage structure 313; and the bit cell device die 320 is assigned address “01”, which is stored in the non-volatile storage structure 323.

[0172] Embedding non-volatile address information in each individual device die (e.g., memory device die 310 and 320) allows location information for each bit cell to be protected. For example, address information may be maintained in an electrical fuse or other non-volatile storage structure against failures due to electrical events such as overcurrent, overvoltage, short circuit, and other electrical failures. In some embodiments, location information is maintained in device die 310 and 320 by non-volatile storage structures 313 and 323. The embedded, non-volatile storage structure may be, but is not limited to, an electrical fuse, an anti-fuse, a floating gate, or other suitable storage structure. Bit cell device die 310 and 320 have the same structural arrangement, including TSVs and address elements. Thus, the disclosed layout design method simplifies manufacturing techniques and reduces masking requirements.

[0173] In some embodiments, each bit cell device die 310 and 320 share the same structure and can be formed using a TSV architecture that spans across multiple bit cell device dies. Figure 3 3. Although a vertical stacked arrangement is shown in FIG. 3, bit cell device die 310 and 320 may be stacked in any other suitable arrangement. Despite the specific arrangement, embodiments of the present design layout method form the same bit cell device die structure, thereby allowing for simplified manufacturing techniques and mask usage.

[0174] Figure 4 A memory structure 400 according to some embodiments is shown. The memory structure 400 includes a first memory die 410, a second memory die 420, a third memory die 430, and a fourth memory die 440. Each of the memory die 410 to 440 includes multiplexers 411 to 441 and inverters 412 to 442, respectively, and the multiplexers and inverters are used to convert the memory addresses provided to each memory die.

[0175] In some embodiments, memory die 410-440 may share the same structure and may be stacked vertically (e.g., in the y-direction). In other embodiments, memory die 410-440 may be arranged in any suitable arrangement (such as a side-to-side arrangement) while retaining the benefits of a simplified formation process and reduced masking requirements.

[0176] like Figure 4 As shown in FIG. 1 , stacking the individual memory dies 410 to 440 allows the dies to be arranged in such a way that the TSVs and connecting lines can extend linearly together (e.g., in the y direction). In this way, the dies can be connected to provide simplified addressing. The memory dies 410 to 440 can be connected so that four identically structured dies have different address information. Specifically, as Figure 4 As shown in and described in more detail below, memory dies 410-440 may be individually connected to a processor die (not shown) via TSVs such that each respective die retains unique address information.

[0177] For example, the first memory die 410 may include TSVs 415 (e.g., a three-bit TSV bus) connected to another die through an electrical connector (connection path 413), which may be a control logic, such as an application processor (also referred to as a processor die in the disclosed embodiment, not shown). The connection path 413 runs through each TSV to the processor die. Therefore, a logic high signal (e.g., "1") can be transmitted through each TSV 415 of the first memory di3 410 through the processor die. The resulting logic through the TSVs generates a binary signal "111", providing a unique address "7" to the first memory die 410.

[0178] In some embodiments, each of the first and fourth memory dies 410 to 440 is coupled to an adjacent die by similar but different connection paths. Connection paths 413, 423, and 433 may include electrical connections formed by any electrical conductor, such as one or more metals (e.g., copper, metal alloys, or any combination thereof). Connection paths 413, 423, and 433 may be formed by any connector forming process. In some embodiments, connection paths 413, 423, and 433 are formed by a hybrid bonding (HB) process.

[0179] Connection paths 413, 423, 433, and 443 are unique and include unique address identifiers. In each memory die 410 to 440, the connection paths used for addressing are connected differently in the TSV stack. For example, the TSVs of each memory die may be internally pulled down and assigned a logic low value (e.g., "0"); while the electrically connected TSVs are assigned a logic high value (e.g., "1") applied by the processor die. Therefore, a different address identifier may be provided for each memory die.

[0180] Specifically, the TSV corresponding to the most significant bit (MSB) is internally pulled down (e.g., pulled down to ground or 0V), while the remaining TSVs are HB connected (connected by a hybrid bonding process). Therefore, the MSB is operable to provide such that a logic low (e.g., "0") is maintained at the MSB of the memory die 420. The resulting logic through the TSV 415 generates a binary signal "011", providing a unique address "3" to the second memory die 420. Similarly, changing the connection path 433 so that only the least significant bit (LSB) is electrically connected through the TSV bus 415 generates a binary signal "001", providing a unique address "1" to the third memory die 430. Finally, the TSV bus (e.g., connection path 443) of the fourth memory die 440 is not connected. Each corresponding bit of the corresponding TSV is internally pulled down to, for example, ground or 0V. A unique address "0" is thereby assigned.

[0181] Thus, unique address information can be provided to two or more memory dies that have been formed by simplifying mask requirements without requiring substantial structural differences. Changing the connectivity of the three-wide TSV bus (TSV 415) between each of the first to fourth memory dies 410, 420, 430, and 440 allows each memory die to be uniquely addressed. Each memory die can ultimately be addressed to inverters 412, 422, 432, and 442, respectively, by a processor die for memory operations, such as via a chip enable connection (not shown).

[0182] like Figure 4As shown in , vertically stacked memory dies 410 to 440 achieve other advantages and performance improvements in reducing the critical connection path of the signal. That is, vertical stacking allows the shortest connection path to be achieved by arranging TSVs in overlapping or linearly co-extending respective memory dies 410 to 440. 3DIC stacked in this manner and controlled by reducing the critical connection path achieves performance improvements relative to higher bandwidth and power consumption. By providing a stacked structure, memory dies and connections can be arranged in three dimensions, thereby achieving greater diversity of connection paths (and shorter connection paths), as well as scalability. Therefore, greater memory density, faster access time, reduced power consumption, and faster data transfer can be achieved.

[0183] Figure 5 1. The arrangement of a SOIC component unit 500 with co-extending TSVs 515 is illustrated in accordance with some embodiments. The SOIC component unit 500 includes a processor die 550, which is illustrated as the bottom die in the stack. The processor die 550 includes a controller for providing processing and input / output functions. The SOIC component unit 500 also includes a first component die 510, a second component die 520, a third component die 530, and a fourth component die 540. Although the TSVs 515 are arranged vertically, other components of each component die may have a different arrangement. In this example, the CE signal circuits 532 and 542 of the third component die 530 and the fourth component die 540 may be different or have different structural arrangements, as described below with respect to FIG. Figure 6 Describe in more detail.

[0184] Figure 6 The stack of memory dies is shown to include memory elements of different circuits. In some embodiments, the memory elements may be SRAM, DRAM, MRAM, or other memory elements. The memory elements may include, for example, four memory dies stacked on top of each other, the stack being arranged on top of control logic, also known as an application processor (AP) or processor die. Figure 6 As shown in , the memory element may include a stack of memory cubes (specifically, memory element die 610, 620, 630 and 640) that are stacked vertically and connected to a processor die 650. The processor die 650 sends control signals, address signals, and data signals to each memory element die. Addresses and data may be shared with four memory element dies. However, some control signals are not shared. For example, a chip enable signal (CE) provided to turn on each corresponding memory element die for memory operations is not shared.

[0185] To enable each corresponding memory die for memory operation, the processor die 650 may provide a CE signal to one or more memory dies 610 to 640. The CE signal may be provided by a non-uniform TSV bus 615 via a connection path. The CE signal of each corresponding TSV of the TSV 615 is connected to the CE wiring 612, 622, 633, and 642 of each corresponding memory die 610, 620, 630, and 640. Although other elements (not shown) of each memory die 610 to 640 may include common structures, Figure 6 The arrangement shown in requires a dedicated and different TSV path for each CE signal. Therefore, each memory die has a different configuration with respect to the TSV CE.

[0186] In some embodiments, by adding counters and comparators, a unique address identifier can be provided to each memory cell without requiring excessive or dummy TSVs. Figure 7 As shown in , an embodiment may include four memory dies 710, 720, 730, and 740 arranged in a vertical memory stack 700 and electrically connected to a processor die 750. Each memory die 710, 720, 730, and 740 includes a counter 711, 721, 731, and 741, respectively. The counters may be electrically connected in series (e.g., via a daisy chain topology) as shown. Address information may be uniquely assigned to each corresponding memory die 710 to 740 via the counters 711 to 741, respectively.

[0187] For example, control logic signal 707 may be received by memory die 710 having two logic low bits (e.g., "00"). Memory die 710 is assigned a unique binary address "00". Counter 711 of memory die 710 increments the control logic signal by 1, outputting a binary address "01" to an adjacent memory die 720. Thus, memory die 720 is assigned a unique binary address "01" and includes counter 721 for continuing to increment the control logic signal. Memory die 730 and 740 include counter structures and are assigned unique binary addresses (counters 731 and 741 and addresses "10" and "11", respectively).

[0188] Each memory die 710 to 740 also includes the same comparator and TSV structure. For example, memory die 710, 720, 730 and 740 include comparators 712, 722, 732 and 742, respectively. Each memory die also includes the same formed TSV for carrying one or more CE signal lines 715. In some embodiments, the CE signal line 715 includes two wires connected to each memory die. Signals can be transmitted from the processor die 750 to each memory die 710 to 740 via the CE signal line 715. The comparators 712 to 742 are electrically connected to the CE signal line 715 and the unique memory address assigned by the neighboring die, as described above.

[0189] In this example, processor die 750 sends a CE signal "10" to address a memory die having a unique address for a memory operation. Comparator 712 of memory die 710 is connected to the CE signal ("10") and control logic signal 707, which includes the assigned memory address ("00"; as described above). Comparator 712 may include, but is not limited to, a logic gate such as an exclusive-or-not (XNOR) or other logic element. In this example, the comparison operation determines that the signal does not match the unique address, "CE, Comp = 0". Therefore, memory die 710 is not turned on for memory operations. Comparisons are similarly performed by comparators 722, 732, and 742 of memory die 720, 730, and 740, respectively. Comparator 732 of memory die 730 determines that its unique address ("10") corresponds to the CE signal, "CE, Comp = 1". As a result, comparator 731 provides a logic high ("1") output that is transmitted to a memory circuit (not shown). The logic high output enables or turns on the memory die 730 for performing one or more operations.

[0190] Thus, in some embodiments, the arrangement of counters may be electrically connected via a daisy chain topology to enable the generation of unique identifiers. A CE signal from a processor is transmitted to enable each memory die, whereby the CE signal is evaluated by a comparator based on each unique identifier. The memory dies are structurally identical and may include the same memory array circuitry (not shown). Thus, the memory stack 700 may include memory dies having the same structure, thereby reducing manufacturing requirements, including the use of masks.

[0191] Figure 8 8 is a diagram of an embodiment of a memory circuit 800 according to some embodiments. The memory circuit 800 includes a memory addressing circuit 810 and a memory array 814. The memory addressing circuit 810 is used to receive a memory address signal 801 from an adjacent die and receive a CE signal 805 from a processor die (not shown). In addition, the memory circuit 800 is used to receive a memory operation instruction 803 from the processor die.

[0192] The memory addressing circuit 810 may include one or more logic circuits. For example, the memory addressing circuit 810 includes a counter 811 and a comparator 812. The counter 811 performs an operation to increase the memory address signal 801 to an incremented memory address signal 802. The incremented memory address signal 802 is output by the counter 811, and the signal can be provided to an adjacent memory die (not shown) as a memory address signal.

[0193] The comparator 812 compares the CE signal 805 to the memory address signal 801 and generates a comparator output 813 based on a determination of whether the CE signal 805 matches the memory address signal 801. For example, if the comparison operation determines that the signals do not match, the comparator may be configured to output a logic low value (e.g., “0”) as the comparator output 813. If the comparison operation determines that the signals match, the comparator may output a logic high value (e.g., “1”) as the comparator output 813.

[0194] The memory array 814 can be used to receive the comparator output 813 to determine whether to enable a memory operation, such as a memory read or write operation based on the memory operation instruction 803. The memory output 804 of the memory array 814 can be transmitted, for example, to the control logic based on the memory operation. For example, if the CE signal 805 matches the memory address signal 801, and if the memory operation instruction 803 includes a memory read command, the memory value stored in the memory array 814 is output as the memory output 804.

[0195] Fig. 9 A cross section of a memory element 900 according to some embodiments is shown. The memory element 900 includes a processor die 950, a first memory die 910, a second memory die 920, a third memory die 930, and a fourth memory die 940. In some embodiments, the first to fourth memory dies 910 to 940 are stacked vertically. However, the dies may be alternatively arranged in any suitable manner (e.g., side-to-side).

[0196] The processor die 950 is used to output a memory address initialization signal 951, a CE signal 952, a memory operation address signal 957, a memory operation command signal 956, and a data_in signal 955. The processor die 950 is further used to receive a signal from a data_out signal line 954 from the stack of the first to fourth memory die 910 to 940. Each of the above signals 951, 952, and 954 to 957 includes one or more signal lines. In addition, each of the signals 951, 952, and 954 to 957, which may include one or more signal lines, may be provided to the first to fourth memory device die 910 to 940 through one or more TSVs. For example, the data_in signal 955 may be provided in each TSV (not shown) of the first to fourth memory die 910 to 940. As described throughout the embodiments of the present disclosure, one advantage is that each of the first to fourth memory dies 910 to 940 may have the same structural arrangement such that the TSVs may be linearly co-extended (eg, in the y-direction).

[0197] The first memory die 910 includes a counter 911, a comparator 912, and a memory array 914. In this example, the first memory die 940 receives a memory address initialization signal 951 from the processor die 950. The memory address initialization signal 951 is initialized to a logic low value (e.g., "00") by the processor die 950. Therefore, the first memory die 940 is assigned a first memory die address "00". The counter 911 increments the memory address initialization signal and outputs the incremented result (e.g., "01") to the second memory die 920.

[0198] The comparator 912 compares the memory address initialization signal 951 with the Ce signal 952 received from the processor die 950. In this example, the CE signal 952 is set to a binary value of "01". The comparator 912 determines that the value of the Ce signal 952 (e.g., "01") does not match the memory address of the first memory die 910, and outputs "0" as the comparator result.

[0199] The memory array 914 is used to receive a data_in signal 915, a memory operation signal 916, a memory operation address signal 917, and a memory operation enable signal 918. The output signal line of the memory array 914 is also connected to the data_out signal line 954. In this example, the output from the comparator 912 is provided to the memory array 914 as the memory operation enable signal 918, thereby providing an enable instruction "0" for the memory array without executing a memory operation instruction.

[0200] In some embodiments, the second memory die 920, the third memory die 930, and the fourth memory die 940 include the same structure as the first memory die 910. That is, the memory die 910 to 940 include counters 911 to 941 and comparators 912 to 942, respectively, and the counters and comparators may correspond to the following. Figure 8 , the logic circuits (e.g., memory addressing circuit 810) shown in FIG. Similarly, memory chips 910 to 940 include memory arrays 914 to 944, respectively. Figure 8 In the embodiment of the present invention, the counters 911 to 941 are used to sequentially increase the value of the memory address activated by the processor die 950 as the memory address initialization signal 951, and to output the incremented value to the next adjacent memory die.

[0201] Comparators 912 and 942 each compare the CE signal from processor die 950 with the corresponding memory die address assigned to the respective memory die 910 to 940. In this example, comparator 922 of second memory die 920 determines that the value of CE signal 952 (e.g., "01") matches the memory address (e.g., "01") provided to second memory die 920. Therefore, comparator 922 outputs "1" as the comparator result. Therefore, comparator 922 result "1" enables memory array 924 to perform operations based on the memory operation signal received from processor die 950.

[0202] like Fig. 9 As shown in FIG. 1 , the input ports and output ports of the memory die 910 to 940 corresponding to the CE signal 952 of the processor die 950 may be arranged to overlap (e.g., such as in FIG. 1 ). Fig. 9 y-direction as shown in FIG).

[0203] As described above, the processor die 950 provides instruction signals (e.g., data_in signal 955, memory operation signal 956, and memory operation address signal 957) to each memory die. In this example, the memory array 924 is enabled by the comparator 922. Specifically, the memory array 924 receives the instruction from the comparator output ("1") as the memory operation enable signal 928, enabling the memory array 924 to perform the memory operation. The memory operation is performed based on the memory operation address signal 957, the memory operation instruction signal 956, and the data_in signal 955 received from the processor die 950. The memory operation address signal 957, the memory operation instruction signal 956, and the data_in signal 955 are received in the memory array 924 as the memory operation address signal 957, the memory operation signal 956, and the data_in signal 955, respectively. If a memory operation, such as a read operation, generates data to be output, the memory array 924 sends the output to the data_out signal line 954 to be received by the processor die 950 .

[0204] Fig.10 FIG. 1 is a flow chart of a method 100 for addressing a device structure according to some embodiments of the present disclosure. In some embodiments, the device structure may be a SOIC structure, such as the one described above with respect to FIG. Figures 1 to 9 Based on the disclosed content of the embodiments of the present disclosure, the operations in method 1000 can be performed in a different order and / or differently.

[0205] See also Fig.10 At operation 1002, the processor die sends address signals, data signals, and control signals to a first component die, which may be a processor die such as Fig. 9 9. The first device receives an address signal in a first TSV and receives a control signal via a second TSV. The first and second TSVs may be disposed in the first memory device.

[0206] At operation 1003, the first component die generates a second address signal based on the first address signal. In some embodiments, the second address signal may be generated using a counter component, such as using Fig. 9 or by using an arithmetic processor or other increment operation. The first component die outputs the second address signal to the second component die. In some embodiments, the second component die may be a memory component die, such as Fig. 9In some embodiments, the control signal is output to or allowed to pass through the second TSV of the first memory die 910 to the second device die. The second address signal and the control signal can be received by the second device die via the third TSV and the fourth TSV, which can be disposed in the second device die.

[0207] At operation 1004, based on the control signal, the first component die determines whether to enable a circuit for performing a circuit-specific operation (e.g., enabling a memory circuit to perform a memory read or memory write operation). In some embodiments, the first component die determines whether to enable a circuit based on comparing the control signal to the first address signal. For example, if the control signal corresponds to the first address signal, the circuit may be enabled; and if the control signal does not correspond to the first address signal, the circuit may be disabled or not enabled. Operations 1003 and 1004 may be repeated based on the second component die (and subsequent component dies).

[0208] Embodiments of the present disclosure are directed to a layout design method for implementing the same mask set or reduced mask set in a manufacturing process to be used for a device die (e.g., multiple memory device dies stacked on top of each other). The method reduces the need for mask changes in the manufacturing process, even for different design considerations. In addition, using the same mask set or reduced mask set can reduce the risk of using incorrect masks in the manufacturing process. Further, because the same input / output (I / O) routing can be used in each memory die, the design and simulation of the circuit can become redundant and efficient. Embodiments of the present disclosure describe but are not limited to SOIC structures, 3DIC memory stacks, or memory circuits. In other embodiments, one or more memory dies may be replaced by one or more other chip packages, such as one or more processors or other appropriate packages. In addition, although the above arrangement is described with respect to a vertical stack of two to four memory dies, other arrangements are also possible. For example, other embodiments may include stacks having any number of vertically arranged device dies, side-to-side arrangements of individual bit cells or device dies, or any other suitable arrangements while retaining the benefits described in the embodiments of the present disclosure.

[0209] Embodiments of the present disclosure include an element including a processor die, a first memory die stacked on the processor die, and a second memory die stacked on the first memory die. The first memory die includes a first TSV and a first memory circuit. The second memory die includes a second TSV and a second memory circuit. The first TSV and the second TSV extend linearly together. In some embodiments, the first memory die and the second memory die are three-dimensional integrated circuit (3DIC) memory cells. The first memory die and the second memory die may be 3DIC memory die stacked face to back (F2B) on the processor die. In some embodiments, the first memory die includes a first logic circuit, and the second memory die includes a second logic circuit electrically connected to the first logic circuit. The first logic circuit is used to generate a first memory die address, and the second logic circuit is used to generate a second memory die address different from the first memory die address. The first logic circuit includes a first comparator, and the second logic circuit includes a second comparator. In some embodiments, the first logic circuit includes a first counter, and the second logic circuit includes a second counter. The second logic circuit is electrically connected to the first logic circuit through the first TSV and the second TSV. In some embodiments, the element further includes a third memory die stacked on the second memory die, and a fourth memory die stacked on the third memory die. The third memory die includes a third TSV, a third logic circuit, and a third memory circuit. The fourth memory die includes a fourth TSV, a fourth logic circuit, and a fourth memory circuit. In some embodiments, the first TSV, the second TSV, the third TSV, and the fourth TSV extend linearly together. The third logic circuit includes a third comparator and a third counter. The fourth logic circuit includes a fourth comparator and a fourth counter. In some embodiments, the first counter, the second counter, the third counter, and the fourth counter are electrically connected in series in the first TSV, the second TSV, the third TSV, and the fourth TSV.

[0210] Embodiments disclosed herein include an element including a first die, a second die, and a third die. The second die is stacked on the first die. The second die includes a first through silicon via (TSV) and a first circuit. The third die is stacked on the second die. The third die includes a second TSV and a second circuit. The first TSV and the second TSV extend linearly together. In some embodiments, the second die and the third die form a 3DIC memory stack. In some embodiments, the second die and the third die are F2B stacked on the first die. In some embodiments, the second die includes a first logic circuit. The third die includes a second logic circuit electrically connected to the first logic circuit. The first die is used to generate a first memory die address corresponding to the second die. The first logic circuit is used to generate a second memory die address corresponding to the third die. The second logic circuit is used to generate a third memory die address different from the first memory die address and the second memory die address. In some embodiments, the first logic circuit includes a first comparator, and the second logic circuit includes a second comparator. In some embodiments, the first logic circuit includes a first counter, and the second logic circuit includes a second counter. In some embodiments, the second logic circuit is electrically connected to the first logic circuit through the first TSV and the second TSV. In some embodiments, the element further includes a fourth die and a fifth die. The fourth die is stacked on the third die. The fourth die includes a third TSV, a third logic circuit, and a third memory circuit. The fifth die is stacked on the fourth die. The fifth die includes a fourth TSV, a fourth logic circuit, and a fourth memory circuit. The first TSV, the second TSV, the third TSV, and the fourth TSV extend linearly together. In some embodiments, the first logic circuit includes a first comparator and a first counter. The second logic circuit includes a second comparator and a second counter. The third logic circuit includes a third comparator and a third counter. The fourth logic circuit includes a fourth comparator and a fourth counter. In some embodiments, the first counter, the second counter, the third counter, and the fourth counter are electrically connected in series through the first TSV, the second TSV, and the third TSV.

[0211] According to some embodiments, the memory die includes a first through silicon via (TSV) having a first input port. The memory die further includes a first output port and a second output port, wherein the second TSV includes a second TSV, and the second TSV includes a second input port and a second output port. The memory die also includes a memory circuit and a logic circuit. The first input port is used to receive a first input value, and the second input port is used to receive a second input value. The logic circuit is used to generate a memory die address based on the first input value and compare the address with the second input value. In some embodiments, the logic circuit of the memory die includes a comparator and a counter. In some embodiments, the logic circuit of the memory die is used to output the memory die address to the first output port. In some embodiments, the memory die receives the first input value and the second input value from a second memory die having the same structure as the memory die. In some embodiments, the second input port and the second output port extend linearly together.

[0212] Embodiments disclosed herein include a memory die, including a first TSV, a first output port, a second TSV, a memory circuit, and a logic circuit. The first TSV includes a first input port. The second TSV includes a second input port and a second output port. The first input port is used to receive a first input value as a memory die address. The second input port is used to receive a second input value. The logic circuit is used to compare the first input value with the second input value. In some embodiments, the logic circuit includes a comparator and a counter. In some embodiments, the comparator is used to receive the first input value and the second input value. In some embodiments, the second input port and the second output port extend linearly together. In some embodiments, the logic circuit is used to generate a second memory die address based on the first input value, and wherein the memory die is used to output the second memory die address. In some embodiments, the memory die is used to output the second memory die address to another memory die. In some embodiments, the other memory die is structurally identical to the memory die.

[0213] According to some embodiments, a processor or logic die provides a processor storing one or more instructions. A control element die may execute one or more instructions that, when executed by the processor, configure the processor to provide a memory address initialization signal to a connected element die. The element die may be connected in series to the memory address initialization signal, with each element incrementing the signal. According to some embodiments, a control element die transmits an address signal, a data signal, and a control signal to a first memory die. The first memory die may receive an address signal in a first through silicon via (TSV), and a control signal obtained from a second TSV. The first memory die may generate a second address signal based on the first address signal and determine whether to enable the memory circuit based on the control signal. The first memory die may output a second address signal to a second memory die.

[0214] The first memory die may determine whether to enable the memory circuit based on comparing the control signal with the second address signal. According to some embodiments, if the control signal corresponds to the second address signal, the memory circuit is enabled; and if the control signal does not correspond to the second address signal, the memory circuit is not enabled. The second memory die may receive the second address signal in the third TSV and the control signal obtained from the fourth TSV. The second memory die may generate a third address signal based on the second address signal. The second memory die may enable the second memory circuit based on the control signal, and output the third address signal and the control signal.

[0215] Embodiments of the present disclosure include methods, including: transmitting a first address signal, a data signal, and a control signal to a first memory element by a processor; receiving the first address signal by the first memory element via a first TSV; receiving the control signal by the first memory element via a second TSV; generating a second address signal by the first memory element based on the first address signal; determining whether to enable a memory circuit by the first memory element based on the control signal; outputting the second address signal to the second memory element by the first memory element; and outputting the control signal to the second memory element by the first memory die via the second TSV. In some embodiments, the determination includes: determining by the first memory element whether to enable the memory circuit based on comparing the control signal with the first address signal. The memory circuit is enabled in response to the control signal corresponding to the first address signal. The memory circuit is not enabled in response to the control signal not corresponding to the first address signal. In some embodiments, the method further includes: receiving a second address signal through a third TSV through a second memory element; receiving a control signal through a fourth TSV through a second memory element; generating a third address signal based on the second address signal through the second memory element; determining whether to enable the second memory circuit based on the control signal through the second memory element; and outputting a third address signal and a control signal through the second memory element.

[0216] It should be understood that the implementation part, rather than the abstract part of the present disclosure, is intended to be used to interpret the scope of the claims. The abstract part of the present disclosure may set forth one or more, but not all possible embodiments of the present disclosure as contemplated by the inventor, and therefore the abstract part is not intended to limit the attached claims in any way.

[0217] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art will understand that they may easily use the embodiments of the present disclosure as a basis for designing or modifying other processes and structures that are used to achieve the same purposes and / or achieve the same advantages of the embodiments introduced in the present disclosure. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that those skilled in the art may make various changes, substitutions, and modifications without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A stacking element, characterized in that: Include: a first crystal grain; a second die stacked on the first die, wherein the second die comprises: a first through silicon via (TSV) comprising a first input port and a first output port; An addressable TSV including a second input port; a second output port; and a first circuit comprising a first memory and a first counter for assigning a first binary address to the first memory, wherein the first input port is used to receive a first input value, wherein the second input port is used to receive a second input value as the first binary address, and wherein the first circuit is used to compare the first input value with the second input value; and a third die stacked on the second die, wherein the third die comprises: a second TSV; and a second circuit comprising a second memory and a second counter for assigning a second binary address to the second memory, The first TSV and the second TSV extend linearly together.

2. The stacking element according to claim 1, characterized in that The second die and the third die form a three-dimensional integrated circuit (3DIC) memory stack.

3. The stacking element according to claim 1, characterized in that The second die and the third die are stacked face to back (F2B) on the first die.

4. The stacking element according to claim 1, characterized in that The second die includes a first logic circuit, and the third die includes a second logic circuit electrically connected to the first logic circuit; The first die is used to generate a first memory die address corresponding to the second die, The first logic circuit is used to generate a second memory chip address corresponding to the third chip, The second logic circuit is used to generate a third memory chip address which is different from the first memory chip address and the second memory chip address.

5. The stacking element according to claim 4, characterized in that The first logic circuit includes a first comparator, and the second logic circuit includes a second comparator.

6. The stacking element according to claim 4, characterized in that The first logic circuit includes a first counter, and the second logic circuit includes a second counter.

7. The stacking element according to claim 4, characterized in that The second logic circuit is electrically connected to the first logic circuit through the first TSV and the second TSV.

8. The stacking element according to claim 7, characterized in that Further including: a fourth die stacked on the third die, wherein the fourth die comprises a third TSV, a third logic circuit, and a third memory circuit; and A fifth die is stacked on the fourth die, wherein the fifth die includes a fourth TSV, a fourth logic circuit, and a fourth memory circuit. The first TSV, the second TSV, the third TSV, and the fourth TSV extend linearly together.

9. The stacking element according to claim 8, characterized in that in: The first logic circuit includes a first comparator and a first counter; The second logic circuit includes a second comparator and a second counter; The third logic circuit includes a third comparator and a third counter; and The fourth logic circuit includes a fourth comparator and a fourth counter.

10. The stacking element according to claim 9, characterized in that The first counter, the second counter, the third counter, and the fourth counter are electrically connected in series via the first TSV, the second TSV, and the third TSV.

11. A memory chip, characterized in that: Include: a first through silicon via (TSV) comprising a first input port; a first output port; a second TSV including a second input port and a second output port; a memory circuit; and A logic circuit, The first input port is used to receive a first input value as a memory chip address. The second input port is used to receive a second input value, and The logic circuit is used to compare the first input value with the second input value.

12. The memory chip according to claim 11, characterized in that: The logic circuit includes a comparator and a counter.

13. The memory chip according to claim 12, characterized in that: The comparator is used for receiving the first input value and the second input value.

14. The memory chip according to claim 11, characterized in that The second input port and the second output port extend linearly together.

15. The memory chip according to claim 11, characterized in that The logic circuit is used to generate a second memory chip address based on the first input value, and the memory chip is used to output the second memory chip address.

16. The memory chip according to claim 15, characterized in that The memory chip is used to output the second memory chip address to another memory chip.

17. The memory chip according to claim 16, characterized in that The structure of the other memory chip is the same as that of the memory chip.

18. An addressing method, characterized in that: Include: Transmitting a first address signal, a data signal, and a control signal to a first memory element by a processor; Receiving the first address signal through a first through silicon via (TSV) by the first memory element, wherein the first TSV comprises a first input port and a first output port, and the first input port is used to receive the first address signal as a first memory die address; The control signal is received by the first memory element via a second TSV, wherein the second TSV comprises a second input port and a second output port, and the second input port is used to receive the control signal; generating a second address signal based on the first address signal by the first memory element; Determining, by the first memory element, whether to enable a memory circuit based on the control signal, wherein the determining comprises: determining, by the first memory element, whether to enable the memory circuit based on comparing the control signal with the first address signal; Outputting the second address signal to a second memory element via the first memory element; and The control signal is output to the second memory element through the first memory die and the second TSV.

19. The addressing method according to claim 18, characterized in that: in: The memory circuit is enabled in response to the control signal corresponding to the first address signal, and The memory circuit is de-enabled in response to the control signal not corresponding to the first address signal.

20. The addressing method according to claim 19, characterized in that: Further including: Receiving the second address signal through a third TSV by the second memory element; Receiving the control signal through a fourth TSV by the second memory element; generating a third address signal based on the second address signal by the second memory element; Determining whether to enable a second memory circuit based on the control signal by the second memory element; and The third address signal and the control signal are outputted through the second memory element.

21. A stacking element, characterized in that: Include: A die processing step includes: a microprocessor circuit formed on a front side of the processing die; and an electrical connector formed on a back side of the processed die; and A memory stack is disposed above the processing die, the memory stack comprising a plurality of memory dies, each of the memory dies comprising: a memory circuit formed on a front side of the memory die; an interconnect structure formed on a back side of the memory die; a through silicon via (TSV) coupling the memory circuit to the interconnect structure, wherein the TSV includes a first input port and a first output port; An addressable TSV including a second input port; a second output port; and A logic circuit includes a counter for assigning a binary address to the memory die, wherein the first input port is used to receive a first input value, wherein the second input port is used to receive a second input value as the binary address, and wherein the logic circuit is used to compare the first input value with the second input value.

22. The stacking element according to claim 21, characterized in that Each of the memory dies further includes information embedded in a non-volatile storage structure.

23. The stacking element according to claim 21, characterized in that The two or more TSVs of the respective memory dies in the memory stack are vertically aligned with each other.

24. The stacked element according to claim 21, characterized in that The memory chips are used to receive address signals and a common control signal respectively.

25. The stacked element according to claim 21, characterized in that The memory dies are stacked face to face so that the respective memory circuits face each other.

26. The stacked element according to claim 21, characterized in that The memory dies are stacked face to face so that a memory circuit of a memory die faces the interconnection structure of an adjacent memory die.

27. A memory device, characterized in that: Include: A first memory chip, comprising: a first memory circuit formed on a front side of the first memory die; a first interconnect structure formed on a back side of the first memory die; a first through silicon via (TSV) coupling the first memory circuit to the first interconnect structure, wherein the first TSV comprises a first input port and a first output port; An addressable TSV including a second input port; a second output port; and a logic circuit including a first counter for assigning a binary address to the first memory die, formed on the front side of the first memory die, wherein the first input port is for receiving a first input value, wherein the second input port is for receiving a second input value as the binary address, and wherein the logic circuit is for comparing the first input value with the second input value; and A second memory die, on the first memory die, the second memory die comprising: a second memory circuit formed on a front side of the second memory die; a second interconnect structure formed on a back side of the second memory die; a second TSV coupling the second memory circuit to the second interconnect structure; and A second counter formed on the front side of the second memory die, the second counter being electrically connected in series with the first counter; The first memory circuit and the second memory circuit are different from each other.

28. The memory device according to claim 27, characterized in that The first memory die and the second memory die include static random access memory, dynamic random access memory, magnetoresistive random access memory and a combination thereof.

29. The memory device according to claim 27, wherein: The first memory circuit and the second memory circuit are used to receive respective address signals.

30. The memory device according to claim 27, wherein: The first memory circuit and the second memory circuit are used to receive a common control signal via the first TSV and the second TSV.

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