Active MOSFET voltage clamp circuit, clamping method and double pulse test circuit

Abstract

The invention relates to an active MOSFET voltage clamping circuit, a clamping method and a double pulse test circuit. The voltage clamping circuit comprises a device under test drain connected to an active clamping tube drain, an active clamping tube source connected to a clamping end X node, a source of the device under test connected to a clamping end Y node, a capacitor C1, a resistor R1 and a Zener diode D2 connected in parallel between the X node and the Y node through a diode D1, a capacitor C2 and a series resistor R connected between the gate of the active clamping tube and a common end of the source of the device under test and the clamping end Y node g , Power Supply (V cc );The gate of the active clamp tube is applied with a fixed gate bias (V cc ), when the device under test is in the off state, the voltage V between the clamping terminal node X and the clamping terminal node Y XY Clamped V cc ‑V TH,MT When the device under test is in the on state, the voltage V XY Follow the on-state voltage V DSON .

Description

Technical Field

[0001] The present invention relates to the technical field of voltage clamping measurement modules for high-voltage power devices, and in particular to an active MOSFET voltage clamping circuit, a clamping method and a double pulse test circuit for characterizing the dynamic resistance of a commercial p-GaN gate power device. Background Art

[0002] Commercial p-GaN gate gallium nitride high voltage devices have the problem of dynamic resistance decay during high voltage switching. The huge drain-source voltage swing makes it difficult to accurately monitor the dynamic on-voltage, which in turn affects the evaluation of the dynamic resistance of p-GaN gate high voltage devices. The dynamic on-resistance can be characterized by dividing the dynamic on-voltage by the dynamic on-current, and the dynamic on-current can be accurately monitored by the shunt resistor. The dynamic on-voltage needs to be measured by a voltage clamp module.

[0003] The current voltage clamping module can be mainly divided into two types: active clamping module (containing active devices) and passive clamping module (only passive devices). In the traditional active clamping module (patent number: US20080309355A1), the impedance network between the source of the active clamping tube and the power ground is composed of only resistors and diodes. When the input voltage is higher than 200V, an obvious voltage spike will appear at the clamping end and the voltage spike will significantly affect the measurement accuracy of the oscilloscope. The passive clamping module is mainly composed of a high-voltage diode. The simple passive clamping structure contains a high-voltage Schottky diode, but the on-voltage detected by the circuit contains the forward conduction voltage drop of the Schottky diode. The forward conduction voltage drop is related to the current flowing through the Schottky diode and the junction temperature, thereby affecting the measurement accuracy of the on-voltage. Another voltage clamping circuit based on a mirror current source (patent number: US9000791B2) includes two identical high-voltage Schottky diodes. The same current flows through the two identical Schottky diodes and has the same conduction voltage drop, thereby playing a role in voltage cancellation and eliminating the influence of the diode forward voltage drop on the measurement. However, the circuit structure is complex, and the adjustment of the clamping voltage requires the use of multiple low-voltage diodes in series. In addition, the device tolerance of the high-voltage Schottky diode will cause the measurement error of the conduction voltage.

[0004] Voltage clamp circuits are mainly divided into passive clamp circuits and active clamp circuits. Both use the voltage at the clamp end (X node and Y node) to follow the on-state voltage of the device under test. Figure 1(a) is a traditional active clamp circuit. The clamp module consists of an active device (MT) and passive devices (diodes and resistors). A fixed gate bias (V cc ), when the device under test is in the off state, the voltage between node X and node Y (V XY ) is clamped to V cc -V TH,MTWhen the device under test is in the on state, V XY Follower On Voltage (V DSON ). Figure 1(b) is a passive clamping circuit based on a single high-voltage diode, V XY Includes the on-state voltage drop of the device under test (V DSON ) and the forward voltage drop of the high-voltage diode (V F ). The forward voltage drop of the diode (V F ) is very sensitive to temperature, so the clamp circuit is sensitive to ambient temperature. Figure 1(c) shows a passive clamp circuit based on two high-voltage diodes. The circuit uses a mirror current source structure to make the current in the upper branch where the X node is located and the lower branch where the Y node is located equal. When the two high-voltage diodes are exactly the same, the conduction voltage drop (V F ) are the same, thus canceling each other out, so the clamping terminal voltage (V XY ) directly follows the on-state voltage of the device under test (V DSON ). This circuit has many components and a complex circuit structure. picture The design requirements are high (the upper and lower branches need to be designed symmetrically), and the parameter tolerance of high-voltage diodes of the same model will lead to measurement errors of the on-state voltage. Summary of the invention

[0005] The purpose of the present invention is to provide an active MOSFET voltage clamping circuit and a double pulse test circuit. The circuit is based on a traditional active clamping module and is an active clamping module optimized for the impedance network between the source and the power ground of the active clamping tube. The impedance network is composed of a capacitor, a resistor and a diode. The network can present a very low dynamic impedance in the switching transient state, and can effectively suppress the voltage spike appearing at the clamping end when the high voltage input (such as: 600V) is applied. At the same time, it does not affect the follow-up speed of the clamping end to the on-voltage, thereby meeting the measurement requirements of the dynamic resistance of the 600V / 650V high voltage p-GaN gate gallium nitride device within the rated voltage range. The active clamping circuit is insensitive to the junction temperature, does not require additional temperature correction, and can conveniently adjust the amplitude of the clamping voltage by adjusting the gate voltage of the active tube. Another purpose of the present invention is to provide an active MOSFET voltage clamping circuit that can ensure a wide voltage measurement range and avoid the significant influence of changes in ambient temperature and device parameters on the on-voltage measurement. Another object of the present invention is to provide an active MOSFET voltage clamping circuit for characterizing the dynamic resistance of commercial p-GaN gate power devices, which solves the problems of temperature sensitivity, numerous components and complex structure of passive clamping modules.

[0006] The technical solution of the present invention is the active MOSFET voltage clamping circuit, which is special in that it includes a device under test (DUT), an active clamping tube (MT) and a passive device, the drain of the device under test (DUT) is connected to the drain of the active clamping tube (MT), the source of the active clamping tube (MT) is connected to the clamping end X node, the source of the device under test (DUT) is connected to the clamping end Y node, the X node is connected in parallel with the capacitor C1, the resistor R1 and the Zener diode D2 between the diode D1 and the Y node, the gate of the active clamping tube (MT) and the common end of the source of the device under test (DUT) and the clamping end Y node are connected in parallel with the capacitor C2 and the series resistor R g , Power Supply (V cc ); A fixed gate bias (V cc ), when the device under test (DUT) is in the off state, the voltage V between the clamping terminal node X and the clamping terminal node Y XY Clamped V cc -V TH,MT When the device under test (DUT) is in the on state, the voltage V XY Follow the on-state voltage V DSON .

[0007] As a preferred embodiment, the active clamping tube (MT) is IPD60R280P7 (650V-240mΩ-12A), and the gate voltage of the active clamping tube (MT) is set at 6.6V. Since the threshold voltage of MT is 3.3V, the clamping voltage V CLAMP It is set at 3.3V, diode D1 uses VS18TQ040-N3 (40V-18A) silicon-based Schottky rectifier, Zener diode D2 (4.7V-0.5W), resistor R1 is set to 10kΩ, and capacitor C1 is set to 2μF.

[0008] Another technical solution of the present invention is a clamping method of the active MOSFET voltage clamping circuit, which is special in that it includes the steps of:

[0009] ⑴ When the device under test (DUT) is just turned off, the capacitance C of the device under test (DUT) oss Start charging;

[0010] ⑵ The drain-source voltage of the device under test (DUT) changes from the on-state voltage V DSON Rising to the clamping voltage V CLAMP =V cc -V TH,MT , the active clamp tube (MT) is passively turned off;

[0011] ⑶ The load current starts to act on the capacitance C of the device under test (DUT) and the active clamp tube (MT) at the same time. ossCharges and flows through the active clamp tube (MT) capacitor C ds The current charges the clamping node X. After the voltage of the clamping node X overshoots, the diode D1 conducts forward.

[0012] ⑷ The transient impedance between the clamping end node X and the clamping end node Y is determined by the capacitor C1. If the capacitor C1 is in the μF range, the capacitor C of the active clamping tube (MT) is ds Charge from 0V (-104pF) to V DSQ ~ V CLAMP (-20pF) corresponding charge (Q ds ) has almost negligible effect on the voltage of capacitor C1, where: V DSQ It is the high voltage bias (such as bus voltage) applied to the drain and source of the device when the power device is in the off state. CLAMP is the clamping voltage;

[0013] ⑸ During the entire turn-off transient, the voltage at the clamping node X is slightly greater than the clamping voltage V CLAMP , will not cause obvious voltage spikes;

[0014] ⑹ In the stable DUT off state, the DUT drain voltage is stable at the bus voltage V DSQ , and the voltage at the clamping node X will drop slightly as the capacitor C1 discharges through the resistor R1 and the Zener diode D2 and remain stable at the clamping voltage V CLAMP nearby;

[0015] ⑺When the device under test (DUT) is turned on transiently, the capacitance C of the device under test (DUT) and the active clamp tube (MT) oss Discharge through the channel of the device under test (DUT);

[0016] ⑻ The drain-source voltage of the device under test (DUT) is proportional to the bus voltage V DSQ Drops to the clamping voltage V CLAMP , the drain-source voltage of the active clamp transistor (MT) also changes from V DSQ -V CLAMP Drops to nearly 0V;

[0017] ⑼ The drain-source capacitance C of the active clamp tube (MT) ds The displacement current caused by the discharge causes the voltage of the clamping end node X to drop slightly, the diode D1 will change from forward bias to reverse bias, and the capacitor C1 will continue to discharge through the resistor R1;

[0018] ⑽The drain-source voltage of the device under test (DUT) is less than the clamping voltage V CLAMPAfter that, the channel of the active clamp tube (MT) is turned on, and the clamping end node X begins to follow the drain-source voltage until the drain-source voltage drops to the linear region conduction voltage V DSON ;

[0019] ⑾After the device under test (DUT) is fully turned on, the on-state voltage V DSON With the on-current I DSON The clamping terminal node X will always follow the on-state voltage V DSON changes.

[0020] Another technical solution of the present invention is the double pulse test circuit, which is special in that it includes a device under test (DUT), a shunt resistor R shunt , DC power supply V IN , capacitor C IN , inductor L, Schottky diode D SBD The voltage clamping circuit and oscilloscope are connected in parallel between the drain and source of the device under test (DUT). The drain of the device under test (DUT) is connected to the shunt resistor R shunt and grounded, the shunt resistor R shunt The other end of the parallel capacitor C is connected between the source of the device under test (DUT) IN and DC power supply, the source of the device under test (DUT) and the parallel capacitor CIN and the common end of the DC power supply are associated with the inductor L, the Schottky diode D SBD The double pulse test circuit is used to evaluate the switching speed and switching loss of the power device. The drain-source terminal of the device under test is connected in parallel with the voltage clamp module to reduce the monitoring range of the oscilloscope to increase the on-state voltage V of the device under test. DSON The measurement accuracy, combined with the shunt resistor R shunt The measured on-state current I DSON , and then accurately evaluate the on-resistance.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] ⑴ Compared with the traditional active voltage clamping circuit, this technology improves the passive network so that the clamping circuit can effectively suppress the voltage spike of the clamping node at a higher input voltage (such as: exceeding 300V), meeting the dynamic resistance characterization requirements of 600V / 650V high-voltage p-GaN gate gallium nitride power devices within the calibrated voltage range.

[0023] ⑵Compared to the passive clamping circuit, the active clamping circuit directly follows the on-state voltage of the power device, without the need to correct the forward voltage drop of the diode. Therefore, the active clamping circuit proposed in this paper is not sensitive to the environment or junction temperature. Compared with the voltage clamping circuit based on the mirror current source, the circuit structure is relatively simple and the clamping voltage amplitude is easy to adjust.

[0024] ⑶ The measurement results show that the active MOSFET voltage clamping circuit proposed in the present invention has a good voltage clamping function, can accurately measure the on-state voltage of the DUT under a bus voltage of 500V, and effectively suppresses the voltage spike of the DUT shutdown transient.

[0025] (4) This double pulse test circuit is used to evaluate the switching speed and switching loss of power devices. For p-GaN gate gallium nitride devices, if a voltage clamp module is connected in parallel between the drain and source of the device under test, the monitoring range of the oscilloscope can be reduced, the measurement accuracy of the on-state voltage of the device under test can be improved, and the on-state resistance can be accurately evaluated by combining the on-state current measured by the shunt resistor.

[0026] (5) The active clamping circuit proposed in the present invention can not only ensure a very wide voltage measurement range, but also avoid the significant impact of changes in ambient temperature and device parameters on the on-state voltage measurement. Attached picture illustrate

[0027] Figure 1a It is a traditional active voltage clamp circuit picture ;

[0028] Figure 1b It is a traditional passive clamp circuit based on a single high voltage diode. picture ;

[0029] Figure 1c It is a traditional passive clamp circuit based on two high voltage diodes (mirror current source) picture ;

[0030] Figure 2 The invention is an application circuit of the clamp circuit in the dynamic resistance characterization of high voltage p-GaN gate gallium nitride devices. picture ;

[0031] Figure 3 The active MOSFET voltage clamp circuit of the present invention picture ;

[0032] Figure 4A This is the circuit of the clamping circuit of the present invention at the initial shutdown moment of the DUT picture ;

[0033] Figure 4B This is the circuit for the high dv / dt charging stage during the DUT shutdown process of the clamp circuit of the present invention. picture ;

[0034] Figure 4C The clamp circuit of the present invention is in a stable off state of the DUT. picture ;

[0035] Figure 4D This is the circuit of the clamp circuit of the present invention during the high dv / dt discharge stage during the DUT opening process. picture ;

[0036] Figure 4E The clamping circuit of the present invention is a circuit in which the clamping node follows the DUT conduction voltage. picture ;

[0037] Figure 4F This is the circuit of the clamp circuit DUT in the stable open state process of the present invention. picture ;

[0038] Figure 5A The waveform of the gate measured waveform of the device under test under 500V bus voltage and 50Ω resistive load is shown in the present invention. picture ;

[0039] Figure 5B The gate waveform of the MT of the device under test under 500V bus voltage and 50Ω resistive load is shown in the present invention. picture ;

[0040] Figure 5C The waveform of the voltage difference (VXY) between the node X and the node Y of the device under test under 500V bus voltage and 50Ω resistive load is shown in FIG. picture ;

[0041] Figure 5D The waveform of the on-current flowing through the device under test under 500V bus voltage and 50Ω resistive load is shown in the present invention. picture . DETAILED DESCRIPTION

[0042] The present invention will be combined with the following picture To further elaborate:

[0043] See also Figure 2 As shown, the double pulse test circuit includes the device under test (DUT), the shunt resistor R shunt , DC power supply V IN , capacitor C IN , inductor L, Schottky diode D SBD The voltage clamping circuit and oscilloscope are connected in parallel between the drain and source of the device under test (DUT). The drain of the device under test (DUT) is connected to the shunt resistor R shunt and grounded, the shunt resistor R shunt The other end of the parallel capacitor C is connected between the source of the device under test (DUT) IN and DC power supply, the source of the device under test (DUT) and the parallel capacitor CIN and the common end of the DC power supply are associated with the inductor L, the Schottky diode DSBD The double pulse test circuit is used to evaluate the switching speed and switching loss of the power device. The drain-source terminal of the device under test is connected in parallel with the voltage clamp module to reduce the monitoring range of the oscilloscope to increase the on-state voltage V of the device under test. DSON The measurement accuracy, combined with the shunt resistor R shunt The measured on-state current I DSON , and then accurately evaluate the on-resistance.

[0044] See also Figure 3 As shown, the active MOSFET voltage clamp circuit includes a device under test (DUT), an active clamp tube (MT) and a passive device. The drain of the device under test (DUT) is connected to the drain of the active clamp tube (MT), the source of the active clamp tube (MT) is connected to the clamping end X node, the source of the device under test (DUT) is connected to the clamping end Y node, the X node is connected to the Y node through the diode D1, the capacitor C1, the resistor R1 and the Zener diode D2 are connected in parallel between the X node and the Y node, the capacitor C2 and the series resistor R are connected between the gate of the active clamp tube (MT) and the common end of the source of the device under test (DUT) and the clamping end Y node. g , Power Supply (V cc ); a fixed gate bias (V cc ), when the device under test (DUT) is in the off state, the voltage V between the clamping terminal node X and the clamping terminal node Y XY Clamped V cc -V TH,MT When the device under test (DUT) is in the on state, the voltage V XY Follow the on-state voltage V DSON .

[0045] In this embodiment, the active clamping tube (MT) uses IPD60R280P7 (650V-240mΩ-12 A), and the gate voltage of the active clamping tube (MT) is set at 6.6V. Since the MT threshold voltage is 3.3V, the clamping voltage V CLAMP It is set at 3.3V, diode D1 uses VS18TQ040-N3 (40V-18A) silicon-based Schottky rectifier, Zener diode D2 (4.7V-0.5W), resistor R1 is set to 10kΩ, and capacitor C1 is set to 2μF.

[0046] The active MOSFET clamping circuit of the present invention has the same clamping mechanism as the traditional active clamping circuit. However, compared with the traditional active clamping circuit, the passive network between the clamping end node X and the clamping end node Y adds capacitor C1, and changes the connection mode of the passive components; the introduction of capacitor C1 is to reduce the transient impedance between the clamping end node X and the clamping end node Y, so as to meet the requirement that within the rated voltage range of the power device (such as: 600V), the clamping end node X has a very small voltage spike (the voltage spike is too large and will affect the measurement accuracy of the on-state voltage of the oscilloscope). Compared with the passive clamping circuit composed of a single high-voltage diode shown in Figure 1 (b), the circuit is not sensitive to temperature and can be used for measurement occasions where the ambient temperature changes significantly. The passive clamping circuit composed of two high-voltage diodes shown in Figure 1 (c) is not sensitive to ambient temperature because the ambient temperature acts on the two high-voltage diodes at the same time and plays a compensating role. However, the device tolerance still brings measurement errors, and the structure of the circuit is complex and has high requirements for the design of the PCB.

[0047] Please refer to FIG. 4 , which analyzes the working mechanism of the active clamp circuit when the device under test (DUT) is in different switching states.

[0048] The clamping method of the active MOSFET voltage clamping circuit comprises the steps of:

[0049] ⑴ When the device under test (DUT) is just turned off (see Figure 4A ), the capacitance of the device under test (DUT) C oss Start charging;

[0050] ⑵ The drain-source voltage of the device under test (DUT) changes from the on-state voltage V DSON Rising to the clamping voltage V CLAMP =V cc -V TH,MT , the active clamp tube (MT) is passively turned off;

[0051] ⑶ The load current starts to act on the capacitance C of the device under test (DUT) and the active clamp tube (MT) at the same time. oss Charges and flows through the active clamp tube (MT) capacitor C ds The current charges the clamping node X. After the voltage of the clamping node X overshoots, the diode D1 is forward-conducted (see Figure 4B );

[0052] ⑷ The transient impedance between the clamping end node X and the clamping end node Y is determined by the capacitor C1. If the capacitor C1 is in the μF range, the capacitor C of the active clamping tube (MT) is ds From 0V(-10 4 pF) to V DSQ ~ V CLAMP(-20pF) corresponding charge (Q ds ) has almost negligible effect on the voltage of capacitor C1, where: V DSQ It is the high voltage bias (such as bus voltage) applied to the drain and source of the device when the power device is in the off state. CLAMP is the clamping voltage;

[0053] ⑸ During the entire turn-off transient, the voltage at the clamping node X is slightly greater than the clamping voltage V CLAMP , will not cause obvious voltage spikes;

[0054] ⑹ In the stable DUT off state, the DUT drain voltage is stable at the bus voltage V DSQ , and the voltage at the clamping node X will drop slightly as the capacitor C1 discharges through the resistor R1 and the Zener diode D2 and remain stable at the clamping voltage V CLAMP Nearby (see Figure 4C );

[0055] ⑺When the device under test (DUT) is turned on transiently, the capacitance C of the device under test (DUT) and the active clamp tube (MT) oss Discharge through the channel of the device under test (DUT) (see Figure 4D );

[0056] ⑻ The drain-source voltage of the device under test (DUT) is proportional to the bus voltage V DSQ Drops to the clamping voltage V CLAMP , the drain-source voltage of the active clamp transistor (MT) also changes from V DSQ -V CLAMP Drops to nearly 0V (see Figure 4-E);

[0057] ⑼ The drain-source capacitance C of the active clamp tube (MT) ds The displacement current caused by the discharge causes the voltage of the clamping end node X to drop slightly, the diode D1 will change from forward bias to reverse bias, and the capacitor C1 will continue to discharge through the resistor R1;

[0058] ⑽The drain-source voltage of the device under test (DUT) is less than the clamping voltage V CLAMP After that, the channel of the active clamp tube (MT) is turned on, and the clamping end node X begins to follow the drain-source voltage until the drain-source voltage drops to the linear region conduction voltage V DSON ;

[0059] ⑾After the device under test (DUT) is fully turned on, the on-state voltage V DSON With the on-current I DSON The clamping terminal node X will always follow the on-state voltage V DSON Changes in (see Figure 4F ).

[0060] Please refer to Figure 5, which shows the measured waveform of a p-GaN gate gallium nitride power device under a 500V bus voltage and a 50Ω resistive load. Figure 5A is the gate drive waveform of the device under test (DUT), with an on-state voltage of 6.0V and an off-state voltage of -3.6V. The gate voltage waveform of the active clamp tube (MT) ( Figure 5B ) There is obvious noise in the DUT turn-on transient, and the gate voltage peak is close to 10V. Therefore, in order to ensure the reliability of long-term operation, the active clamp tube (MT) needs to have a wide gate drive margin and good stability when driven at 10V. The voltage between the clamp nodes (V XY )like picture As shown in Figure 5C, the voltage between the clamping node X and the clamping node Y is effectively clamped at about 3.3V during the shutdown period of the device under test (DUT), and the voltage spike is effectively suppressed during the shutdown transient of the device under test (DUT). During the on-state of the device under test (DUT), the on-state voltage V DSON Accurately measured.

[0061] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should fall within the scope of the claims of the present invention.

Claims

1. An active MOSFET voltage clamp circuit, characterized in that: The device under test (DUT), active clamp tube (MT) and passive device are included. The drain of the device under test (DUT) is connected to the drain of the active clamp tube (MT), the source of the active clamp tube (MT) is connected to the clamping end X node, the source of the device under test (DUT) is connected to the clamping end Y node, the X node is connected to the Y node through the diode D1, the capacitor C1, the resistor R1 and the Zener diode D2 in parallel, the gate of the active clamp tube (MT) and the common end of the source of the device under test (DUT) and the clamping end Y node are connected to the capacitor C2 in parallel and the resistor R2 in series. g , Power supply V cc1 ; A fixed gate bias voltage V is applied to the gate of the active clamp transistor (MT) cc2 , when the device under test (DUT) is in the off state, the voltage V between the clamping terminal node X and the clamping terminal node Y XY Clamped V cc1 -V TH,MT When the device under test (DUT) is in the on state, the voltage V XY Follow the on-state voltage V DSON .

2. The active MOSFET voltage clamp circuit according to claim 1, characterized in that: The active clamping tube (MT) uses IPD60R280P7, 650V-240mΩ-12A. The gate voltage of the active clamping tube (MT) is set at 6.6V. Since the threshold voltage of MT is 3.3V, the clamping voltage V CLAMP It is set at 3.3V, diode D1 uses VS18TQ040-N3-40V-18A silicon-based Schottky rectifier, Zener diode D2 4.7V~0.5W, resistor R1 is set to 10kΩ, and capacitor C1 is set to 2μF.

3. A clamping method for the active MOSFET voltage clamping circuit according to claim 1, characterized in that: Includes steps: ⑴ When the device under test (DUT) is just turned off, the capacitance C of the device under test (DUT) oss Start charging; ⑵ The drain-source voltage of the device under test (DUT) changes from the on-state voltage V DSON Rising to the clamping voltage V CLAMP =V cc1 -V TH,MT , the active clamp tube (MT) is passively turned off; ⑶ The load current starts to act on the capacitance C of the device under test (DUT) and the active clamp tube (MT) at the same time. oss Charges and flows through the active clamp tube (MT) capacitor C ds The current charges the clamping node X. After the voltage of the clamping node X overshoots, the diode D1 conducts forward. ⑷ The transient impedance between the clamping end node X and the clamping end node Y is determined by the capacitor C1. If the capacitor C1 is in the μF range, the capacitor C of the active clamping tube (MT) is ds From 0V, -10 4 pF charged to V DSQ ~V CLAMP ,-20pF corresponding to the charge Q ds The effect on the voltage of capacitor C1 is almost negligible, where: V DSQ It is the high voltage bias applied to the drain and source of the device when the power device is in the off state. V CLAMP is the clamping voltage; ⑸ During the entire turn-off transient, the voltage at the clamping node X is slightly greater than the clamping voltage V CLAMP , will not cause obvious voltage spikes; (6) In the stable DUT off state, the DUT drain voltage is stable at the bus voltage, and the voltage at the clamping node X will drop slightly as the capacitor C1 discharges through the resistor R1 and the Zener diode D2 and remains stable at the clamping voltage V CLAMP nearby; ⑺When the device under test (DUT) is turned on transiently, the capacitance C of the device under test (DUT) and the active clamp tube (MT) oss Discharge through the channel of the device under test (DUT); ⑻ The drain-source voltage of the device under test (DUT) is proportional to the bus voltage V DSQ Drops to the clamping voltage V CLAMP , the drain-source voltage of the active clamp transistor (MT) also changes from V DSQ -V CLAMP Drops to nearly 0V; ⑼ The drain-source capacitance C of the active clamp tube (MT) ds The displacement current caused by the discharge causes the voltage of the clamping end node X to drop slightly, the diode D1 will change from forward bias to reverse bias, and the capacitor C1 will continue to discharge through the resistor R1; ⑽The drain-source voltage of the device under test (DUT) is less than the clamping voltage V CLAMP After that, the channel of the active clamp tube (MT) is turned on, and the clamping end node X begins to follow the drain-source voltage until the drain-source voltage drops to the linear region conduction voltage V DSON ; ⑾After the device under test (DUT) is fully turned on, the on-state voltage V DSON With the on-current I DSON The clamping terminal node X will always follow the on-state voltage V DSON changes.

4. A double pulse test circuit for the voltage clamp circuit according to any one of claims 1 to 2, characterized in that: Including the device under test (DUT), shunt resistor R shunt , DC power supply V IN , capacitor C IN , inductor L, Schottky diode D SBD The voltage clamping circuit and oscilloscope are connected in parallel between the drain and source of the device under test (DUT). The drain of the device under test (DUT) is connected to the shunt resistor R shunt and grounded, the shunt resistor R shunt The other end of the parallel capacitor C is connected between the source of the device under test (DUT) IN and DC power supply, the source of the device under test (DUT) and the parallel capacitor C IN The common terminal of the DC power supply is connected to the inductor L and the Schottky diode D SBD The double pulse test circuit is used to evaluate the switching speed and switching loss of the power device. The drain-source terminal of the device under test is connected in parallel with the voltage clamp module to reduce the monitoring range of the oscilloscope to increase the on-state voltage V of the device under test. DSON The measurement accuracy, combined with the shunt resistor R shunt The measured on-state current I DSON , and then accurately evaluate the on-resistance.

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