Dynamic semiconductor memory device and memory system having the same

Abstract

A dynamic semiconductor memory device and a memory system including the same are provided. The dynamic semiconductor memory device includes: a memory cell array including a first memory cell array block having a plurality of first dynamic memory cells connected between a first word line and a first bit line, a second memory cell array block having a plurality of second dynamic memory cells connected between a second word line and a second bit line, and a sense amplifier block having a sense amplifier, the sense amplifier being configured to amplify the voltage of the first bit line and the second bit line to a first sense power supply voltage or a second sense power supply voltage higher than the first sense power supply voltage; a temperature sensor unit being configured to sense temperature and generate a temperature sense signal; and a voltage generator being configured to generate a first or second sense power supply voltage in response to the temperature sense signal, apply the first or second sense power supply voltage to the memory cell array, and apply a sense ground voltage to the memory cell array.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0153800 filed on December 3, 2018, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Devices and systems consistent with the inventive concept relate to a dynamic semiconductor memory device and a memory system including the same. Background Art

[0003] A dynamic semiconductor memory device (e.g., a dynamic random access memory (DRAM) device) includes a plurality of dynamic memory cells, and each of the plurality of dynamic memory cells may include a transistor and a capacitor. Charge accumulated in the capacitors of the plurality of dynamic memory cells of the dynamic semiconductor memory device may leak, and therefore, a refresh operation may be periodically performed to refresh the charge accumulated in the capacitors of the plurality of dynamic memory cells. As the temperature of the dynamic semiconductor memory device increases, the charge accumulated in the capacitors of the plurality of dynamic memory cells may leak faster. Summary of the invention

[0004] Example embodiments of the inventive concept are directed to providing a dynamic semiconductor memory device configured to compensate for charges leaked from a plurality of dynamic memory cells of the dynamic semiconductor memory device as the temperature of the dynamic semiconductor memory device increases, and a memory system including the dynamic semiconductor memory device.

[0005] The scope of the inventive concept is not limited to the above-mentioned objects, and other unmentioned objects can be clearly understood by those skilled in the art from the following description.

[0006] According to an example embodiment of the inventive concept, there is provided a dynamic semiconductor memory device, the dynamic semiconductor memory device comprising: a memory cell array having a first memory cell array block including a plurality of first dynamic memory cells connected between a plurality of first word lines and a plurality of first bit lines, a second memory cell array block including a plurality of second dynamic memory cells connected between a plurality of second word lines and a plurality of second bit lines, and a sense amplification block including a plurality of sense amplifiers configured to amplify voltages of the plurality of first bit lines and voltages of the plurality of second bit lines to a first sense power supply voltage or at least one second sense power supply voltage higher than the first sense power supply voltage during a sense amplification operation; a temperature sensor unit configured to sense temperature and generate a temperature sense signal; and a voltage generator configured to generate a first sense power supply voltage or at least one second sense power supply voltage in response to the temperature sense signal, and to apply the first sense power supply voltage or the at least one second sense power supply voltage to the memory cell array, and to apply a sense ground voltage to the memory cell array.

[0007] A dynamic semiconductor memory device according to the present invention includes: a memory cell array having a plurality of dynamic memory cells connected between a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers configured to amplify voltages of the plurality of bit lines; a temperature sensor unit configured to sense temperature and generate a temperature sensing signal; and a voltage generator configured to generate a first sensing power supply voltage or at least one second sensing power supply voltage higher than the first sensing power supply voltage in response to the temperature sensing signal, and apply the first sensing power supply voltage or the at least one second sensing power supply voltage to the memory cell array, and apply a sensing ground voltage to the memory cell array. The plurality of sense amplifiers are also configured to amplify the voltage of a bit line corresponding to a dynamic memory cell connected to at least one word line selected from the plurality of word lines to the first sensing power supply voltage or the at least one second sensing power supply voltage during a sensing amplification operation.

[0008] A memory system according to an example embodiment of the present invention includes: a controller configured to send commands and addresses and send or receive data; and a dynamic memory configured to receive commands and addresses and send or receive data. The dynamic memory includes: a memory cell array having a plurality of dynamic memory cells connected between a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers configured to amplify voltages of the plurality of bit lines; a temperature sensor unit configured to sense temperature and generate a temperature sensing signal; and a voltage generator configured to generate a first sensing power supply voltage or at least one second sensing power supply voltage higher than the first sensing power supply voltage in response to the temperature sensing signal, and apply the first sensing power supply voltage or the at least one second sensing power supply voltage to the memory cell array, and apply a sensing ground voltage to the memory cell array. The plurality of sense amplifiers amplify the voltage of the bit line corresponding to the dynamic memory cell connected to at least one word line selected from the plurality of word lines to the first sensing power supply voltage or the at least one second sensing power supply voltage during a sensing amplification operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a dynamic semiconductor memory device according to some embodiments of the inventive concept;

[0011] Figure 2 According to some embodiments of the invention Figure 1 A block diagram of a temperature sensor unit;

[0012] Figure 3 is a diagram showing some components of a voltage generator according to some embodiments of the inventive concept;

[0013] Figure 4A and Figure 4B is a timing diagram illustrating the operation of a dynamic semiconductor memory device according to some embodiments of the inventive concept;

[0014] Figure 5 and Figure 6 The invention is a diagram showing some embodiments of the invention. Figure 1 A schematic diagram of a memory cell array;

[0015] Figure 7 is a block diagram of a row decoder according to some embodiments of the inventive concept;

[0016] Fig. 8A and Figure 8B The invention is a diagram showing some embodiments of the invention. Figure 6 A diagram of a sub-word line driver;

[0017] Fig. 9A and Fig. 9B They are respectively some embodiments according to the inventive concept. Figure 6 Figure 1 is a diagram of a precharge circuit and a sense amplifier;

[0018] Fig.10 The invention is a diagram showing some embodiments of the invention. Figure 1 A timing diagram of a refresh operation of a memory cell array; and

[0019] Fig.11 is a block diagram of a memory system according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0020] The inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments of the inventive concept are shown. Throughout this specification, the same reference numerals may represent the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. It is noted that the aspects described with respect to one embodiment may be included in different embodiments, although no specific description related thereto is performed. That is, all embodiments and / or features of any embodiment may be combined in any manner and / or combination.

[0021] Figure 1 1 is a block diagram of a dynamic semiconductor memory device according to some embodiments of the inventive concept. The dynamic semiconductor memory device 100 may include a command decoder and address generator 10, a mode setting register 12, a refresh address generator 14, a row address generator 16, a column address generator 18, a row decoder 20, a column decoder 22, a memory cell array 24, a voltage generator 26, a temperature sensor unit 28, a data write path unit 30, and a data read path unit 32. The dynamic semiconductor memory device may be a dynamic random access memory (DRAM) device.

[0022] The following will describe Figure 1 Example functionality of the blocks shown in .

[0023] The command decoder and address generator 10 can receive a command and address CA applied from the outside of the DRAM device 100, generate commands such as an activation command ACT, a read command RD, a write command WR, a refresh command REF and / or a mode setting command MRS by decoding the command signal included in the command and address CA, and generate a row address RADD, a column address CADD and / or a mode setting code OPC from the address signal included in the command and address CA.

[0024] The mode setting register 12 may generate a temperature sensor enable signal TEN in response to the mode setting code OPC.

[0025] The refresh address generator 14 may generate a refresh address rra in response to a refresh command REF.

[0026] The row address generator 16 may generate a row address signal ra from a row address RADD in response to an active command ACT, and generate a row address signal ra from a refresh address rra in response to a refresh command REF.

[0027] The column address generator 18 may generate a column address signal ca from a column address CADD in response to a write command WR or a read command RD.

[0028] The row decoder 20 may generate a word line selection signal wl by decoding a row address signal ra.

[0029] The column decoder 22 may generate a column selection signal csl by decoding the column address signal ca.

[0030] The memory cell array 24 may include a plurality of dynamic memory cells (not shown), store data in the dynamic memory cells selected by the word line selection signal wl and the column selection signal csl in response to a write command WR, and output data from the dynamic memory cells selected by the word line selection signal wl and the column selection signal csl in response to a read command RD. In addition, the memory cell array 24 may perform a refresh operation on the dynamic memory cells selected by at least one word line selection signal in response to a refresh command REF.

[0031] The voltage generator 26 may generate a high voltage VPP, a first sensing power supply voltage VDD or a second sensing power supply voltage VDD+α, a sensing ground voltage GND, and a precharge voltage VBL. In response to the temperature sensing signal TD, the voltage generator 26 may generate a first sensing power supply voltage VDD when the temperature sensing signal TD is not activated, and generate a second sensing power supply voltage VDD+α higher than the first sensing power supply voltage VDD when the temperature sensing signal TD is activated. As another example, the voltage generator 26 may generate a first sensing power supply voltage VDD when the temperature sensing signal TD indicates that the temperature does not exceed a specific temperature, and may generate a second sensing power supply voltage VDD+α that increases in proportion to the increase in temperature when the temperature sensing signal TD indicates that the temperature exceeds a specific temperature. Here, α may represent a voltage that increases linearly or stepwise from the first sensing power supply voltage VDD as the temperature increases.

[0032] The temperature sensor unit 28 may sense the temperature in response to the temperature sensor enable signal TEN, deactivate the temperature sensing signal TD when the temperature does not exceed a specific temperature, and activate the temperature sensing signal TD when the temperature exceeds a specific temperature. That is, in some embodiments of the inventive concept, the temperature sensing signal TD may be 1-bit digital data. In other embodiments, the temperature sensing signal TD may be multi-bit digital data. In this case, the temperature sensor unit 28 may generate a temperature sensing signal TD having a predetermined number of states. That is, the temperature sensor unit 28 may generate a temperature sensing signal TD having a first state when the temperature does not exceed a specific temperature, and generate a temperature sensing signal TD having at least two different states when the temperature exceeds a specific temperature. In other embodiments, the temperature sensor unit 28 may be configured to be enabled when a refresh operation is performed in response to a refresh command REF in addition to being enabled in response to the temperature sensor enable signal TEN, or may be configured to be enabled in response to a write command WR or a read command RD.

[0033] The data write path unit 30 may receive data DQ applied from the outside of the DRAM device 100 and transfer the data DQ to the memory cell array 24 in response to a write command WR.

[0034] The data read path unit 32 may output data output from the memory cell array 24 as data DQ in response to a read command RD.

[0035] Figure 2 is a block diagram of a temperature sensor unit 28 according to some embodiments of the inventive concept. The temperature sensor unit 28 may include a temperature sensor 28-2, an analog-to-digital converter (ADC) 28-4, and a temperature sensing signal generator 28-6.

[0036] The following will describe Figure 2 Example functionality of the blocks shown in .

[0037] The temperature sensor 28 - 2 may generate a temperature signal TEMP that increases according to an increase in temperature. In some embodiments, the temperature signal TEMP may be a voltage or a current that increases according to an increase in temperature.

[0038] The ADC 28 - 4 may generate a digital signal CODE by converting the temperature signal TEMP, which is an analog signal, into a digital signal. The digital signal CODE may be digital data of a predetermined number of bits.

[0039] When the digital signal CODE exceeds a specific digital data corresponding to a specific temperature, the temperature sensing signal generator 28-6 may activate the temperature sensing signal TD. That is, the temperature sensing signal generator 28-6 may deactivate the temperature sensing signal TD when the digital signal CODE does not exceed the specific digital data, and activate the temperature sensing signal TD when the digital signal CODE exceeds the specific digital data. That is, in some embodiments, the temperature sensing signal TD may be 1-bit digital data.

[0040] Figure 3 2 is a diagram showing some components of the voltage generator 26 according to some embodiments of the inventive concept. The voltage generator 26 may be a power supply voltage generator including a reference voltage generator 26-2, a switch 26-4, a comparator 26-6, and a driver D. The driver D may be a PMOS transistor.

[0041] The following will describe some embodiments according to the inventive concept. Figure 3 The operation of the voltage generator 26 is shown in FIG.

[0042] The reference voltage generator 26 - 2 may be supplied with the external power supply voltage EVDD, and generates a first reference voltage Vref1 and a second reference voltage Vref2 .

[0043] In response to the temperature sensing signal TD, the switch 26 - 4 may enable the first reference voltage Vref1 or the second reference voltage Vref2 to be generated as the reference voltage Vref. The second reference voltage Vref2 may be higher than the first reference voltage Vref1.

[0044] The comparator 26-6 may compare the reference voltage Vref with the first sensing power supply voltage VDD or the second sensing power supply voltage VDD+α, and generate a driving signal d when the first sensing power supply voltage VDD or the second sensing power supply voltage VDD+α is lower than the reference voltage Vref. For example, when the first sensing power supply voltage VDD or the second sensing power supply voltage VDD+α is lower than the reference voltage Vref, the comparator 26-6 may generate a driving signal d having a “low” level.

[0045] The driver D may be turned on in response to the driving signal d and drive the first sensing power supply voltage VDD or the second sensing power supply voltage VDD+α.

[0046] Figure 4A and Figure 4B 2 is an operational timing diagram illustrating operations of the temperature sensor unit 28 and the voltage generator 26 according to some embodiments of the inventive concept.

[0047] Reference Figures 2 to 4A, the temperature sensor 28-2 may generate a temperature signal TEMP. The temperature signal TEMP may be a voltage or current that increases as the temperature increases. The ADC 28-4 may convert the temperature signal TEMP, which is an analog signal, into a digital signal CODE. For example, if the digital signal CODE is 4-bit digital data, the specific temperature ts1 is 90°C and the specific digital data corresponding to the specific temperature ts1 is c1 (e.g., "0111"), then the temperature sensing signal generator 28-6 may activate the temperature sensing signal TD when the specific digital data exceeds c1. When the temperature sensing signal TD is not activated, the switch 26-4 may generate a first reference voltage Vref1, and the voltage generator 26 may generate a first sensing power supply voltage VDD. When the temperature sensing signal TD is activated, the switch 26-4 may generate a second reference voltage Vref2, and the voltage generator 26 may generate a second sensing power supply voltage VDD+α as a fixed voltage. That is, the voltage generator 26 may generate the first sensing power supply voltage VDD when the specific digital data indicates that the temperature does not exceed the specific temperature ts1 , and generate the second sensing power supply voltage VDD+α when the specific digital data indicates that the temperature exceeds the specific temperature ts1 .

[0048] In other embodiments of the inventive concept, reference is made to Figure 2 , Figure 3 and Figure 4B, the ADC 28-4 may convert the temperature signal TEMP as an analog signal into a digital signal CODE. For example, if the digital signal CODE is 4-bit digital data, the first specific temperature ts1 is 90°C, the first specific digital data corresponding to the first specific temperature ts1 is c1 (e.g., "0111"), the second specific temperature ts2 is 110°C and the second specific digital data corresponding to the second specific temperature ts2 is c2 (e.g., "1101"), then the temperature sensing signal generator 28-6 may generate a temperature sensing signal TD having a first state td1 when the digital signal CODE does not exceed c1, generate a temperature sensing signal TD having a second state td2 when the digital signal CODE exceeds c1 and does not exceed c2, and generate a temperature sensing signal TD having a third state td3 when the digital signal CODE exceeds c2. Therefore, according to some embodiments of the inventive concept, the reference voltage generator 26-2 may generate three first to third reference voltages, and the switch 26-4 may generate the first reference voltage in response to the temperature sensing signal TD having the first state td1, generate the second reference voltage in response to the temperature sensing signal TD having the second state td2, and generate the third reference voltage in response to the temperature sensing signal TD having the third state td3. Therefore, the voltage generator 26 may generate the first sensing power supply voltage VDD when the digital signal CODE indicates that the temperature does not exceed the first specific temperature ts1, generate the second sensing power supply voltage VDD+Δv1 when the digital signal CODE indicates that the temperature exceeds the first specific temperature ts1 and does not exceed the second specific temperature ts2, and generate the third sensing power supply voltage VDD+Δv2 when the digital signal CODE indicates that the temperature exceeds the second specific temperature ts2.

[0049] As described above, the temperature sensor unit 28 and the voltage generator 26 may generate a temperature sensing signal TD having at least one state that increases gradually as the temperature increases, and generate at least one of the second sensing power supply voltage VDD+α or VDD+Δv1 and the third sensing power supply voltage VDD+Δv2 when the digital signal CODE indicates that the temperature exceeds a specific temperature. However, unlike what is shown in the drawings, the temperature sensor unit 28 may generate a temperature sensing signal TD that increases linearly as the temperature increases, and the voltage generator 26 may generate a second sensing power supply voltage that increases linearly when the digital signal CODE indicates that the temperature exceeds a specific temperature.

[0050] Figure 5 is a diagram schematically illustrating a memory cell array 24 according to some embodiments of the inventive concept.

[0051] The following will describe Figure 5 Memory cell array 24 is shown in FIG.

[0052] The memory cell array 24 may include 32 memory cell array blocks BLK1 to BLK32 and 31 sense amplification blocks SA12 to SA3132. Each of the 32 memory cell array blocks BLK1 to BLK32 may include n sub-memory cell array blocks SMCA11 to SMCA1n, SMCA21 to SMCA2n, ... or SMCA321 to SMCA32n and n sub-word line driver blocks SWD11 to SWD1n, SWD21 to SWD2n, ... or SWD321 to SWD32n. Each of the 31 sense amplifier blocks SA12 to SA3132 may include n sub-sense amplifier blocks SA121 to SA12n, SA231 to SA23n, ... or SA31321 to SA3132n and n junction blocks CJ121 to CJ12n, CJ231 to CJ23n, ... or CJ31321 to CJ3132n. There are 128 main word lines NWEL1 to NWEL128 and 1024 sub-word lines WL1 to WL1024, which may be arranged in each of the 32 memory cell array blocks BLK1 to BLK32. Each of the 32 memory cell array blocks BLK1 to BLK32 may include a plurality of dynamic memory cells (not shown) connected between the 1024 sub-word lines WL1 to WL1024 and a plurality of bit lines (not shown). Each of the 31 sense amplification blocks SA12 to SA3132 may be arranged between adjacent memory cell array blocks. There are 8 word line selection signal lines PXL1 to PXL8, which may be arranged in each of the 31 sense amplification blocks SA12 to SA3132.

[0053] The sub-word line driver blocks SWD11 to SWD1n, SWD21 to SWD2n, ..., and SWD321 to SWD32n arranged on the left side of each of the sub-memory cell array blocks SMCA11 to SMCA1n, SMCA21 to SMCA2n, ..., and SMCA321 to SMCA32n- can select one of the sub-word lines WL1 to WL1024 when one of the main word lines NWEL1 to NWEL128 and one of the word line selection signal lines PXL1 to PXL8 are selected. For example, the sub-word line driver blocks SWD11 to SWD1n, SWD21 to SWD2n, ... or SWD321 to SWD32n of the memory cell array blocks BLK1 to BLK32 can select the sub-word line WL1 of the sub-memory cell array blocks SMCA11 to SMCA1n, SMCA21 to SMCA2n, ... or SMCA321 to SMCA32n- of each of the memory cell array blocks BLK1 to BLK32 when the main word line NWEL1 is selected and the word line selection signal line PXL1 of each of the sense amplification blocks SA12 to SA3132 is selected. The sub-word line driver blocks SWD11 to SWD1n, SWD21 to SWD2n, ... or SWD321 to SWD32n of each of the memory cell array blocks BLK1 to BLK32 can select the sub-word line WL1024 of the sub-memory cell array blocks SMCA11 to SMCA1n, SMCA21 to SMCA2n, ... or SMCA321 to SMCA32n of each of the memory cell array blocks BLK1 to BLK32 when the main word line NWEL128 of each of the memory cell array blocks BLK1 to BLK32 is selected and the word line selection signal line PXL8 of each of the sense amplifier blocks SA12 to SA3132 is selected. That is, when one of the main word lines NWEL1 to NWEL128 and one of the word line selection signal lines PXL1 to PXL8 are selected, the sub-word lines WL1 to WL1024 in the sub-word line driver blocks SWD11 to SWD1n, SWD21 to SWD2n, ... or SWD321 to SWD32n of each of the memory cell array blocks BLK1 to BLK32 can be selected.

[0054] Each of the 31 sense amplification blocks SA12 to SA3132 can be shared by a memory cell array block adjacent thereto. During a refresh operation, each of the 31 sense amplification blocks SA12 to SA3132 can amplify data read from a plurality of dynamic memory cells through a bit line (not shown) and rewrite the amplified data, the plurality of dynamic memory cells being connected to a selected word line of a memory cell array block adjacent to each of the 31 sense amplification blocks SA12 to SA3132. The 31 sense amplification blocks SA12 to SA3132 are configured to be shared by two adjacent memory cell array blocks, but may not be used to perform a refresh operation on two adjacent memory cell array blocks at the same time.

[0055] In some embodiments, Figure 1 The high voltage VPP generated by the voltage generator 26 can be applied to the sub-word line driver blocks SWD11 to SWD1n, SWD21 to SWD2n, ... and SWD321 to SWD32n, the sensing power supply voltage VDD or VDD+α and the sensing ground voltage GND can be applied to the junction blocks CJ121 to CJ12n, CJ231 to CJ23n, ... and CJ31321 to CJ3132n, and the pre-charge voltage VBL can be applied to the sensing amplifier blocks SA12, SA23, ..., SA3132.

[0056] Figure 6 Detailed diagram showing some components of the memory cell array 24 according to some embodiments of the present invention, wherein the structures of the sub-word line driver block SWD11, the sub-memory cell array block SMCA11, the junction block CJ121, the sub-sense amplification block SA121, the sub-word line driver block SWD21, and the sub-memory cell array block SMCA21 of the memory cell array 24 are shown in detail. The memory cell array 24 may have an open bit line structure.

[0057] Reference Figure 6, each of the sub-memory cell array blocks SMCA11 and SMCA21 may include 128×k partial blocks PMCA11 to PMCA1k, ..., PMCA1281 to PMCA128k. Each of the 128×k partial blocks PMCA11 to PMCA1k, ..., PMCA1281 to PMCA128k may include 32 dynamic memory cells MC connected between eight sub-word lines WL1 to WL8 and four odd and even bit lines BL1 to BL4. Each of the dynamic memory cells MC may include an access transistor AT connected between the sub-word line and the odd or even bit line and a capacitor C connected between the access transistor AT and a voltage (e.g., a ground voltage). The memory cell array 24 may have an open bit line structure in which each of the odd bit lines BL1 and BL3 in the sub-memory cell array block SMCA11 and each of the even bit lines BL2 and BL4 in the sub-memory cell array block SMCA21 form a pair of bit lines. The sub-word line driver block SWD11 may include a sub-word line driver D1. Each of the sub-word line drivers D1 may be supplied with a high voltage VPP, and may select eight sub-word lines WL1 to WL8 in the sub-memory cell array block SMCA11 by driving sub-word line drive selection signals px11 to px18 generated from the junction block CJ121 in response to the corresponding main word line selection signal NWE11, ... or NWE1128. Each of the sub-word line drivers D1 may be supplied with a high voltage VPP, and may apply the high voltage VPP to the selected sub-word line. The sub-word line driver block SWD21 may include a sub-word line driver D1'. Each of the sub-word line drivers D1' can select eight sub-word lines WL1 to WL8 in the sub-memory cell array block SMCA21 by driving the sub-word line drive selection signals px11, px13, px15, px17 generated from the junction block CJ121 and the sub-word line drive selection signals px22, px24, px26, and px28 generated from the junction block CJ231 (not shown) in response to the corresponding main word line selection signals NWE21 to NWE2128. Each of the sub-word line drivers D1' can be supplied with a high voltage VPP and apply the high voltage VPP to the selected sub-word line. Each sub-word line driver block in the memory cell array 24 can be used as follows Figure 5 The memory cell array block adjacent to its right side in the word line direction X shown in FIG.

[0058] The junction block CJ121 may include a sub-word line selection signal driver D2 and a control signal driver CSD. The sub-word line selection signal driver D2 may generate sub-word line drive selection signals px11 to px18 by driving word line selection signals PX11 to PX18 in response to a Y block selection signal YB1 to be described later. The Y block selection signal YB1 may be generated by decoding some bits of the column address CADD. The control signal driver CSD may generate a first bit line isolation gate drive control signal isogc1 and a second bit line isolation gate drive control signal isogc2 and a pair of sense amplifier voltages LA and LAB in response to the X block selection signal XB1 or XB2, the bit line isolation gate control signal ISOGC1 and the sense amplifier control signal SE1. The control signal driver CSD may be supplied with a first sense power supply voltage VDD or a second sense power supply voltage VDD+α and a sense ground voltage GND, and transmit them as a pair of sense amplifier voltages LA and LAB. The positive sensing voltage LA of the pair of sensing amplification voltages LA and LAB may be the first sensing power supply voltage VDD or the second sensing power supply voltage VDD+α, and the negative sensing voltage LAB may be the sensing ground voltage GND. Therefore, during the refresh operation of the memory cell array 24, when the temperature exceeds a certain temperature, the positive sensing voltage LA may be amplified to the second sensing power supply voltage VDD+α, and thus, the amount of charge accumulated in the capacitor C of the plurality of dynamic memory cells MC may be increased. Therefore, even when the amount of charge leaked from the capacitor C of the plurality of dynamic memory cells MC of the memory cell array 24 increases due to an increase in temperature, the amount of charge accumulated in the capacitor C increases, thereby preventing or reducing the loss of data stored in the memory cell array 24. In the memory cell array 24, each junction block may be used for a sub-word line driver block adjacent to the top and / or bottom of each junction block in the bit line direction Y and a sub-sense amplification block adjacent to the right side of each junction block in the word line direction X.

[0059] The sense amplification block SA121 may include k sense amplification circuits PSA1 to PSAk, each of which includes precharge circuits P1 and P2, sense amplifiers sa1 and sa2, first and second bit line isolation gates ISOG1 and ISOG2, and input / output gates IOG1 and IOG2. The precharge circuits P1 and P2 may perform a precharge operation of precharging odd bit lines BL1 and BL3 included in the sub-memory cell array block SMCA11, even bit lines BL2 and BL4 included in the sub-memory cell array block SMCA21, and sense bit lines SBL1 to SBL4 included in the sub-sense amplification block SA121 to a precharge voltage VBL in response to a precharge control signal pre. The precharge operation may be an operation of precharging all bit lines and all sense bit lines included in the memory cell array 24 to a precharge voltage VBL simultaneously or substantially synchronously. In the sub-sense amplification block SA121, the sense amplifiers sa1 and sa2 included in the sense amplification circuits PSA1 to PSAk may amplify data of the odd sense bit lines SBL1 and SBL3 connected to the odd bit lines BL1 and BL3 of the sub-memory cell array block SMCA11 and voltages of the even sense bit lines SBL2 and SBL4 connected to the even bit lines BL2 and BL4 of the sub-memory cell array block SMCA21 in response to the pair of sense amplification voltages LA and LAB, respectively. In the sub-sense amplification block SA121, the first bit line isolation gate ISOG1 of each of the sense amplification circuits PSA1 to PSAk may include NMOS transistors N1 and N2, which are turned on in response to the first bit line isolation gate drive control signal isogc1 to connect the odd bit lines BL1 and BL3 of the sub-memory cell array block SMCA11 and the odd sense bit lines SBL1 and SBL3 of the sub-sense amplification block SA121. In the sub-sense amplification block SA121, the second bit line isolation gate ISOG2 of each of the sense amplification circuits PSA1 to PSAk may include NMOS transistors N3 and N4, which are turned on in response to the second bit line isolation gate drive control signal isogc2 to connect the even bit lines BL2 and BL4 of the sub-memory cell array block SMCA21 and the even sensing bit lines SBL2 and SBL4 of the sub-sense amplification block SA121. In the sub-sense amplification block SA121, the input / output gate IOG1 of each of the sense amplification circuits PSA1 to PSAk may include NMOS transistors N5 and N6, which are turned on in response to the corresponding column selection signals CSL11, CSL12 (not shown), ... or CSL1k to connect the sensing bit lines SBL1 and SBL2 and a pair of input / output lines LIO1.In the sub-sense amplification block SA121, the input / output gate IOG2 of each of the sense amplification circuits PSA1 to PSAk may include NMOS transistors N7 and N8, which are turned on in response to corresponding column selection signals CSL11, CSL12 (not shown), ..., CSL1k to connect the sense bit lines SBL3 and SBL4 and a pair of input / output lines LIO2.

[0060] Figure 7 2 is a block diagram of a row decoder 20 according to some embodiments of the inventive concept. The row decoder 20 may include a first row address decoder 20-2 and a second row address decoder 20-4. The second row address decoder 20-4 may include first block row decoders BRD1 to BRD32 and second block row decoders BRD12 to BRD3132.

[0061] exist Figure 7 In FIG. 1 , the row decoder 20 is shown based on the following assumptions: Figure 5 Four memory cell array blocks are selected approximately simultaneously among the 32 memory cell array blocks BLK1 to BLK32, and refresh operations are performed on a plurality of dynamic memory cells connected to one word line of each of the four memory cell array blocks approximately simultaneously.

[0062] The following will describe Figure 7 Example functionality of the blocks shown in .

[0063] The first row address decoder 20-2 can generate block selection signals B1 to B32 by decoding the 5-bit first row address signal ra1 in response to the activation command ACT or the refresh command REF. The first row address decoder 20-2 can activate one of the block selection signals B1 to B32 in response to the activation command ACT, or can simultaneously or substantially synchronously activate four block selection signals B1, B9, B17 and B25, four block selection signals B2, B10, B18 and B26, four block selection signals B3, B11, B19 and B27, four block selection signals B4, B12, B20 and B28, four block selection signals B5, B13, B21 and B29, four block selection signals B6, B14, B22 and B30, four block selection signals B7, B15, B23 and B31, or four block selection signals B8, B16, B24 and B32 in response to the refresh command REF. For example, in response to the refresh command REF, the first row address decoder 20 - 2 may simultaneously or substantially synchronously activate four block selection signals by decoding lower three bits except for upper two bits of the 5-bit first row address signal ra1 .

[0064] Each of the first block row decoders BRD1 to BRD32 can generate a corresponding main word line selection signal NWE1, NWE2, ... or NWE32 by decoding the x bits of the second row address signal ra2 in response to the corresponding block selection signal B1, B2, ... or B32. For example, each of the first block row decoders BRD1 to BRD32 can generate a corresponding main word line selection signal NWE1, NWE2, ... or NWE32 by decoding the upper seven bits of the 10-bit second row address signal ra2. The number of each of the main word line selection signals NWE1 to NWE32 can be 128.

[0065] Each of the second block row decoders BRD12 to BRD3132 can generate a corresponding word line selection signal PX12, PX23, ... or PX3132 by decoding the y bits of the second row address signal ra2 in response to the corresponding block selection signal B1, B2, ... or B32. For example, each of the second block row decoders BRD12 to BRD3132 can generate a corresponding word line selection signal PX12, PX23, ... or PX3132 by decoding the lower three bits of the 10-bit second row address ra2. The number of each of the word line selection signals PX12 to PX3132 can be eight.

[0066] The word line selection signals NWE1, NWE2, ... or NWE32 and the corresponding eight word line selection signals PX12, PX23, ... or PX3132 can be used to select the word line. Figure 5 The sub word lines WL1 to WL1024 of each of the memory cell array blocks BLK1 to BLK32 are shown in FIG.

[0067] Fig. 8A 1 is a diagram showing a structure of a sub-word line driver D1 according to some embodiments of the inventive concept. The sub-word line driver D1 may include first to eighth logic gates G1 to G8. The first to eighth logic gates G1 to G8 may include NAND gates NA1 to NA8 and inverters I1 to I8, respectively.

[0068] exist Fig. 8A , each of the first to eighth logic gates G1 to G8 may select a corresponding sub-word line WL1, WL2, ..., WL8 by performing an AND operation on a main word line selection signal NWE11 and a corresponding sub-word line drive selection signal px11, px12, ..., px18. When the sub-word lines WL1 to WL8 are respectively selected, the first to eighth logic gates G1 to G8 may generate a high voltage VPP.

[0069] Figure 8B1 is a diagram showing a structure of a sub-word line driver D2 according to some embodiments of the inventive concept. The sub-word line selection signal driver D2 may include ninth to sixteenth logic gates G9 to G16. The ninth to sixteenth logic gates G9 to G16 may include NAND gates NA9 to NA16 and inverters I9 to I16, respectively.

[0070] exist Figure 8B , each of the ninth to sixteenth logic gates G9 to G16 may generate a corresponding sub word line drive selection signal px11, px12, . . . or px18 by performing an AND operation on the Y block selection signal YB1 and the corresponding word line selection signal PX11, PX12, . . . or PX18.

[0071] Fig. 9A is a diagram illustrating a structure of a precharge circuit P1 according to some embodiments of the inventive concept. The precharge circuit P1 may include NMOS transistors N9 to N11.

[0072] exist Fig. 9A In the embodiment, NMOS transistors N9 and N10 may be turned on in response to a precharge control signal pre to precharge the sensing bit lines SBL1 and SBL3 to a precharge voltage VBL. NMOS transistor N11 may be turned on in response to a precharge control signal pre to equalize the voltages of the sensing bit lines SBL1 and SBL3.

[0073] Fig. 9B is a diagram illustrating a structure of a sense amplifier sa1 according to some embodiments of the inventive concept. The sense amplifier sa1 may include PMOS transistors P1 and P2 and NMOS transistors N12 and N13.

[0074] exist Fig. 9B In the embodiment, when the positive sensing voltage LA changes from the precharge voltage VBL to the first sensing power supply voltage VDD or the second sensing power supply voltage VDD+α and the negative sensing voltage LAB changes from the precharge voltage VBL to the sensing ground voltage GND, the PMOS transistors P1 and P2 may be turned on when the sensing bit line SBL1 or SBL2 changes to a "low" level to amplify the sensing bit line SBL2 or SBL1 to the first sensing power supply voltage VDD or the second sensing power supply voltage VDD+α, and the NMOS transistors N12 and N13 may be turned on when the sensing bit line SBL1 or SBL2 changes to a "high" level to amplify the sensing bit line SBL2 or SBL1 to the sensing ground voltage GND. That is, the sense amplifier sa1 may sense the difference between the voltages of the pair of sensing bit lines SBL1 and SBL2, and may amplify the sensing bit lines SBL2 and SBL1 to the first sensing power supply voltage VDD and the sensing ground voltage GND or to the second sensing power supply voltage VDD+α and the sensing ground voltage GND.

[0075] Fig.10 is an operation timing diagram illustrating a refresh operation of the memory cell array 24 according to some embodiments of the present inventive concept, wherein “high” level data is stored in all of the plurality of dynamic memory cells connected to the sub-word lines WL1 of the memory cell array blocks BLK1, BLK9, BLK17, and BLK25 of the memory cell array 24, and the sub-word lines WL1 of the memory cell array blocks BLK1, BLK9, BLK17, and BLK25 are activated simultaneously or substantially synchronously to perform a refresh operation on the plurality of dynamic memory cells connected to the sub-word lines WL1 of the memory cell array blocks BLK1, BLK9, BLK17, and BLK25.

[0076] Reference Figures 5 to 10 , in the first period T1, when the precharge control signal pre is driven to a "high" level, all precharge circuits P1 and P2 of the memory cell array 24 are enabled, and therefore, all bit lines and sense bit lines of the memory cell array 24 can be precharged to the precharge voltage VBL. That is, the first period T1 can be a precharge operation period for performing a precharge operation. In the first period T1, the control signal driver CSD of all junction blocks of each of the sense amplifier blocks can generate a first bit line isolation gate drive control signal isogc1 and a second bit line isolation gate drive control signal isogc2 having a "high" level and generate a pair of sense amplifier voltages LA and LAB having a precharge voltage VBL. Therefore, both the first bit line isolation gate ISOG1 and the second bit line isolation gate ISOG2 of all sub-sense amplifier blocks of all sense amplifier blocks of the memory cell array 24 can be turned on, and all sense amplifiers sa1 and sa2 of the memory cell array 24 can be turned off.

[0077] Reference Figures 1 to 10, in the second period T2, the high voltage VPP may be applied to the sub-word lines WL1 of the sub-memory cell array blocks SMCA11 to SMCA1n, SMCA91 to SMCA9n, SMCA171 to SMCA17n, and SMCA251 to SMCA25n of the memory cell array blocks BLK1, BLK9, BLK17, and BLK25. In addition, the control signal driver CSD of the junction blocks CJ121 to CJ12n, CJ9101 to CJ910n, CJ17181 to CJ1718n, and CJ25261 to CJ2526n of the sense amplifier blocks SA12, SA910, SA1718, and SA2526 may generate the first bit line isolation gate drive control signal isogc1 and the second bit line isolation gate drive control signal isogc2 having a "low" level and generate a pair of sense amplifier voltages LA and LAB having a precharge voltage VBL. Therefore, all first bit line isolation gates ISOG1 and second bit line isolation gates ISOG2 of the sub-sense amplification blocks SA121 to SA12n, SA9101 to SA910n, SA17181 to SA1718n, and SA25261 to SA2526n of the sense amplification blocks SA12, SA910, SA1718, and SA2526 can be turned off, and all of their sense amplifiers sa1 and sa2 can be turned off. Therefore, charge sharing can be performed between the charge accumulated in each dynamic memory cell connected between the sub-word line WL1 of the memory cell array blocks BLK1, BLK9, BLK17, and BLK25 and the odd bit lines BL1 and BL3 of the sub-memory cell array blocks SMCA11 to SMCA1n, SMCA91 to SMCA9n, SMCA171 to SMCA17n, and SMCA251 to SMCA25n and the charge corresponding to the precharge voltage VBL of the corresponding odd bit line BL1 or BL3. Therefore, the voltages of the odd bit lines BL1 and BL3 of the sub-memory cell array blocks SMCA11 to SMCA1n, SMCA91 to SMCA9n, SMCA171 to SMCA17n, and SMCA251 to SMCA25n of the memory cell array blocks BLK1, BLK9, BLK17, and BLK25 may be increased by a third predetermined voltage ΔVa from the precharge voltage VBL. That is, the second period T2 may be a charge sharing period in which charge sharing is performed. In this case, when the charge accumulated in the dynamic memory cell decreases as the temperature increases, as Fig.10 As indicated by the alternating long-short dash lines in FIG. 8 , the voltages of the odd bit lines BL1 and BL3 may be increased from the precharge voltage VBL by a fourth predetermined voltage ΔVa′ (ΔVa′ is lower than the third predetermined voltage ΔVa).

[0078] Reference Figures 1 to 10, in the third period T3, the high voltage VPP may be applied to the sub-word lines WL1 of the sub-memory cell array blocks SMCA11 to SMCA1n, SMCA91 to SMCA9n, SMCA171 to SMCA17n, and SMCA251 to SMCA25n of the memory cell array blocks BLK1, BLK9, BLK17, and BLK25. The control signal driver CSD of the junction blocks CJ121 to CJ12n, CJ9101 to CJ910n, CJ17181 to CJ1718n, and CJ25261 to CJ2526n of the sense amplifier blocks SA12, SA910, SA1718, and SA2526 may generate the first bit line isolation gate drive control signal isogc1 and the second bit line isolation gate drive control signal isogc2 having a "high" level and generate a pair of sense amplifier voltages LA and LAB having a first sense power supply voltage VDD and a sense ground voltage GND. Therefore, all the first bit line isolation gates ISOG1 and the second bit line isolation gates ISOG2 of the sub-sense amplification blocks SA121 to SA12n, SA9101 to SA910n, SA17181 to SA1718n, and SA25261 to SA2526n of the sense amplification blocks SA12, SA910, SA1718, and SA2526 may be turned on, and all of their sense amplifiers sa1 and sa2 may be enabled, thereby amplifying the voltages of the odd bit lines BL1 and LB3 to the first sense power supply voltage VDD (see Fig.10 Curve SL). Therefore, the dynamic memory cells connected between the sub-word line WL1 of the memory cell array blocks BLK1, BLK9, BLK17 and BLK25 and the odd bit lines BL1 and BL3 of the sub-memory cell array blocks SMCA11 to SMCA1n, SMCA91 to SMCA9n, SMCA171 to SMCA17n and SMCA251 to SMCA25n can be restored by the sensing power supply voltage VDD. That is, the third period T3 can be a sensing amplification period. In this case, when the charge accumulated in the dynamic memory cell decreases due to an increase in temperature, the second sensing power supply voltage VDD+α and the sensing ground voltage GND can be applied to the sensing amplifiers sa1 and sa2 of the sub-sensing amplification blocks SA121 to SA12n, SA9101 to SA910n, SA17181 to SA1718n and SA25261 to SA2526n of the sensing amplification blocks SA12, SA910, SA1718, SA2526, and as Fig.10 As indicated by the alternating long-short dash lines in FIG. 1 , the voltages of the odd bit lines BL1 and BL3 may be amplified to the second sensing power supply voltage VDD+α (see Fig.10Therefore, even when the charge accumulated in the dynamic memory cell leaks and decreases due to the increase in temperature, the odd bit lines BL1 and BL3 can be amplified to the second sensing power supply voltage VDD+α by applying the second sensing power supply voltage VDD+α to the sense amplifiers sa1 and sa2, thereby compensating for the charge leakage of the dynamic memory cell.

[0079] As described above, according to some embodiments of the inventive concept, all dynamic memory cells of the memory cell array 24 may be refreshed by repeatedly performing a refresh operation.

[0080] The dynamic semiconductor memory device according to some embodiments of the present invention may be configured to generate a fixed second sensing power supply voltage VDD+α or to generate a second sensing power supply voltage VDD+α that increases gradually or linearly as the temperature increases, even during write and read operations and during refresh operations when the temperature exceeds a specific temperature.

[0081] The above-described sense amplification operation may be performed during a write or read operation as well as during a refresh operation.

[0082] The memory cell array of the above-mentioned dynamic semiconductor memory device may have an open bit line structure in some embodiments, but may have a folded bit line structure in other embodiments. In the memory cell array with the open bit line structure, the reference bit line is located in a memory cell array block adjacent thereto, while in the memory cell array with the folded bit line structure, the reference bit line may be located in the same memory cell array block. The memory cell array of the dynamic semiconductor memory device according to some embodiments of the present invention may be configured to amplify the voltage of each of the bit lines corresponding to the dynamic memory cells connected to at least one word line selected from a plurality of word lines to a first sensing power supply voltage VDD or at least one second sensing power supply voltage VDD+α applied according to temperature or to a sensing ground voltage GND during a sensing amplification operation, regardless of the bit line structure.

[0083] Fig.11 1 is a block diagram of a memory system according to some embodiments of the inventive concept. The memory system 1000 may include a controller 200 and a dynamic memory 300. The dynamic memory 300 may be a dynamic semiconductor memory device, or a memory module including a plurality of dynamic semiconductor memory devices.

[0084] The following will describe Fig.11 Example functionality of the blocks shown in .

[0085] The controller 200 may transmit commands and addresses CA and receive or output data DQ.

[0086] The dynamic memory 300 may receive a command and an address CA and receive or output data DQ. The dynamic memory 300 may be the above-referenced memory according to some embodiments of the inventive concept. Figures 1 to 10 That is, when the temperature exceeds a certain temperature, the dynamic memory 300 may generate a fixed second sensing power supply voltage VDD+α higher than the first sensing power supply voltage VDD, or generate a second sensing power supply voltage VDD+α that increases gradually or linearly as the temperature increases.

[0087] According to an example embodiment of the inventive concept, even when the charge accumulated in the dynamic memory cell of the dynamic semiconductor memory device is rapidly leaked as the temperature increases, the leaked charge can be compensated by sensing the temperature during the sense amplification operation and increasing the sense power supply voltage. Therefore, the reliability of the operation of the dynamic semiconductor memory device and the memory system including the dynamic semiconductor memory device can be improved.

[0088] Although the embodiments of the present invention have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the present invention and without changing the essential features of the present invention. Therefore, the above embodiments should be considered only in a descriptive sense and not for the purpose of limitation.

Claims

1. A dynamic semiconductor memory device, comprising: A memory cell array, comprising: a first memory cell array block, comprising a plurality of first dynamic memory cells connected between a plurality of first word lines and a plurality of first bit lines; a second memory cell array block, comprising a plurality of second dynamic memory cells connected between a plurality of second word lines and a plurality of second bit lines; and a sense amplification block, comprising a plurality of sense amplifiers, the plurality of sense amplifiers being configured to amplify voltages of the plurality of first bit lines and voltages of the plurality of second bit lines to a first sense power supply voltage or at least one second sense power supply voltage higher than the first sense power supply voltage during a sense amplification operation; a temperature sensor unit configured to sense temperature and generate a temperature sensing signal; and A voltage generator is configured to generate a first sensing power supply voltage or the at least one second sensing power supply voltage in response to a temperature sensing signal, apply the first sensing power supply voltage or the at least one second sensing power supply voltage to a memory cell array, and apply a sensing ground voltage to the memory cell array.

2. The dynamic semiconductor memory device according to claim 1, wherein: The temperature sensor unit is further configured to generate a temperature sensing signal having a first state when the temperature does not exceed a specific temperature, and to generate a temperature sensing signal having at least one second state different from the first state when the temperature exceeds the specific temperature; and The voltage generator is further configured to generate a first sensing supply voltage in response to the temperature sensing signal having the first state, and to generate the at least one second sensing supply voltage in response to the temperature sensing signal having the at least one second state.

3. The dynamic semiconductor memory device according to claim 2, wherein: The temperature sensor unit consists of: a temperature sensor configured to sense temperature and generate a temperature signal; an analog-to-digital converter configured to receive the temperature signal and convert the temperature signal from an analog signal to a digital signal; and The temperature sensing signal generator is configured to receive the digital signal and generate a temperature sensing signal in response to the digital signal.

4. The dynamic semiconductor memory device according to claim 3, wherein: The voltage generator includes: a reference voltage generator configured to receive an external power supply voltage and generate a first reference voltage and at least one second reference voltage higher than the first reference voltage; a switch configured to generate the first reference voltage or the at least one second reference voltage as a reference voltage in response to a temperature sensing signal; a comparator configured to compare a reference voltage with the first sensing power supply voltage or the at least one second sensing power supply voltage, and to generate a driving signal when the first sensing power supply voltage or the at least one second sensing power supply voltage is lower than the reference voltage; and The driver is configured to drive the first sensing power supply voltage or the at least one second sensing power supply voltage in response to the driving signal.

5. The dynamic semiconductor memory device according to claim 1, further comprising: a command decoder and an address generator configured to receive a command and an address from a source external to the dynamic semiconductor memory device, generate a mode setting command by decoding a command signal included in the command and the address, and generate a mode setting code from an address signal included in the command and the address; as well as a mode setting register configured to generate a temperature sensor enable signal in response to a mode setting code, and The temperature sensor unit is further configured to sense temperature and generate a temperature sensing signal in response to a temperature sensor enable signal.

6. The dynamic semiconductor memory device according to claim 1, further comprising: a command decoder and an address generator configured to receive a command and an address from a source external to the dynamic semiconductor memory device and to generate a refresh command, a write command, or a read command by decoding a command signal included in the command and the address; and The temperature sensor unit is further configured to sense temperature and generate a temperature sensing signal in response to a refresh command, a write command or a read command.

7. The dynamic semiconductor memory device according to claim 6, wherein: The sense amplifier block also includes: a precharge circuit configured to precharge the plurality of first bit lines and the plurality of second bit lines during a precharge operation, and Wherein, each of the plurality of sense amplifiers is connected between a corresponding first bit line among the plurality of first bit lines and a corresponding second bit line among the plurality of second bit lines, and is configured to amplify a voltage of the corresponding first bit line among the plurality of first bit lines and a voltage of the corresponding second bit line among the plurality of second bit lines to a first sensing power supply voltage or to the at least one second sensing power supply voltage when at least one of the plurality of first word lines and the plurality of second word lines is selected during a sensing amplification operation performed in response to a refresh command, a write command, or a read command.

8. A dynamic semiconductor memory device, comprising: A memory cell array, comprising: a plurality of dynamic memory cells connected between a plurality of word lines and a plurality of bit lines; and a plurality of sense amplifiers configured to amplify voltages of the plurality of bit lines; a temperature sensor unit configured to sense temperature and generate a temperature sensing signal; and a voltage generator configured to generate a first sensing power supply voltage or at least one second sensing power supply voltage higher than the first sensing power supply voltage in response to a temperature sensing signal, and apply the first sensing power supply voltage or the at least one second sensing power supply voltage to a memory cell array, and apply a sensing ground voltage to the memory cell array, The plurality of sense amplifiers are further configured to amplify a voltage of a bit line corresponding to a dynamic memory cell connected to at least one word line selected from the plurality of word lines to a first sense power supply voltage or the at least one second sense power supply voltage during a sense amplification operation.

9. The dynamic semiconductor memory device according to claim 8, wherein: The temperature sensor unit is further configured to generate a temperature sensing signal having a first state when the temperature does not exceed a specific temperature, and to generate a temperature sensing signal having at least one second state different from the first state when the temperature exceeds the specific temperature; and The voltage generator is further configured to generate a first sensing supply voltage in response to the temperature sensing signal having the first state, and to generate the at least one second sensing supply voltage in response to the temperature sensing signal having the at least one second state.

10. The dynamic semiconductor memory device according to claim 9, wherein: The temperature sensor unit consists of: a temperature sensor configured to sense temperature and generate a temperature signal; an analog-to-digital converter configured to receive the temperature signal and convert the temperature signal from an analog signal to a digital signal; and The temperature sensing signal generator is configured to receive the digital signal and generate a temperature sensing signal in response to the digital signal.

11. The dynamic semiconductor memory device according to claim 10, wherein: The voltage generator includes: a reference voltage generator configured to receive an external power supply voltage and generate a first reference voltage and at least one second reference voltage higher than the first reference voltage; a switch configured to generate the first reference voltage or the at least one second reference voltage as a reference voltage in response to a temperature sensing signal; a comparator configured to compare a reference voltage with the first sensing power supply voltage or the at least one second sensing power supply voltage, and to generate a driving signal when the first sensing power supply voltage or the at least one second sensing power supply voltage is lower than the reference voltage; and The driver is configured to drive the first sensing power supply voltage or the at least one second sensing power supply voltage in response to the driving signal.

12. The dynamic semiconductor memory device according to claim 8, further comprising: a command decoder and an address generator configured to receive a command and an address from a source external to the dynamic semiconductor memory device, generate a mode setting command by decoding a command signal included in the command and the address, and generate a mode setting code from an address signal included in the command and the address; as well as a mode setting register configured to generate a temperature sensor enable signal in response to a mode setting code, and The temperature sensor unit is further configured to sense temperature and generate a temperature sensing signal in response to a temperature sensor enable signal.

13. The dynamic semiconductor memory device according to claim 8, further comprising: a command decoder and an address generator configured to receive a command and an address from a source external to the dynamic semiconductor memory device and to generate a refresh command, a write command, or a read command by decoding a command signal included in the command and the address; and The temperature sensor unit is further configured to sense temperature and generate a temperature sensing signal in response to a refresh command, a write command or a read command.

14. The dynamic semiconductor memory device according to claim 13, wherein: The sense amplification operation is performed in response to a refresh command, a write command, or a read command.

15. A memory system, comprising: a controller configured to send commands and addresses and to transmit or receive data; as well as Dynamic memory, configured to receive commands and addresses and to send or receive data, Among them, the dynamic memory includes: A memory cell array, comprising: a plurality of dynamic memory cells connected between a plurality of word lines and a plurality of bit lines; and a plurality of sense amplifiers configured to amplify voltages of the plurality of bit lines; a temperature sensor unit configured to sense temperature and generate a temperature sensing signal; and a voltage generator configured to generate a first sensing power supply voltage or at least one second sensing power supply voltage higher than the first sensing power supply voltage in response to a temperature sensing signal, and apply the first sensing power supply voltage or the at least one second sensing power supply voltage to a memory cell array, and apply a sensing ground voltage to the memory cell array, and The plurality of sense amplifiers amplify voltages of bit lines corresponding to dynamic memory cells connected to at least one word line selected from the plurality of word lines to a first sense power supply voltage or the at least one second sense power supply voltage during a sense amplification operation.

16. The memory system of claim 15, wherein: The temperature sensor unit is further configured to generate a temperature sensing signal having a first state when the temperature does not exceed a specific temperature, and to generate a temperature sensing signal having at least one second state different from the first state when the temperature exceeds the specific temperature; as well as The voltage generator is further configured to generate a first sensing supply voltage in response to the temperature sensing signal having the first state, and to generate the at least one second sensing supply voltage in response to the temperature sensing signal having the at least one second state.

17. The memory system of claim 16, wherein: The temperature sensor unit consists of: a temperature sensor configured to sense temperature and generate a temperature signal; an analog-to-digital converter configured to receive the temperature signal and convert the temperature signal from an analog signal to a digital signal; and The temperature sensing signal generator is configured to receive the digital signal and generate a temperature sensing signal.

18. The memory system of claim 17, wherein: The voltage generator includes: a reference voltage generator configured to receive an external power supply voltage and generate a first reference voltage and at least one second reference voltage higher than the first reference voltage; a switch configured to generate the first reference voltage or the at least one second reference voltage as a reference voltage in response to a temperature sensing signal; a comparator configured to compare a reference voltage with the first sensing power supply voltage or the at least one second sensing power supply voltage, and to generate a driving signal when the first sensing power supply voltage or the at least one second sensing power supply voltage is lower than the reference voltage; and The driver is configured to drive the first sensing power supply voltage or the at least one second sensing power supply voltage in response to the driving signal.

19. The memory system according to claim 15, wherein: The dynamic memory further includes a command decoder and an address generator configured to generate a refresh command, a write command, or a read command by decoding a command signal included in the command and the address, and The temperature sensor unit is further configured to sense temperature and generate a temperature sensing signal in response to a refresh command, a write command, or a read command.

20. The memory system of claim 19, wherein: The sense amplification operation is performed in response to a refresh command, a write command, or a read command.

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