LED display module and manufacturing method thereof

Abstract

The LED display module includes: an LED package having one or more layers of molding compound and an LED chip array arranged therein; a plurality of conductive pads arranged on a surface of the LED package away from the LED chip array; a thermal rail connecting the LED chip arrays to each other, and a plurality of conductive paths connecting the plurality of conductive pads and the thermal rail network. The thermal rail network includes a first thermal rail layer connecting the LED chip arrays to each other, and a second thermal rail layer arranged between the first thermal rail layer and the plurality of conductive pads.

Description

Technical Field

[0001] The present invention relates to a light emitting diode (LED) display module and a display panel made of such a module, and more particularly to an LED display module made of an LED chip with a built-in conductive path. Background Art

[0002] LED packages are components that house LED chips. The functions of LED packages include protecting the LED chip and solder leads from direct contact with the environment, fixing and encapsulating the chip with epoxy or silicone, and achieving versatility and standardization in LED lighting applications. Today, many types of LED packages are used for different applications with different advantages and disadvantages. Surface mount device (SMD) LEDs, chip on board (COB) LEDs, and multi-chip on board (MCOB) LEDs are several common LED packaging technologies, among which, compared to ordinary SMD LEDs, chip on board (COB) LED technology can provide higher efficiency and lumens per watt.

[0003] Chip-on-board (COB) LEDs or multi-chip-on-board (MCOB) LED modules have an array of LED chips directly attached to a substrate, such as a printed circuit board (PCB). Since COB LEDs do not require attachments such as lead frames, they take up less space on the printed circuit board (PCB), so COB LED modules can have a greater LED density than SMD LED modules. When a COB LED package is powered, it may look like a uniform lighting panel rather than a single lighting array when using SMD LEDs mounted closely together.

[0004] Chip-on-board (COB) LED modules are of two types, wire bond COB and flip chip COB. In wire bond COB, the lateral LED chip is attached to the PCB substrate via bonding epoxy and connected to the conductive pads on the PCB via two soldering leads. The heat generated by the lateral LED chip is dissipated through the chip's sapphire substrate, bonding epoxy, and PCB substrate. On the other hand, flip chip COB enables the LED chip to be directly bonded to the conductive pads of the PCB without soldering leads and epoxy. The heat generated by the flip chip LED is dissipated through the chip pads, conductive pads, and PCB in sequence. Compared with wire bond COB, flip chip COB has a lower thermal resistance because its heat dissipation path does not include the sapphire substrate and bonding epoxy, which are materials with relatively high thermal resistance. Moreover, without wire bonding and its associated soldering process, the packaging cost is lower.

[0005] LED modules tend to generate a lot of heat when powered, which may require active cooling. Therefore, metal core PCBs are often selected for LED applications due to their enhanced heat dissipation capabilities. Although metal core PCBs transfer heat much more efficiently than traditional rigid PCBs, they are expensive. In chip-on-board (COB) LED modules, the manufacturing cost of metal core PCBs is even further increased because it requires more layers or more elaborate pattern printing in the PCB to accommodate densely packed LEDs and their associated thermal pads and tracks in a limited space. Multi-layer PCBs with complex thermal track patterns may also make it difficult to suppress noise on the PCB and control other performance parameters. Therefore, new methods of manufacturing LED modules are needed to overcome the above issues. Summary of the invention

[0006] The present invention provides an LED component, an LED display module and a manufacturing method thereof. In one embodiment, the LED component includes an LED (light emitting diode) chip array, a passivation layer arranged around the LED chip array and a metal pad array. The LED array has a plurality of LED chips, each of which has a first terminal and a second terminal. The first terminal of each LED chip in the LED chip array is electrically coupled to a first heat-conducting track, and the second terminal of each LED chip in the LED chip array is electrically coupled to a second heat-conducting track. Each metal pad in the metal pad array has a first surface in contact with the passivation layer and a second surface located outside the passivation layer. The first terminal and the second terminal of the LED chip are electrically coupled to the first surfaces of two metal pads in the metal pad array, respectively.

[0007] In addition, the first heat-conducting track network and the second heat-conducting track network both include heat-conducting tracks arranged in a planar direction and a vertical direction in the passivation layer. The passivation layer includes one or more dielectric materials.

[0008] In this scheme, in one aspect, the first terminal is a cathode and the second terminal is an anode. In another aspect, the first terminal is an anode and the second terminal is a cathode.

[0009] In another aspect, the thermal rails of the first thermal rail network are located in a first plane, and the thermal rails of the second thermal rail network are located in a second plane, and the first plurality of through holes are disposed between the first plane and the second plane.

[0010] In another aspect, a first surface of a metal pad in the array of metal pads is located on a third plane in the passivation layer, and a second plurality of vias is disposed between the second plane and the third plane.

[0011] In another aspect of the solution of the present invention, the LED chips in the LED chip array include red LED chips, green LED chips and blue LED chips.

[0012] The present invention also provides a method for manufacturing a light emitting diode (LED) assembly. The method includes arranging an LED chip array consisting of a plurality of LED chips on a carrier, wherein each LED chip in the LED chip array has a first terminal and a second terminal facing away from the carrier; covering the LED chip array with a molding compound layer; disposing a first passivation layer on the molding compound layer; disposing a second passivation layer on the first passivation layer; disposing a metal pad array on the second passivation layer; forming a first heat conductive track network in the first passivation layer; and forming a second heat conductive track network in the second passivation layer.

[0013] In this solution, on the one hand, a first thermal rail connects a first terminal of each LED chip in the LED chip array and at least one metal pad in the metal pad array, and a second thermal rail connects a second terminal of each LED chip and the LED chips in the LED chip array and at least one metal pad in the metal pad array.

[0014] In another aspect of this aspect, the method further includes attaching the metal pad array to a plurality of test circuits and testing the LED chip array on the carrier board.

[0015] In the solution of the present invention, each LED chip in the LED chip array is a substrate-less LED chip.

[0016] In another embodiment of the present invention, the LED display panel includes a plurality of LED chips, each of which includes a plurality of LED components mounted on a printed circuit board (PCB). The LED chip array can be arranged in a common cathode topology or a common anode topology. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The principles of the present invention may be more easily understood in conjunction with the following drawings and detailed description.

[0018] Figure 1 , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig.9A The invention shows a method for manufacturing an LED package composed of an LED chip array in accordance with the first embodiment of the present invention.

[0019] Figure 2B , Figure 3B , Figure 4B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Fig. 9BThe invention shows a method for manufacturing an LED package composed of an LED chip array in accordance with the second embodiment of the present invention.

[0020] Fig.10 The steps of tape and reel packaging of a plurality of LED packages manufactured using the method of the present invention are shown.

[0021] Fig.11 A schematic cross-sectional view of an LED package manufactured using the first method of the present invention is shown.

[0022] FIG. 12A to FIG. 12I The steps of building a layered structure on a molding layer are shown, which can be applied to the solution of the present invention.

[0023] Fig.13A 4X4LED package of the present invention.

[0024] Fig. 13B Yes Connect Fig.13A Top view of the pads and thermal rails of the multi-layer interconnects of the 4X4 LED package.

[0025] Fig. 13C yes Fig. 13B Exploded view of the LED package.

[0026] Fig.13D Shows Fig.13A The connections between the R, G, B LEDs in the 4X4LED package, the scan connections, the channel connections, and the thermal pads.

[0027] Fig.14A This is a perspective view of the top surface of the 10X15 LED patch.

[0028] Fig. 14B yes Fig.14A A perspective view of the bottom surface of the 10X15 LED patch.

[0029] Fig. 14C is a perspective view of a single LED patch attached to a PCB driver board.

[0030] Fig.14D is a perspective view of multiple LED patches covering the PCB driver board. DETAILED DESCRIPTION

[0031] Aspects of the present invention will be described in detail, examples of which are illustrated in the accompanying drawings. Note that, where practicable, like or similar reference numerals may be used in the drawings and may indicate like or similar elements.

[0032] These drawings describe the scheme of the present invention for illustration purposes only. It is easy for a person skilled in the art to recognize the objective existence of alternative schemes from the following description without departing from the general principles of the present invention.

[0033] Figure 1 , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig.9A According to the first solution of the present invention, a brief introduction to the manufacturing method of the LED package composed of the LED chip array is given respectively.

[0034] Figure 1 A carrier 10 for carrying an array of LED chips is given. The carrier 10 includes a base carrier 11 and a heat release tape 12 attached to the base carrier 11. The base carrier 11 is made of a material that can withstand high temperatures, such as glass, thermosetting plastic, etc. The base carrier 11 can be transparent or opaque. The heat release tape 12 is an adhesive tape adhered to the base carrier 11 at room temperature, but can be peeled off by heating at a high temperature, such as about 210°C.

[0035] Figure 2A An array of LED chips arranged on a carrier board 10 is given. In this scheme, each LED chip 20a has a substrate 21a made of, for example, sapphire or silicon carbide (SiC). A light-emitting layer 22a is provided on the substrate 21a, and the light-emitting layer 22a emits light of a certain color when powered on. In this scheme, each LED chip is composed of a red LED (R), a green LED (G), and a blue LED (B). A cluster of R, G, and B LEDs defines a display pixel. Each LED chip 20a with a substrate 21a can have the same height, for example, about 100 μm.

[0036] In this scheme, each LED chip 20a has a p-electrode and an n-electrode, both designated as 23a. Some of the drawings show only one electrode because they can be oriented in a direction where one electrode blocks the line of sight of the other electrode. When the LED chip array is placed on the thermal release tape 12, the LED chip array is flipped so that one or both electrodes 23a in each LED chip 20a are directly attached to the surface of the thermal release tape 12.

[0037] Figure 3AA carrier board 30a for carrying an array of LED chips is provided. The carrier board 30a may have the same width (or diameter) as the carrier board 10. The carrier board 30a has a base carrier board 31a and a temporary bonding (TBA) layer 32a disposed on the base carrier board 31a. The base carrier board 31a may be made of transparent glass. The edges of the glass panel may be polished to prevent cracking during the manufacturing process. The TBA layer 32a may be deposited on the surface of the base carrier board 31a by a spin coating process. It has a thickness of about 10 μm and can withstand temperatures up to 300°C.

[0038] like Figure 4A As shown, the carrier board 10 carrying the LED chip array (the preparation method is as shown in Figure 2A The substrate 10 is flipped over and aligned with the substrate 30a so that the LED chip array of the substrate 10 is bonded to the TBA layer 32a of the substrate 30a. Then, the substrate 10 is released from the LED chip array by heating it to a predetermined temperature, for example, 210° C. The LED chip array remains attached to the TBA layer 32a on the substrate 30a. As a result, the electrodes 23a of the LED chips 20a are exposed.

[0039] like Figure 5A As shown, the carrier board 30a with the LED chip array is covered by a molding layer 40a, which can be an opaque molding compound, such as a black resin. The black resin can be a mixture of black pigment and resin, epoxy resin or silicone resin.

[0040] Fig. 6A Three layers of interconnected thermal rails and / or metal pads are schematically shown. A first layer 60a-1 is disposed on the molding layer 40a and in contact with the LED chip array. A second layer 60a-2 is disposed above the first layer 60a-1, and a third layer 60a-3 is disposed above the second layer 60a-2. All three layers are partially or fully disposed in the interconnect layer 50a. The interconnect layer 50a is made of a passivation compound.

[0041] The first layer 60a-1 or the second layer 60a-2 each includes a thermally conductive track network that connects the anode or cathode of the LED chip array. When the thermally conductive track network connects the cathode of the LED in the LED chip array, it is called a scan connection. When the thermally conductive track network connects the anode of the LED in the LED chip array, it is called a cathode connection. In one embodiment, the first layer 60a-1 includes a scan connection and the second layer 60a-2 includes a cathode connection. In addition, the second layer 60a-2 includes a plurality of bypass thermally conductive tracks that are not connected to the LED terminals (see Fig. 13C), for example, to form a conductive path between the first layer 60a-1 and the third layer 60a-3. As shown in FIG3, the cathode connection in the second layer 60a-2 is "bypassed". The third layer 60a-3 includes an array of metal pads. The side of the metal pad facing the second layer 60a-2 is connected to the first layer 60a-1 and the second layer 60a-2 through a plurality of through holes 70a-1 or 70b-1, while the pad on the opposite side of the metal pad is exposed to be bonded to a PCB and / or other equipment.

[0042] Looking back Fig. 6A As shown, the first layer 60a-1 and the second layer 60a-2 have thermal rails connected to the LED terminals in the LED chip array. The third layer 60a-3 including the metal pad array is also connected to the first layer 60a-1 and the second layer 60a-2. Specifically, the first layer 60a-1 is electrically connected to the second layer 60a-2 through a first set of through holes 70a-1 filled with conductive material. The second layer 60a-2 is electrically connected to the third layer 60a-3 including the metal pad array through a second set of through holes 70a-2.

[0043] It should be noted that Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B and Fig.11 It is a simplified diagram showing the vertical positional relationship of the LED, three layers and carrier board, but it is not necessarily displayed in the original diagram size of the cross section between the plane and the LED package. In an actual product, the cross section of the LED chip array, the cross section of the metal pad marked as 60a-3, the cross section of the thermal rail marked as 60a-2, the cross section of the thermal rail marked as 60a-1, and the through hole marked as 70a-1 or 70a-2 cannot be located on the same plane. Fig. 13C and 13D LED, the layout and interconnections between the array, 60a-1 layer, 60a-2 layer, 60a-3 layer and bypass layer are well shown and explained.

[0044] FIG. 12A to FIG. 12I Further steps are given in an exemplary method for constructing interconnected thermal tracks / pads in interconnect layer 50a, for example, in Figure 5A On the device, get Fig. 6A equipment.

[0045] Fig. 12AThe device is shown after a mold layer 40a (eg, epoxy) is deposited on a carrier 30a having a base carrier 31a (eg, a glass panel) and a TBA layer 32a (eg, glue). The surface of the mold layer 40a may be cleaned using oxygen plasma.

[0046] exist Fig. 12B In the embodiment, the first conductive material is deposited on the mold layer 40a to form the first conductive layer 50a-1, for example, by electron beam deposition using an electron gun. The first conductive material may have a titanium (Ti) layer and a copper (Cu) layer, which are deposited in two separate steps.

[0047] Fig. 12C A photoresist (PR) material is provided on the first conductive layer 50a-1 to form the first convex layer 50a-2. The process begins by coating the first conductive layer 50a-1 with a photoresist (PR) material to form a PR layer. A patterned mask is then applied to the surface of the PR layer to block light so that only the unmasked areas of the material are exposed to light. A solvent called a developer is then applied to the PR layer. The photodegraded PR material is dissolved in the developer, leaving a coating (i.e., the first convex layer 50a-2) that matches the mask pattern. After this photolithography process, the first conductive layer 50a-1 and the first convex layer 50a-2 can be cleaned using oxygen plasma.

[0048] exist Fig.12D In the embodiment, the first conductive layer 50a-1 and the first convex layer 50a-2 are covered by the second conductive material to form the second conductive layer 50a-3. The process can be performed by electroplating which requires an electric current or by electroless electroplating which is performed by an autocatalytic chemical process. In electroplating, electrons are provided to an ionic metal to form a non-ionic coating on the substrate. In this scheme, a copper layer can be deposited to cover the first conductive layer 50a-1 and the first convex layer 50a-2.

[0049] like Fig.12E As shown, the first protrusion 50a-2 is removed to expose the thermal rail on the first conductive layer 50a-1. The stripping process can be performed by photoresist stripping by dry etching using a plasma etching device. During the stripping process, the second conductive material (copper) deposited on the first protrusion 50a-2 is also removed. Fig.12F As shown, the heat conducting track in the first conductive layer 50a-1 is further removed by etching to expose a portion of the molding layer 40a. The etching process may be performed using laser etching or plasma etching.

[0050] In this embodiment, the first conductive layer 50a-1 and the remaining portion of the second conductive layer 50a-3 form Fig. 6A or Fig. 13C The first layer 60a-1 in.

[0051] exist Figure 12G In the step shown, a first dielectric material is coated on the exposed portion of the second conductive layer 50a-3 and the mold layer 40a to form a first passivation layer 50a-4. This process can be performed by surface passivation with SiNR (silicon nanoribbon). Then, as shown in FIG. Fig.12H As shown, a plurality of through holes or trenches are formed in the first passivation layer 50a-4, for example, by laser etching. After the etching process, the surface of the first passivation layer 50a-4 may be cleaned by plasma ashing or scum removal.

[0052] like Fig.12I As shown, a plurality of vias or trenches are filled with a third conductive material to form a first set of conductive paths through via 70a-1. This process can be performed using electron beam evaporation or inkjet printing. The third conductive material can be tin-lead, nickel, silver or gold, or a mixture of tin-lead and silver.

[0053] Can be executed repeatedly FIG. 12B to FIG. 12I , to build additional layers on top of each other and to build interconnect paths between these layers. For example, a fourth conductive material may be deposited on the first passivation layer 50a-4, such as by electron beam deposition, to form a fourth conductive layer (similar to Fig. 12B 50a-1 is deposited on the layer 40a), a photoresist (PR) material is disposed on the fourth conductive layer to form a second convex layer (similar to Fig. 12C Steps shown), depositing a fifth conductive material coating on the fourth conductive layer and the second convex layer to form a fifth conductive layer by electroplating (similar to Fig.12D The second protrusion is peeled off to expose the thermal tracks on the fourth conductive layer (similar to Fig.12E The fourth conductive layer is removed by laser etching on a portion of the thermal track to expose a portion of the passivation layer (similar to Fig.12F The step shown in FIG. 4 is a step of forming a second passivation layer (similar to the step of forming a second passivation layer) by coating the exposed portion of the fifth conductive layer and the first passivation layer 50a-4 with a second passivation material. Figure 12G Then, a plurality of through holes or trenches are formed on the second passivation layer by etching (similar to Fig.12H and depositing a sixth conductive material in the plurality of through holes 70a-2 to form a second set of conductive paths (similar to Fig.12I In this scheme, the fourth conductive layer and the remaining part of the fifth conductive layer constitute the second layer 60a-2, as shown in FIG. Fig. 6A and Fig. 13C shown.

[0054] The metal pads in the third layer 60a-3 can be set on the second passivation layer. In this embodiment, the metal pads are flat, usually non-porous tin-lead, silver or gold-plated copper pads. This process can be performed by electroless nickel plating (ENIG) with immersion gold coating. In a preferred embodiment, the first passivation layer and the second passivation layer are dark. In an alternative embodiment, the second passivation layer can be covered by an opaque molding compound before the multiple conductive pads are set. The first passivation layer and the second passivation layer alone or together with another additional molding layer can constitute Fig. 6A The interconnect layer 50a in.

[0055] Fig. 6A The devices in the can be cut into LED packages. Fig. 7A In the embodiment, the mold layer 40a and the interconnection layer 50a are cut in a direction perpendicular to the top surface of the interconnection layer 50a by plasma cutting or a cutting saw to separate the plurality of LED packages from each other. In this scheme, the TBA layer 32a is preferably cut at least partially together with the mold layer 40a and the interconnection layer 50a so that the TBA layer 32a and the other layers can be peeled off from the base carrier 31a. Fig.9A .

[0056] Fig. 8A It is shown that each LED package (Ba-1 or Ba-2) can be tested and classified (commonly referred to as "binning") according to the physical characteristics of the LED chips in each LED package. Although not illustrated in the drawings, in an alternative, multiple test circuits can be set on the interconnect layer 50a to connect multiple metal pads before cutting, and the entire LED chip can be tested to measure performance characteristics. Then, the mold layer 40a and the interconnect layer 50a can be cut in a vertical direction by plasma cutting or a cutting saw to manufacture LED packages.

[0057] After binning, each LED package (Ba-1 or Ba-2) can be separated from the carrier 30a, as shown in FIG. Fig.9A As shown. In a preferred embodiment, the TBA layer 32a is debonded from each LED package for subsequent attachment to the tape. After peeling, the remaining substrate carrier 31a can be recycled. Fig.10 As shown, a plurality of LED packages peeled from the carrier board 30a are packaged using a tape.

[0058] exist Fig.11 In the embodiment, a plurality of LED packages (Ba-1, Ba-2, Ba-3, Ba-4) are mounted on a printed circuit board (PCB) 80 by, for example, a surface mount technology (SMT) using a reflow soldering process. Fig.11Although not illustrated in the figure, PCB 80 may contain a plurality of electronic components, including integrated circuit (IC) passive components, such as inductors, resistors, capacitors, etc. On the top surface of PCB 80, conductive pads are provided to connect with the metal pads of each LED package. In some embodiments, the metal pads are flat, typically tin-lead, silver or gold-plated copper pads without holes. PCB 80 may also include a driver circuit.

[0059] Although the details of the driver circuit are not described in the present invention, in some aspects, the driver circuit may include a phase-locked loop, multiple pulse width modulation engines, configuration registers, multiple gain-adjustable fast charging current sources, and a serial input / output interface.

[0060] As a reflow soldering process, a lead-free solder paste 81 may be disposed on a plurality of conductive pads on the top surface of the PCB 80, and a plurality of LED packages are arranged so that a metal pad of each LED package is attached to the solder paste 81 on each conductive pad of the PCB 80. After the surface mount technology (SMT) process is completed, the plurality of LED packages mounted on the PCB 80 may be packaged by a transparent molding compound (e.g., epoxy resin) to form a packaging layer 90.

[0061] Figure 2B , Figure 3B , Figure 4B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Fig. 9B According to a second embodiment of the present invention, a method for manufacturing an LED package composed of an LED chip array is provided.

[0062] In the second embodiment, the LED chip 20b does not have a substrate. The LED chip or die typically has a light-emitting layer, such as indium gallium nitride (InGaN), on top of a sapphire substrate. A common alternative to sapphire is silicon carbide (SiC). Sapphire substrates are typically used because their thermal properties are similar to InGaN. However, a disadvantage of sapphire is that there is a large mismatch between its lattice structure and that of InGaN. This mismatch introduces microcracks into the LED structure during the manufacturing process, thereby compromising the efficiency of the LED. Without a substrate, manufacturing costs can be reduced and LED efficiency can be improved. In addition, in the absence of such a substrate, the height of the LED chip 20b can be significantly reduced, and the thickness of the LED package will also be reduced accordingly, making the display module thinner and lighter. In this embodiment, the LED chip 20b without a substrate (such as Figure 2B The thickness of the LED chip 20a is about 5 μm, which is much smaller than that of the LED chip 20a with a substrate (as shown in FIG. Figure 2A), and its thickness is about 100 μm. A detailed method of manufacturing an LED package using such an LED chip 20 b without a substrate will be described below.

[0063] like Figure 2B As shown, the LED chip array is arranged on a carrier board 10 (see Figure 1 ), wherein the LED chip 20b does not have a substrate. Each LED chip 20b without a substrate can have the same height, for example, about 5 μm. Due to its orientation problem, the figure only shows one electrode 23b, but in this scheme, each LED chip 20b has two electrodes, a p-electrode and an n-electrode. When the LED chip array is placed on the heat release tape 12, the LED chip is turned over so that at least one electrode in each LED chip 20b is directly attached to the surface of the heat release tape 12.

[0064] exist Figure 3B In the embodiment, a carrier 30b for carrying an array of LED chips is prepared. The carrier 30b may have the same width as the carrier 10. The carrier 30b includes: a base carrier 31b; a temporary bonding (TBA) layer 32b disposed on the base carrier 31b; and a transparent layer 33b disposed on the TBA layer 32b. The array of LED chips is disposed on the transparent layer 33b. The base carrier 31b may be made of transparent glass. The transparent layer 33b may be formed of a transparent molding compound such as epoxy resin, and may have a thickness of approximately 50 to 100 μm. The transparent layer 33b is thicker, so it can be used for certain functions of the substrate that are lacking in the present solution.

[0065] like Figure 4B As shown, the carrier board 10 carrying the LED chip array (the preparation method is as shown in Figure 2B The substrate 10 is flipped over and aligned with the substrate 30b so that the LED chip array of the substrate 10 is bonded to the transparent layer 33b of the substrate 30b. The substrate 10 is then released from the LED chip array. The LED chip array remains attached to the transparent layer 33b of the substrate 30b. As a result, the electrodes of each LED chip 20b are exposed.

[0066] The substrate 30b with the LED chip array is covered with an opaque molding compound to form a molding layer 40b (eg, Figure 5B shown).

[0067] like Figure 6B As shown, three conductive layers are constructed on the mold layer 40b, including a first layer 60b-1 (scan connection), a second layer 60b-2 (channel connection) and a third layer 60b-3 including a metal pad array (see also Fig. 13C). The first layer 60b-1 is disposed on the molding layer 40b and electrically connects the LED chip arrays to each other through a common electrode, and the second layer 60b-2 is disposed between the first layer 60b-1 and the third layer 60b-3 including the metal pad array and connects the LED chip arrays through another electrode.

[0068] Likewise, the first layer 60b-1 or the second layer 60b-2 may contain scan connections or channel connections. Conductive paths through vias 70b-1 and 70b-2 connect the layers vertically, thereby enabling the LED to be energized when connected to a power source. A passivation compound is coated on the mold layer 40b to form an interconnect layer 50b that contains or supports three conductive layers.

[0069] Figure 6B The equipment shown can also be FIG. 12A to FIG. 12I It can be further cut into LED chips, tested, binned and packaged, such as Figure 7B , Figure 8B , Fig. 9B and Fig.10 shown. Figure 7B It is shown that the mold layer 40b, the interconnection layer 50b and the transparent layer 33b are cut in a direction perpendicular to the top surface of the interconnection layer 50b by plasma cutting or a cutting saw, thereby separating the plurality of LED packages from each other. In this scheme, the TBA layer 32b is preferably cut at least partially together with the transparent layer 33b, so that the TBA layer 32b and other layers can be peeled off from the base carrier 31b, see Fig. 9B .

[0070] like Figure 8B As shown, each LED package (Bb-1 or Bb-2) is tested and classified (commonly referred to as "binning") according to the physical characteristics of the LED chips in each LED package. Although not illustrated in the drawings, in an alternative, before cutting, multiple test circuits can be set on the interconnection layer 50b to interconnect multiple conductive pads, and all LED chips can be tested by multiple test circuits according to the physical characteristics of the LED chips. The molding layer 40b and the interconnection layer 50b can then be cut in a vertical direction by plasma cutting or a cutting saw to separate the multiple LED packages from each other.

[0071] like Fig. 9B As shown, after the binning process, each LED package is peeled off from the carrier 30b. In a preferred embodiment, the TBA layer 32b can be debonded from each LED package so that it can be subsequently attached to the tape. After peeling, the remaining carrier 30b can be recycled and reused. Fig.10In the process, the plurality of LED packages peeled from the carrier board 30b are further packaged with a tape and then mounted on a printed circuit board (PCB) by a surface mount technology (SMT) using a reflow soldering process. After the surface mount technology (SMT) process is completed, the plurality of LED packages mounted on the PCB can be packaged again by a transparent molding compound such as epoxy resin.

[0072] Fig.9A and Fig. 9B The LED package shown in has a 2X2 matrix of RGB LED units (four total). Larger LED packages may contain a 4X4 matrix or more. Fig.13A An LED package (4X4 LED package) having a 4X4 matrix of RGB LED units manufactured according to one embodiment of the present invention is provided.

[0073] like Fig.13A As shown, the 4X4 LED package includes a total of 16 RGB LED units, each unit having a red LED, a green LED and a blue LED. The LED package has multiple layers, including a molding layer 40a, an interconnection layer 50a and three conductive layers. Fig. 13B and 13C LEDs and three conductive layers (60a-1, 60a-2, 60a-3) are shown, but the mold layer 40a and the interconnect layer 50a are omitted. The three conductive layers include a first layer 60a-1 of the network, a second layer 60a-2, and a third layer 60a-3 containing a metal pad array. The RGB LED chip array is arranged on the first layer 60a-1.

[0074] Fig.13D A top view of a 4X4 LED package and an exploded view of the device are given. An array of RGB LED chips is arranged on the first layer 60a-1. The thermal rails connecting the cathodes of multiple LED chips in the first layer 60a-1 are scanned. On the other hand, the anode nodes of the RGB LED chips are not interconnected in the first layer 60a-1.

[0075] For example, M and P are two clusters of anode nodes, while nodes O and N are in a scanning connection connecting the cathodes of multiple LED chips. M, P, O, and N are all set in the first layer 60a-1. O and N are further connected to nodes O' and N' on the bypass thermal rail in the second layer 60a-2 (through vias in the interconnect layer 50a, not shown). Nodes O' and N' are connected to metal pads in the third layer 60a-3 through vias. M and P are connected to corresponding nodes M' and P' in the channel connection of the second layer 60a-2, respectively, and are further connected to the metal pads of the third layer 60a-3 through the channel connection and the vias of the interconnect layer 50a. In this way, the anode of the LED chip (through nodes M, P, M', P' and corresponding thermal rails and vias) and the cathode of the LED chip (through nodes O, N, O', N' and corresponding thermal rails and vias) are connected to the metal pads. Note that the dotted line represents the conductive path between two nodes.

[0076] In this scheme, the first layer, the second layer and the third layer are partially or completely arranged in the interconnection layer 50a of each LED package (Ba-1, Ba-2, Ba-3 or Ba-4) instead of being arranged on the PCB 80, thereby creating additional space in the vertical direction of the LED chip.

[0077] Such a chip-on-board (COB) LED package is beneficial for the following reasons. First, it reduces the number of pads and the complexity and manufacturing cost of the thermal rails on the PCB. In addition, establishing a thermal rail layer in the LED chip can free up the space on the PCB that was originally occupied by the thermal rail, so that more LED chips can be installed on the PCB, thereby achieving a higher density of LED chips and a higher resolution display module.

[0078] The solution of the present invention can be applied to LED displays with common cathode topology or common anode topology. In the common anode topology, the anodes of the RGB LEDs are effectively connected to the same power supply through scan lines controlled by scan switches, while the cathodes of the LEDs are connected to the output of the current driver. In the common cathode topology, the anodes of the R, G or B LEDs can be effectively connected to their respective power supplies. In this way, the red LED with a lower forward voltage can be powered by a power supply with a lower output voltage than the green or blue LEDs. One of the applicant's patents, such as US8,963,810, describes the common cathode LED panel and related drive circuits in detail.

[0079] Figures 13B-13DThe scheme shown in can be arranged in a common cathode topology or a common anode topology. In the common cathode topology, the anode of the LED chip is connected to the channel connection and the cathode is connected to the scan connection. Conversely, in the common anode topology, the cathode of the LED chip is connected to the channel connection and the anode is connected to the scan connection.

[0080] An LED package having a large matrix (eg, a 10×15 matrix or more) of RGB LED units may be referred to as an LED chip. Fig.14A and 14B The top and bottom perspective views of the patch are shown. On the bottom of the patch, each metal pad covers an RGB LED unit. Fig. 14C As shown, the LED patch can be mounted on a PCB (i.e., a driver board) so that each metal pad of the LED patch is connected to a corresponding conductive pad on the driver board. After all necessary LED patches are arranged and connected to the driver board, as shown in FIG. Fig.14D As shown, the surface of the LED patch can be encapsulated to facilitate fixing the LED patch to the driver board and protect the LED chip thereon.

[0081] The scheme of the present invention has been described in detail. Other schemes will become apparent to those skilled in the art through consideration and practice of the present invention. Therefore, this specification and the accompanying drawings are considered to be exemplary and explanatory only, and the true scope of the present invention is set forth one by one in the appended claims.

Claims

1. An LED assembly, comprising: LED chip array, a passivation layer and a metal pad array arranged around the LED chip array, The LED chip array includes a plurality of LED chips, each LED chip includes a first terminal and a second terminal. The first terminal of each LED chip in the LED chip array is electrically coupled to the first thermal conductive track network, and The second terminal of each LED chip in the LED chip array is electrically coupled to the second thermal conductive track network. Each metal pad in the metal pad array has a first surface in contact with the passivation layer and a second surface outside the passivation layer. The first terminal and the second terminal of the LED chip are electrically coupled to the first surfaces of two metal pads in the metal pad array respectively. The first heat-conducting track network and the second heat-conducting track network include heat-conducting tracks arranged in the passivation layer along the plane direction and the vertical direction, and wherein the passivation layer comprises one or more dielectric materials; The first thermally conductive track network includes thermally conductive tracks located in a first plane, and the second thermally conductive track network includes thermally conductive tracks located in a second plane, and a first plurality of through holes are disposed between the first plane and the second plane; The LED chips in the LED chip array include red LED chips, green LED chips and blue LED chips.

2. The LED assembly according to claim 1, wherein: The first terminal is a cathode and the second terminal is an anode.

3. The LED assembly according to claim 1, wherein: The first terminal is an anode and the second terminal is a cathode.

4. The LED assembly according to claim 1, wherein: First surfaces of metal pads in the array of metal pads are located on a third plane in the passivation layer, and a second plurality of vias are disposed between the second plane and the third plane.

5. A method for manufacturing an LED assembly, comprising: Arranging an LED chip array consisting of a plurality of LED chips on the carrier, wherein each LED chip in the LED chip array has a first terminal and a second terminal facing away from the carrier; Covering the LED chip array with a molding compound layer; Disposing a first passivation layer on the molding compound layer; Disposing a second passivation layer on the first passivation layer; Disposing a metal pad array on the second passivation layer; forming a first thermal conductive track in the first passivation layer, wherein the first thermal conductive track connects a first terminal of each LED chip in the LED chip array and at least one metal pad in the metal pad array; and A second thermal conductive track is formed in the second passivation layer, wherein the second thermal conductive track connects the second terminal of each LED chip in the LED chip array and at least one metal pad in the metal pad array.

6. The method according to claim 5, further comprising: attaching the metal pad array to a plurality of test circuits; as well as Test the LED chip array on the carrier board.

7. The method according to claim 5, further comprising: cutting the first passivation layer and the second passivation layer to separate the light emitting diode array; as well as The cut LED chip array is peeled off from the carrier board to obtain a plurality of LED packages.

8. The method according to claim 5, wherein: Each LED chip in the LED chip array is a substrate-less LED chip.

9. The method according to claim 5, wherein: The first thermally conductive track network includes thermally conductive tracks located in a first plane, and the second thermally conductive track network includes thermally conductive tracks located in a second plane, and a first plurality of through holes is disposed between the first plane and the second plane.

10. The method according to claim 9, wherein: First surfaces of metal pads in the array of metal pads are located on a third plane in the second passivation layer, and a second plurality of vias are disposed between the second plane and the third plane.

11. The method according to claim 5, wherein: The first terminal is a cathode and the second terminal is an anode.

12. The method according to claim 5, wherein: The first terminal is an anode and the second terminal is a cathode.

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