Display device

Abstract

A display device is provided. The display device includes a substrate having a display area configured to display an image and a peripheral area located outside the display area. A first thin film transistor is disposed in the display area. A display element is electrically connected to the first thin film transistor. The display element includes a pixel electrode, an intermediate layer, and a counter electrode. An embedded driving circuit portion is disposed in the peripheral area. The embedded driving circuit portion includes a second thin film transistor. A common voltage supply line is disposed in the peripheral area. The common voltage supply line is positioned closer to the display area than the embedded driving circuit portion. The common voltage supply line is electrically connected to the counter electrode.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2018-0161182, filed with the Korean Intellectual Property Office on December 13, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a display device. Background Art

[0003] A display device is a device for visually displaying an image. Such a display device may include a substrate divided into a display area and a peripheral area. The display area may include scan lines and data lines formed to be insulated from each other, and include a plurality of pixels. In addition, the display area may include thin film transistors and pixel electrodes, and the pixel electrodes are electrically connected to the thin film transistors corresponding to each pixel. The display area may also include counter electrodes commonly provided in the pixels. The peripheral area may include various wirings, a scan driver, a data driver, and a controller for transmitting an electrical signal to the display area.

[0004] The uses of such display devices have been diversified. Accordingly, the design of the peripheral area of the display device has also been diversified, and there is a tendency to reduce the size of the peripheral area. Summary of the Invention

[0005] One or more exemplary embodiments include a display device that reduces the space occupied by the peripheral area and realizes a high-quality image. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0007] According to one or more embodiments, a display device includes a substrate having a display area configured to display an image and a peripheral area positioned outside the display area. A first thin film transistor is provided in the display area. A display element is electrically connected to the first thin film transistor. The display element includes a pixel electrode, an intermediate layer, and a counter electrode. An embedded driving circuit part is provided in the peripheral area. The embedded driving circuit part includes a second thin film transistor. A common voltage supply line is provided in the peripheral area. The common voltage supply line is positioned closer to the display area than the embedded driving circuit part. The common voltage supply line is electrically connected to the counter electrode.

[0008] The display device may further include: a planarization layer covering at least a part of the embedded driving circuit part; and a shielding layer positioned on the planarization layer, the shielding layer at least partially overlapping with the embedded driving circuit part. The planarization layer may include a via hole exposing the common voltage supply line.

[0009] The shielding layer may include a material same as that of the pixel electrode and may be in contact with the common voltage supply line through a via hole. A part of the shielding layer may be in contact with the counter electrode.

[0010] The shielding layer may be integrated with the counter electrode and may be in contact with the common voltage supply line through a via hole.

[0011] The shielding layer may include: a first shielding layer including a material same as that of the pixel electrode; and a second shielding layer extending from the counter electrode.

[0012] The shielding layer may include a plurality of through holes.

[0013] The display device may further include: a dam portion located outside the common voltage supply line, the dam portion protruding from the substrate. The dam portion may at least partially overlap with the embedded driving circuit portion.

[0014] The dam portion may include a first dam and a second dam separated from each other. The height of the first dam and the height of the second dam may be substantially equal to each other.

[0015] The dam portion may include a first layer and a second layer, and a side surface of the first layer may be curved by a halftone mask process.

[0016] The display device may further include a support member located outside the dam portion, the support member protruding from an upper surface of the substrate. A height of the support member from the upper surface of the substrate may be less than a height of the dam portion from the upper surface of the substrate.

[0017] The display device may further include a wiring portion located outside the embedded driving circuit portion, the wiring portion transmitting a signal to the embedded driving circuit portion. At least one of the dam portion and the support member may at least partially overlap with the wiring portion.

[0018] The display device may further include: a planarization layer located between the first thin film transistor and the display element, the planarization layer including an organic material; and an inorganic protection layer located between the planarization layer and the first thin film transistor. The inorganic protection layer may cover a source electrode and a drain electrode of the first thin film transistor and extend to a peripheral region. In the peripheral region, the inorganic protection layer may include a region not covered by the planarization layer and an organic material formed in the same layer as the planarization layer.

[0019] The inorganic protection layer may include a hole exposing the common voltage supply line. A conductive protection layer for protecting the common voltage supply line may be arranged corresponding to the hole.

[0020] The display device may further include a thin film encapsulation layer covering the display area, and the thin film encapsulation layer includes at least one inorganic encapsulation layer and at least one organic encapsulation layer. In the peripheral area, the at least one inorganic encapsulation layer may be in contact with the inorganic protection layer.

[0021] The display device may further include: a color filter glass facing the substrate; and a sealing member located outside the peripheral area, and the sealing member bonds the substrate and the color filter glass together.

[0022] According to one or more exemplary embodiments of the inventive concept, a display device includes a substrate having a display area configured to display an image and a peripheral area located outside the display area. A first thin film transistor is disposed in the display area. A display element is electrically connected to the first thin film transistor. A planarization layer is disposed between the first thin film transistor and the display element. The planarization layer includes an organic material. An inorganic protection layer is disposed between the planarization layer and the first thin film transistor. The inorganic protection layer covers source and drain electrodes of the first thin film transistor and extends into the peripheral area. A thin film encapsulation layer covers the display area. The thin film encapsulation layer includes at least one inorganic encapsulation layer and at least one organic encapsulation layer. The inorganic encapsulation layer contacts the inorganic protection layer in the peripheral area.

[0023] The display device may further include: a dam portion disposed in the peripheral area, the dam portion protruding from the substrate; and an embedded driving circuit portion disposed in the peripheral area, the embedded driving circuit portion including a second thin film transistor. The inorganic encapsulation layer contacts the inorganic protection layer in a peripheral area farther from the display area than the dam portion.

[0024] The display device may further include: a planarization layer covering at least a portion of the embedded driving circuit portion; and a shielding layer located on the planarization layer. The shielding layer may at least partially overlap with the embedded driving circuit portion. The planarization layer may include via holes exposing a common voltage supply line.

[0025] The dam portion may at least partially overlap with the second thin film transistor of the embedded driving circuit portion.

[0026] The display device may further include: a wiring portion located outside the embedded driving circuit portion; and a protruding portion located outside the dam portion. The protruding portion may have a height lower than that of the dam portion. At least one of the dam portion and the protruding portion may overlap with the wiring portion.

[0027] The display device may further include: a sealing member located outside the protruding portion; and an upper substrate facing the substrate. The substrate and the upper substrate may be bonded together by the sealing member.

[0028] According to one or more embodiments, a display device includes a substrate having a display area configured to display an image and a peripheral area located outside the display area. A first thin film transistor is disposed in the display area. A display element is electrically connected to the first thin film transistor. The display element includes a pixel electrode, an intermediate layer, and a counter electrode. An embedded driving circuit portion is disposed in the peripheral area. The embedded driving circuit portion includes a second thin film transistor. A wiring portion is disposed at one side of the embedded driving circuit portion. The wiring portion has a wiring connected to the embedded driving circuit portion. A first shielding layer at least partially overlaps with the second thin film transistor, and a planarization layer is disposed between the first shielding layer and the second thin film transistor. The first shielding layer includes the same material as that of the pixel electrode. A second shielding layer is disposed on the first shielding layer. The second shielding layer extends from the counter electrode. One end of the second shielding layer is disposed between the wiring portion and the display area.

[0029] The first shielding layer may include a plurality of through holes.

[0030] The display device may further include: an inorganic protection layer disposed between the second thin film transistor and the planarization layer; and a conductive protection layer disposed between the inorganic protection layer and the planarization layer. The conductive protection layer may include a conductive material. The conductive protection layer may overlap with the second thin film transistor.

[0031] The display device may further include a dam portion in the peripheral area protruding from the substrate. The dam portion may at least partially overlap with the embedded driving circuit portion.

[0032] The display device may further include: a planarization layer disposed between the first thin film transistor and the display element, the planarization layer including an organic material; and an inorganic protection layer disposed between the planarization layer and the first thin film transistor. The inorganic protection layer may cover source and drain electrodes of the first thin film transistor and extend to the peripheral area. In the peripheral area, the inorganic protection layer may include an area not covered by the planarization layer and an organic material formed in the same layer as the planarization layer.

[0033] According to an exemplary embodiment of the inventive concept, a display device includes a substrate having a display area configured to display an image and a peripheral area positioned outside the display area. The peripheral area includes a top peripheral area, a bottom peripheral area, a left peripheral area, and a right peripheral area. A first thin film transistor is disposed in the display area. A display element is electrically connected to the first thin film transistor. The display element includes a pixel electrode, an intermediate layer, and a counter electrode. An embedded driving circuit portion is disposed in the left peripheral area and the right peripheral area. The embedded driving circuit portion includes a second thin film transistor. A common voltage supply line is disposed in at least one of the top peripheral area and the bottom peripheral area and not in the left peripheral area and the right peripheral area. The common voltage supply line is electrically connected to the counter electrode.

[0034] Aspects, features, and advantages other than those described above can be more easily understood by reference to the accompanying drawings, claims, and detailed description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] These and / or other aspects will become apparent and more readily appreciated from the following description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:

[0036] Figure 1 is a plan view of a display device according to an exemplary embodiment of the inventive concept;

[0037] Figure 2A is according to an exemplary embodiment of the inventive concept Figure 1 equivalent circuit diagram of a pixel in the display device of;

[0038] Figure 2B is according to another exemplary embodiment of the inventive concept Figure 1 equivalent circuit diagram of a pixel in the display device of;

[0039] Figure 3A is according to an exemplary embodiment of the inventive concept along Figure 1 cross-sectional view of the display device taken along lines I-I' and II-II';

[0040] Figure 3B is according to an exemplary embodiment of the inventive concept along Figure 1 cross-sectional view of the display device including a mask support on a support taken along lines I-I' and II-II';

[0041] Figure 4 is according to another exemplary embodiment of the inventive concept along Figure 1 cross-sectional view of the display device taken along lines I-I' and II-II';

[0042] Figure 5 is according to another exemplary embodiment of the inventive concept along Figure 1 cross-sectional view of the display device taken along lines I-I' and II-II';

[0043] Figure 6 is according to another exemplary embodiment of the inventive concept along Figure 1 cross-sectional view of the display device taken along lines I-I' and II-II';

[0044] Figure 7 is according to another exemplary embodiment of the inventive concept along Figure 1 cross-sectional view of the display device taken along lines I-I' and II-II';

[0045] Figure 8A is a cross-sectional view of a display device taken along line I-I' and line II-II' of another exemplary embodiment according to the inventive concept; Figure 1

[0046] Figure 8B is a cross-sectional view of a display device taken along line I-I' and line II-II' of another exemplary embodiment according to the inventive concept; Figure 1

[0047] Figure 9 is a cross-sectional view of a display device taken along line I-I' and line II-II' of another exemplary embodiment according to the inventive concept; Figure 1

[0048] Figure 10 is a cross-sectional view of a display device taken along line I-I' and line II-II' of another exemplary embodiment according to the inventive concept; Figure 1

[0049] Figure 11 is a plan view of a display device of another exemplary embodiment according to the inventive concept; and

[0050] Figure 12 is a cross-sectional view of a display device taken along line II-II' and line III-III' of an exemplary embodiment according to the inventive concept. Figure 11 DETAILED DESCRIPTION

[0051] Although embodiments that can have various modifications are disclosed, exemplary embodiments are shown in the drawings and described in the detailed description. The advantages and features of the exemplary embodiments and methods of implementing them will be clarified by the embodiments described below with reference to the drawings. In this regard, the disclosed embodiments can have different forms and should not be construed as limited to the descriptions set forth herein.

[0052] Now, exemplary embodiments will be described in detail. Examples of the exemplary embodiments are shown in the drawings, where like reference numerals always denote like elements, and repeated descriptions thereof will be omitted.

[0053] It will be understood that although terms such as "first" and "second" may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

[0054] Expressions used in the singular include the plural expression unless the expression has a clearly different meaning in the context.

[0055] ​​​​​It will also be understood that the terms "comprises", "comprising" and / or "having" used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0056] It will be understood that when a film, region or element is referred to as being "on" another part, the film, region or element can be directly or indirectly on the other part. For example, there can be intermediate films, regions or elements.

[0057] For ease of illustration, the dimensions of components in the drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the drawings are arbitrarily shown for ease of illustration, the following embodiments are not limited thereto.

[0058] It will be understood that when a layer, region or component is connected to another part, the layer, region or component can be directly connected to the other part, or there can be intermediate layers, regions or components. For example, when a layer, region or component is electrically connected to another part, the layer, region or component can be directly electrically connected to the other part, or can be indirectly connected to the other part through another layer, region or component.

[0059] In addition, the x-axis, y-axis and z-axis are not limited to the three axes on a rectangular coordinate system. For example, the x-axis, y-axis and z-axis can be perpendicular to each other or can represent different directions that are not perpendicular to each other.

[0060] The display device can be used to display images, texts, etc., and can be classified into a liquid crystal display, an electrophoretic display, an organic light-emitting display, an inorganic light-emitting display, a quantum dot light-emitting display, a field emission display, a surface conduction electron emission display, and a plasma display.

[0061] Hereinafter, the organic light-emitting display will be described as the display device according to an exemplary embodiment, but the display device according to the exemplary embodiments of the inventive concept is not limited thereto, and various display devices can be used.

[0062] Figure 1 is a plan view of a display device according to an exemplary embodiment of the inventive concept.

[0063] Referring to Figure 1 , the display device can include a display area DA and a peripheral area PA disposed around the display area DA. The display device can generate an image by using light emitted from a plurality of pixels disposed in the display area DA.

[0064] The display area DA can include pixels P, and the pixels P are connected to data lines DL extending in a first direction and scan lines SL extending in a second direction intersecting the first direction. Each of the pixels P can also be connected to a driving voltage line PL extending in the first direction.

[0065] Each of the pixels P may include a display element such as an organic light emitting element. In an exemplary embodiment, each pixel P may emit light of, for example, red, green, blue, or white through the organic light emitting element. The pixel P in the present specification may be understood as a pixel that emits any one of red, green, blue, and white as described above.

[0066] Each pixel P may be electrically connected to an embedded circuit disposed in the peripheral area PA. The peripheral area PA may include an embedded driving circuit portion 40, a wiring portion 50, a terminal portion 30, a first power line 10, and a second power line 20.

[0067] The embedded driving circuit portion 40 may include a plurality of thin film transistors (TFTs) and may provide a scan signal to each pixel P through a scan line SL. In an exemplary embodiment, the embedded driving circuit portion 40 may be disposed on both sides of the display area DA, and the display area DA is located between the embedded driving circuit portions 40. A part of the pixels P disposed in the display area DA may be electrically connected to the embedded driving circuit portion 40 disposed on the left side of the display area DA, and the remaining pixels P may be electrically connected to the embedded driving circuit portion 40 disposed on the right side of the display area DA. In another exemplary embodiment, the embedded driving circuit portion 40 may be disposed only on one side of the display area DA.

[0068] The wiring portion 50 may be disposed on one side of the embedded driving circuit portion 40. The wiring portion 50 refers to an area where wirings for transmitting signals for driving the embedded driving circuit portion 40 are disposed. For example, as Figure 1 shown, the wiring portion 50 may be located in the peripheral area PA adjacent to the embedded driving circuit portion 40 and is disposed farther from the display area DA than the embedded driving circuit portion 40.

[0069] The terminal portion 30 may be disposed on one side of the substrate 100. The terminal portion 30 may be exposed without being covered by an insulating layer. The terminal portion 30 may be electrically connected to a printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal portion 30.

[0070] The printed circuit board PCB may transmit signals or power of the control portion to the terminal portion 30. The control portion may respectively supply a driving power voltage ELVDD and a common voltage ELVSS (see Figure 2A and Figure 2B) is supplied to the first power supply line 10 and the second power supply line 20. The driving power supply voltage ELVDD can be supplied to each pixel P through the driving voltage line PL connected to the first power supply line 10, and the common voltage ELVSS can be supplied to the counter electrode of the pixel P connected to the second power supply line 20. The second power supply line 20 can at least partially surround the display area DA. The second power supply line 20 can at least partially surround the first power supply line 10. In another exemplary embodiment, the second power supply line 20 can be arranged between the first power supply line 10 and the display area DA. As Figure 1 shown in the exemplary embodiment of, the second power supply line 20 can be arranged between the embedded driving circuit portion 40 and the display area DA. Since the second power supply line 20 supplies the common voltage ELVSS, the second power supply line 20 can be referred to as a common voltage supply line. As Figure 1 shown in, the second power supply line 20 can be arranged in the peripheral area PA adjacent to the upper side, lower side, left side, and right side of the display area DA. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, the second power supply line 20 can be arranged to correspond to at least one of the upper side, lower side, left side, and right side of the display area DA.

[0071] The control signal generated in the control portion can be transmitted to the embedded driving circuit portion 40 and the wiring portion 50 through the printed circuit board PCB and the third connection line 31 and the fourth connection line 41. In addition, the signal transmitted to the wiring portion 50 can be transmitted to the embedded driving circuit portion 40.

[0072] The data driving circuit 60 can be electrically connected to the data line DL. The data signal of the data driving circuit 60 can be supplied to each pixel P through the connection line connected to the terminal portion 30 and the data line DL connected to the connection line. Figure 1 It is shown that the data driving circuit 60 is provided on the printed circuit board PCB, but in another exemplary embodiment, the data driving circuit 60 can be provided on the substrate 100. For example, the data driving circuit 60 can be provided between the terminal portion 30 and the first power supply line 10.

[0073] The dam portion 120 can be provided in the peripheral area PA. The dam portion 120 can include at least one dam. Figure 1 A structure in which two dams (including the first dam 121 and the second dam 123) are arranged is shown. When forming the organic encapsulation layer 420 of the thin film encapsulation layer 400 (see Figure 3A) When [condition not specified in the original], the dam portion 120 can prevent the organic material from flowing towards the edge of the substrate 100. Accordingly, the formation of the edge tails of the organic encapsulation layer 420 can be prevented. The dam portion 120 located in the peripheral area PA can surround at least a part of the display area DA. When a plurality of dams (such as the first dam 121 and the second dam 123) are provided, the first dam 121 and the second dam 123 can be separated from each other, and the first dam 121 can be arranged to surround at least a part of the second dam 123.

[0074] In some exemplary embodiments, at least a part of the dam portion 120 can overlap with the embedded driving circuit portion 40. For example, the first dam 121 or the second dam 123 can overlap with the embedded driving circuit portion 40. In other embodiments, as Figure 1 shown, both the first dam 121 and the second dam 123 can overlap with the embedded driving circuit portion 40.

[0075] In some exemplary embodiments, at least a part of the dam portion 120 can overlap with the wiring portion 50. For example, the first dam 121 or the second dam 123 can overlap with the wiring portion 50. In other embodiments, both the first dam 121 and the second dam 123 can overlap with the wiring portion 50.

[0076] Since the dam portion 120 overlaps with the embedded driving circuit portion 40 and / or the wiring portion 50, it may not be necessary to provide a separate dedicated area for the dam portion 120 in the peripheral area PA. Accordingly, the size of the peripheral area PA can be reduced.

[0077] On the lower side of the display area DA, the dam portion 120 can overlap with the second power supply line 20. However, the present disclosure is not limited thereto. Various modifications can be made thereto. For example, the dam portion 120 can overlap with the first power supply line 10, or the first dam 121 can overlap with the second power supply line 20 and the second dam 123 can overlap with the first power supply line 10, etc.

[0078] Figure 2A and Figure 2B is an equivalent circuit diagram of any one pixel in the display device according to an exemplary embodiment.

[0079] Referring to Figure 2A , each pixel P can include a pixel circuit PC connected to the scan line SL and the data line DL and an organic light emitting diode (hereinafter, also referred to as an organic light emitting device) OLED connected to the pixel circuit PC.

[0080] The pixel circuit PC may include a driving TFT T1, a switching TFT T2, and a storage capacitor Cst. The switching TFT T2 may be connected to a scan line SL and a data line DL, and may transmit a data signal Dm input through the data line DL to the driving TFT T1 according to a scan signal Sn.

[0081] The storage capacitor Cst may be connected to the switching TFT T2 and a driving voltage line PL, and may store a voltage corresponding to the difference between the voltage received from the switching TFT T2 and a first power supply voltage (e.g., a driving power supply voltage ELVDD) supplied to the driving voltage line PL.

[0082] The driving TFT T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current corresponding to the voltage value stored in the storage capacitor Cst flowing from the driving voltage line PL through the organic light emitting device OLED. The organic light emitting device OLED may emit light with a predetermined brightness according to the driving current.

[0083] Although Figure 2A the case where the pixel circuit PC includes two TFTs and one storage capacitor Cst is shown, exemplary embodiments of the inventive concept are not limited thereto.

[0084] Referring Figure 2B , each pixel P may include an organic light emitting diode OLED and a pixel circuit PC including a plurality of TFTs for driving the organic light emitting diode OLED. The pixel circuit PC may include a driving TFT T1, a switching TFT T2, a sensing TFT T3, and a storage capacitor Cst.

[0085] The scan line SL may be connected to the gate electrode G2 of the switching TFT T2. The data line DL may be connected to the source electrode S2 of the switching TFT T2. A first electrode CE1 of the storage capacitor Cst may be connected to the drain electrode D2 of the switching TFT T2.

[0086] Accordingly, the switching TFT T2 supplies the data voltage of the data line DL to the first node N in response to the scan signal Sn of the scan line SL from each pixel P.

[0087] The gate electrode G1 of the driving TFT T1 may be connected to the first node N, the source electrode S1 of the driving TFT T1 may be connected to a first power line PL1 for transmitting the driving power supply voltage ELVDD, and the drain electrode D1 of the driving TFT T1 may be connected to the anode of the organic light emitting diode OLED.

[0088] Therefore, the driving TFT T1 can adjust the amount of current flowing through the organic light-emitting diode OLED according to the gate-source voltage of the driving TFT T1 (i.e., the voltage applied between the driving power supply voltage ELVDD and the first node N).

[0089] The gate electrode G3 of the sensing TFT T3 can be connected to the sensing control line SSL. The source electrode S3 of the sensing TFT T3 can be connected to the second node S. The drain electrode D3 of the sensing TFT T3 can be connected to the reference voltage line RL. In an exemplary embodiment, the sensing TFT T3 can be controlled by the scan line SL instead of the sensing control line SSL.

[0090] The sensing TFT T3 can sense the potential of the anode of the organic light-emitting diode OLED. During the sensing period, the sensing TFT T3 can supply the pre-charge voltage from the reference voltage line RL to the second node S in response to the sensing signal SSn from the sensing control line SSL, or supply the voltage of the anode of the organic light-emitting diode OLED to the reference voltage line RL.

[0091] The first electrode CE1 of the storage capacitor Cst can be connected to the first node N. The second electrode CE2 of the storage capacitor Cst can be connected to the second node S. The storage capacitor Cst can be charged with the voltage difference between the voltages respectively supplied to the first node N and the second node S, and can supply the driving power supply voltage ELVDD to the driving TFT T1. For example, the storage capacitor Cst can be charged with the voltage difference between the data voltage and the pre-charge voltage respectively supplied to the first node N and the second node S.

[0092] The bias electrode BSM can be formed to face the driving TFT T1 and can be connected to the source electrode S3 of the sensing TFT T3. Since the bias electrode BSM receives a voltage by cooperating with the potential of the source electrode S3 of the sensing TFT T3, the driving TFT T1 can be stabilized. In an exemplary embodiment, the bias electrode BSM may not be connected to the source electrode S3 of the sensing TFT T3 and may be connected to a separate bias wiring.

[0093] The counter electrode (e.g., cathode) of the organic light-emitting diode OLED can receive the common voltage ELVSS through the second power line PL2. The organic light-emitting diode OLED can emit light by receiving a driving current from the driving TFT T1.

[0094] Although Figure 2BAn embodiment is shown in which each pixel P includes signal lines SL, SSL, and DL, a reference voltage line RL, a first power line PL1, and a second power line PL2, but the present disclosure is not limited thereto. For example, at least one of the signal lines SL, SSL, and DL, the reference voltage line RL, the first power line PL1, and the second power line PL2 may be shared with adjacent pixels.

[0095] Exemplary embodiments of the pixel circuit PC according to the inventive concept are not limited to the number of thin film transistors and storage capacitors and the circuit design described with reference to Figure 2A and Figure 2B and the number of thin film transistors and storage capacitors and the circuit design may be variously changed.

[0096] Figure 3A are cross-sectional views of a display device taken along lines I-I' and II-II' respectively according to an exemplary embodiment. Figure 1 is a cross-sectional view of a display device including a mask support on a support taken along lines I-I' and II-II' of Figure 3B is along Figure 1 which can explain the role of the support for the display device.

[0097] Referring to Figure 3A , the display device according to the present exemplary embodiment may include a display area DA and a peripheral area PA located outside the display area DA. At least one TFT (e.g., driving TFT T1) and a display element connected to the at least one TFT may be arranged in the display area DA. A second power supply line 20 as a common voltage supply line, an embedded driving circuit portion 40, a wiring portion 50, a shielding layer 140, a dam portion 120, and a support 130 may be arranged in the peripheral area PA.

[0098] The display device according to the present exemplary embodiment further includes a thin film encapsulation layer 400 that seals a part of the display area DA and the peripheral area PA. The first inorganic encapsulation layer 410 and / or the second inorganic encapsulation layer 430 of the thin film encapsulation layer 400 may be in contact with the inorganic protective layer PVX.

[0099] In the present exemplary embodiment, the second power supply line 20 may be arranged closer to the display area DA than the embedded driving circuit portion 40. The shielding layer 140 may be at least partially overlapped with the embedded driving circuit portion 40. The dam portion 120 may be overlapped with the embedded driving circuit portion 40 and / or the wiring portion 50.

[0100] Hereinafter, the display device according to the exemplary embodiment will be described in more detail.

[0101] In Figure 3A the display area DA of Figure 2A andFigure 2B The driving TFT T1 and the storage capacitor Cst in the pixel circuit PC of each described pixel P. For ease of description, it will be based on the stacking order of the components arranged in Figure 3A the display area DA to describe the components arranged in Figure 3A the display area DA.

[0102] The substrate 100 may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. In embodiments where the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin, such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). The substrate 100 may have a single-layer or multi-layer structure including the above materials. In embodiments where the substrate 100 has a multi-layer structure, the substrate 100 may further include an inorganic layer. In an exemplary embodiment, the substrate 100 may have a structure of organic material / inorganic material / organic material.

[0103] The first buffer layer 111 may increase the flatness of the top surface of the substrate 100. The first buffer layer 111 may include SiO 2 , SiN x , SiO x N y , Al 2 O 3 , TiO 2 , Ta 2 O 5 , HfO 2 or ZnO 2 .

[0104] A barrier layer may be further arranged between the substrate 100 and the first buffer layer 111. The barrier layer may prevent impurities from penetrating from the substrate 100 etc. into the semiconductor layer A1, or minimize the penetration of impurities from the substrate 100 etc. into the semiconductor layer A1. The barrier layer may include an inorganic material such as an oxide or a nitride, an organic material, or an organic / inorganic composite material. The barrier layer may have a single-layer or multi-layer structure.

[0105] The bias electrode BSM may be arranged on the first buffer layer 111 to correspond to the driving TFT T1 and the storage capacitor Cst. A voltage may be applied to the bias electrode BSM. For example, the bias electrode BSM may be connected to the source electrode S3 of the sensing TFT T3 (see Figure 2B ) (see Figure 2B), and can receive the voltage of the source electrode S3. In addition, the bias electrode BSM can prevent external light from reaching the semiconductor layer A1. Therefore, the characteristics of the driving TFT T1 can be stabilized.

[0106] The second buffer layer 112 can cover the bias electrode BSM and can be formed over the entire surface of the substrate 100. In an exemplary embodiment, the second buffer layer 112 can include SiO 2 、SiN x 、SiO x N y 、Al 2 O 3 、TiO 2 、Ta 2 O 5 、HfO 2 、 or ZnO 2 。

[0107] The semiconductor layer A1 can be disposed on the second buffer layer 112. The semiconductor layer A1 can include amorphous silicon or polycrystalline silicon. In another exemplary embodiment, the semiconductor layer A1 can include an oxide of at least one of In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, Al, Cs, Ce, and Zn. In an exemplary embodiment, the semiconductor layer A1 can include a Zn oxide-based material, such as Zn oxide, In-Zn oxide, and Ga-In-Zn oxide. In another exemplary embodiment, the semiconductor layer A1 can include a semiconductor that includes IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O) in which ZnO contains a metal such as In, Ga, or Sn. The semiconductor layer A1 can include a channel region and source and drain regions disposed on two opposite sides of the channel region. The semiconductor layer A1 can include a single layer or multiple layers.

[0108] The gate electrode G1 can be disposed over the semiconductor layer A1, and the gate insulating layer 113 is provided between the gate electrode G1 and the semiconductor layer A1 to at least partially overlap the semiconductor layer A1. The gate electrode G1 can include one of Mo, Al, Cu, and Ti and can include a single layer or multiple layers. For example, the gate electrode G1 can include a single layer containing Mo. The first electrode CE1 of the storage capacitor Cst can be disposed in the same layer as the gate electrode G1. The first electrode CE1 can include the same material as the material of the gate electrode G1.

[0109] The interlayer insulating layer 115 can be provided to cover the gate electrode G1 and the first electrode CE1 of the storage capacitor Cst. The interlayer insulating layer 115 can include SiO 2 、SiN x 、SiOx N y 、 Al 2 O 3 、 TiO 2 、 Ta 2 O 5 、 HfO 2 or ZnO 2 。

[0110] The second electrode CE2 of the storage capacitor Cst, the source electrode S1, the drain electrode D1, and the data line DL may be disposed on the interlayer insulating layer 115.

[0111] The second electrode CE2 of the storage capacitor Cst, the source electrode S1, the drain electrode D1, and the data line DL may include a conductive material including one of Mo, Al, Cu, and Ti, and may include a single layer or multiple layers including the above materials. For example, the second electrode CE2, the source electrode S1, the drain electrode D1, and the data line DL may have a multilayer structure of Ti / Al / Ti. The source electrode S1 and the drain electrode D1 may be connected to the source region and the drain region of the semiconductor layer A1 through contact holes, respectively.

[0112] The second electrode CE2 of the storage capacitor Cst is stacked on the first electrode CE1, and the interlayer insulating layer 115 is located between the second electrode CE2 and the first electrode CE1 of the storage capacitor Cst, and the second electrode CE2 of the storage capacitor Cst may include capacitance. In this embodiment, the interlayer insulating layer 115 may be used as the dielectric layer of the storage capacitor Cst.

[0113] The second electrode CE2 of the storage capacitor Cst, the source electrode S1, the drain electrode D1, and the data line DL may be covered by the inorganic protective layer PVX.

[0114] The inorganic protective layer PVX may include a single layer or multiple layers including SiN x and SiO x . The inorganic protective layer PVX may be introduced to cover and protect some wirings disposed on the interlayer insulating layer 115. The wirings formed together with the data line DL in the same process as the data line DL may be exposed in a part of the substrate 100 (for example, a part of the peripheral region). The exposed part of the wiring may be damaged by the etchant used in patterning the pixel electrode 310 to be described later. However, as in this embodiment, since the inorganic protective layer PVX covers at least a part of the data line DL and the wirings formed together with the data line DL, the inorganic protective layer PVX can prevent the wirings from being damaged in the process of patterning the pixel electrode 310.

[0115] The planarization layer 118 may be disposed on the inorganic protective layer PVX, and the organic light-emitting diode 300 may be disposed on the planarization layer 118.

[0116] The planarization layer 118 may include a single layer or multiple layers containing an organic material and may provide a flat top surface. The planarization layer 118 may include common polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS), or polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorene polymers, parylene polymers, vinyl alcohol polymers, or mixtures thereof.

[0117] The organic light-emitting diode 300 may be disposed on the planarization layer 118 in the display area DA of the substrate 100. The organic light-emitting diode 300 may include a pixel electrode 310, an intermediate layer 320 including an organic emission layer, and a counter electrode 330.

[0118] The pixel electrode 310 may include a (semi)transparent electrode or a reflective electrode. In an exemplary embodiment, the pixel electrode 310 may include a reflective layer containing one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and mixtures thereof and a transparent or semi-transparent electrode layer disposed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In an exemplary embodiment, the pixel electrode 310 may include ITO / Ag / ITO.

[0119] The pixel defining layer 119 may be disposed on the planarization layer 118. The pixel defining layer 119 may define the emission region of the pixel by including openings corresponding to each sub-pixel in the display area DA. The first opening OP1 may expose at least a central portion of the pixel electrode 310. The pixel defining layer 119 may prevent arcs and the like from occurring at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 disposed above the pixel electrode 310.

[0120] The pixel defining layer 119 may be formed by a method such as spin coating that uses at least one organic insulating material among polyimide, polyamide, acrylic resin, BCB, and phenolic resin.

[0121] The intermediate layer 320 of the organic light-emitting diode 300 may include an organic emission layer. The organic emission layer may include an organic material containing a fluorescent material or a phosphorescent material that emits red, green, blue, or white light. The organic emission layer may include a low molecular weight organic material or a polymeric organic material. Functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be selectively further disposed under or on the organic emission layer. The intermediate layer 320 may correspond to each of the plurality of pixel electrodes 310. However, the exemplary embodiments of the intermediate layer 320 are not limited thereto. The intermediate layer 320 may include a single integral layer located above the plurality of pixel electrodes 310. However, various modifications may be made.

[0122] The counter electrode 330 may include a transmissive electrode or a reflective electrode. In an exemplary embodiment, the counter electrode 330 may include a transparent electrode or a semi-transparent electrode, and may include a metal thin film having a small work function and including one of Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and mixtures thereof. A transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, or In 2 O 3 may be further disposed on the metal thin film. The counter electrode 330 may be disposed over the display area DA and the peripheral area PA, and disposed over the intermediate layer 320 and the pixel defining layer 119. The counter electrode 330 may be provided as a single integral layer located over the plurality of organic light-emitting diodes 300, and may be stacked with the plurality of pixel electrodes 310.

[0123] Spacers 119S for preventing mask chopping may be further provided on the pixel defining layer 119. The spacers 119S may be integrated with the pixel defining layer 119. For example, the spacers 119S and the pixel defining layer 119 may be simultaneously formed in the same process using a halftone mask process.

[0124] Since the organic light-emitting diode 300 is easily damaged by external moisture or oxygen, a thin film encapsulation layer 400 may be disposed on the organic light-emitting diode 300, and may cover and protect the organic light-emitting diode 300. The thin film encapsulation layer 400 may cover the display area DA and extend to the peripheral area PA. The thin film encapsulation layer 400 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, the thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

[0125] The first inorganic encapsulation layer 410 may cover the counter electrode 330 and may include silicon oxide, silicon nitride, and / or silicon oxynitride. In some exemplary embodiments, an additional layer such as a capping layer may be disposed between the first inorganic encapsulation layer 410 and the counter electrode 330. Since the first inorganic encapsulation layer 410 is formed on the structure disposed thereunder, the top surface of the first inorganic encapsulation layer 410 is not flat. The organic encapsulation layer 420 may cover the first inorganic encapsulation layer 410, and unlike the first inorganic encapsulation layer 410, the organic encapsulation layer 420 may have a substantially flat top surface. Specifically, the organic encapsulation layer 420 may have a substantially flat top surface in the region corresponding to the display area DA. The organic encapsulation layer 420 may include one or more selected from polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. The second inorganic encapsulation layer 430 may cover the organic encapsulation layer 420 and may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0126] If cracks occur in the thin film encapsulation layer 400 including the above multi-layer structure, the thin film encapsulation layer 400 may prevent the cracks from connecting between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420 or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. Therefore, the formation of a path through which external moisture or oxygen penetrates into the display area DA can be prevented or minimized by the multi-layer encapsulation layer.

[0127] The second power line 20, the embedded driving circuit portion 40, the wiring portion 50, the dam portion 120, the support 130, and the shielding layer 140 may be disposed in the peripheral area PA outside the display area DA.

[0128] The second power line 20 may be positioned adjacent to the display area DA. For example, the second power line 20 may be positioned between the embedded driving circuit portion 40 and the display area DA. The second power line 20 may be in the same layer as the source electrode S1 and / or the drain electrode D1 of the driving TFT T1. In this embodiment, during the manufacturing process of the display device, the second power line 20 may be formed of the same material as the source electrode S1 and / or the drain electrode D1 and formed simultaneously with the source electrode S1 and / or the drain electrode D1.

[0129] The signal transmitted from the embedded driving circuit portion 40 to the display area DA may be transmitted through the first wiring W1 disposed in the same layer as the gate electrode G1 and / or the second wiring W2 disposed in the same layer as the bias electrode BSM.

[0130] The planarization layer 118 may have a via hole VH that overlaps with the second power line 20, and the inorganic protection layer PVX may also have a hole PVXh that overlaps with the second power line 20. Accordingly, the second power line 20 may be in contact with the shielding layer 140 via the via hole VH and the hole PVXh.

[0131] One side of the shielding layer 140 may be in contact with the counter electrode 330, and thus the common voltage ELVSS supplied to the second power line 20 may be transmitted to the counter electrode 330. In an exemplary embodiment, the counter electrode 330 may extend into the interior of the via hole VH, and thus the second power line 20 may be in direct contact with the counter electrode 330 without passing through the shielding layer 140.

[0132] The embedded driving circuit portion 40 may provide a scan signal or the like to the pixels P included in the display area DA, and may include a plurality of TFTs T'. The TFTs T' in the embedded driving circuit portion 40 may have the same structure as that of the driving TFT T1 in the display area DA and may be formed by the same process as that of the driving TFT T1.

[0133] The planarization layer 118 may extend to the peripheral area PA and cover at least a part of the embedded driving circuit portion 40. The shielding layer 140 may be disposed above the planarization layer 118. The shielding layer 140 may overlap with at least a part of the embedded driving circuit portion 40. The shielding layer 140 may be used to protect the embedded driving circuit portion 40 from static electricity. The shielding layer 140 may extend to one end of the planarization layer 118 and terminate in a region adjacent to the dam portion 120.

[0134] A plurality of through holes 140h may be located in the shielding layer 140 disposed on the planarization layer 118. Due to the presence of the plurality of through holes 140h, the gas generated from outgassing in the planarization layer 118 may easily escape from the planarization layer 118 through the through holes 140h, and the planarization layer 118 is disposed below the shielding layer 140.

[0135] The shielding layer 140 may be formed of the same material as that of the pixel electrode 310 and may be formed simultaneously with the pixel electrode 310. For example, the shielding layer 140 may include Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a mixture thereof. Additionally, the shielding layer 140 may include at least one of ITO, IZO, ZnO, In 2 O 3 , IGO, and AZO. In an exemplary embodiment, the shielding layer 140 may include ITO / Ag / ITO. As described above, one side of the shielding layer 140 may be in contact with the counter electrode 330, and a part of the shielding layer 140 may be in contact with the second power line 20.

[0136] In the drawings, the shielding layer 140 is shown as not overlapping with the dam portion 120. However, the present disclosure is not limited thereto. The shielding layer 140 may extend to the sides and upper portions of the first layers 121a and 123a of the dam portion 120, and various modifications may be made.

[0137] A portion of the pixel defining layer 119 may extend to the peripheral region PA, and may include a second opening OP2 corresponding to the via hole VH in the planarization layer 118 and a plurality of third openings OP3 corresponding to the regions between the through holes 140h of the shielding layer 140. The pixel defining layer 119 may cover and protect the through holes 140h, and the third openings OP3 may be disposed between the through holes 140h.

[0138] The wiring portion 50 may be disposed in the peripheral region PA farther from the display area DA than the embedded driving circuit portion 40. The wiring portion 50 may include a third wiring W3, a fourth wiring W4, and a fifth wiring W5. The third wiring W3 and the fourth wiring W4 may be connected to the terminal portion 30 (see Figure 1 ) to transmit the control signal supplied from the control portion. The fifth wiring W5 may be connected to the third wiring W3 or the fourth wiring W4 to transmit the control signal to the embedded driving circuit portion 40.

[0139] The third wiring W3 may be disposed in the same layer as the gate electrode G1, and may be formed of the same material as the gate electrode G1 and formed simultaneously with the gate electrode G1. The fourth wiring W4 may be disposed in the same layer as the bias electrode BSM, and may be formed of the same material as the bias electrode BSM and formed simultaneously with the bias electrode BSM. The fifth wiring W5 may be disposed in the same layer as the source electrode S1 or the drain electrode D1, and may be formed of the same material as the source electrode S1 or the drain electrode D1 and formed simultaneously with the source electrode S1 or the drain electrode D1.

[0140] The dam portion 120 may be disposed in the peripheral region PA farther from the display area DA than the planarization layer 118 and the pixel defining layer 119 extending from the display area DA. The dam portion 120 may include a first dam 121 and a second dam 123. The dam portion 120 may be separated from the planarization layer 118 and the pixel defining layer 119, and may prevent the organic material from flowing to the edge of the substrate 100 when forming the organic encapsulation layer 420 of the thin film encapsulation layer 400. In embodiments where the dam portion 120 includes a plurality of dams, the plurality of dams may be separated from each other. For example, the first dam 121 and the second dam 123 may be separated from each other.

[0141] Each of the first dam 121 and the second dam 123 may have a single-layer or multi-layer structure. As shown in the accompanying drawings, the first dam 121 may have a structure in which a first layer 121a, a second layer 121b, and a third layer 121c are stacked. The second dam 123 may have a structure in which a first layer 123a and a second layer 123b are stacked. Therefore, the height of the first dam 121 may be higher than the height of the second dam 123.

[0142] In this embodiment, the first layer 121a of the first dam 121 and the first layer 123a of the second dam 123 may be formed simultaneously with the planarization layer 118 and formed of the same material as the material of the planarization layer 118. The second layer 121b of the first dam 121 and the second layer 123b of the second dam 123 may be formed simultaneously with the pixel defining layer 119 and formed of the same material as the material of the pixel defining layer 119. The third layer 121c may be formed simultaneously with the spacer 119S and formed of the same material as the material of the spacer 119S.

[0143] The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 of the thin film encapsulation layer 400 may be in direct contact with the outside of the first dam 121. Therefore, the organic encapsulation layer 420 may not be exposed to the outside, and external air or moisture may be prevented from penetrating through the organic material by the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430.

[0144] The inorganic protection layer PVX may be in direct contact with the first inorganic encapsulation layer 410 in the region between the first dam 121 and the second dam 123 and in the region outside the first dam 121. Since both the first inorganic encapsulation layer 410 and the inorganic protection layer PVX include inorganic materials, the adhesion may be enhanced. In addition, since no organic material is located between the first dam 121 and the support 130, the penetration of moisture from external air may be effectively blocked.

[0145] The dam portion 120 may at least partially overlap with the embedded driving circuit portion 40 and / or the wiring portion 50. For example, both the first dam 121 and the second dam 123 may overlap with the TFT T' of the embedded driving circuit portion 40. Alternatively, the first dam 121 may overlap with the wiring portion 50 and the second dam 123 may overlap with the embedded driving circuit portion 40. In addition, the dam portion 120 may not overlap with the embedded driving circuit portion 40, but may only overlap with the wiring portion 50, but various modifications can be made thereto.

[0146] Since the dam portion 120 at least partially overlaps with the embedded driving circuit portion 40 and / or the wiring portion 50, there is no need to ensure a separate space for forming the dam portion 120. Therefore, the size of the peripheral area PA can be reduced.

[0147] The support member 130 may be disposed outside the dam portion 120. The support member 130 may be a member for supporting a mask M used in a mask process as shown in Figure 3B . The mask support member 130M may be disposed on one side of the mask M by engaging with the support member 130 of the display device to support the mask M. The support member 130 may include an organic material and may be capable of buffering when supporting the mask M. In addition to the function of supporting the mask M, the support member 130 may be used to suppress crack transmission into the display area DA.

[0148] The support member 130 may protrude from the top surface of the substrate 100, and the support member 130 may be formed simultaneously with the planarization layer 118 and using the same material as that of the planarization layer 118. The height of the support member 130 may be less than the height of the dam portion 120 (e.g., the first dam 121 and the second dam 123). The support member 130 may be stacked with at least a part of the wiring portion 50. Accordingly, the size of the peripheral area PA may be reduced.

[0149] Figure 4 is a cross-sectional view of a display device according to another exemplary embodiment. In Figure 4 , reference numerals identical to those in Figure 3A represent members identical to those in Figure 3A . Accordingly, repeated descriptions will be omitted.

[0150] Referring to Figure 4 , the display device according to the present exemplary embodiment includes a display area DA and a peripheral area PA located outside the display area DA. At least one TFT (such as a driving TFT T1) and display elements connected to the at least one TFT may be disposed in the display area DA. A second power supply line 20 as a common voltage supply line, an embedded driving circuit portion 40, a wiring portion 50, a shielding layer 140, a dam portion 120, and a support member 130 may be disposed in the peripheral area PA.

[0151] The display device according to the present exemplary embodiment further includes a thin film encapsulation layer 400 that seals a part of the display area DA and the peripheral area PA, and the first inorganic encapsulation layer 410 and / or the second inorganic encapsulation layer 430 of the thin film encapsulation layer 400 may be in contact with the inorganic protection layer PVX.

[0152] In addition, in the display device according to the present exemplary embodiment, the second power supply line 20 may be disposed closer to the display area DA than the embedded driving circuit portion 40. The shielding layer 140 may be at least partially stacked with the embedded driving circuit portion 40. The dam portion 120 may be stacked with the embedded driving circuit portion 40 and / or the wiring portion 50.

[0153] The dam portion 120 may include a first dam 121 and a second dam 123 which are separated from each other. Each of the first dam 121 and the second dam 123 may include a plurality of layers. For example, the first dam 121 may include: a first layer 121a formed simultaneously with the planarization layer 118 and formed of the same material as that of the planarization layer 118; a second layer 121b formed simultaneously with the pixel defining layer 119 and formed of the same material as that of the pixel defining layer 119; and a third layer 121c formed simultaneously with the spacer 119S and formed of the same material as that of the spacer 119S. The second dam 123 may include: a first layer 123a formed simultaneously with the planarization layer 118 and formed of the same material as that of the planarization layer 118; and a second layer 123b formed simultaneously with the pixel defining layer 119 and formed of the same material as that of the pixel defining layer 119.

[0154] In Figure 4 In the exemplary embodiment shown in, the first layers 121a and 123a of the dam portion 120 are formed using a halftone mask process and may have steps or bends formed on their side surfaces. For example, steps or bends may be formed on the side surfaces of the first layers 121a and 123a of the dam portion 120.

[0155] Since steps or bends are formed on the first layers 121a and 123a of the dam portion 120, cracks and the like that may occur in the members disposed on the dam portion 120 can be prevented.

[0156] In Figure 4 In, the shielding layer 140 is shown as not overlapping the dam portion 120. However, the exemplary embodiments of the inventive concept are not limited thereto. The shielding layer 140 may extend to the sides and upper portions of the first layers 121a and 123a of the dam portion 120.

[0157] In an embodiment where the shielding layer 140 is disposed above the first layers 121a and 123a of the dam portion 120, the distance between the shielding layer 140 and the TFT T' of the embedded driving circuit portion 40 increases, and thus parasitic capacitance can be reduced.

[0158] Figure 5 is a cross-sectional view of a display device according to another exemplary embodiment. In Figure 5 In, the same reference numerals as those in Figure 3A represent the same members as those in Figure 3A Therefore, repeated descriptions will be omitted.

[0159] Referring to Figure 5, a display device according to an exemplary embodiment may include a display area DA and a peripheral area PA located outside the display area DA. At least one TFT (such as a driving TFT T1) and a display element connected to the at least one TFT may be arranged in the display area DA. A second power supply line 20 serving as a common voltage supply line, an embedded driving circuit portion 40, a wiring portion 50, a shielding layer 140, a dam portion 120, and a support 130 may be arranged in the peripheral area PA.

[0160] The display device according to an exemplary embodiment further includes a thin film encapsulation layer 400 that seals a part of the display area DA and the peripheral area PA, and the first inorganic encapsulation layer 410 and / or the second inorganic encapsulation layer 430 of the thin film encapsulation layer 400 may be in contact with the inorganic protection layer PVX.

[0161] In addition, in the display device according to an exemplary embodiment, the second power supply line 20 may be arranged closer to the display area DA than the embedded driving circuit portion 40. The shielding layer 140 may be at least partially overlapped with the embedded driving circuit portion 40. The dam portion 120 may be overlapped with the embedded driving circuit portion 40 and / or the wiring portion 50.

[0162] The dam portion 120 may include a first dam 121 and a second dam 123 separated from each other. In Figure 5 the exemplary embodiment shown, the height of the first dam 121 may be equal to the height of the second dam 123. In addition, Figure 3A the spacer 119S in

[0163] each of the first dam 121 and the second dam 123 may include multiple layers. For example, the first dam 121 may include: a first layer 121a, formed simultaneously with the planarization layer 118 and formed of the same material as the planarization layer 118; and a second layer 121b, formed simultaneously with the pixel defining layer 119 and formed of the same material as the pixel defining layer 119. The second dam 123 may include: a first layer 123a, formed simultaneously with the planarization layer 118 and formed of the same material as the planarization layer 118; and a second layer 123b, formed simultaneously with the pixel defining layer 119 and formed of the same material as the pixel defining layer 119.

[0164] In an exemplary embodiment, the first layers 121a and 123a of the dam portion 120 are formed using a halftone mask process, so steps or bends may be formed on their side surfaces. For example, steps or bends may be formed on the side surface of the first layer 121a of the dam portion 120.

[0165] Figure 6is a cross-sectional view of a display device according to another exemplary embodiment. In Figure 6 , reference numerals identical to those in Figure 3A denote components identical to those in Figure 3A . Accordingly, repeated descriptions will be omitted.

[0166] Referring to Figure 6 , the display device according to the present exemplary embodiment includes a display area DA and a peripheral area PA located outside the display area DA. At least one TFT (such as driving TFT T1) and a display element connected to the at least one TFT may be disposed in the display area DA. A second power supply line 20 as a common voltage supply line, an embedded driving circuit portion 40, a wiring portion 50, a shielding layer 140', a dam portion 120, and a support member 130 may be disposed in the peripheral area PA.

[0167] According to Figure 6 , the display device according to the exemplary embodiment shown further includes a thin film encapsulation layer 400 that seals a part of the display area DA and the peripheral area PA, and the first inorganic encapsulation layer 410 and / or the second inorganic encapsulation layer 430 of the thin film encapsulation layer 400 may be in contact with the inorganic protection layer PVX.

[0168] In addition, in the display device according to the exemplary embodiment shown in Figure 6 , the second power supply line 20 may be disposed closer to the display area DA than the embedded driving circuit portion 40. The shielding layer 140' may at least partially overlap with the embedded driving circuit portion 40. The dam portion 120 may overlap with the embedded driving circuit portion 40 and / or the wiring portion 50.

[0169] In Figure 6 , at least a part of the TFT T' of the embedded driving circuit portion 40 may be covered by a planarization layer 118, and the shielding layer 140' disposed on the planarization layer 118 and overlapping with the embedded driving circuit portion 40 may include multiple layers.

[0170] For example, the shielding layer 140' may include a first shielding layer 141 containing the same material as that of the pixel electrode 310 and a second shielding layer 143 extending from the counter electrode 330. Since the shielding layer 140' includes multiple layers, the embedded driving circuit portion 40 can be protected more stably.

[0171] The first shielding layer 141 may include a plurality of through holes 140h. During the manufacturing process of the display device, outgassing that may occur in the planarization layer 118 can be easily discharged through the plurality of through holes 140h.

[0172] The second shielding layer 143 may extend from the counter electrode 330 and be disposed on the first shielding layer 141. In some exemplary embodiments, a plurality of through holes may also be formed in the second shielding layer 143. In some exemplary embodiments, an insulating layer formed in the same layer as the pixel defining layer 119 may be disposed between the first shielding layer 141 and the second shielding layer 143. However, various modifications can be made thereto.

[0173] In Figure 6 the shielding layer 140' is shown as terminating at a portion that overlaps with the embedded driving circuit portion 40. However, the exemplary embodiments are not limited thereto. For example, the shielding layer 140' may extend to the outside of the dam portion 120. In the exemplary embodiments, only one of the first shielding layer 141 and the second shielding layer 143 of the shielding layer 140' may extend to the outside of the first dam 121 or the second dam 123.

[0174] Figure 7 is a cross-sectional view of a display device according to another exemplary embodiment. In Figure 7 the same reference numerals as those in Figure 3A denote the same components as the components in Figure 3A Therefore, repeated descriptions will be omitted.

[0175] Referring to Figure 7 according to the exemplary embodiment of the present disclosure, a display device includes a display area DA and a peripheral area PA provided outside the display area DA. At least one TFT (such as a driving TFT T1) and a display element connected to the at least one TFT may be disposed in the display area DA. A second power supply line 20 as a common voltage supply line, an embedded driving circuit portion 40, a wiring portion 50, a shielding layer 140'', a dam portion 120, and a support 130 may be disposed in the peripheral area PA.

[0176] According to Figure 7 the exemplary embodiment shown in the display device further includes a thin film encapsulation layer 400 that seals a part of the display area DA and the peripheral area PA, and the first inorganic encapsulation layer 410 and / or the second inorganic encapsulation layer 430 of the thin film encapsulation layer 400 may be in contact with the inorganic protection layer PVX.

[0177] In addition, in the display device according to Figure 7 the exemplary embodiment shown, the second power supply line 20 may be disposed closer to the display area DA than the embedded driving circuit portion 40. The shielding layer 140'' may at least partially overlap with the embedded driving circuit portion 40. The dam portion 120 may overlap with the embedded driving circuit portion 40 and / or the wiring portion 50.

[0178] In Figure 7In the exemplary embodiment shown, at least a portion of the TFT T' of the embedded driving circuit portion 40 may be covered by the planarization layer 118, and the shielding layer 140'' may be disposed on the planarization layer 118 and at least partially overlap with the embedded driving circuit portion 40.

[0179] In Figure 7 the exemplary embodiment shown, the shielding layer 140'' may be integrated with the counter electrode 330. The shielding layer 140'' may extend from the counter electrode 330 in the display area DA and may at least partially overlap with the embedded driving circuit portion 40 in the peripheral area PA.

[0180] Although Figure 7 the embodiment shown does not include a shielding layer having a plurality of through holes, in the exemplary embodiment, the shielding layer 140'' may include a plurality of through holes. Thus, outgassing that may occur in the planarization layer 118 can be easily excluded.

[0181] In Figure 7 the shielding layer 140'' is shown corresponding to a portion of the embedded driving circuit portion 40. However, the exemplary embodiment of the inventive concept is not limited thereto. For example, the shielding layer 140'' may extend to the outside of the dam portion 120.

[0182] Figure 8A is a cross-sectional view of a display device according to another exemplary embodiment of the inventive concept. In Figure 8A the same reference numerals as in Figure 3A denote the same components as in Figure 3A Thus, repeated descriptions will be omitted.

[0183] Referring to Figure 8A , a display device according to an exemplary embodiment includes a display area DA and a peripheral area PA located outside the display area DA. At least one TFT (such as the driving TFT T1) and a display element connected to the at least one TFT may be disposed in the display area DA. The second power supply line 20 as a common voltage supply line, the embedded driving circuit portion 40, the wiring portion 50, the shielding layer 140, the dam portion 120, and the support 130 may be disposed in the peripheral area PA.

[0184] According to Figure 8A the exemplary embodiment shown, the display device further includes a thin film encapsulation layer 400 that seals a portion of the display area DA and the peripheral area PA, and the first inorganic encapsulation layer 410 and / or the second inorganic encapsulation layer 430 of the thin film encapsulation layer 400 may be in contact with the inorganic protection layer PVX.

[0185] In addition, in the display device according to the exemplary embodiment, the second power line 20 may be arranged closer to the display area DA than the embedded driving circuit portion 40. The shielding layer 140 may be at least partially overlapped with the embedded driving circuit portion 40. The dam portion 120 may be overlapped with the embedded driving circuit portion 40 and / or the wiring portion 50.

[0186] In Figure 8A the exemplary embodiment shown, a conductive protection layer 116 for protecting the second power line 20 may be further arranged on the second power line 20 exposed by the inorganic protection layer PVX. The inorganic protection layer PVX may include a hole PVXh corresponding to the second power line 20, and the conductive protection layer 116 may be arranged corresponding to the hole PVXh.

[0187] Since the second power line 20 must be electrically connected to the counter electrode 330 in subsequent processes, the second power line 20 may be exposed by partially removing the inorganic protection layer PVX. In this embodiment, the second power line 20 may be damaged by the etchant used in subsequent processes.

[0188] The conductive protection layer 116 may be a layer formed to protect the second power line 20 from such damage. In addition, the conductive protection layer 116 may have conductivity and may electrically connect the second power line 20 to the counter electrode 330.

[0189] In the present exemplary embodiment, since the conductive protection layer 116, the shielding layer 140, and the counter electrode 330 are in contact with each other, the common voltage ELVSS provided by the second power line 20 may be transmitted to the counter electrode 330.

[0190] The conductive protection layer 116 may include at least one of ITO, IZO, ZnO, In 2 O 3 , IGO, and AZO.

[0191] Figure 8B is a cross-sectional view of a display device according to another exemplary embodiment. In Figure 8B it, the reference numerals identical to those in Figure 8A represent the same components as those in Figure 8A . Therefore, the repeated description will be omitted.

[0192] Referring to Figure 8B , according to Figure 8BThe display device of the exemplary embodiment shown includes a display area DA and a peripheral area PA located outside the display area DA. At least one TFT (such as the driving TFT T1) and a display element connected to the at least one TFT may be arranged in the display area DA. A second power supply line 20 serving as a common voltage supply line, an embedded driving circuit portion 40, a wiring portion 50, a shielding layer 140, a dam portion 120, and a support 130 may be arranged in the peripheral area PA.

[0193] According to Figure 8B The display device of the exemplary embodiment shown further includes a thin film encapsulation layer 400 that seals a part of the display area DA and the peripheral area PA, and the first inorganic encapsulation layer 410 and / or the second inorganic encapsulation layer 430 of the thin film encapsulation layer 400 may be in contact with the inorganic protection layer PVX.

[0194] In Figure 8B In the exemplary embodiment shown, the conductive protection layer 116 may extend to overlap with the embedded driving circuit portion 40 and / or the wiring portion 50, and the inorganic protection layer PVX is located between the conductive protection layer 116 and the embedded driving circuit portion 40 and / or the wiring portion 50. In this embodiment, the conductive protection layer 116 may serve as a shielding layer for protecting the embedded driving circuit portion 40 from static electricity.

[0195] Like the conductive protection layer 116, conductive layers that are insulated from the TFT T' in the embedded driving circuit portion 40 by an insulating layer and are stacked on each other may all serve as shielding layers.

[0196] In Figure 8B In this case, the conductive protection layer 116 is connected to the second power supply line 20 and may extend to the embedded driving circuit portion 40. However, the exemplary embodiment of the inventive concept is not limited thereto. The conductive protection layer 116 may be arranged in such a way that the portion arranged above the embedded driving circuit portion 40 and the portion arranged above the second power supply line 20 may be separated from each other.

[0197] In addition, the conductive protection layer 116 may extend to overlap with the wiring portion 50. Referring to Figure 1 , the conductive protection layer 116 may be arranged on any one of the upper side, lower side, left side, and right side of the display area DA. In Figure 8B In this case, the conductive protection layer 116 is shown not to overlap with the dam portion 120. However, the exemplary embodiment of the inventive concept is not limited thereto. The conductive protection layer 116 may extend to the side and upper part of the first dam 121 or the second dam 123, and may be modified in various ways.

[0198] Figure 9 is a cross-sectional view of a display device according to another exemplary embodiment. InFigure 9 In, reference numerals identical to those in Figure 3A represent components identical to those in Figure 3A . Accordingly, repeated descriptions will be omitted.

[0199] Referring to Figure 9 , a display device according to the exemplary embodiment includes a display area DA and a peripheral area PA located outside the display area DA. At least one TFT (such as a driving TFT T1) and a display element connected to the at least one TFT may be disposed in the display area DA. A second power supply line 20 that may serve as a common voltage supply line, an embedded driving circuit portion 40, a wiring portion 50, a shielding layer 140, a dam portion 120, and a support 130 may be disposed in the peripheral area PA.

[0200] In the display device according to the exemplary embodiment, the second power supply line 20 may be disposed closer to the display area DA than the embedded driving circuit portion 40. The shielding layer 140 may be at least partially overlapped with the embedded driving circuit portion 40. The dam portion 120 may be overlapped with the embedded driving circuit portion 40 and / or the wiring portion 50.

[0201] The display device according to the exemplary embodiment may not include an inorganic protective layer PVX (see Figure 3A ). As described above, the inorganic protective layer PVX is provided to protect wirings formed in the same layer as the source electrodes S1 and drain electrodes D1 of the TFT T1 and the TFT T'. Accordingly, when there is no risk of exposing the wirings formed in the same layer as the source electrodes S1 and drain electrodes D1, the inorganic protective layer PVX may not be disposed.

[0202] For example, when wirings disposed in the peripheral area PA serve as a first wiring W1 and a third wiring W3, wirings disposed in the same layer serve as a gate electrode G1 or serve as a second wiring W2 and a fourth wiring W4, and the wirings are disposed in the same layer as a bias electrode BSM, the inorganic protective layer PVX may not be formed.

[0203] Figure 10 is a cross-sectional view of a display device according to another exemplary embodiment. In Figure 10 , reference numerals identical to those in Figure 3A represent components identical to those in Figure 3A . Accordingly, repeated descriptions will be omitted.

[0204] Referring to Figure 10, the display device according to the exemplary embodiment includes a display area DA and a peripheral area PA located outside the display area DA. At least one TFT (such as the driving TFT T1) and a display element connected to the at least one TFT may be arranged in the display area DA. A second power supply line 20 as a common voltage supply line, an embedded driving circuit portion 40, a wiring portion 50, a shielding layer 140, a dam portion 120, and a support 130 may be arranged in the peripheral area PA.

[0205] In the display device according to Figure 10 the exemplary embodiment shown, the second power supply line 20 may be arranged closer to the display area DA than the embedded driving circuit portion 40. The shielding layer 140 may be at least partially overlapped with the embedded driving circuit portion 40. The dam portion 120 may be overlapped with the embedded driving circuit portion 40 and / or the wiring portion 50.

[0206] In the present exemplary embodiment, the display device may further include an upper substrate 200. In the exemplary embodiment, the upper substrate 200 may include at least one of a color filter glass, a polarizer, and a window. When the upper substrate 200 includes a color filter glass, the upper substrate 200 may be a quantum dot color filter.

[0207] The substrate 100 and the upper substrate 200 may be bonded together by a sealing member 500. The sealing member 500 may be outside the support 130 and around the outer periphery of the peripheral area PA. The sealing member 500 may include a sealant, a glass frit, etc.

[0208] A filler 600 may be further arranged between the substrate 100 and the upper substrate 200. The filler 600 may buffer external pressure, etc. The filler 600 may include an organic material such as polyimide.

[0209] Figure 11 is a plan view of a display device according to another exemplary embodiment, Figure 12 is a cross-sectional view taken along the Figure 11 lines II-II' and III-III'. In Figure 11 , the reference numerals identical to those in Figure 1 represent the same components as those in Figure 1 . In Figure 12 , the reference numerals identical to those in Figure 6 represent the same components as those in Figure 6 .

[0210] Referring to Figure 11, the second power line 20 may be disposed on the upper and lower sides of the display area DA, or may be disposed only on the upper or lower side. Since the second power line 20 may not be included on the left and right sides of the display area DA, the size of the peripheral area PA can be reduced.

[0211] In Figure 11 the exemplary embodiment shown, the second power line 20 may be disposed in the same layer as the source or drain electrodes of the TFTs T1 and T', and may not be disposed between the embedded driving circuit portion 40 and the display area DA.

[0212] The second power line 20 disposed on the lower side of the display area DA may be connected to the terminal portion 30 disposed on the lower side of the second power line 20 via the second connection line 21. The terminal portion 30 may be exposed without being covered by an insulating layer, and may be electrically connected to the printed circuit board PCB. The printed circuit board PCB connected to the terminal portion 30 may supply the common voltage ELVSS to the second power line 20 via the second connection line 21.

[0213] The second power line 20 positioned on the upper side of the display area DA may be connected to the additional terminal 30' positioned on the upper side of the second power line 20 via the additional connection line 21'. The additional terminal 30' may be exposed without being covered by an insulating layer, and may be connected to an additional printed circuit board or a driver integrated circuit (IC). The additional printed circuit board or driver IC connected to the additional terminal 30' may supply the common voltage ELVSS to the second power line 20. Although the second power line 20 is shown in Figure 11 to be disposed on the upper and lower sides of the display area DA, the exemplary embodiments of the inventive concept are not limited thereto. For example, the second power line 20 may be disposed only on the lower side of the display area DA.

[0214] The counter electrode 330 may correspond to the entire display area DA, and may at least partially overlap with the second power lines 20 disposed on the upper and lower sides of the display area DA, and be electrically connected to the second power lines 20 disposed on the upper and lower sides of the display area DA. For example, the counter electrode 330 may be directly connected to the second power line 20, or may be electrically connected to the second power line 20 through another conductive layer located between the counter electrode 330 and the second power line 20.

[0215] The counter electrodes 330 located on the left and right sides of the display area DA may be in contact with the first shielding layer 141 (see Figure 12 ), and the first shielding layer 141 is disposed in the same layer as the pixel electrode 310 (see Figure 12 ). Therefore, the counter electrode 330 may be in contact with other conductive layers on the upper, lower, left, and right sides of the display area DA on four sides.

[0216] In an exemplary embodiment, the first shielding layer 141 may be electrically connected to a second power line 20 located on the upper side and / or the lower side of the display area DA. Accordingly, the first shielding layer 141 may be used to transmit a common voltage ELVSS to the counter electrode 330.

[0217] Referring to Figure 12 According to Figure 12 the display device according to the exemplary embodiment shown in

[0218] includes a display area DA and a peripheral area PA located outside the display area DA. At least one TFT (such as a driving TFT T1) and a display element connected to the at least one TFT may be arranged in the display area DA. An embedded driving circuit portion 40, a wiring portion 50, a shielding layer 140', a dam portion 120, and a support 130 may be arranged in the peripheral area PA.

[0219] In addition, the display device according to Figure 12 the exemplary embodiment shown in

[0220] also includes a thin film encapsulation layer 400 that seals a part of the display area DA and the peripheral area PA, and the first inorganic encapsulation layer 410 and / or the second inorganic encapsulation layer 430 of the thin film encapsulation layer 400 may be in contact with the inorganic protection layer PVX.

[0221] For example, the shielding layer 140' may include a first shielding layer 141 containing the same material as the pixel electrode 310 and a second shielding layer 143 extending from the counter electrode 330. Since the shielding layer 140' includes multiple layers, the embedded driving circuit portion 40 can be protected more stably.

[0222] The first shielding layer 141 may include a plurality of through holes. During the manufacturing process of the display device, outgassing occurring in the planarization layer 118 can be easily discharged through the plurality of through holes.

[0223] The second shielding layer 143 may extend from the counter electrode 330 and be arranged on the first shielding layer 141. Although not shown in Figure 12Although shown in [FIGURE], a plurality of through holes may also be formed in the second shielding layer 143. Additionally, an insulating layer formed in the same layer as the pixel defining layer 119 may be disposed between the first shielding layer 141 and the second shielding layer 143, but various modifications thereto are possible.

[0224] In Figure 12 the exemplary embodiment shown in [FIGURE], the first shielding layer 141 and the second shielding layer 143 may be in contact with each other, and one end of the second shielding layer 143 may be disposed between the wiring portion 50 and the display area DA. For example, the second shielding layer 143 may be arranged to overlap with the embedded driving circuit portion 40 without overlapping with the wirings W3, W4, and W5 that transmit driving signals to the embedded driving circuit portion 40.

[0225] In Figure 12 [FIGURE], the shielding layer 140' is shown as terminating at a part of the embedded driving circuit portion 40, but the exemplary embodiment is not limited thereto. For example, the shielding layer 140' may extend to the outside of the dam portion 120. In the exemplary embodiment, only one of the first shielding layer 141 and the second shielding layer 143 of the shielding layer 140' may extend to the outside of the first dam 121 or the second dam 123.

[0226] In the present exemplary embodiment, the second power line 20 (see Figure 3A ) may not be disposed between the embedded driving circuit portion 40 and the display area DA in the peripheral area PA. As a result, the size of the peripheral area PA can be reduced. The first shielding layer 141 of the shielding layer 140' may be used to transmit the common voltage ELVSS in the area where the second power line 20 is not partially disposed.

[0227] In this embodiment, the point where the first shielding layer 141 contacts the counter electrode 330 may be formed between the wiring portion 50 and the display area DA. Alternatively, the point where the first shielding layer 141 contacts the counter electrode 330 may be formed between the dam portion 120 and the display area DA.

[0228] Exemplary embodiments applicable to the inventive concept have been described. Such exemplary embodiments may be implemented as separate embodiments or as combined embodiments. For example, in the exemplary embodiment described with reference to Figure 12 , neither the first shielding layer 141 nor the second shielding layer 143 may be disposed. In the exemplary embodiment described with reference to Figure 12 , the conductive protection layer 116 described with reference to Figure 8B or the upper substrate 200 described with reference to Figure 10 may be applied.

[0229] As described above, in the exemplary embodiments of the present disclosure, since the arrangement of components in the peripheral region is optimized, the size of the peripheral region can be reduced. Additionally, due to the introduction of the shielding layer, high quality can be achieved.

[0230] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments.

[0231] Although one or more embodiments have been described with reference to the drawings, those of ordinary skill in the art will understand that various changes may be made in form and detail without departing from the spirit and scope defined by the claims.

Claims

1. A display device, the display device comprises: a substrate including a display area configured to display an image and a peripheral area positioned outside the display area; a first thin film transistor disposed in the display area; a display element electrically connected to the first thin film transistor, the display element including a pixel electrode, an intermediate layer, and a counter electrode; an embedded driving circuit portion disposed in the peripheral area, the embedded driving circuit portion including a second thin film transistor; a wiring portion disposed in the peripheral area farther from the display area than the embedded driving circuit portion, the wiring portion configured to transmit a signal to the embedded driving circuit portion; and a common voltage supply line disposed in the peripheral area, the common voltage supply line positioned closer to the display area than the embedded driving circuit portion, wherein the common voltage supply line is electrically connected to the counter electrode.

2. The display device according to claim 1, the display device further comprises: a planarization layer covering at least a part of the embedded driving circuit portion; and a shielding layer disposed on the planarization layer, the shielding layer at least partially overlapping with the embedded driving circuit portion, wherein the planarization layer includes a via hole exposing the common voltage supply line.

3. The display device according to claim 2, wherein the shielding layer includes the same material as that of the pixel electrode and contacts the common voltage supply line through the via hole, wherein a part of the shielding layer contacts the counter electrode to electrically connect the common voltage supply line to the counter electrode.

4. The display device according to claim 2, wherein the shielding layer is integrated with the counter electrode and contacts the common voltage supply line through the via hole.

5. The display device according to claim 2, wherein the shielding layer includes: a first shielding layer including the same material as that of the pixel electrode; and a second shielding layer extending from the counter electrode.

6. The display device according to claim 2, wherein the shielding layer includes a plurality of through holes.

7. The display device according to claim 1, the display device further comprises: a dam portion disposed in the peripheral area farther from the display area than the common voltage supply line, the dam portion protruding from the substrate, wherein the dam portion at least partially overlaps with the embedded driving circuit portion.

8. The display device according to claim 7, wherein the dam portion includes a first dam and a second dam separated from each other, wherein the height of the first dam is equal to the height of the second dam.

9. The display device according to claim 7, wherein the dam portion includes a first layer and a second layer, and a side surface of the first layer is curved by a halftone mask process.

10. The display device according to claim 7, the display device further comprises: a support member disposed in the peripheral area farther from the display area than the dam portion, the support member protruding from an upper surface of the substrate, Wherein, the height of the support member from the upper surface of the substrate is less than the height of the dam portion from the upper surface of the substrate.

11. The display device according to claim 10, wherein, at least one of the dam portion and the support member is at least partially stacked with the wiring portion.

12. The display device according to claim 1, the display device further comprises: a planarization layer disposed between the first thin film transistor and the display element, the planarization layer comprising an organic material; and an inorganic protection layer disposed between the planarization layer and the first thin film transistor, the inorganic protection layer covering source and drain electrodes of the first thin film transistor and extending to the peripheral region, wherein, in the peripheral region, the inorganic protection layer includes a region not covered by the planarization layer and an organic material formed in the same layer as the planarization layer.

13. The display device according to claim 12, wherein, the inorganic protection layer includes a hole exposing the common voltage supply line, and a conductive protection layer for protecting the common voltage supply line is disposed to overlap with the hole.

14. The display device according to claim 12, the display device further comprises: a thin film encapsulation layer covering the display region, the thin film encapsulation layer including at least one inorganic encapsulation layer and at least one organic encapsulation layer, wherein, in the peripheral region, the at least one inorganic encapsulation layer contacts the inorganic protection layer.

15. The display device according to claim 1, the display device further comprises: a color filter glass facing the substrate; and a sealing member disposed near an outer periphery of the peripheral region, the sealing member being configured to bond the substrate and the color filter glass together.

16. A display device, the display device comprises: a substrate including a display region configured to display an image and a peripheral region located outside the display region; a first thin film transistor disposed in the display region; a display element electrically connected to the first thin film transistor; an embedded driving circuit portion disposed in the peripheral region, the embedded driving circuit portion including a second thin film transistor; a wiring portion disposed in the peripheral region farther from the display region than the embedded driving circuit portion; a planarization layer disposed between the first thin film transistor and the display element, the planarization layer comprising an organic material; an inorganic protection layer disposed between the planarization layer and the first thin film transistor, the inorganic protection layer covering source and drain electrodes of the first thin film transistor and extending to the peripheral region; a thin film encapsulation layer covering the display region, the thin film encapsulation layer including at least one inorganic encapsulation layer and at least one organic encapsulation layer; wherein, the inorganic encapsulation layer contacts the inorganic protection layer in the peripheral region.

17. The display device according to claim 16, the display device further comprises: a dam portion disposed in the peripheral region, the dam portion protruding from the substrate, Among them, the inorganic encapsulation layer contacts the inorganic protection layer in the peripheral region that is farther from the display region than the dam portion.

18. The display device according to claim 17, wherein, the planarization layer further covers at least a part of the embedded driving circuit portion; and the display device further includes: a shielding layer disposed on the planarization layer, the shielding layer being at least partially stacked with the embedded driving circuit portion, wherein the planarization layer includes a via hole that exposes the common voltage supply line.

19. The display device according to claim 17, wherein, the dam portion is at least partially stacked with the second thin film transistor of the embedded driving circuit portion.

20. The display device according to claim 17, the display device further includes: a protruding support member disposed in the peripheral region farther from the display region than the dam portion, the height of the protruding support member being lower than the height of the dam portion, wherein at least one of the dam portion and the protruding support member is stacked with the wiring portion.

21. The display device according to claim 20, the display device further includes: a sealing member disposed in the peripheral region farther from the display region than the protruding support member; and an upper substrate facing the substrate, wherein the substrate and the upper substrate are bonded together by the sealing member.

22. A display device, the display device includes: a substrate including a display region configured to display an image and a peripheral region located outside the display region; a first thin film transistor disposed in the display region; a display element electrically connected to the first thin film transistor, the display element including a pixel electrode, an intermediate layer, and a counter electrode; an embedded driving circuit portion disposed in the peripheral region, the embedded driving circuit portion including a second thin film transistor; a wiring portion disposed in the peripheral region farther from the display region than the embedded driving circuit portion, the wiring portion having a wiring connected to the embedded driving circuit portion; a first shielding layer at least partially stacked with the second thin film transistor, and a planarization layer is disposed between the first shielding layer and the second thin film transistor, the first shielding layer including a material same as that of the pixel electrode; and a second shielding layer disposed on the first shielding layer, the second shielding layer extending from the counter electrode, wherein one end of the second shielding layer is disposed between the wiring portion and the display region.

23. The display device according to claim 22, wherein, the first shielding layer includes a plurality of through holes.

24. The display device according to claim 22, the display device further includes: an inorganic protection layer disposed between the second thin film transistor and the planarization layer; and a conductive protection layer disposed on the inorganic protection layer, the conductive protection layer including a conductive material, wherein the conductive protection layer is stacked with the second thin film transistor.

25. The display device according to claim 22, the display device further includes: A dam portion is disposed in the peripheral region, and the dam portion protrudes from the substrate, wherein the dam portion at least partially overlaps with the embedded driving circuit portion.

26. The display device according to claim 22, wherein, a planarization layer is further disposed between the first thin film transistor and the display element, and the planarization layer includes an organic material; and the display device further includes: an inorganic protection layer disposed between the planarization layer and the first thin film transistor, the inorganic protection layer covering source and drain electrodes of the first thin film transistor and extending to the peripheral region, wherein in the peripheral region, the inorganic protection layer includes a region not covered by the planarization layer and an organic material formed in the same layer as the planarization layer.

27. A display device, the display device comprising: a substrate including a display region configured to display an image and a peripheral region located outside the display region, the peripheral region including a top peripheral region, a bottom peripheral region, a left peripheral region, and a right peripheral region; a first thin film transistor disposed in the display region; a display element electrically connected to the first thin film transistor, the display element including a pixel electrode, an intermediate layer, and a counter electrode; an embedded driving circuit portion disposed in the left peripheral region and the right peripheral region, the embedded driving circuit portion including a second thin film transistor; a wiring portion disposed in the peripheral region farther from the display region than the embedded driving circuit portion; and a common voltage supply line disposed in at least one of the top peripheral region and the bottom peripheral region and not disposed in the left peripheral region and the right peripheral region, wherein the common voltage supply line is electrically connected to the counter electrode.

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