Scan Driver and Display Device Including the Same

Abstract

Provided is a scan driver and a display device. The scan driver includes: first to nth scan signal output circuits (n is a natural number greater than or equal to 2), which respectively apply scan signals to scan lines, and the first to nth scan signal output circuits are connected to each other through the scan lines. Each of the first to nth scan signal output circuits includes: a driving circuit, which based on i) an input signal that is one of a scan start signal and a scan signal applied by another scan signal output circuit, ii) a clock signal, and iii) a conduction level voltage, applies a first driving signal to a first driving node, applies a second driving signal to a second driving node, and applies a connection signal to a connection signal output node; and a buffer circuit, which receives the connection signal, the first driving signal, and the second driving signal from the driving circuit, and outputs one of the scan signals to one of the scan lines based on the first driving signal, the second driving signal, and the clock signal.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2018-0166337, filed on Dec. 20, 2018, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. Technical Field

[0002] Exemplary embodiments of the invention generally relate to a scan driver and a display device including the scan driver, and more particularly, to a scan driver capable of sensing characteristics of display elements during an edge period of a display and a display device including the scan driver. Background Art

[0003] Generally, a display device includes a display panel, a scan driver, a data driver, a timing controller, etc. At this time, the scan driver supplies a scan signal to the display panel through a scan line, and each of the scan signals may be a scan-on signal or a scan-off signal.

[0004] To this end, the scan driver includes scan signal output circuits connected in sequence, and each of the scan signal output circuits is composed of an oxide thin film transistor.

[0005] In recent years, a display device compensates for deterioration of pixels and changes in characteristics (e.g., changes in characteristics according to temperature) by sensing information related to the mobility of a driving transistor included in a pixel circuit or information related to deterioration of a light emitting element. At this time, the scan driver may generate and output a scan signal for a display operation, a mobility sensing operation, and a deterioration sensing operation of the light emitting element.

[0006] The above information disclosed in this background art section is only for understanding the background of the inventive concept, and thus, it may include information that does not constitute the prior art. Summary of the Invention

[0007] A scan driver and a display device including the scan driver constructed according to the principles and exemplary embodiments of the invention can accurately sense characteristics such as mobility and deterioration of display elements (which may be pixels). In addition, the sensing operation can be completed within a relatively short time, such as during an edge period of a display.

[0008] A scan driver and a display device including the scan driver constructed according to the principles and exemplary embodiments of the invention can reduce voltage stress applied to some transistors included in the scan driver.

[0009] Additional features of the inventive concept will be set forth in the following description, and will be partly apparent from the description, or may be learned by practice of the inventive concept.

[0010] A scan driver configured according to one or more embodiments for a display device includes a first scan signal output circuit to an nth (where n is a natural number greater than or equal to 2) scan signal output circuit for applying scan signals to scan lines respectively, and the first scan signal output circuit to the nth scan signal output circuit are connected to each other through the scan lines. Each of the first scan signal output circuit to the nth scan signal output circuit includes: a driving circuit for applying a first driving signal to a first driving node, applying a second driving signal to a second driving node, and applying a connection signal to a connection signal output node based on i) an input signal that is one of a scan start signal and a scan signal applied by another scan signal output circuit, ii) a clock signal, and iii) a conduction level voltage; and a buffer circuit for receiving the connection signal, the first driving signal, and the second driving signal from the driving circuit, and for outputting one of the scan signals to one of the scan lines based on the first driving signal, the second driving signal, and the clock signal.

[0011] The buffer circuit can be operable to select one of the scan lines for mobility sensing by storing a sampled voltage at a sampling node based on a sensed conduction signal.

[0012] The scan driver can be operable to apply scan signals to frames, each frame having a display period and an edge period; the first scan signal output circuit to the nth scan signal output circuit can output scan signals through the scan lines during the display period; at least one of the first scan signal output circuit to the nth scan signal output circuit can output at least one of the scan signals through at least one of the scan lines during the edge period.

[0013] The first scan signal output circuit to the nth scan signal output circuit can be connected to pixels through the scan lines, and the pixels can be operable to display an image during a frame having a display period and an edge period; during the display period, the buffer circuit can be operable to select one of the scan lines by transmitting the connection signal of another scan signal output circuit among the first scan signal output circuit to the nth scan signal output circuit to the sampling node to charge the sampling node in response to an enabled control signal; during the edge period, the buffer circuit can be operable to output the one of the scan signals to the one of the scan lines in response to the voltage of the sampling node.

[0014] The clock signal may include a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, and each scan signal output circuit among the first scan signal output circuit to the nth scan signal output circuit may receive at least two clock signals among the first clock signal to the fourth clock signal.

[0015] The driving circuit included in the mth (where m is a natural number less than n) scan signal output circuit for receiving the first clock signal and the third clock signal may include: a third transistor having a first terminal for receiving the first clock signal, a second terminal connected to a second node, and a gate terminal connected to a first node; a fourth transistor having a first terminal for receiving a conductive level voltage, a second terminal connected to the first node, and a gate terminal for receiving an input signal; a fifth transistor having a first terminal connected to the second node, a second terminal for receiving the conductive level voltage, and a gate terminal for receiving the first clock signal; a sixth transistor having a first terminal connected to the second node, a second terminal for receiving the conductive level voltage, and a gate terminal connected to the second node; a seventh transistor having a second terminal, a first terminal connected to the first node, and a gate terminal for receiving the third clock signal; an eighth transistor having a first terminal connected to the second terminal of the seventh transistor, a second terminal connected to a connection signal output node, and a gate terminal connected to the second node; a ninth transistor having a first terminal connected to the first node, a second terminal connected to the connection signal output node, and a gate terminal for receiving a connection signal of another scan signal output circuit among the first scan signal output circuit to the nth scan signal output circuit; a first capacitor having a first terminal connected to the first node and a second terminal connected to the connection signal output node; a tenth transistor having a first terminal for receiving the third clock signal, a second terminal connected to the connection signal output node, and a gate terminal connected to the first node; an eleventh transistor having a first terminal connected to the connection signal output node, a second terminal for receiving an auxiliary cut-off level voltage, and a gate terminal connected to the second node; a second capacitor having a first terminal connected to the second node and a second terminal for receiving the auxiliary cut-off level voltage; a twelfth transistor having a first terminal connected to the first node, a second terminal connected to a first driving node, and a gate terminal for receiving a display conduction signal; and a thirteenth transistor having a first terminal connected to the second node, a second terminal connected to a second driving node, and a gate terminal for receiving the display conduction signal.

[0016] The fourth transistor included in the first scan signal output circuit may receive a scan start signal as an input signal, and the fourth transistors included in the second scan signal output circuit to the nth scan signal output circuit may be operable to receive the scan signals applied by the first scan signal output circuit to the (n - 1)th scan signal output circuit as input signals respectively.

[0017] The fourth transistors included in the first scan signal output circuit and the second scan signal output circuit may be operable to receive a scan start signal as an input signal, and the fourth transistors included in the ith (where i is a natural number greater than or equal to 3 and less than or equal to n) scan signal output circuit may be operable to receive the scan signal applied by the (i - 2)th scan signal output circuit as an input signal.

[0018] The buffer circuit included in the mth scan signal output circuit may include: a fourteenth transistor having a first terminal for receiving a connection signal of the other scan signal output circuit among the first scan signal output circuit to the nth scan signal output circuit, a second terminal connected to a sampling node, and a gate terminal for receiving a sense conduction signal; a third capacitor having a first terminal connected to the sampling node and a second terminal for receiving an auxiliary cut-off level voltage; a fourth capacitor having a first terminal connected to the sampling node and a second terminal for receiving a sense conduction signal; a fifteenth transistor having a first terminal for receiving a sense mode activation clock signal, a second terminal connected to a third node, and a gate terminal connected to the sampling node; a sixteenth transistor having a second terminal, a first terminal connected to a second driving node, and a gate terminal for receiving a sense mode activation clock signal; a seventeenth transistor having a first terminal connected to the second terminal of the sixteenth transistor, a second terminal for receiving a cut-off level voltage higher than the auxiliary cut-off level voltage, and a gate terminal connected to the sampling node; an eighteenth transistor having a first terminal connected to the third node, a second terminal connected to a first driving node, and a gate terminal connected to the sampling node; a nineteenth transistor having a first terminal connected to the third node, a second terminal connected to a connection signal output node, and a gate terminal connected to the first driving node; a first transistor having a first terminal for receiving a third clock signal, a second terminal for outputting one of the scan signals, and a gate terminal connected to the first driving node; and a second transistor having a first terminal for outputting the one of the scan signals, a second terminal for receiving a cut-off level voltage, and a gate terminal connected to the second driving node.

[0019] The (m + 1)th scan signal output circuit may be operable to receive a second clock signal and a fourth clock signal.

[0020] A display device constructed according to one or more embodiments includes: a display unit including a plurality of pixels; a data driver for supplying data signals to the display unit; a scan driver for supplying scan signals to the display unit; and a timing controller for controlling the data driver and the scan driver, wherein the scan driver includes a first scan signal output circuit to an nth (where n is a natural number greater than or equal to 2) scan signal output circuit for applying the scan signals to the display unit through scan lines respectively. Each of the first scan signal output circuit to the nth scan signal output circuit includes: a driving circuit for applying a first driving signal to a first driving node, applying a second driving signal to a second driving node, and applying a connection signal to a connection signal output node based on i) an input signal which is one of a scan start signal and a scan signal applied from another scan signal output circuit, ii) a clock signal, and iii) a conduction level voltage; and a buffer circuit for receiving the connection signal, the first driving signal, and the second driving signal from the driving circuit, and for outputting one of the scan signals to one of the scan lines based on the first driving signal, the second driving signal, and the clock signal.

[0021] The display unit may be operable to display an image during a frame having a display period and an edge period; the buffer circuit may be operable to select one of the scan lines by transmitting the connection signal of another scan signal output circuit among the first scan signal output circuit to the nth scan signal output circuit to a sampling node to charge the sampling node in response to an enabled control signal during the display period; and the buffer circuit may also be operable to output one of the scan signals to the one of the scan lines in response to the voltage of the sampling node during the edge period.

[0022] The display unit may be operable to display an image during a frame having a display period and an edge period when the display device is in a display mode; the first scan signal output circuit to the nth scan signal output circuit may be operable to output scan signals through the scan lines during the display period; at least one of the first scan signal output circuit to the nth scan signal output circuit may be operable to output at least one of the scan signals through at least one of the scan lines during the edge period.

[0023] When the display device is in a non-display mode, the frame may further include a threshold voltage sensing period, and the first scan signal output circuit to the nth scan signal output circuit may be operable to sequentially output scan signals through the scan lines during the threshold voltage sensing period.

[0024] The timing controller can be operated to supply clock signals including a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal to a scan driver, and each of the first to nth scan signal output circuits can be operated to receive at least two of the first to fourth clock signals.

[0025] The driving circuit included in the mth (where m is a natural number less than n) scan signal output circuit and capable of receiving the first clock signal and the third clock signal may include: a third transistor having a first terminal for receiving the first clock signal, a second terminal connected to a second node, and a gate terminal connected to a first node; a fourth transistor having a first terminal for receiving a conduction level voltage, a second terminal connected to the first node, and a gate terminal for receiving an input signal; a fifth transistor having a first terminal connected to the second node, a second terminal for receiving the conduction level voltage, and a gate terminal for receiving the first clock signal; a sixth transistor having a first terminal connected to the second node, a second terminal for receiving the conduction level voltage, and a gate terminal connected to the second node; a seventh transistor having a second terminal, a first terminal connected to the first node, and a gate terminal for receiving the third clock signal; an eighth transistor having a first terminal connected to the second terminal of the seventh transistor, a second terminal connected to a connection signal output node, and a gate terminal connected to the second node; a ninth transistor having a first terminal connected to the first node, a second terminal connected to the connection signal output node, and a gate terminal for receiving a connection signal of another scan signal output circuit among the first to nth scan signal output circuits; a first capacitor having a first terminal connected to the first node and a second terminal connected to the connection signal output node; a tenth transistor having a first terminal for receiving the third clock signal, a second terminal connected to the connection signal output node, and a gate terminal connected to the first node; an eleventh transistor having a first terminal connected to the connection signal output node, a second terminal for receiving an auxiliary cut-off level voltage, and a gate terminal connected to the second node; a second capacitor having a first terminal connected to the second node and a second terminal for receiving the auxiliary cut-off level voltage; a twelfth transistor having a first terminal connected to the first node, a second terminal connected to a first driving node, and a gate terminal for receiving a display conduction signal; and a thirteenth transistor having a first terminal connected to the second node, a second terminal connected to a second driving node, and a gate terminal for receiving the display conduction signal.

[0026] The fourth transistor included in the first scan signal output circuit can be capable of operating to receive a scan start signal as an input signal, and the fourth transistors included in the second scan signal output circuit to the n-th scan signal output circuit can be capable of operating to receive the scan signals applied by the first scan signal output circuit to the (n-1)-th scan signal output circuit as input signals respectively.

[0027] The fourth transistors included in the first scan signal output circuit and the second scan signal output circuit can be capable of operating to receive a scan start signal as an input signal, and the fourth transistors included in the i-th (where i is a natural number greater than or equal to 3 and less than or equal to n) scan signal output circuit can be capable of operating to receive the scan signal applied by the (i-2)-th scan signal output circuit as an input signal.

[0028] The buffer circuit included in the m-th scan signal output circuit may include: a fourteenth transistor having a first terminal for receiving a connection signal of the other scan signal output circuit among the first scan signal output circuit to the n-th scan signal output circuit, a second terminal connected to a sampling node, and a gate terminal for receiving a sense conduction signal; a third capacitor having a first terminal connected to the sampling node and a second terminal for receiving an auxiliary cut-off level voltage; a fourth capacitor having a first terminal connected to the sampling node and a second terminal for receiving a sense conduction signal; a fifteenth transistor having a first terminal for receiving a sense mode activation clock signal, a second terminal connected to a third node, and a gate terminal connected to the sampling node; a sixteenth transistor having a second terminal, a first terminal connected to a second driving node, and a gate terminal for receiving a sense mode activation clock signal; a seventeenth transistor having a first terminal connected to the second terminal of the sixteenth transistor, a second terminal for receiving a cut-off level voltage higher than the auxiliary cut-off level voltage, and a gate terminal connected to the sampling node; an eighteenth transistor having a first terminal connected to the third node, a second terminal connected to a first driving node, and a gate terminal connected to the sampling node; a nineteenth transistor having a first terminal connected to the third node, a second terminal connected to a connection signal output node, and a gate terminal connected to the first driving node; a first transistor having a first terminal for receiving a third clock signal, a second terminal for outputting one of the scan signals, and a gate terminal connected to the first driving node; and a second transistor having a first terminal for outputting the one of the scan signals, a second terminal for receiving a cut-off level voltage, and a gate terminal connected to the second driving node.

[0029] Each of a plurality of pixels may include: a light-emitting element; a driving transistor configured to control an amount of current flowing through the light-emitting element based on one of data signals; a switching transistor having a gate terminal connected to one of the scan lines and configured to receive a data signal; and a sensing transistor having a gate terminal connected to one of the scan lines and connected to a first terminal of the light-emitting element.

[0030] It will be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings illustrate exemplary embodiments of the invention and, together with the description, are used to explain the inventive concept. The drawings are included to provide a further understanding of the invention, and the drawings are incorporated into and constitute a part of this specification.

[0032] Figure 1 is a block diagram of an exemplary embodiment of a display device constructed according to the principles of the invention.

[0033] Figure 2 is Figure 1 a circuit diagram of an exemplary embodiment of a representative pixel in a pixel of

[0034] Figure 3 is Figure 1 a block diagram of an exemplary embodiment of a scan driver of

[0035] Figure 4 is Figure 3 a circuit diagram of an exemplary embodiment of any one of scan signal output circuits of

[0036] Figure 5 is a timing diagram showing Figure 4 some signals related to generation of a scan signal during a display period in signals of a scan signal output circuit of

[0037] Figure 6 is a timing diagram showing Figure 4 some signals related to selection of a scan line for sensing a pixel during a display period in signals of a scan signal output circuit of

[0038] Figure 7 is a timing diagram showing Figure 4 some signals in an edge period in signals of a scan signal output circuit of

[0039] Figure 8 is a timing diagram showing Figure 4 some signals in a threshold voltage sensing period in signals of a scan signal output circuit of

[0040] Figure 9 is Figure 1 a block diagram of another exemplary embodiment of a scan driver.

[0041] Figure 10 is Figure 9 a circuit diagram of an exemplary embodiment of any one of the scan signal output circuits of

[0042] Figure 11 is a timing diagram showing Figure 10 some signals related to the generation of the scan signal among the signals of the scan signal output circuit of Detailed implementation manners

[0043] In the following description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable terms and are non-limiting examples of a device or method that employs one or more of the inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring various exemplary embodiments. Additionally, various exemplary embodiments may be different but not necessarily exclusive. For example, without departing from the inventive concept, the specific shapes, configurations, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0044] Unless otherwise specified, the exemplary embodiments shown are understood to provide exemplary features of different details of some ways in which the inventive concept may be implemented in practice. Thus, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of various embodiments may be additionally combined, separated, interchanged, and / or rearranged without departing from the inventive concept.

[0045] In the drawings, for clarity and / or description purposes, the sizes and relative sizes of elements may be exaggerated. When an exemplary embodiment may be implemented differently, the specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. Additionally, the same reference numerals denote the same elements.

[0046] When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there can be intervening elements or layers. However, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. For this reason, the term "connected" can refer to physical connection, electrical connection, and / or fluid connection with or without intervening elements. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, by way of example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below may be referred to as a second element without departing from the teachings of the disclosure.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. Further, when the terms "comprises", "comprising" are used in this specification, it indicates the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, and are thus used to interpret the inherent deviations of measured, calculated, and / or set values that would be recognized by one of ordinary skill in the art.

[0049] As is customary in the art, some exemplary embodiments are described and illustrated in the drawings in terms of functional blocks, functional units, and / or functional modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic circuits (or optical circuits) (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.), and these electronic circuits (or optical circuits) can be formed using semiconductor-based manufacturing technologies or other manufacturing technologies. In the case where blocks, units, and / or modules are implemented by a microprocessor or other similar hardware, software (e.g., microcode) can be used to program and control the blocks, units, and / or modules to perform the various functions discussed herein, and the blocks, units, and / or modules can be optionally driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or each block, unit, and / or module can be implemented as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. Additionally, without departing from the scope of the inventive concept, each block, unit, and / or module of some exemplary embodiments can be physically separated into two or more interacting and discrete blocks, units, and / or modules. Further, without departing from the scope of the inventive concept, the blocks, units, and / or modules of some exemplary embodiments can be physically combined into more complex blocks, units, and / or modules.

[0050] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0051] Figure 1 is a block diagram of an exemplary embodiment of a display device constructed in accordance with the principles of the invention.

[0052] Referring to Figure 1 , the display device may include a display unit 100 including a plurality of pixels PX, a scan driver 210, a data driver 220, a sensing unit 230, and a timing controller 240.

[0053] The timing controller 240 may generate a scan drive control signal and a data drive control signal based on an external input signal. The scan drive control signal and the data drive control signal generated by the timing controller 240 may be supplied to the scan driver 210 and the data driver 220, respectively.

[0054] The scan driving control signal may include a scan start signal SSP and a plurality of clock signals. The scan start signal SSP may control the output timing of the first scan signal.

[0055] The plurality of clock signals supplied to the scan driver 210 may include a first clock signal CLK1 to a fourth clock signal CLK4. The first clock signal CLK1 to the fourth clock signal CLK4 may be used to shift the scan start signal SSP. In addition, the scan driver 210 may also receive clock signals other than the first clock signal CLK1 to the fourth clock signal CLK4 described above.

[0056] The data driving control signal may include a source start pulse and a clock signal. The source start pulse may be used to control the sampling start time of data, and the clock signal may be used to control the sampling operation.

[0057] The scan driver 210 may output a scan signal in response to the scan driving control signal. The scan driver 210 may sequentially supply the scan signal to the scan lines S1 to Sn. Here, the scan signal may be set to a gate-on voltage (e.g., a high-level voltage) so that the transistors included in the pixel PX can be turned on.

[0058] The data driver 220 may supply data signals to the data lines D1 to Dx in response to the data driving control signal. The data signals may be supplied to the pixel PX supplied with the scan signal through the data lines D1 to Dx. To this end, the data driver 220 may supply the data signals to the data lines D1 to Dx in synchronization with the scan signal.

[0059] The sensing unit 230 may supply initialization power to the pixel PX through the sensing lines SL1 to SLx, and measure the mobility information and degradation information of the pixel PX. Although the sensing unit 230 is shown as a separate structure in Figure 1 the sensing unit 230 may be included in the data driver 220.

[0060] The display unit 100 may include a plurality of pixels PX connected to the data lines D1 to Dx, the scan lines S1 to Sn, and the sensing lines SL1 to SLx.

[0061] The pixel PX may receive a first power ELVDD and a second power ELVSS from an external source outside the display unit 100.

[0062] When a scan signal is supplied through the scan lines S1 to Sn connected to the pixel PX, the pixel PX may receive data signals through the data lines D1 to Dx, respectively. The pixel PX receiving the data signal may control the amount of current flowing from the first power supply supplying the first power ELVDD through the light-emitting element to the second power supply supplying the second power ELVSS in response to the data signal.

[0063] At this time, the light-emitting element can generate light having a brightness corresponding to the amount of current. The first power supply ELVDD can be set to a voltage higher than the voltage of the second power supply ELVSS.

[0064] In an exemplary embodiment, in addition to the scan lines S1 to Sn and the data lines D1 to Dx, each of the pixels PX may also be connected to a light emission control line. In this case, the display device may further include a light emission driver for outputting a light emission control signal to the light emission control line.

[0065] Figure 2 Yes Figure 1 A circuit diagram of an exemplary embodiment of a representative pixel among the pixels. For convenience of description, Figure 2 shows a pixel connected to the i-th scan line Si and the j-th data line Dj, where i is an integer equal to or greater than 1 and equal to or less than n, and j is an integer equal to or greater than 1 and equal to or less than x.

[0066] The pixel may include a driving transistor M1, a switching transistor M2, a sensing transistor M3, a storage capacitor C ST and a light-emitting element LED.

[0067] The switching transistor M2 may have: a first terminal connected to the j-th data line Dj; a gate terminal connected to the i-th scan line Si; and a second terminal connected to the first node Na.

[0068] When a scan signal is supplied through the i-th scan line Si, the switching transistor M2 may be turned on to supply a data signal from the j-th data line Dj to the storage capacitor C ST . Accordingly, the potential of the first node Na can be controlled.

[0069] At this time, the storage capacitor C including a first terminal connected to the first node Na and a second terminal connected to the second node Nb ST can be charged with a voltage corresponding to the data signal.

[0070] The driving transistor M1 may have: a first terminal connected to a first power supply that supplies the first power ELVDD; a second terminal connected to the light-emitting element LED; and a gate terminal connected to the first node Na.

[0071] The driving transistor M1 can control the amount of current flowing through the light-emitting element LED in response to a gate-source voltage value that is a voltage between the first terminal and the second terminal of the storage capacitor C ST .

[0072] The sensing transistor M3 may have: a first terminal connected to the j-th sensing line SLj; a second terminal connected to the second node Nb; and a gate terminal connected to the i-th scan line Si. When a scan signal is supplied to the i-th scan line Si, the sensing transistor M3 may be turned on to control the potential of the second node Nb.

[0073] The light-emitting element LED may have: a first terminal such as an anode terminal connected to the second terminal of the driving transistor M1; and a second terminal such as a cathode terminal connected to a second power supply that supplies the second power ELVSS. The light-emitting element LED may generate light corresponding to the amount of current supplied through the driving transistor M1.

[0074] In Figure 2 each of the first terminals of the first terminal of the driving transistor M1, the first terminal of the switching transistor M2, and the first terminal of the sensing transistor M3 may be set as a source terminal or a drain terminal, and each of the second terminals of the second terminal of the driving transistor M1, the second terminal of the switching transistor M2, and the second terminal of the sensing transistor M3 may be set as the other of the source terminal and the drain terminal. For example, if the first terminal is set as the source terminal, the second terminal may be set as the drain terminal.

[0075] In addition, the driving transistor M1, the switching transistor M2, and the sensing transistor M3 may be NMOS transistors as shown in Figure 2 .

[0076] When sensing the mobility of the driving transistor M1, an activation signal (or an enable signal) is supplied to the i-th scan line Si. For example, when the sensing transistor M3 is turned on in response to the scan signal supplied through the i-th scan line Si, the mobility of the driving transistor M1 may be sensed by the Figure 1 sensing unit 230 through the j-th sensing line SLj.

[0077] Figure 3 is Figure 1 a block diagram of an exemplary embodiment of a scan driver of

[0078] Referring to Figure 3 , the scan driver 210 may include a plurality of scan signal output circuits SSC1 to SSCn. The scan driver 210 may supply scan signals to the scan lines S1 to Sn respectively, so that the display device can display an image. In addition, the scan driver 210 may supply scan signals to the scan lines S1 to Sn respectively, so that the display device can perform a mobility sensing operation and a threshold voltage sensing operation.

[0079] The scan signal output circuits SSC1 to SSCn may be sequentially connected to each other. In an exemplary embodiment, the k-th scan line Sk may be connected to the k-th scan signal output circuit SSCk and the (k + 1)-th scan signal output circuit SSCk+1, where k is an integer equal to or greater than 1 and equal to or less than n. Each of the scan signal output circuits SSC1 to SSCn may receive at least two of the first clock signal CLK1 to the fourth clock signal CLK4.

[0080] In an exemplary embodiment, the odd-numbered scan signal output circuits receive the first clock signal CLK1 and the third clock signal CLK3, and the even-numbered scan signal output circuits receive the second clock signal CLK2 and the fourth clock signal CLK4. The first scan signal output circuit SSC1 may receive the first clock signal CLK1, the third clock signal CLK3, and the scan start signal SSP, and may be connected to the first scan line S1. The second scan signal output circuit SSC2 may be connected to the first scan signal output circuit SSC1 through the first scan line S1, may receive the scan signal output from the first scan signal output circuit SSC1, and may receive the second clock signal CLK2 and the fourth clock signal CLK4. The second scan signal output circuit SSC2 may be connected to the second scan line S2. The n-th scan signal output circuit SSCn may be connected to the (n - 1)-th scan signal output circuit SSCn-1 through the (n - 1)-th scan line Sn-1, may receive the scan signal output from the (n - 1)-th scan signal output circuit SSCn-1, and may receive the second clock signal CLK2 and the fourth clock signal CLK4. The n-th scan signal output circuit SSCn may be connected to the n-th scan line Sn.

[0081] When the display device performs an operation of displaying an image, the scan driver 210 may sequentially apply scan signals to the first scan line S1 to the n-th scan line Sn in response to the scan start signal SSP. For example, after the first scan signal output circuit SSC1 outputs a scan signal, the second scan signal output circuit SSC2 may output a scan signal, after the second scan signal output circuit SSC2 outputs a scan signal, the third scan signal output circuit SSC3 may output a scan signal, and after the (n - 1)-th scan signal output circuit SSCn-1 outputs a scan signal, the n-th scan signal output circuit SSCn may output a scan signal.

[0082] To perform a mobility sensing operation, the scan driver 210 may select a scan line connected to a pixel to be sensed, and then may output a sensing signal to the selected scan line.

[0083] The display device displays an image in the display unit 100 during each frame. The scan driver 210 may sequentially apply scan signals to the first scan line S1 to the nth scan line Sn during a display period of the frame in which the image is displayed, and apply scan signals to at least one of the first scan line S1 to the nth scan line Sn during a porch period of the frame in which a mobility sensing operation is performed.

[0084] Figure 4 Is Figure 3 A circuit diagram of an exemplary embodiment of any one of the scan signal output circuits. For the purpose of convenient description, Figure 4 Shows the structure of the mth scan signal output circuit SSCm.

[0085] Referring to Figure 4 , the mth scan signal output circuit SSCm may include a driving circuit 211 and a buffer circuit 213.

[0086] The driving circuit 211 may include a third transistor T3 to a thirteenth transistor T13 and a first capacitor C1 and a second capacitor C2.

[0087] The third transistor T3 may have: a first terminal for receiving a first clock signal CLK1; a second terminal connected to a second node N2; and a gate terminal connected to a first node N1.

[0088] The fourth transistor T4 may have: a first terminal connected to a conductive level voltage VGH; a second terminal connected to the first node N1; and a gate terminal for receiving the (m - 1)th scan signal SCAN[m - 1]. Although in Figure 4 the (m - 1)th scan signal SCAN[m - 1] is shown as being input to the gate terminal of the fourth transistor T4, the scan start signal SSP may be input as an input signal to the gate terminal of the fourth transistor T4 included in the first scan signal output circuit SSC1.

[0089] The fifth transistor T5 may have: a first terminal connected to the second node N2; a second terminal connected to the conductive level voltage VGH; and a gate terminal for receiving the first clock signal CLK1.

[0090] The sixth transistor T6 may have: a first terminal connected to the second node N2; a second terminal connected to the conductive level voltage VGH; and a gate terminal connected to the second node N2.

[0091] The seventh transistor T7 may have: a first terminal connected to the first node N1; a second terminal connected to a first terminal of an eighth transistor T8; and a gate terminal for receiving a third clock signal CLK3.

[0092] The eighth transistor T8 may have: a first terminal connected to the second terminal of the seventh transistor T7; a second terminal connected to the connection signal output node LN; and a gate terminal connected to the second node N2.

[0093] The ninth transistor T9 may have: a first terminal connected to the first node N1; a second terminal connected to the connection signal output node LN; and a gate terminal for receiving a subsequent connection signal L[m+2]. Although the subsequent connection signal L[m+2] is shown as a connection signal output from the (m+2)-th scan signal output circuit SSCm+2, according to an exemplary embodiment, the subsequent connection signal L[m+2] may be a connection signal output from another scan signal output circuit.

[0094] The first capacitor C1 may have: a first terminal connected to the first node N1; and a second terminal connected to the connection signal output node LN.

[0095] The tenth transistor T10 may have: a first terminal for receiving a third clock signal CLK3; a second terminal connected to the connection signal output node LN; and a gate terminal connected to the first node N1.

[0096] The eleventh transistor T11 may have: a first terminal connected to the connection signal output node LN; a second terminal for receiving an auxiliary cut-off level voltage VGL1 lower than the cut-off level voltage VGL; and a gate terminal connected to the second node N2. The cut-off level voltage VGL may be lower than the conduction level voltage VGH.

[0097] The second capacitor C2 may have: a first terminal connected to the second node N2; and a second terminal for receiving the auxiliary cut-off level voltage VGL1.

[0098] The twelfth transistor T12 may have: a first terminal connected to the first node N1; a second terminal connected to the first driving node Q1N; and a gate terminal for receiving a display conduction signal DIS_ON.

[0099] The thirteenth transistor T13 may have: a first terminal connected to the second node N2; a second terminal connected to the second driving node Q2N; and a gate terminal for receiving a display conduction signal DIS_ON.

[0100] Secondly, the buffer circuit 213 may include a first transistor T1, a second transistor T2, fourteenth transistors T14 to nineteenth transistors T19, a third capacitor C3, and a fourth capacitor C4.

[0101] The fourteenth transistor T14 may have: a first terminal for receiving a subsequent connection signal L[m+2]; a second terminal connected to a sampling node SN; and a gate terminal for receiving a sense conduction signal SEN_ON.

[0102] The third capacitor C3 may have: a first terminal connected to the sampling node SN; and a second terminal for receiving an auxiliary cut-off level voltage VGL1. According to an exemplary embodiment, the second terminal of the third capacitor C3 may receive a cut-off level voltage VGL.

[0103] The fourth capacitor C4 may have: a first terminal connected to the sampling node SN; and a second terminal for receiving a sense conduction signal SEN_ON.

[0104] The fifteenth transistor T15 may have: a first terminal for receiving a sense mode activation clock signal S_CLK; a second terminal connected to a third node N3; and a gate terminal connected to the sampling node SN.

[0105] The sixteenth transistor T16 may have: a first terminal connected to a second driving node Q2N; a second terminal connected to a first terminal of a seventeenth transistor T17; and a gate terminal for receiving a sense mode activation clock signal S_CLK.

[0106] The seventeenth transistor T17 may have: a first terminal connected to the second terminal of the sixteenth transistor T16; a second terminal for receiving a cut-off level voltage VGL; and a gate terminal connected to the sampling node SN.

[0107] The eighteenth transistor T18 may have: a first terminal connected to the third node N3 (i.e., the second terminal of the fifteenth transistor T15); a second terminal connected to a first driving node Q1N; and a gate terminal connected to the sampling node SN.

[0108] The nineteenth transistor T19 may have: a first terminal connected to the third node N3; a second terminal for receiving a connection signal L[m] of a connection signal output node LN; and a gate terminal connected to the first driving node Q1N.

[0109] The first transistor T1 may have: a first terminal for receiving a third clock signal CLK3; a second terminal connected to a scan signal output node ON_SC; and a gate terminal connected to the first driving node Q1N.

[0110] The second transistor T2 may have: a first terminal connected to the scan signal output node ON_SC; a second terminal for receiving a cut-off level voltage VGL; and a gate terminal connected to the second driving node Q2N.

[0111] Figure 1 The timing controller 240 can provide control signals such as a display on signal DIS_ON, a sense on signal SEN_ON, and a sense mode activation clock signal S_CLK.

[0112] In an exemplary embodiment, the buffer circuit 213 may further include a capacitor having a first terminal connected to the first driving node Q1N and a second terminal connected to the scan signal output node ON_SC.

[0113] In an exemplary embodiment, the buffer circuit 213 may further include a capacitor having a first terminal connected to the second driving node Q2N and a second terminal for receiving a cut-off level voltage VGL.

[0114] Each of the scan signal output circuits SSC1 to SSCn may receive a plurality of clock signals and output a scan signal to the scan signal output node ON_SC based on the received clock signals.

[0115] For example, the m-th scan signal output circuit SSCm may receive a first clock signal CLK1 and a third clock signal CLK3 and output a scan signal SCAN[m] based on the first clock signal CLK1 and the third clock signal CLK3.

[0116] In this way, the rising edge of the third clock signal CLK3 may be adjacent to the falling edge of the first clock signal CLK1, the rising edge of the first clock signal CLK1 may be adjacent to the falling edge of the third clock signal CLK3, and the activation period of the first clock signal CLK1 may not overlap with the activation period of the third clock signal CLK3.

[0117] When the display device is in a display mode, one frame may include a display period and an edge period. During the display period, the display on signal DIS_ON may be activated and the sense mode activation clock signal S_CLK may be deactivated. During the edge period, when the display on signal DIS_ON is deactivated (or disabled), the sense mode activation clock signal S_CLK may be activated.

[0118] In addition, when a subsequent connection signal L[m+2] is activated during a display period, the sense conduction signal SEN_ON may be activated or deactivated. For example, if the sense conduction signal SEN_ON is activated when a subsequent connection signal L[m+2] is activated during a display period, the activated subsequent connection signal L[m+2] may be transmitted to a sampling node SN through a fourteenth transistor T14, so that a sampling voltage may be stored in the sampling node SN of the m-th scan signal output circuit SSCm. If the sense conduction signal SEN_ON is not activated when a subsequent connection signal L[m+2] is activated during a display period, the fourteenth transistor T14 may be turned off, and the sampling voltage may not be stored in the sampling node SN of the m-th scan signal output circuit SSCm.

[0119] Figure 5 is a timing diagram of some signals related to the generation of scan signals among the signals of the scan signal output circuit shown Figure 4 during a display period.

[0120] Although Figure 5 the first clock signal CLK1 to the fourth clock signal CLK4 are shown in, it is assumed that the m-th scan signal output circuit SSCm receives the first clock signal CLK1 and the third clock signal CLK3. In this case, the (m+1)-th scan signal output circuit SSCm+1 may receive the second clock signal CLK2 and the fourth clock signal CLK4.

[0121] Referring to Figure 5 , during a display period of a frame, the sense mode activation clock signal S_CLK may remain deactivated (e.g., logic low level), while the display conduction signal DIS_ON may remain activated (e.g., logic high level).

[0122] When the m-1-th scan signal SCAN[m-1] is input and the fourth transistor T4 is turned on, the first node N1 and the first driving node Q1N are charged with a conduction level voltage VGH, so that the signal applied to the first node N1 and the first driving signal Q1 applied to the first driving node Q1N may have the conduction level voltage VGH.

[0123] When the m-1-th scan signal SCAN[m-1] is input and the fourth transistor T4 is turned on, since the third transistor T3 is turned on by the signal of the first node N1 having the conduction level voltage VGH, the second node N2 and the second driving node Q2N are charged with the non-activated voltage of the first clock signal CLK1. Thus, the signal applied to the second node N2 and the second driving signal Q2 applied to the second driving node Q2N may have the non-activated voltage of the first clock signal CLK1.

[0124] Therefore, as the third clock signal CLK3 is activated, a scan signal SCAN[m] having an activation voltage of the third clock signal CLK3, such as a scan conduction signal, can be output through the scan signal output node ON_SC.

[0125] Due to the first driving signal Q1 having a conductive level voltage VGH and the second driving signal Q2 having a non-activation voltage of the first clock signal CLK1, the tenth transistor T10 can be turned on, while the eleventh transistor T11 can be turned off. As the third clock signal CLK3 is activated, a connection signal L[m] having an activation voltage of the third clock signal CLK3 can be output through the connection signal output node LN.

[0126] When the first driving node Q1N is charged with the conductive level voltage VGH, the nineteenth transistor T19 is turned on, so that the third node N3 can be charged with the connection signal L[m] having an activation voltage of the third clock signal CLK3.

[0127] That is, the drain-source voltage of the eighteenth transistor T18 (i.e., the voltage between the second terminal and the first terminal) can be the voltage difference between the conductive level voltage VGH charged in the first driving node Q1N and the voltage of the connection signal L[m] having an activation voltage of the third clock signal CLK3. In addition, the drain-source voltage of the fifteenth transistor T15 can be the voltage difference between the connection signal L[m] having an activation voltage of the third clock signal CLK3 and the voltage of the deactivated sense mode activation clock signal S_CLK.

[0128] For example, when the conductive level voltage VGH charged in the first driving node Q1N is about 54V, the voltage of the connection signal L[m] having an activation voltage of the third clock signal CLK3 is about 25V, and the voltage of the deactivated sense mode activation clock signal S_CLK is about -12V, the drain-source voltage of the eighteenth transistor T18 can be about 29V, and the drain-source voltage of the fifteenth transistor T15 is about 37V.

[0129] Different from the scan signal output circuit according to the illustrated embodiment, if the scan signal output circuit does not include the eighteenth transistor T18 and the nineteenth transistor T19, when the first driving node Q1N is charged with the conductive level voltage VGH and the sense mode activation clock signal S_CLK is deactivated, a very high voltage is applied between the drain and the source of the fifteenth transistor T15. In this way, a high voltage stress is continuously applied to the fifteenth transistor T15.

[0130] However, in the illustrated embodiment, when the eighteenth transistor T18 is connected between the fifteenth transistor T15 and the first driving node Q1N and the nineteenth transistor T19 transmits the connection signal L[m] to the third node N3 connected between the fifteenth transistor T15 and the eighteenth transistor T18, a high voltage stress applied to the fifteenth transistor T15 can be reduced.

[0131] Thereafter, the third clock signal CLK3 is deactivated again, so that a scan signal SCAN[m] having an inactive voltage of the third clock signal CLK3, such as a scan cut-off signal, can be output through the scan signal output node ON_SC. In addition, the connection signal L[m] can have an inactive voltage of the third clock signal CLK3.

[0132] Furthermore, as the third clock signal CLK3 is deactivated again, the connection signal L[m] having an inactive voltage of the third clock signal CLK3 can be output through the connection signal output node LN.

[0133] In this way, during the display period of one frame of the display device, the scan signal output circuits SSC1 to SSCn sequentially connected to each other can sequentially output scan signals having an active voltage.

[0134] Figure 6 is a Figure 4 timing diagram of some signals related to the selection of the scan lines for sensing pixels during the display period among the signals of the scan signal output circuit shown.

[0135] Referring to Figure 6 , when the first clock signal CLK1 is activated for the first time, the conduction level voltage VGH is supplied to the second node N2 through the fifth transistor T5, and the second node N2 is charged with the conduction level voltage VGH, so that the eleventh transistor T11 is turned on. At this time, when the subsequent connection signal L[m + 2] is activated, the auxiliary cut-off level voltage VGL1 is supplied to the first node N1 and the first driving node Q1N through the eleventh transistor T11 and the ninth transistor T9 to reset the first node N1 and the first driving node Q1N. Since the display conduction signal DIS_ON is activated during the display period, the first driving node Q1N can have the auxiliary cut-off level voltage VGL1, and the auxiliary cut-off level voltage VGL1 is transmitted to the first driving node Q1N through the turned-on twelfth transistor T12.

[0136] In a state where the subsequent connection signal L[m + 2] is activated, as the sense conduction signal SEN_ON is activated, the fourteenth transistor T14 is turned on, so that the sampling node SN can be charged with the active voltage of the subsequent connection signal L[m + 2]. As a result, the sampling node SN can store and hold the sampling voltage by using the third capacitor C3.

[0137] In an exemplary embodiment, for all of the scan signal output circuits SSC1 to SSCn, the sense-on signal SEN_ON may be activated.

[0138] Although the subsequent connection signal L[m+2] is shown as a connection signal output from the (m+2)-th scan signal output circuit SSCm+2, according to an exemplary embodiment, the subsequent connection signal may be a connection signal output from another scan signal output circuit.

[0139] Figure 7 is a diagram showing Figure 4 the timing of some of the signals in the edge period among the signals of the scan signal output circuit.

[0140] Referring to Figure 7 , in the scan signal output circuit SSCm in which the sampling node SN holds the sampling voltage using the third capacitor C3, the fifteenth transistor T15 and the eighteenth transistor T18 may be turned on by the sampling voltage. The twelfth transistor T12 and the thirteenth transistor T13 may be turned off in response to the display-on signal DIS_ON deactivated in the edge period. Thus, the first driving node Q1N and the second driving node Q2N may be disconnected from the first node N1 and the second node N2, respectively.

[0141] When the sense-mode activation clock signal S_CLK is activated in the edge period of one frame while the fifteenth transistor T15 and the eighteenth transistor T18 are turned on, the first driving node Q1N may be charged with the activation voltage of the sense-mode activation clock signal S_CLK.

[0142] Accordingly, the first driving signal Q1 applied to the first driving node Q1N may have the activation voltage of the sense-mode activation clock signal S_CLK. As a result, the first transistor T1 may be turned on, and a scan signal SCAN[m] having the activation voltage of the third clock signal CLK3, such as a sense-on signal, may be output through the scan signal output node ON_SC. At this time, the remaining clock signals (the first clock signal CLK1, the second clock signal CLK2, and the fourth clock signal CLK4) other than the third clock signal CLK3 may have the activation voltage, but the exemplary embodiment is not limited thereto, and the remaining clock signals (the first clock signal CLK1, the second clock signal CLK2, and the fourth clock signal CLK4) may also have the non-activation voltage.

[0143] During the edge period of a frame, the fifteenth transistor T15 and the eighteenth transistor T18 in the scan signal output circuits SSC1 to SSCm-1 and SSCm+1 to SSCn that do not store the sampled voltage are not turned on, so that the sense conduction signal SEN_ON having the activation voltage of the third clock signal CLK3 cannot be output to the scan signal output node ON_SC.

[0144] According to some exemplary embodiments, by selecting a scan line during the display period and applying a scan signal to the selected scan line during the edge period, the scan signal can be output to the scan line for sensing the pixels connected to the scan line. Therefore, it can take only a relatively short time to sense the pixels.

[0145] Figure 8 is a timing diagram showing Figure 4 some of the signals in the threshold voltage sensing period among the signals of the scan signal output circuit.

[0146] Referring to Figure 8 , when the display device is in the non-display mode, one frame for sensing or scanning the pixels PX of the display unit 100 includes a threshold voltage sensing period (VTH sensing period), and the display device can perform a threshold voltage sensing operation during the threshold voltage sensing period (VTH sensing period).

[0147] During the threshold voltage sensing period (VTH sensing period) of the frame, the first scan signal output circuit SSC1 to the nth scan signal output circuit SSCn can sequentially apply a scan conduction signal to the first scan line S1 to the nth scan line Sn in the same manner as in the display period.

[0148] At this time, the threshold voltage sensing period (VTH sensing period) can be longer than the display period, which can be achieved by adjusting the pulse widths of the first clock signal CLK1 to the fourth clock signal CLK4.

[0149] During the threshold voltage sensing period (VTH sensing period) of the frame of the display device, the sense mode activation clock signal S_CLK can be kept active, and the display conduction signal DIS_ON can be kept active.

[0150] At this time, when the (m - 1)th scan signal SCAN[m - 1] is activated and the fourth transistor T4 is turned on, the first node N1 and the first driving node Q1N are charged with the conduction level voltage VGH, so that the signal applied to the first node N1 and the signal applied to the first driving node Q1N can have the conduction level voltage VGH.

[0151] When the (m - 1)-th scan signal SCAN[m - 1] is activated and the fourth transistor T4 is turned on, when the first clock signal CLK1 is deactivated, the second node N2 and the second driving node Q2N are charged with the inactive voltage of the first clock signal CLK1 through the deactivated first clock signal CLK1, so that the signal applied to the second node N2 and the second driving signal Q2 applied to the second driving node Q2N can have the inactive voltage of the first clock signal CLK1.

[0152] As a result, the first transistor T1 and the tenth transistor T10 can be turned on, and the second transistor T2 and the eleventh transistor T11 can be turned off.

[0153] Therefore, as the third clock signal CLK3 is activated, a scan signal SCAN[m] having the active voltage of the third clock signal CLK3, such as a scan-on signal, can be output through the scan signal output node ON_SC, and a connection signal L[m] having the active voltage of the third clock signal CLK3 can be output through the connection signal output node LN.

[0154] Thereafter, as the third clock signal CLK3 is deactivated again, a scan signal SCAN[m] having the inactive voltage of the third clock signal CLK3, such as a scan-off signal, can be output through the scan signal output node ON_SC, and a connection signal L[m] having the inactive voltage of the third clock signal CLK3 can be output through the connection signal output node LN.

[0155] Since the display-on signal DIS_ON remains activated, the scan signal SCAN[m] and the connection signal L[m] can have substantially the same waveform.

[0156] In this way, during the threshold voltage sensing period (VTH sensing period) of a frame of the display device, the scan signal output circuits SSC1 to SSCn connected to each other in the scan driver 210 can sequentially output scan signals having the active voltage of the third clock signal CLK3, such as scan-on signals.

[0157] Figure 9 Yes Figure 1 is a block diagram of another exemplary embodiment of the scan driver. In Figure 9 the description will focus on the parts modified compared to the above-described exemplary embodiment, and the repeated description will be omitted to avoid redundancy. Therefore, the description will focus on the connection relationship between the scan signal output circuits SSC1' to SSCn'.

[0158] Referring to Figure 9, the scan driver 210' may include a plurality of scan signal output circuits SSC1' to SSCn' connected to the first scan line S1 to the nth scan line. At least two of the scan signal output circuits SSC1' to SSCn' may be connected to each other. In an exemplary embodiment, the scan signal output circuits SSC1' to SSCn' may be divided into two groups, and the scan signal output circuits in each group may be sequentially connected to each other.

[0159] For example, the first scan signal output circuit SSC1' receives the scan start signal SSP', and may be connected to the first scan line S1. The second scan signal output circuit SSC2' receives the scan start signal SSP', and may be connected to the second scan line S2. The third scan signal output circuit SSC3' may be connected to the first scan signal output circuit SSC1' through the first scan line S1 to receive the scan signal output from the first scan signal output circuit SSC1', and may be connected to the third scan line S3. The fourth scan signal output circuit SSC4' may be connected to the second scan signal output circuit SSC2' through the second scan line S2 to receive the scan signal output from the second scan signal output circuit SSC2', and may be connected to the fourth scan line S4. The nth scan signal output circuit SSCn' may be connected to the (n-2)th scan signal output circuit SSCn-2' through the (n-2)th scan line Sn-2 to receive the scan signal output from the (n-2)th scan signal output circuit SSCn-2', and may be connected to the nth scan line Sn.

[0160] Figure 10 is Figure 9 a circuit diagram of an exemplary embodiment of any one of the scan signal output circuits. In Figure 10 , for the purpose of convenient description, the structure of the mth scan signal output circuit SSCm' is shown.

[0161] In Figure 10 , the description will focus on the parts modified compared to the above-described exemplary embodiment, and the repeated description will be omitted.

[0162] Referring to Figure 10 , the fourth transistor T4 included in the driving circuit 211 may have: a first terminal for receiving the conductive level voltage VGH; a second terminal connected to the first node N1; and a gate terminal for receiving the (m-2)th scan signal SCAN[m-2].

[0163] Compared with when the (m-1)th scan signal SCAN[m-1] is input to the gate terminal of the fourth transistor T4, when the (m-2)th scan signal SCAN[m-2] is input to the gate terminal of the fourth transistor T4, during the process of generating the scan signal for the display operation, the pre-charge period of the first driving node Q1N may be increased.

[0164] Figure 11 It is shown Figure 10 A timing diagram of some signals related to the generation of scan signals in the scan signal output circuit.

[0165] As described above, when the activated signal of the (m-2)th scan signal SCAN[m-2] is input to the gate terminal of the fourth transistor T4, the first driving node Q1N starts to be charged with the on-level voltage VGH.

[0166] Therefore, if Figure 11 As shown in , when the (m-2)th scan signal SCAN[m-2] is input to the gate terminal of the fourth transistor T4, the first driving node Q1N may be precharged during the first period P1, and the voltage V[Q1N] of the first driving node Q1N may increase relatively high.

[0167] In contrast, if the m-1th scan signal SCAN[m-1] is input to the gate terminal of the fourth transistor T4, the first driving node Q1N is precharged during the second period P2 shorter than the first period P1. That is, in the case of the scan driver according to the exemplary embodiment, by precharging the first driving node Q1N in response to the m-2th scan signal SCAN[m-2] to increase the precharge period of the first driving node Q1N, a more accurate scan signal can be output.

[0168] As reference Figures 9 to 11 As described, according to the exemplary embodiment, not only the first scan signal output circuit SSC1' receives the scan start signal SSP' as an input signal, but also the second scan signal output circuit SSC2' receives the scan start signal SSP' as an input signal. Here, the period during which the scan start signal SSP' is activated can be set to be longer than the period from the time point when the first clock signal CLK1 starts to be activated (corresponding to the rising edge of the first clock signal CLK1) to the time point when the second clock signal CLK2 starts to be deactivated (corresponding to the falling edge of the second clock signal CLK2).

[0169] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those of ordinary skill in the art.

Claims

1. A scan driver for a display device, the scan driver comprising: The first to the nth scan signal output circuits are configured to apply scan signals to scan lines respectively, and the first to the nth scan signal output circuits are connected to each other through the scan lines, where n is a natural number greater than or equal to 2. Among them, each of the first to the nth scan signal output circuits includes: A driving circuit configured to apply a first driving signal to a first driving node, a second driving signal to a second driving node, and a connection signal to a connection signal output node based on i) an input signal which is one of a scan start signal and a scan signal applied by another scan signal output circuit, ii) a clock signal, and iii) a conduction level voltage. A buffer circuit configured to receive the connection signal from the connection signal output node, the first driving signal from the first driving node, and the second driving signal from the second driving node, and configured to output one of the scan signals to one of the scan lines based on the first driving signal, the second driving signal, and the clock signal. Among them, the buffer circuit included in the mth scan signal output circuit includes: A fifteenth transistor having a first terminal for receiving a sense mode activation clock signal, a second terminal connected to a third node, and a gate terminal connected to a sampling node. An eighteenth transistor having a first terminal connected to the third node, a second terminal connected to the first driving node, and a gate terminal connected to the sampling node. A nineteenth transistor having a first terminal connected to the third node, a second terminal connected to the connection signal output node, and a gate terminal connected to the first driving node, and Among them, when the first driving node is charged with the conduction level voltage, the nineteenth transistor is turned on, so that the third node is charged with the connection signal having the activation voltage of the third clock signal.

2. The scan driver according to claim 1, wherein, The buffer circuit can operate to select one of the scan lines for mobility sensing by storing a sampling voltage at the sampling node based on a sense conduction signal.

3. The scan driver according to claim 1, wherein: The scan driver can operate to apply the scan signal to a frame, each of the frames having a display period and an edge period. During the display period, the first to the nth scan signal output circuits output the scan signals through the scan lines. And During the edge period, at least one of the first to the nth scan signal output circuits outputs at least one of the scan signals through at least one of the scan lines.

4. The scan driver according to claim 1, wherein: The first to the nth scan signal output circuits are connected to pixels through the scan lines, and the pixels can operate to display an image during a frame having a display period and an edge period. During the display period, the buffer circuit is operable to: in response to an enabled control signal, select one of the scan lines by transmitting the connection signal from the first scan signal output circuit to another scan signal output circuit among the nth scan signal output circuits to the sampling node to charge the sampling node; and During the edge period, the buffer circuit is operable to: in response to the voltage of the sampling node, output the one scan signal among the scan signals to the one scan line among the scan lines.

5. The scan driver according to claim 1, wherein, The clock signal includes a first clock signal, a second clock signal, the third clock signal, and a fourth clock signal, and wherein each of the scan signal output circuits from the first scan signal output circuit to the nth scan signal output circuit receives at least two of the first clock signal to the fourth clock signal.

6. The scan driver according to claim 5, wherein, The driving circuit included in the mth scan signal output circuit for receiving the first clock signal and the third clock signal includes: A third transistor having a first terminal for receiving the first clock signal, a second terminal connected to a second node, and a gate terminal connected to a first node; A fourth transistor having a first terminal for receiving the conductive level voltage, a second terminal connected to the first node, and a gate terminal for receiving the input signal; A fifth transistor having a first terminal connected to the second node, a second terminal for receiving the conductive level voltage, and a gate terminal for receiving the first clock signal; A sixth transistor having a first terminal connected to the second node, a second terminal for receiving the conductive level voltage, and a gate terminal connected to the second node; A seventh transistor having a second terminal, a first terminal connected to the first node, and a gate terminal for receiving the third clock signal; An eighth transistor having a first terminal connected to the second terminal of the seventh transistor, a second terminal connected to the connection signal output node, and a gate terminal connected to the second node; A ninth transistor having a first terminal connected to the first node, a second terminal connected to the connection signal output node, and a gate terminal for receiving the connection signal from another scan signal output circuit among the first scan signal output circuit to the nth scan signal output circuit; A first capacitor having a first terminal connected to the first node and a second terminal connected to the connection signal output node; A tenth transistor having a first terminal for receiving the third clock signal, a second terminal connected to the connection signal output node, and a gate terminal connected to the first node; An eleventh transistor having a first terminal connected to the connection signal output node, a second terminal for receiving the auxiliary cut-off level voltage, and a gate terminal connected to the second node; A second capacitor having a first terminal connected to the second node and a second terminal for receiving the auxiliary cut-off level voltage; A twelfth transistor, having a first terminal connected to the first node, a second terminal connected to the first driving node, and a gate terminal for receiving a display on signal; and A thirteenth transistor, having a first terminal connected to the second node, a second terminal connected to the second driving node, and a gate terminal for receiving the display on signal, where m is a natural number less than n.

7. The scan driver according to claim 6, wherein, The fourth transistor included in the first scan signal output circuit receives the scan start signal as the input signal, and where the fourth transistors included in the second scan signal output circuit to the nth scan signal output circuit can be operated to receive the scan signals applied by the first scan signal output circuit to the (n - 1)th scan signal output circuit as the input signals respectively.

8. The scan driver according to claim 6, wherein, The fourth transistors included in the first scan signal output circuit and the second scan signal output circuit can be operated to receive the scan start signal as the input signal, and where the fourth transistor included in the ith scan signal output circuit can be operated to receive the scan signal applied by the (i - 2)th scan signal output circuit as the input signal, where i is a natural number greater than or equal to 3 and less than or equal to n.

9. The scan driver according to claim 6, wherein, The buffer circuit included in the mth scan signal output circuit further includes: A fourteenth transistor, having a first terminal for receiving the connection signal of the other scan signal output circuit among the first scan signal output circuit to the nth scan signal output circuit, a second terminal connected to the sampling node, and a gate terminal for receiving a sense on signal; A third capacitor, having a first terminal connected to the sampling node and a second terminal for receiving the auxiliary cut-off level voltage; A fourth capacitor, having a first terminal connected to the sampling node and a second terminal for receiving the sense on signal; A sixteenth transistor, having a second terminal, a first terminal connected to the second driving node, and a gate terminal for receiving the sense mode activation clock signal; A seventeenth transistor, having a first terminal connected to the second terminal of the sixteenth transistor, a second terminal for receiving a cut-off level voltage higher than the auxiliary cut-off level voltage, and a gate terminal connected to the sampling node; A first transistor, having a first terminal for receiving the third clock signal, a second terminal for outputting one of the scan signals, and a gate terminal connected to the first driving node; and A second transistor, having a first terminal for outputting the one of the scan signals, a second terminal for receiving the cut-off level voltage, and a gate terminal connected to the second driving node.

10. The scan driver according to claim 6, wherein, The (m + 1)th scan signal output circuit can be operated to receive the second clock signal and the fourth clock signal.

11. A display device, the display device comprising: A display unit, including a plurality of pixels; A data driver, for supplying a data signal to the display unit; A scan driver, for supplying a scan signal to the display unit; and A timing controller for controlling the data driver and the scan driver, wherein the scan driver includes a first scan signal output circuit to an nth scan signal output circuit for applying the scan signal to the display unit through scan lines respectively, where n is a natural number greater than or equal to 2, wherein each of the first scan signal output circuit to the nth scan signal output circuit includes: a driving circuit for applying a first driving signal to a first driving node, applying a second driving signal to a second driving node, and applying a connection signal to a connection signal output node based on i) an input signal which is one of a scan start signal and a scan signal applied by another scan signal output circuit, ii) a clock signal, and iii) a conduction level voltage; and a buffer circuit for receiving the connection signal from the connection signal output node, receiving the first driving signal from the first driving node, receiving the second driving signal from the second driving node, and for outputting one of the scan signals to one of the scan lines based on the first driving signal, the second driving signal, and the clock signal, wherein the buffer circuit included in the mth scan signal output circuit includes: a fifteenth transistor having a first terminal for receiving a sense mode activation clock signal, a second terminal connected to a third node, and a gate terminal connected to a sampling node; an eighteenth transistor having a first terminal connected to the third node, a second terminal connected to the first driving node, and a gate terminal connected to the sampling node; a nineteenth transistor having a first terminal connected to the third node, a second terminal connected to the connection signal output node, and a gate terminal connected to the first driving node, and wherein when the first driving node is charged with the conduction level voltage, the nineteenth transistor is turned on, such that the third node is charged with the connection signal having an activation voltage of a third clock signal.

12. The display device according to claim 11, wherein: The display unit is operable to display an image during a frame having a display period and an edge period; The buffer circuit is operable to, during the display period, select one of the scan lines by transmitting the connection signal of another scan signal output circuit among the first scan signal output circuit to the nth scan signal output circuit to the sampling node to charge the sampling node in response to an enabled control signal; and The buffer circuit is further operable to, during the edge period, output the one of the scan signals to the one of the scan lines in response to the voltage of the sampling node.

13. The display device according to claim 12, wherein: The display unit is operable to display an image during the frame having the display period and the edge period when the display device is in a display mode; The first scan signal output circuit to the nth scan signal output circuit are operable to output the scan signal through the scan lines during the display period; and At least one of the first to nth scan signal output circuits can operate to output at least one of the scan signals through at least one of the scan lines during the edge period.

14. The display device according to claim 13, wherein, When the display device is in the non-display mode, the frame further includes a threshold voltage sensing period, and wherein, the first to nth scan signal output circuits can operate to sequentially output the scan signals through the scan lines during the threshold voltage sensing period.

15. The display device according to claim 14, wherein, The timing controller can operate to supply the clock signals including the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal to the scan driver, and wherein, each of the first to nth scan signal output circuits can operate to receive at least two of the first to fourth clock signals.

16. The display device according to claim 15, wherein, The driving circuit included in the mth scan signal output circuit and capable of receiving the first clock signal and the third clock signal includes: A third transistor having a first terminal for receiving the first clock signal, a second terminal connected to a second node, and a gate terminal connected to a first node; A fourth transistor having a first terminal for receiving the conduction level voltage, a second terminal connected to the first node, and a gate terminal for receiving the input signal; A fifth transistor having a first terminal connected to the second node, a second terminal for receiving the conduction level voltage, and a gate terminal for receiving the first clock signal; A sixth transistor having a first terminal connected to the second node, a second terminal for receiving the conduction level voltage, and a gate terminal connected to the second node; A seventh transistor having a second terminal, a first terminal connected to the first node, and a gate terminal for receiving the third clock signal; An eighth transistor having a first terminal connected to the second terminal of the seventh transistor, a second terminal connected to the connection signal output node, and a gate terminal connected to the second node; A ninth transistor having a first terminal connected to the first node, a second terminal connected to the connection signal output node, and a gate terminal for receiving the connection signal of another scan signal output circuit among the first to nth scan signal output circuits; A first capacitor having a first terminal connected to the first node and a second terminal connected to the connection signal output node; A tenth transistor having a first terminal for receiving the third clock signal, a second terminal connected to the connection signal output node, and a gate terminal connected to the first node; An eleventh transistor having a first terminal connected to the connection signal output node, a second terminal for receiving the auxiliary cut-off level voltage, and a gate terminal connected to the second node; A second capacitor having a first terminal connected to the second node and a second terminal for receiving the auxiliary cut-off level voltage; A twelfth transistor having a first terminal connected to the first node, a second terminal connected to the first driving node, and a gate terminal for receiving a display on signal; and A thirteenth transistor having a first terminal connected to the second node, a second terminal connected to the second driving node, and a gate terminal for receiving the display on signal, where m is a natural number less than n.

17. The display device according to claim 16, wherein, The fourth transistor included in the first scan signal output circuit can operate to receive the scan start signal as the input signal, and where the fourth transistors included in the second scan signal output circuit to the nth scan signal output circuit can operate to receive the scan signals applied by the first scan signal output circuit to the (n - 1)th scan signal output circuit as the input signals respectively.

18. The display device according to claim 16, wherein, The fourth transistors included in the first scan signal output circuit and the second scan signal output circuit can operate to receive the scan start signal as the input signal, and where the fourth transistor included in the ith scan signal output circuit can operate to receive the scan signal applied by the (i - 2)th scan signal output circuit as the input signal, where i is a natural number greater than or equal to 3 and less than or equal to n.

19. The display device according to claim 16, wherein, The buffer circuit included in the mth scan signal output circuit further includes: A fourteenth transistor having a first terminal for receiving the connection signal of the other scan signal output circuit among the first scan signal output circuit to the nth scan signal output circuit, a second terminal connected to the sampling node, and a gate terminal for receiving a sense on signal; A third capacitor having a first terminal connected to the sampling node and a second terminal for receiving the auxiliary cut-off level voltage; A fourth capacitor having a first terminal connected to the sampling node and a second terminal for receiving the sense on signal; A sixteenth transistor having a second terminal, a first terminal connected to the second driving node, and a gate terminal for receiving the sense mode activation clock signal; A seventeenth transistor having a first terminal connected to the second terminal of the sixteenth transistor, a second terminal for receiving a cut-off level voltage higher than the auxiliary cut-off level voltage, and a gate terminal connected to the sampling node; A first transistor having a first terminal for receiving the third clock signal, a second terminal for outputting one of the scan signals, and a gate terminal connected to the first driving node; and A second transistor having a first terminal for outputting one of the scan signals, a second terminal for receiving the cut-off level voltage, and a gate terminal connected to the second driving node.

20. The display device according to claim 19, wherein, Each of the plurality of pixels includes: A light-emitting element; A driving transistor for controlling the amount of current flowing through the light-emitting element based on one of the data signals; A switching transistor having a gate terminal connected to one of the scan lines for receiving the one data signal; and A sensing transistor having a gate terminal connected to one of the scan lines and connected to a first terminal of the light-emitting element.

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