Chip layout image generation method based on boundary tracking scanning line algorithm

Abstract

The invention discloses a chip layout image generation method based on a boundary tracking scanning line algorithm. A sub-graph-polygon data structure is designed, a maximum matrix of adjacent polygons of a sub-graph is established, the boundary scanning line algorithm is improved through the method, a complete chip layout is rapidly cut into a sub-graph, and a corresponding binary image is generated. According to the algorithm, a sub-graph circumscribed frame-polygon circumscribed frame data structure is designed, and polygons which are likely to intersect with the sub-graphs are quickly positioned. The data are stored to construct the maximum bounding box of all polygons contained in the current sub-graph, so that the algorithm does not need to calculate the intersection points of the polygons and the sub-graphs, and the time consumption for calculating the intersection points by the algorithm is reduced; in addition, a boundary tracking mode is designed, a scanning line algorithm is improved, intersection points of scanning lines and polygon boundaries do not need to be calculated when a certain line is scanned by storing all points in the boundaries, and algorithm complexity is further reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip layout image processing, and particularly relates to a method for generating a chip layout image based on a boundary tracking scan line algorithm. Background Art

[0002] With the continuous progress of semiconductor manufacturing technology, the complexity of modern circuit design and process steps has been continuously increasing, and mask optimization technology is also facing huge challenges. Traditional mask optimization methods rely on empirical formulas and rules. To a certain extent, these methods can solve some problems, but their limitations gradually become apparent when facing increasingly complex circuit designs and process requirements. The traditional mask optimization methods mainly include the following several types: geometry-based optimization, rule-based optimization, and simulation-based optimization. These methods often require a large amount of manual intervention, and the optimization process is time-consuming, making it difficult to meet the design requirements of high efficiency and high precision. In addition, with the continuous reduction of feature sizes, the effects of traditional optimization methods are often unsatisfactory when dealing with nanoscale circuits.

[0003] With the progress of computing hardware and the rapid development of deep learning technology, researchers have begun to explore the possibility of combining inverse lithography technology (ILT) with GPU acceleration and deep learning models. Existing methods all rely on the input of pixel-level format data, which means they need to process a large amount of raw image data. In the fields of image recognition and deep learning, pixel-level input is the most basic data form, directly taking the original image or video frame as the state input into the neural network. This method of directly using pixel values, although data-intensive, can provide the richest information and allows the model to capture fine features and patterns in the image. However, this also brings some challenges. In actual chip layout data, there are usually more than one million polygons in a 0.5mm * 0.5mm chip data block, and there are approximately 100 million polygons in a 5mm * 5mm single-layer chip data. How to quickly obtain the corresponding image pixel-level input from chip layout data has become a key step in using deep learning to solve the mask optimization problem. Currently, in the field of chip layout processing, the research on quickly segmenting and generating binary images for actual chip layouts is relatively scarce. The existing research work related to the papers is basically based on open-source data that already has good image data or has already been pre-segmented polygon vertex data, lacking a practical solution for segmenting and generating binary images from a large amount of polygon data starting from the real layout.

[0004] Therefore, we propose a method for quickly segmenting a chip layout and generating a binary image based on a boundary tracking scan line algorithm. By constructing a data structure and improving the scan line algorithm, a specified-size subgraph can be quickly divided from a huge chip design layout, and the corresponding binary image can be generated. Summary of the Invention

[0005] In view of the problems existing in the prior art, the present invention provides a method for generating a chip layout image based on a boundary tracking scan line algorithm to solve the problems of high requirements for the generation accuracy of binary images, high polygon complexity, large data volume, and long solution time in the processing of chip layout mask optimization by current artificial intelligence image algorithms.

[0006] The technical solution of the present invention is realized as follows:

[0007] A method for generating a chip layout image based on a boundary tracking scan line algorithm includes the following steps:

[0008] S1. Read the chip layout data and perform preprocessing to generate key-value pairs of sub-graph indexes and polygon indexes;

[0009] S2. According to the key-value pairs of sub-graph indexes and polygon indexes, construct the maximum matrix M of the polygons included in and adjacent to the sub-graph;

[0010] S3. Through the tracking scan line algorithm, obtain the coordinates of the vertices and edges of the polygons adjacent to the sub-graph, traverse the vertices of the polygons, insert the data of the edges into the vertical edge dictionary and the horizontal edge list for filling, and assign values to the maximum matrix M in S2 to obtain the assigned matrix;

[0011] S4. According to the relative position of the sub-graph, read out the sub-graph matrix and save it;

[0012] S5. Loop through each sub-graph, execute steps S2 - 24 for each sub-graph, obtain all sub-graph matrices in the chip layout and save them to obtain the final picture.

[0013] Further, in S1, it specifically includes:

[0014] Read the chip layout data. The chip layout includes multiple polygons. Construct a plane rectangular coordinate system, store the vertices of the polygons as coordinates, and obtain the coordinates of the outer frame of the entire chip layout, that is, (x min , y min , x max , y max ),

[0015] where x min represents the minimum value of the abscissa x of all polygons in the current chip layout, y min represents the minimum value of the ordinate y of all polygons in the current chip layout, x max represents the maximum value of the abscissa x of all polygons in the current chip layout, and y min represents the maximum value of the ordinate y of all polygons in the current chip layout;

[0016] Set the size of the sub - figure as H, and divide the chip layout into multiple identical sub - figures.

[0017] Furthermore, the method of dividing the chip layout into multiple identical sub - figures is as follows:

[0018] Expand the left and right sides of the chip layout so that the chip layout can be evenly divisible by the size of the sub - figure, that is:

[0019] clip len = x max - x min ;

[0020]

[0021] j right = j x - j left ;

[0022] Among them, clip len represents the length of the abscissa of the chip layout, and j x represents the length that the chip layout needs to be expanded to the left and right to be evenly divisible by the size of the sub - figure. j left represents the length of the left - hand expansion of the chip layout, and j right represents the length of the right - hand expansion of the chip layout;

[0023] According to the calculation method of expanding the chip layout to the left and right, expand the upper and lower ends of the chip layout so that the chip layout can be evenly divisible by the size of the sub - figure, and obtain the length j up of the upward expansion of the chip layout and the length j down of the downward expansion of the chip layout; thus, divide the chip layout into multiple identical sub - figures.

[0024] Furthermore, according to the expanded chip layout and the divided sub - figures, obtain the outer - frame coordinates of the sub - figure (tile xmin , tile xmin , tile xmin , tile xmin );

[0025] Among them, tile xmin represents the value of the minimum abscissa of the outer - frame of the sub - figure; tile xmin represents the value of the minimum ordinate of the outer - frame of the sub - figure; tile xmin represents the value of the maximum abscissa of the outer - frame of the sub - figure; tile xmin represents the value of the maximum ordinate of the outer - frame of the sub - figure;

[0026] Obtain the vertex coordinates P all = [(P 11 , P12 , …… P 1q ), (P 21 P 22 , …… P 2q ), …… (P p1 , P p2 , …… P pq )], P all represents the sequence set of vertex coordinates of all polygons, (P p1 , P p2 , …… P pq ) represents the sequence set of vertex coordinates of the P-th polygon, P pq represents one of the vertex coordinates of the P-th polygon. Starting from any vertex coordinate of any polygon and traversing all the vertices of the polygon it belongs to in a clockwise or counterclockwise direction, a sequence set of vertex coordinates of one of the polygons is obtained;

[0027] Traverse the vertex coordinates of each polygon to obtain the sequence set of vertex coordinates of all polygons, and then further obtain the outer bounding box rectangle coordinates of all polygon vertices (polygen xmin , polygen ymin , polygen xmax , polygen ymax );

[0028] Among them, polygen xmin represents the value range of the minimum abscissa of the outer bounding box rectangle of polygon vertices;

[0029] polygen ymin represents the value range of the minimum ordinate of the outer bounding box rectangle of polygon vertices; polygen xmax represents the value range of the maximum abscissa of the outer bounding box rectangle of polygon vertices; polygen ymax represents the value range of the maximum ordinate of the outer bounding box rectangle of polygon vertices;

[0030] Initialize the outer bounding box coordinates of all subgraphs as keys and an empty array Tilepolygondict as the value according to the outer bounding box coordinates of the subgraphs and the outer bounding box rectangle coordinates of polygon vertices.

[0031] Furthermore, calculate the subgraphs contained in the polygon according to the outer bounding box rectangle coordinates of polygon vertices. The formula is:

[0032]

[0033] Among them, row min *H, row min *H, col min *H, colmax *H respectively represent the index positions of the outer bounding rectangle coordinates of the polygon vertices under the sub - graph. H is the size of the sub - graph, row min , row max , col min , col max As an intermediate reference value, through row min , row max , col min , col max The sub - graph index position is obtained by the values of ;

[0034] Fill the array Tilepolygondict with data, and the index positions of the outer bounding rectangle coordinates of the polygon vertices under the sub - graph are:

[0035]

[0036] Where i represents starting from row min and taking values until row max , k represents starting from col min and taking values until col max , idx polygen represents the index of the polygon vertex, and append(idx polygen ) means adding the index value of the polygon to the sub - graph index key; thus generating the key - value pair of the sub - graph index and the polygon index.

[0037] Furthermore, the sub - graph index is the outer bounding coordinates of all sub - graphs, and the polygon index is the position of the polygon among the vertex coordinates P all in.

[0038] Furthermore, in S2, it specifically includes:

[0039] S2.1. Obtain the sub - graph index and read the polygons included in the sub - graph in the array Tilepolygondict;

[0040] S2.2. Calculate the polygon - sub - graph minimum outer bounding box. The polygon - sub - graph minimum outer bounding box is the minimum outer bounding box coordinates of all the outer bounding rectangle coordinates that simultaneously contain the polygon vertices and the outer bounding box coordinates of the sub - graph, that is:

[0041] out xmin = min(polygens_x, tile_x);

[0042] out ymin = min(polygens_y, tile_y);

[0043] out xmax= max(polygens_x, tile_x);

[0044] out ymax = max(polygens_y, tile_y);

[0045] Among them, out xmin represents the value of the minimum abscissa of the minimum outer bounding box of the polygon-subgraph; out ymin represents the value of the minimum ordinate of the minimum outer bounding box of the polygon-subgraph; out xmax represents the value of the maximum abscissa of the minimum outer bounding box of the polygon-subgraph; out ymax represents the value of the maximum ordinate of the minimum outer bounding box of the polygon-subgraph;

[0046] polygens_x represents the abscissa of the current polygon; polygens_y represents the ordinate of the current polygon; tile_x represents the abscissa of the subgraph; tile_y represents the ordinate of the subgraph;

[0047] Construct a 0 matrix M with a row length of out ymax - out ymin and a column length of out xmax - out xmin to track the scan line algorithm and fill and assign values of 1 to the interior of the polygon.

[0048] Furthermore, in S3, it specifically includes:

[0049] Define the sides of the polygon as [(x u , y w ), (x v , y z )], indicating the side from the point (x u , y w ) to the point (x v , y z ). x u , x v represents the position of the abscissa corresponding to any side, and y w , y z represents the position of the ordinate corresponding to any side;

[0050] Starting from traversing the sequence set of all polygon vertex coordinates, insert the data of each side into the vertical side dictionary dict y and the horizontal side list list x ; specifically including:

[0051] For the insertion method of vertical sides, traverse the remaining points of the vertical side except the upper endpoint and store them in the vertical side dictionary dicty ;

[0052] Vertical edge dictionary dict y is constructed as follows: using the y-axis coordinate as the key and the set list of x-axis coordinates sorted from smallest to largest sortx as the value to construct key-value pairs;

[0053] For vertical edges [(x n , y1), (x n , y2)], when y2 is greater than y1, for each key from y1 to y2 - 1, insert the corresponding x n value in the corresponding position according to the arrangement order of the x-axis coordinates, that is, dict y [y1] = [... x n-1 , x n , x n+1 ...], dict y [y1 + 1] = [... x n-1 , x n , x n+1 ...]... dict y [y2 - 1] = [... x n-1 , x n , x n+1 ...], ignoring y2;

[0054] where x n represents the value of the abscissa in the vertical edge, and y1 and y2 represent the values of the ordinate in the vertical edge;

[0055] At the same time, record the set of horizontal edges to obtain the horizontal edge list list x , that is, {[(x1, y1), (x2, y1)], [(x3, y2), (x4, y2)]... [(x n , y t ), (x m , y t )]}; where t represents the number of horizontal edges, and x1, x2,... x n , x m represent the values of the abscissa in the horizontal edge, and y1, y2,... y t represent the values of the ordinate in the horizontal edge;

[0056] After traversing all the vertex coordinates of the polygon, store the coordinates of the points on the boundaries of all vertical edges, and at the same time record the coordinate sets of the points on each horizontal edge separately.

[0057] Furthermore, in S3, traverse the data structure, that is, traverse the vertical edge dictionary dict y and the horizontal edge list list x , and for the vertical edge dictionary dict yTake out the values of each row without repetition, that is, obtain the values of adjacent two subscripts, and assign values to the points between the two values in the matrix M in order, and the assigned value is 1, that is:

[0058] A r,y = 1 (o < r < q, o = S xi , q = S xi+1 );

[0059] Among them, S xi represents the xi-th element in S, where xi starts from 0 and the step size is 2, that is, the next value of xi is 2, and S represents the set of x coordinates under any key y; A r，y represents an element in the matrix M with abscissa r and ordinate y;

[0060] Take out each element of the horizontal edge list list x , that is, the set of point coordinates of each horizontal edge, and assign values to the points between each horizontal edge, and the assigned value is 1.

[0061] Furthermore, in S4, after the matrix of S3 is assigned, according to the position of the subgraph, cut out the corresponding subgraph matrix, and save the subgraph matrix as a picture file.

[0062] Compared with the prior art, the present invention has the following beneficial effects:

[0063] The present invention designs a subgraph-polygon data structure, establishes the largest matrix of adjacent polygons of the subgraph, and uses this method to improve the boundary scan line algorithm to quickly cut subgraphs from the complete chip layout and generate corresponding binary images. In the prior art, there are quite few real scenarios of a large number of polygons in the chip layout. The algorithm of the present invention designs a subgraph bounding box-polygon bounding box data structure to quickly locate which polygons are likely to intersect with the subgraph. Save these data to construct the largest bounding box of all polygons included in the current subgraph, so that the algorithm does not need to calculate the intersection points of the polygons and the subgraph, reducing the time consumption of the algorithm for calculating intersection points.

[0064] Moreover, the present invention also designs a boundary tracking method to improve the scan line algorithm. By saving each point in the boundary, when scanning a certain row, it is not necessary to access the intersection points of the scan line and the polygon boundary. The complexity is the perimeter of the polygon side, and the points that need to be filled in a certain row of the polygon can be obtained. Through the innovative design of each key step, a set of fast and feasible technical solutions are provided for obtaining subgraph images from a large number of polygon data. Brief Description of the Drawings

[0065] Figure 1 is a flowchart of a method for generating a chip layout image based on a boundary tracking scan line algorithm provided in an embodiment of the present invention;

[0066] Figure 2 It is a schematic diagram of traversing polygon vertices in an embodiment of the present invention;

[0067] Figure 3 It is a schematic diagram of non-repeated value extraction and assignment for vertical edges in a dictionary in an embodiment of the present invention;

[0068] Figure 4 It is a sub-graph picture saved in a method for generating a chip layout image based on a boundary tracking scan line algorithm provided in an embodiment of the present invention. Detailed implementation manners

[0069] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0070] Embodiment

[0071] Such as Figures 1 to 4 , a method for generating a chip layout image based on a boundary tracking scan line algorithm, includes the following steps:

[0072] S1. Read the chip layout data and perform preprocessing to generate key-value pairs of sub-graph indexes and polygon indexes; specifically including:

[0073] S1.1. Read the chip layout data. The chip layout includes multiple polygons. Construct a plane rectangular coordinate system, store the vertices of the polygons as coordinates, and obtain the outer frame coordinates of the entire chip layout, which are (x min , y min , x max , y max ),

[0074] wherein, x min represents the minimum value of the abscissa x of all polygons in the current chip layout, y min represents the minimum value of the ordinate y of all polygons in the current chip layout, x max represents the maximum value of the abscissa x of all polygons in the current chip layout, and y min represents the maximum value of the ordinate y of all polygons in the current chip layout;

[0075] Usually, it is stored in the oas format, that is, the polygon vertex coordinates are stored, and the origin coordinate direction is the lower left corner. Thus, the larger the value, the further to the right and up. (x min , ymin ) The polygon coordinates for adjustment are unified to (x min , y min ) as the origin, and the minimum unit of the normalized polygon coordinates is the nanometer unit.

[0076] Set the sub - figure size to H, and the sub - figure size H is 2048 nanometers; divide the chip layout into multiple identical sub - figures. In order to make the overall chip layout divisible by the sub - figure size, expand the chip layout outward.

[0077] Expand the left and right sides of the chip layout so that the chip layout is divisible by the sub - figure size, that is:

[0078] clip len = x max - x min ;

[0079]

[0080] j right = j x - j left ;

[0081] Among them, clip len represents the length of the abscissa of the chip layout, j x represents the length that the chip layout needs to be expanded to the left and right to be divisible by the sub - figure size, j left represents the length of the left - hand expansion of the chip layout, j right represents the length of the right - hand expansion of the chip layout;

[0082] Similarly, for the y - coordinate, use the same method to expand the layout range. That is, according to the calculation method of expanding the chip layout to the left and right, expand the upper and lower ends of the chip layout so that the chip layout is divisible by the sub - figure size, and obtain the length j up of the upward expansion of the chip layout, and the length j down of the downward expansion of the chip layout; thus divide the chip layout into multiple identical sub - figures.

[0083] According to the expanded chip layout and the divided sub - figures, obtain the outer - frame coordinates of the sub - figure (tile xmin , tile xmin , tile xmin , tile xmin );

[0084] Among them, tile xmin represents the value of the minimum abscissa of the outer - frame of the sub - figure; tile xmin represents the value of the minimum ordinate of the outer - frame of the sub - figure; tile xminRepresents the value of the maximum abscissa of the outer bounding box of the sub - graph; tile xmin Represents the value of the maximum ordinate of the outer bounding box of the sub - graph;

[0085] After expanding the layout size, the corresponding position coordinates of the sub - graph (tile) can be constructed, such as (0, 0, 2047, 2047); (tilexmin, tilexmin, tilexmin, tilexmin) represents the outer bounding box coordinates of any sub - graph.

[0086] Obtain the vertex coordinates P of all polygons all = [(P 11 , P 12 , …… P 1q ), (P 21 P 22 , …… P 2q ), …… (P p1 , P p2 , …… P pq )], P all Represents the sequence set of the vertex coordinates of all polygons, (P p1 , P p2 , …… P pq ) represents the sequence set of the vertex coordinates of the P - th polygon, P pq Represents one of the vertex coordinates of the P - th polygon. Starting from any vertex coordinate of any polygon and traversing all vertices of the polygon it belongs to clockwise or counter - clockwise, a sequence set of the vertex coordinates of one polygon is obtained;

[0087] Traverse the vertex coordinates of each polygon, obtain the sequence set of the vertex coordinates of all polygons, and then further obtain the outer bounding box rectangle coordinates of all polygon vertices (polygen xmin , polygen ymin , polygen xmax , polygen ymax );

[0088] Among them, polygen xmin Represents the value of the minimum abscissa of the outer bounding box rectangle of the polygon vertices;

[0089] polygen ymin Represents the value of the minimum ordinate of the outer bounding box rectangle of the polygon vertices; polygen xmax Represents the value of the maximum abscissa of the outer bounding box rectangle of the polygon vertices; polygen ymax Represents the value of the maximum ordinate of the outer bounding box rectangle of the polygon vertices;

[0090] To accelerate the chip layout segmentation and binary image generation, key-value pairs of sub-graph indexes and polygon indexes are designed;

[0091] According to the outer frame coordinates of the sub-graph and the outer frame rectangle coordinates of the polygon vertices, initialize the outer frame coordinates of all sub-graphs as keys, and the value is an empty array Tilepolygondict.

[0092] S1.2. Calculate the sub-graphs contained in the polygon according to the outer frame rectangle coordinates of the polygon vertices. The formula is:

[0093]

[0094] where row min *H, row min *H, col min *H, col max *H respectively represent the index positions of the outer frame rectangle coordinates of the polygon vertices under the sub-graph. H is the sub-graph size, row min , row max , col min , col max As intermediate reference values, through row min , row max , col min , col max values to obtain the sub-graph index position;

[0095] Assume that the outer frame of a polygon is polygen xmin is 4000, polygen ymin is 0, polygen xmax is 5000, polygen ymax is 1000, and H is taken as 20248. Then row min takes the value of 4000 / 2048, and rounding down is equal to 1, row max takes the value of 5000 / 2048, and rounding down is equal to 2, indicating that two sub-graphs are spanned on the x-axis. col min and col max only take the value of 0, indicating that there is no span on the y-axis. These values of 1, 2, and 0 can be directly converted into the sub-graph index positions (tile xmin , tile ymin , tile xmax , tile ymax)。The position of the first sub - figure is (1 * 2048, 0 * 2048, 1 * 2048 + 2048 - 1, 0 * 2048 + 2048 - 1), and the position of the second sub - figure is (2 * 2048, 0 * 2048, 2 * 2048 + 2048 - 1, 0 * 2048 + 2048 - 1). This polygon is contained within these two sub - figures.

[0096] Fill the array Tilepolygondict with data. The index positions of the outer - bounding rectangle coordinates of the polygon vertices in the sub - figure are as follows:

[0097]

[0098] where i takes values starting from row min and ending at row max , k takes values starting from col min and ending at col max , idx polygen represents the index of the polygon vertex, and append(idx polygen ) means adding the index value of the polygon to the sub - figure index key; in this way, key - value pairs of sub - figure indices and polygon indices are generated.

[0099] The sub - figure index is the outer - bounding coordinates of all sub - figures, and the polygon index is the position of the polygon among the vertex coordinates P all of all polygons.

[0100] S2. Construct the maximum matrix M of the polygons contained in and adjacent to the sub - figure according to the key - value pairs of sub - figure indices and polygon indices;

[0101] S2.1. Obtain the sub - figure index and read the polygons contained in the sub - figure in the array Tilepolygondict;

[0102] For example, (x min , y min , x max , y max ); read the polygons contained in the sub - figure of (x min , y min , x max , y max ) in Tilepolygondict;

[0103] S2.2. Calculate the polygon - sub - figure minimum outer - bounding box. The polygon - sub - figure minimum outer - bounding box is the minimum outer - bounding box coordinates of all outer - bounding rectangle coordinates that simultaneously contain polygon vertices and the outer - bounding box coordinates of the sub - figure, that is:

[0104] out xmin= min(polygens_x, tile_x);

[0105] out ymin = min(polygens_y, tile_y);

[0106] out xmax = max(polygens_x, tile_x);

[0107] out ymax = max(polygens_y, tile_y);

[0108] Among them, out xmin represents the value of the minimum abscissa of the minimum outer bounding box of the polygon - sub - graph; out ymin represents the value of the minimum ordinate of the minimum outer bounding box of the polygon - sub - graph; out xmax represents the value of the maximum abscissa of the minimum outer bounding box of the polygon - sub - graph; out ymax represents the value of the maximum ordinate of the minimum outer bounding box of the polygon - sub - graph;

[0109] polygens_x represents the abscissa of the current polygon; polygens_y represents the ordinate of the current polygon; tile_x represents the abscissa of the sub - graph; tile_y represents the ordinate of the sub - graph;

[0110] Construct a 0 - matrix M with row length out ymax - out ymin and column length out xmax - out xmin to track the scan - line algorithm and fill and assign values to the interior of the polygon, with the fill assignment being 1.

[0111] S3. Through the scan - line algorithm for tracking, obtain the coordinates of the vertices and edges of the polygon adjacent to the sub - graph, traverse the vertices of the polygon, insert the edge data into the vertical - edge dictionary and the horizontal - edge list for filling, and assign values to the maximum matrix M in S2 to obtain the assigned matrix;

[0112] Specifically, the traditional scan - line algorithm needs to calculate the intersection points of the polygon and each row, and the algorithm time highly depends on the time for calculating the intersection points. The present invention proposes a boundary - tracking optimization for this intersection - point calculation.

[0113] Define the edges of the polygon as [(x u , y w ), (x v , y z )], indicating from the point (x u , y w ) to the point (xv , y z ), the side of x u , x v represents the position of the abscissa corresponding to any side, y w , y z represents the position of the ordinate corresponding to any side;

[0114] Starting from the sequence set that traverses all the vertex coordinates of the polygon, insert the data of each side into the vertical side dictionary dict y and the horizontal side list list x ; specifically including:

[0115] For the insertion method of vertical sides, traverse the remaining points of the vertical side except the upper endpoint and store them in the vertical side dictionary dict y ;

[0116] The vertical side dictionary dict y is constructed as follows: using the y-axis coordinate as the key and the set list sortx of the x-axis coordinates sorted from small to large as the value to construct key-value pairs;

[0117] For the vertical side [(x n , y1), (x n , y2)], when y2 is greater than y1, for each key from y1 to y2 - 1, insert the corresponding x n value in the corresponding position according to the arrangement order of the x-axis coordinates, that is, dict y [y1] = [... x n-1 , x n , x n+1 ...], dict y [y1 + 1] = [... x n-1 , x n , x n+1 ...]... dict y [y2 - 1] = [... x n-1 , x n , x n+1 ...] and ignore y2;

[0118] where x n represents the value of the abscissa in the vertical side, and y1 and y2 represent the values of the ordinate in the vertical side;

[0119] At the same time, record the horizontal side set to obtain the horizontal side list list x , that is, {[(x1, y1), (x2, y1)], [(x3, y2), (x4, y2)]... [(x n , y t ), (x m , yt )]}; where t represents the number of horizontal edges, and x1, x2,..., x n , x m represent the abscissa values in the horizontal edges, and y1, y2,..., y t represent the ordinate values in the horizontal edges;

[0120] After traversing the vertex coordinates of all polygons, store the coordinates of the points on the boundaries of all vertical edges, and simultaneously record the coordinate sets of the points of each horizontal edge separately.

[0121] For example, if the polygon vertex sequence is: [(0,0), (0,20), (20,20), (20,0)], when tracking each edge of the polygon and traversing from (0,0) to (0,20), store the corresponding positions in M, i.e., [(0,0), …, (0,i), …, (0,19)] in dict y at the corresponding positions 0, …, i, …, 19, where i ranges from 1 to 18. Also record the horizontal edges {[(0,20), (20,20)], [(20,0), (0,0)]} at this time. After traversing all the edges of the current polygon, all the points on the boundaries of all vertical edges will be stored, and the coordinate sets of the points of each horizontal edge will be recorded separately.

[0122] As Figure 2 shown in the example of a 6*6 image resolution, traverse the vertex coordinate sequence of the polygon. The hollow nodes represent the storage in the vertical edge dictionary dicty, and the white solid nodes represent the storage in the horizontal edge list list_x.

[0123] Traverse the data structure, that is, traverse the vertical edge dictionary dict y and the horizontal edge list list x , and take out the non-repeated values of each row in the vertical edge dictionary dict y , that is, obtain the values of adjacent two subscripts, and assign values to the points between the two values in the matrix M in order, and the assigned value is 1, that is:

[0124] A r,y = 1 (o < r < q, o = S xi , q = S xi+1 );

[0125] where, S xi represents the xi-th element in S, xi starts from 0, with a step size of 2, that is, the next value of xi is 2, and S represents the x coordinate set under any key y; A r，y represents an element in the matrix M with an abscissa of r and an ordinate of y;

[0126] As Figure 3 , for the vertical edge dictionary dict yExtract the values corresponding to a certain vertical coordinate key without repetition, obtain the values of adjacent subscripts, and assign a value of 1 to the points between the two values. As shown in the gray part of the figure, it means being filled with 1. Similarly, other points can be filled in the same way.

[0127] Extract each element of the horizontal edge list list x , that is, the coordinate set of the points on each horizontal edge, and assign a value of 1 to the points between each horizontal edge.

[0128] S4. According to the relative position of the sub-graph, read out the sub-graph matrix and save it;

[0129] After the matrix assignment in S3 is completed, according to the relative position of the sub-graph, cut out the corresponding sub-graph matrix, and save the sub-graph matrix as a picture file, that is, it can be saved as a png file. Such as Figure 4 .

[0130] S5. Loop through each sub-graph, execute steps S2-24 for each sub-graph, and save it as a png picture until all sub-graph matrices in the chip layout are obtained and saved to get the final picture.

[0131] The present invention provides a method for generating a chip layout image based on a boundary tracking scan line algorithm, designs a fast screening method for the outer frame of the sub-graph and the outer frame of the polygon to generate a local maximum circumscribed matrix of the sub-graph polygon, which is used for subsequent direct matrix splitting without calculating the intersection points of the sub-graph and the polygon; and also proposes a new boundary tracking scan line algorithm. By designing different operations for vertical edges and horizontal edges, it quickly records the paired data that need to be filled in each row. In subsequent filling, directly obtain the corresponding position pairs for fast filling. By constructing a data structure and improving the scan line algorithm, it quickly divides sub-graphs of a specified size from a huge chip design layout and generates corresponding binary images. Moreover, the technical solution provided by the present invention can handle the situation where there are holes in the polygon. The current algorithm does not consider the case of bevel edges.

[0132] According to the disclosure and teaching of the above specification, those skilled in the art to which the present invention pertains can also make changes and modifications to the above embodiments. Therefore, the present invention is not limited to the specific embodiments disclosed and described above, and some modifications and changes to the present invention should also fall within the protection scope of the claims of the present invention. In addition, although some specific terms are used in this specification, these terms are only for convenience of description and do not constitute any limitation to the present invention.

Claims

1. A method for generating a chip layout image based on a boundary tracking scan line algorithm, characterized in that, It includes the following steps: S1. Read the chip layout data and perform preprocessing to generate key-value pairs of sub-graph indexes and polygon indexes; S2. According to the key-value pairs of sub-graph indexes and polygon indexes, construct the maximum matrix M of the polygons included in and adjacent to the sub-graph; S3. By following the scan-line algorithm, obtain the coordinates of the vertices and edges of the polygons adjacent to the sub-graph, traverse the vertices of the polygons, insert the edge data into the vertical-edge dictionary and the horizontal-edge list for filling, and assign values to the maximum matrix M in S2 to obtain the assigned matrix; S4. According to the relative position of the sub-graph, read out the sub-graph matrix and save it; S5. Loop through each sub-graph, execute steps S2 - 24 for each sub-graph, obtain all sub-graph matrices in the chip layout and save them to get the final picture.

2. The method for generating a chip layout image based on a boundary tracking scan line algorithm according to claim 1, wherein In S1, it specifically includes: Read the chip layout data. The chip layout includes multiple polygons. Construct a rectangular coordinate system and store the vertices of the polygons as coordinates. Obtain the coordinates of the outer bounding box of the entire chip layout, which are (x min , y min , x max , y max ). Among them, x min represents the value of the minimum abscissa x of all polygons in the current chip layout, and y min represents the value of the minimum ordinate y of all polygons in the current chip layout, and x max represents the value of the maximum abscissa x of all polygons in the current chip layout, and y min represents the value of the maximum ordinate y of all polygons in the current chip layout; Set the sub-graph size to H and divide the chip layout into multiple identical sub-graphs.

3. A method for generating a chip layout image based on a boundary tracking scan line algorithm according to claim 2, characterized in that The specific method for dividing the chip layout into multiple identical sub-graphs is: Expand the left and right sides of the chip layout outward so that the chip layout can be divisible by the sub-graph size, that is: clip len = x max -x min ; j right = j x -j left ; Among them, clip len represents the length of the abscissa of the chip layout, and j x represents the length that needs to be extended to both the left and right when the chip layout is divisible by the sub-graph size, and j left represents the length of the leftward extension of the chip layout, and j right represents the length of the rightward extension of the chip layout; According to the calculation method of expanding the chip layout to the left and right, the upper and lower ends of the chip layout are extended outward so that the chip layout can be evenly divided by the size of the sub-graph, and the upward expansion length j of the chip layout is obtained. up , the downward expansion length j of the chip layout down ; In this way, the chip layout is divided into multiple identical sub-graphs.

4. A method for generating a chip layout image based on a boundary tracking scan line algorithm according to claim 2, characterized in that Obtain the outer bounding box coordinates of the sub - graphs (tile xmin , tile xmin , tile xmin , tile xmin ) according to the extended chip layout and the divided sub - graphs; Among them, tile xmin represents the value of the minimum abscissa of the outer frame of the sub-graph; tile xmin represents the value of the minimum ordinate of the outer frame of the sub-graph; tile xmin represents the value of the maximum abscissa of the outer frame of the sub-graph; tile xmin represents the value of the maximum ordinate of the outer frame of the sub-graph; Obtain the vertex coordinates P of all polygons all = [(P 11 , P 12 , ……P 1q ), (P 21 P 22 , ……P 2q ), ……(P p1 , P p2 , ……P pq ), P all represents the sequence set of the vertex coordinates of all polygons, (P p1 , P p2 , ……P pq ) represents the sequence set of the vertex coordinates of the P-th polygon, P pq represents one of the vertex coordinates of the P-th polygon. Starting from any vertex coordinate of any polygon and traversing all the vertices of its polygon clockwise or counterclockwise, the sequence set of the vertex coordinates of one of the polygons is obtained; Traverse the vertex coordinates of each polygon to obtain a sequence set of the vertex coordinates of all polygons, and then further obtain the coordinates of the bounding rectangle of all polygon vertices (polygen xmin , polygen ymin , polygen xmax , polygen ymax ); where polygen xmin represents the value of the minimum abscissa of the outer bounding rectangle of the polygon vertices; polygen ymin Represents the value of the minimum ordinate of the outer bounding rectangle of the polygon vertices; polygen xmax Represents the value of the maximum abscissa of the outer bounding rectangle of the polygon vertices; polygen ymax Represents the value of the maximum ordinate of the outer bounding rectangle of the polygon vertices; Initialize the outer-frame coordinates of all sub-graphs as keys and an empty array Tilepolygondict as the value according to the outer-frame coordinates of the sub-graph and the outer-frame rectangle coordinates of the polygon vertices.

5. A method for generating a chip layout image based on a boundary tracking scan line algorithm according to claim 4, characterized in that According to the outer-frame rectangle coordinates of the polygon vertices, calculate the sub-graphs included in the polygon. The formula is: Among them, row min *H, row min *H, col min *H, col max *H respectively represent the index positions of the outer bounding rectangle coordinates of the polygon vertices under the sub - graph. H is the size of the sub - graph, row min , row max , col min , col max As intermediate reference values, the sub - graph index positions are obtained through the values of row min , row max , col min , col max ; Fill the data in the array Tilepolygondict to obtain the index position of the outer-frame rectangle coordinates of the polygon vertices under the sub-graph as: where i takes values starting from row min until row max and k takes values starting from col min until col max , idx polygen represents the index of the polygon vertex, and append(idx polygen ) means adding the index value of the polygon to the sub - graph index key; in this way, key - value pairs of sub - graph index and polygon index are generated.

6. A method for generating a chip layout image based on a boundary tracking scan line algorithm according to claim 5, characterized in that, The sub - figure index is the outer - frame coordinates of all sub - figures, and the polygon index is the position of the polygon among the vertex coordinates P of all polygons. all in.

7. A method for generating a chip layout image based on a boundary tracking scan line algorithm according to claim 6, characterized in that, In S2, it specifically includes: S2.

1. Obtain the sub-graph index and read the polygons included in the sub-graph in the array Tilepolygondict; S2.

2. Calculate the polygon-sub-graph minimum outer-frame. The polygon-sub-graph minimum outer-frame is the minimum outer-frame coordinates of all outer-frame rectangle coordinates that simultaneously contain the polygon vertices and the outer-frame coordinates of the sub-graph, that is: out xmin = min(polygens_x, tile_x); out ymin = min(polygens_y, tile_y); out xmax = max(polygens_x, tile_x); out ymax = max(polygens_y, tile_y); Among them, out xmin represents the value of the minimum abscissa of the minimum bounding box of the polygon-subgraph; out ymin represents the value of the minimum ordinate of the minimum bounding box of the polygon-subgraph; out xmax represents the value of the maximum abscissa of the minimum bounding box of the polygon-subgraph; out ymax represents the value of the maximum ordinate of the minimum bounding box of the polygon-subgraph; polygens_x represents the abscissa of the current polygon; polygens_y represents the ordinate of the current polygon; tile_x represents the abscissa of the sub-graph; tile_y represents the ordinate of the sub-graph; Construct a 0 matrix M with row length out ymax -out ymin and column length out xmax -out xmin to track the scan line algorithm and fill the interior of the polygon with a value of 1 for filling assignment.

8. A method for generating a chip layout image based on a boundary tracking scan line algorithm according to claim 7, wherein In S3, it specifically includes: Define the sides of a polygon as [(x u , y w ), (x v , y z )], indicating the side from the point (x u , y w ) to the point (x v , y z ). Here, x u , x v represent the positions of the abscissas corresponding to any side, and y w , y z represent the positions of the ordinates corresponding to any side; Starting from the sequence set that traverses all the vertex coordinates of the polygons, insert the data of each edge into the vertical edge dictionary dict y and the horizontal edge list list x ; specifically including: For the insertion method of vertical edges, traverse the points of the vertical edges except the upper endpoints and store them in the vertical edge dictionary dict y ; Vertical edge dictionary dict y is constructed as follows: using the y-axis coordinate as the key and the set list of x-axis coordinates sorted from smallest to largest sortx as the value to construct key-value pairs; For the vertical edge [(x n , y1), (x n , y2)], when y2 is greater than y1, for each key from y1 to y2 - 1, in the order of the x-axis coordinates, insert the corresponding x n value at the corresponding position, that is, dict y [y1] = [... x n-1 , x n , x n+1 ...], dict y [y1 + 1] = [... x n-1 , x n , x n+1 ...]... dict y [y2 - 1] = [... x n-1 , x n , x n+1 ...], ignoring y2; where x n represents the value of the abscissa in the vertical side, and y1 and y2 represent the values of the ordinate in the vertical side; Meanwhile, record the set of horizontal edges to obtain the horizontal edge list list x , that is, {[(x1, y1), (x2, y1)], [(x3, y2), (x4, y2)]... [(x n , y t ), (x m , y t )]}; where t represents the number of horizontal edges, and x1, x2,... x n , x m represent the abscissa values in the horizontal edges, and y1, y2,... y t represent the ordinate values in the horizontal edges; After traversing all the vertex coordinates of the polygons, store the coordinates of the points on the boundaries of all vertical edges, and separately record the coordinate sets of the points on each horizontal edge.

9. A method for generating a chip layout image based on a boundary tracking scan line algorithm according to claim 8, characterized in that In S3, traverse the data structure, that is, traverse the vertical edge dictionary dict y and the horizontal edge list list x , and for the vertical edge dictionary dict y take out the values of each row without repetition, that is, obtain the values of adjacent two subscripts, and assign values to the points between the two values in the matrix M in order, and the assigned value is 1, that is: A r,y = 1 (o < r < q, o = S xi , q = S xi+1 ); Among them, S xi represents the xi-th element in S, where xi starts from 0 with a step size of 2, that is, the next value of xi is 2, and S represents the set of x coordinates under any key y; A r，y represents an element in matrix M with abscissa r and ordinate y; Take out each element of the horizontal edge list list, that is, the coordinate set of the points of each horizontal edge, and assign a value of 1 to the points between each pair of horizontal edges. x ​ 10. A method for generating a chip layout image based on a boundary tracking scan line algorithm according to claim 1, characterized in that, In S4, after the matrix in S3 is assigned values, according to the position of the sub-graph, cut out the corresponding sub-graph matrix and save the sub-graph matrix as a picture file.

Images